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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_system.h
blobcd80788d314feef13e5f6408812397eb0af1d582
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
22 * All rights reserved.</center></h2>
23 *
24 * This software component is licensed by ST under BSD 3-Clause license,
25 * the "License"; You may not use this file except in compliance with the
26 * License. You may obtain a copy of the License at:
27 * opensource.org/licenses/BSD-3-Clause
28 *
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32H7xx_LL_SYSTEM_H
34 #define __STM32H7xx_LL_SYSTEM_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32h7xx.h"
42
43 /** @addtogroup STM32H7xx_LL_Driver
44 * @{
45 */
46
47 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
48
49 /** @defgroup SYSTEM_LL SYSTEM
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
58 * @{
59 */
60 /** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
61 * @{
62 */
63 #define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
64 #define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U
65 #define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U
66 #define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U
67 #define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U
68 #define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U
69 #define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U
70 #define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U
71 /**
72 * @}
73 */
74
75 /** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
76 * @{
77 */
78 #define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
79 #define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U
80 #define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U
81 #define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U
82 #define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U
83 #define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U
84 #define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U
85 #define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U
86 /**
87 * @}
88 */
89 /**
90 * @}
91 */
92
93 /* Private macros ------------------------------------------------------------*/
94
95 /* Exported types ------------------------------------------------------------*/
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
98 * @{
99 */
100
101 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
102 * @{
103 */
104 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */
105 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */
106 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */
107 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */
108 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
109 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
110 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
111 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
112 /**
113 * @}
114 */
115
116 /** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
117 * @{
118 */
119 #define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */
120 #define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */
121 #define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */
122 #define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */
123 #define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< PC3 Switch Open */
124 /**
125 * @}
126 */
127
128 #if defined(SYSCFG_PMCR_EPIS_SEL)
129 /** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
130 * @{
131 */
132 #define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */
133 #define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL /*!< ETH Media RMII interface */
134 /**
135 * @}
136 */
137 #endif /* SYSCFG_PMCR_EPIS_SEL */
138
139 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
140 * @{
141 */
142 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
143 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
144 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
145 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
146 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
147 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
148 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
149 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
150 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
151 #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */
152 #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */
153 /**
154 * @}
155 */
156
157 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
158 * @{
159 */
160 #define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
161 #define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
162 #define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
163 #define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
164 #define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
165 #define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
166 #define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
167 #define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
168 #define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
169 #define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
170 #define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
171 #define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
172 #define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
173 #define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
174 #define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
175 #define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
176 /**
177 * @}
178 */
179
180 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
181 * @{
182 */
183 #define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
184 with Break Input of TIM1/8/15/16/17 and HRTIM */
185
186 #define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML /*!< Enables and locks the ITCM double ECC error signal
187 with Break Input of TIM1/8/15/16/17 and HRTIM */
188
189 #define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML /*!< Enables and locks the DTCM double ECC error signal
190 with Break Input of TIM1/8/15/16/17 and HRTIM */
191
192 #define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L /*!< Enables and locks the SRAM1 double ECC error signal
193 with Break Input of TIM1/8/15/16/17 and HRTIM */
194
195 #define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal
196 with Break Input of TIM1/8/15/16/17 and HRTIM */
197
198 #define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal
199 with Break Input of TIM1/8/15/16/17 and HRTIM */
200
201 #define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal
202 with Break Input of TIM1/8/15/16/17 and HRTIM */
203
204 #define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML /*!< Enables and locks the BKRAM double ECC error signal
205 with Break Input of TIM1/8/15/16/17 and HRTIM */
206
207 #define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L /*!< Enables and locks the Cortex-M7 LOCKUP signal
208 with Break Input of TIM1/8/15/16/17 and HRTIM */
209
210 #define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL /*!< Enables and locks the FLASH double ECC error signal
211 with Break Input of TIM1/8/15/16/17 and HRTIM */
212
213 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL /*!< Enables and locks the PVD connection
214 with TIM1/8/15/16/17 and HRTIM Break Input
215 and also the PVDE and PLS bits of the Power Control Interface */
216 #if defined(DUAL_CORE)
217 #define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L /*!< Enables and locks the Cortex-M4 LOCKUP signal
218 with Break Input of TIM1/8/15/16/17 and HRTIM */
219 #endif /* DUAL_CORE */
220 /**
221 * @}
222 */
223
224 /** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
225 * @{
226 */
227 #define LL_SYSCFG_CELL_CODE 0U
228 #define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
229 /**
230 * @}
231 */
232
233 /** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
234 * @{
235 */
236 #define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
237 #define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M
238 /**
239 * @}
240 */
241
242 #if defined (DUAL_CORE)
243 /** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
244 * @{
245 */
246 #define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U
247 #define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M
248 /**
249 * @}
250 */
251 #endif /* DUAL_CORE */
252
253 /** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
254 * @{
255 */
256 #define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
257 #define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U
258 #define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U
259 #define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U
260 /**
261 * @}
262 */
263 #ifdef SYSCFG_PKGR_PKG
264 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
265 * @{
266 */
267 #define LL_SYSCFG_LQFP100_PACKAGE 0U
268 #define LL_SYSCFG_TQFP144_PACKAGE 2U
269 #define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U
270 #define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U
271 /**
272 * @}
273 */
274 #endif /* SYSCFG_PKGR_PKG */
275
276 /** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
277 * @{
278 */
279 #define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
280 #define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0
281 #define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1
282 #define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH
283
284 /**
285 * @}
286 */
287
288 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
289 * @{
290 */
291 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
292 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
293 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
294 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
295 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
296 /**
297 * @}
298 */
299
300 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
301 * @{
302 */
303 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */
304 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /*!< TIM3 counter stopped when core is halted */
305 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /*!< TIM4 counter stopped when core is halted */
306 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /*!< TIM5 counter stopped when core is halted */
307 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /*!< TIM6 counter stopped when core is halted */
308 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /*!< TIM7 counter stopped when core is halted */
309 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /*!< TIM12 counter stopped when core is halted */
310 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /*!< TIM13 counter stopped when core is halted */
311 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /*!< TIM14 counter stopped when core is halted */
312 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /*!< LPTIM1 counter stopped when core is halted */
313 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
314 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
315 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
316 /**
317 * @}
318 */
319
320 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
321 * @{
322 */
323 #define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */
324 /**
325 * @}
326 */
327
328 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
329 * @{
330 */
331 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */
332 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /*!< TIM8 counter stopped when core is halted */
333 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */
334 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */
335 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */
336 #define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */
337 /**
338 * @}
339 */
340
341 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
342 * @{
343 */
344 #define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */
345 /**
346 * @}
347 */
348
349 /** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
350 * @{
351 */
352 #define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */
353 #define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /*!< LPTIM2 is frozen while the core is in debug mode */
354 #define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /*!< LPTIM3 is frozen while the core is in debug mode */
355 #define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /*!< LPTIM4 is frozen while the core is in debug mode */
356 #define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /*!< LPTIM5 is frozen while the core is in debug mode */
357 #define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /*!< RTC is frozen while the core is in debug mode */
358 #define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /*!< IWDG1 is frozen while the core is in debug mode */
359 /**
360 * @}
361 */
362
363 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
364 * @{
365 */
366 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
367 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
368 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
369 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
370 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
371 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
372 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
373 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
374 /**
375 * @}
376 */
377
378 /**
379 * @}
380 */
381
382 /* Exported macro ------------------------------------------------------------*/
383
384 /* Exported functions --------------------------------------------------------*/
385 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
386 * @{
387 */
388
389 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
390 * @{
391 */
392
393 #if defined(SYSCFG_PMCR_EPIS_SEL)
394 /**
395 * @brief Select Ethernet PHY interface
396 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface
397 * @param Interface This parameter can be one of the following values:
398 * @arg @ref LL_SYSCFG_ETH_MII
399 * @arg @ref LL_SYSCFG_ETH_RMII
400 * @retval None
401 */
402 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
403 {
404 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
405 }
406
407 /**
408 * @brief Get Ethernet PHY interface
409 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface
410 * @retval Returned value can be one of the following values:
411 * @arg @ref LL_SYSCFG_ETH_MII
412 * @arg @ref LL_SYSCFG_ETH_RMII
413 */
414 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
415 {
416 return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
417 }
418
419 #endif /* SYSCFG_PMCR_EPIS_SEL */
420 /**
421 * @brief Open an Analog Switch
422 * @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch
423 * @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch
424 * @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch
425 * @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch
426 * @param AnalogSwitch This parameter can be one of the following values:
427 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
428 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
429 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
430 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
431 * @retval None
432 */
433 __STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
434 {
435 SET_BIT(SYSCFG->PMCR, AnalogSwitch);
436 }
437
438 /**
439 * @brief Close an Analog Switch
440 * @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch
441 * @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch
442 * @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch
443 * @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch
444 * @param AnalogSwitch This parameter can be one of the following values:
445 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
446 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
447 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
448 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
449 * @retval None
450 */
451 __STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
452 {
453 CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
454 }
455 #ifdef SYSCFG_PMCR_BOOSTEN
456 /**
457 * @brief Enable the Analog booster to reduce the total harmonic distortion
458 * of the analog switch when the supply voltage is lower than 2.7 V
459 * @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster
460 * @note Activating the booster allows to guaranty the analog switch AC performance
461 * when the supply voltage is below 2.7 V: in this case, the analog switch
462 * performance is the same on the full voltage range
463 * @retval None
464 */
465 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
466 {
467 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
468 }
469
470 /**
471 * @brief Disable the Analog booster
472 * @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster
473 * @note Activating the booster allows to guaranty the analog switch AC performance
474 * when the supply voltage is below 2.7 V: in this case, the analog switch
475 * performance is the same on the full voltage range
476 * @retval None
477 */
478 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
479 {
480 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
481 }
482 #endif /*SYSCFG_PMCR_BOOSTEN*/
483 /**
484 * @brief Enable the I2C fast mode plus driving capability.
485 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
486 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus
487 * @param ConfigFastModePlus This parameter can be a combination of the following values:
488 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
489 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
490 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
491 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
492 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
493 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
494 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
495 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
496 *
497 * (*) value not defined in all devices
498 * @retval None
499 */
500 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
501 {
502 SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
503 }
504
505 /**
506 * @brief Disable the I2C fast mode plus driving capability.
507 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
508 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus
509 * @param ConfigFastModePlus This parameter can be a combination of the following values:
510 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
511 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
512 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
513 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
514 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
515 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
516 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
517 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
518 * (*) value not defined in all devices
519 * @retval None
520 */
521 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
522 {
523 CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
524 }
525
526 /**
527 * @brief Configure source input for the EXTI external interrupt.
528 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
529 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
530 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
531 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
532 * @param Port This parameter can be one of the following values:
533 * @arg @ref LL_SYSCFG_EXTI_PORTA
534 * @arg @ref LL_SYSCFG_EXTI_PORTB
535 * @arg @ref LL_SYSCFG_EXTI_PORTC
536 * @arg @ref LL_SYSCFG_EXTI_PORTD
537 * @arg @ref LL_SYSCFG_EXTI_PORTE
538 * @arg @ref LL_SYSCFG_EXTI_PORTF
539 * @arg @ref LL_SYSCFG_EXTI_PORTG
540 * @arg @ref LL_SYSCFG_EXTI_PORTH
541 * @arg @ref LL_SYSCFG_EXTI_PORTI
542 * @arg @ref LL_SYSCFG_EXTI_PORTJ
543 * @arg @ref LL_SYSCFG_EXTI_PORTK
544 *
545 * (*) value not defined in all devices
546 * @param Line This parameter can be one of the following values:
547 * @arg @ref LL_SYSCFG_EXTI_LINE0
548 * @arg @ref LL_SYSCFG_EXTI_LINE1
549 * @arg @ref LL_SYSCFG_EXTI_LINE2
550 * @arg @ref LL_SYSCFG_EXTI_LINE3
551 * @arg @ref LL_SYSCFG_EXTI_LINE4
552 * @arg @ref LL_SYSCFG_EXTI_LINE5
553 * @arg @ref LL_SYSCFG_EXTI_LINE6
554 * @arg @ref LL_SYSCFG_EXTI_LINE7
555 * @arg @ref LL_SYSCFG_EXTI_LINE8
556 * @arg @ref LL_SYSCFG_EXTI_LINE9
557 * @arg @ref LL_SYSCFG_EXTI_LINE10
558 * @arg @ref LL_SYSCFG_EXTI_LINE11
559 * @arg @ref LL_SYSCFG_EXTI_LINE12
560 * @arg @ref LL_SYSCFG_EXTI_LINE13
561 * @arg @ref LL_SYSCFG_EXTI_LINE14
562 * @arg @ref LL_SYSCFG_EXTI_LINE15
563 * @retval None
564 */
565 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
566 {
567 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
568 }
569
570 /**
571 * @brief Get the configured defined for specific EXTI Line
572 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
573 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
574 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
575 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
576 * @param Line This parameter can be one of the following values:
577 * @arg @ref LL_SYSCFG_EXTI_LINE0
578 * @arg @ref LL_SYSCFG_EXTI_LINE1
579 * @arg @ref LL_SYSCFG_EXTI_LINE2
580 * @arg @ref LL_SYSCFG_EXTI_LINE3
581 * @arg @ref LL_SYSCFG_EXTI_LINE4
582 * @arg @ref LL_SYSCFG_EXTI_LINE5
583 * @arg @ref LL_SYSCFG_EXTI_LINE6
584 * @arg @ref LL_SYSCFG_EXTI_LINE7
585 * @arg @ref LL_SYSCFG_EXTI_LINE8
586 * @arg @ref LL_SYSCFG_EXTI_LINE9
587 * @arg @ref LL_SYSCFG_EXTI_LINE10
588 * @arg @ref LL_SYSCFG_EXTI_LINE11
589 * @arg @ref LL_SYSCFG_EXTI_LINE12
590 * @arg @ref LL_SYSCFG_EXTI_LINE13
591 * @arg @ref LL_SYSCFG_EXTI_LINE14
592 * @arg @ref LL_SYSCFG_EXTI_LINE15
593 * @retval Returned value can be one of the following values:
594 * @arg @ref LL_SYSCFG_EXTI_PORTA
595 * @arg @ref LL_SYSCFG_EXTI_PORTB
596 * @arg @ref LL_SYSCFG_EXTI_PORTC
597 * @arg @ref LL_SYSCFG_EXTI_PORTD
598 * @arg @ref LL_SYSCFG_EXTI_PORTE
599 * @arg @ref LL_SYSCFG_EXTI_PORTF
600 * @arg @ref LL_SYSCFG_EXTI_PORTG
601 * @arg @ref LL_SYSCFG_EXTI_PORTH
602 * @arg @ref LL_SYSCFG_EXTI_PORTI
603 * @arg @ref LL_SYSCFG_EXTI_PORTJ
604 * @arg @ref LL_SYSCFG_EXTI_PORTK
605 * (*) value not defined in all devices
606 */
607 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
608 {
609 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
610 }
611
612 /**
613 * @brief Set connections to TIM1/8/15/16/17 and HRTIM Break inputs
614 * @note this feature is available on STM32H7 rev.B and above
615 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs\n
616 * SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs\n
617 * SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs\n
618 * SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs\n
619 * SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs\n
620 * SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs\n
621 * SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs\n
622 * SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs\n
623 * SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs\n
624 * SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs\n
625 * SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs\n
626 * SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs
627 * @param Break This parameter can be a combination of the following values:
628 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
629 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
630 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
631 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
632 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
633 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
634 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
635 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
636 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
637 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
638 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
639 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
640 * @retval None
641 */
642 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
643 {
644 #if defined(DUAL_CORE)
645 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
646 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
647 SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break);
648 #elif defined (SYSCFG_CFGR_AXISRAML)
649 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
650 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
651 SYSCFG_CFGR_PVDL, Break);
652 #else
653 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\
654 SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
655 SYSCFG_CFGR_PVDL, Break);
656 #endif /* DUAL_CORE */
657 }
658
659 /**
660 * @brief Get connections to TIM1/8/15/16/17 and HRTIM Break inputs
661 * @note this feature is available on STM32H7 rev.B and above
662 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs\n
663 * SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs\n
664 * SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs\n
665 * SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs\n
666 * SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs\n
667 * SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs\n
668 * SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs\n
669 * SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs\n
670 * SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs\n
671 * SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs\n
672 * SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs\n
673 * SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs
674 * @retval Returned value can be can be a combination of the following values:
675 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
676 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
677 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
678 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
679 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
680 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
681 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
682 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
683 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
684 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
685 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
686 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
687 */
688 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
689 {
690 #if defined(DUAL_CORE)
691 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
692 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
693 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
694 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L));
695 #elif defined (SYSCFG_CFGR_AXISRAML)
696 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
697 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
698 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
699 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
700 #else
701 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \
702 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
703 #endif /* DUAL_CORE */
704 }
705
706 /**
707 * @brief Enable the Compensation Cell
708 * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell
709 * @note The I/O compensation cell can be used only when the device supply
710 * voltage ranges from 2.4 to 3.6 V
711 * @retval None
712 */
713 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
714 {
715 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
716 }
717
718 /**
719 * @brief Disable the Compensation Cell
720 * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell
721 * @note The I/O compensation cell can be used only when the device supply
722 * voltage ranges from 2.4 to 3.6 V
723 * @retval None
724 */
725 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
726 {
727 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
728 }
729
730 /**
731 * @brief Check if the Compensation Cell is enabled
732 * @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell
733 * @retval State of bit (1 or 0).
734 */
735 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
736 {
737 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
738 }
739
740 /**
741 * @brief Get Compensation Cell ready Flag
742 * @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR
743 * @retval State of bit (1 or 0).
744 */
745 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
746 {
747 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
748 }
749
750 /**
751 * @brief Enable the I/O speed optimization when the product voltage is low.
752 * @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize
753 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
754 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
755 * might be destructive.
756 * @retval None
757 */
758 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
759 {
760 #if defined(SYSCFG_CCCSR_HSLV)
761 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
762 #else
763 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
764 #endif /* SYSCFG_CCCSR_HSLV */
765 }
766
767 #if defined(SYSCFG_CCCSR_HSLV1)
768 /**
769 * @brief Enable the I/O speed optimization when the product voltage is low.
770 * @rmtoll CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize
771 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
772 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
773 * might be destructive.
774 * @retval None
775 */
776 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
777 {
778 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
779 }
780
781 /**
782 * @brief Enable the I/O speed optimization when the product voltage is low.
783 * @rmtoll CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize
784 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
785 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
786 * might be destructive.
787 * @retval None
788 */
789 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
790 {
791 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
792 }
793
794 /**
795 * @brief Enable the I/O speed optimization when the product voltage is low.
796 * @rmtoll CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize
797 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
798 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
799 * might be destructive.
800 * @retval None
801 */
802 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
803 {
804 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
805 }
806 #endif /*SYSCFG_CCCSR_HSLV1*/
807
808
809 /**
810 * @brief To Disable optimize the I/O speed when the product voltage is low.
811 * @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize
812 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
813 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
814 * might be destructive.
815 * @retval None
816 */
817 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
818 {
819 #if defined(SYSCFG_CCCSR_HSLV)
820 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
821 #else
822 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
823 #endif /* SYSCFG_CCCSR_HSLV */
824 }
825
826 #if defined(SYSCFG_CCCSR_HSLV1)
827 /**
828 * @brief To Disable optimize the I/O speed when the product voltage is low.
829 * @rmtoll CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize
830 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
831 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
832 * might be destructive.
833 * @retval None
834 */
835 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
836 {
837 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
838 }
839
840 /**
841 * @brief To Disable optimize the I/O speed when the product voltage is low.
842 * @rmtoll CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize
843 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
844 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
845 * might be destructive.
846 * @retval None
847 */
848 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
849 {
850 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
851 }
852
853 /**
854 * @brief To Disable optimize the I/O speed when the product voltage is low.
855 * @rmtoll CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize
856 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
857 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
858 * might be destructive.
859 * @retval None
860 */
861 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
862 {
863 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
864 }
865 #endif /*SYSCFG_CCCSR_HSLV1*/
866
867 /**
868 * @brief Check if the I/O speed optimization is enabled
869 * @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization
870 * @retval State of bit (1 or 0).
871 */
872 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
873 {
874 #if defined(SYSCFG_CCCSR_HSLV)
875 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
876 #else
877 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
878 #endif /*SYSCFG_CCCSR_HSLV*/
879 }
880
881 #if defined(SYSCFG_CCCSR_HSLV1)
882 /**
883 * @brief Check if the I/O speed optimization is enabled
884 * @rmtoll CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization
885 * @retval State of bit (1 or 0).
886 */
887 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
888 {
889 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
890 }
891
892 /**
893 * @brief Check if the I/O speed optimization is enabled
894 * @rmtoll CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization
895 * @retval State of bit (1 or 0).
896 */
897 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
898 {
899 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
900 }
901
902 /**
903 * @brief Check if the I/O speed optimization is enabled
904 * @rmtoll CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization
905 * @retval State of bit (1 or 0).
906 */
907 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
908 {
909 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
910 }
911 #endif /*SYSCFG_CCCSR_HSLV1*/
912
913 /**
914 * @brief Set the code selection for the I/O Compensation cell
915 * @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode
916 * @param CompCode: Selects the code to be applied for the I/O compensation cell
917 * This parameter can be one of the following values:
918 * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
919 * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
920 * @retval None
921 */
922 __STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
923 {
924 SET_BIT(SYSCFG->CCCSR, CompCode);
925 }
926
927 /**
928 * @brief Get the code selected for the I/O Compensation cell
929 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode
930 * @retval Returned value can be one of the following values:
931 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
932 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
933 */
934 __STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
935 {
936 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
937 }
938
939 #ifdef SYSCFG_CCCSR_CS_MMC
940
941 /**
942 * @brief Get the code selected for the I/O Compensation cell on the VDDMMC power rail
943 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode
944 * @retval Returned value can be one of the following values:
945 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
946 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
947 */
948 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
949 {
950 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
951 }
952 #endif /*SYSCFG_CCCSR_CS_MMC*/
953
954 /**
955 * @brief Get I/O compensation cell value for PMOS transistors
956 * @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue
957 * @retval Returned value is the I/O compensation cell value for PMOS transistors
958 */
959 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
960 {
961 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
962 }
963
964 /**
965 * @brief Get I/O compensation cell value for NMOS transistors
966 * @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue
967 * @retval Returned value is the I/O compensation cell value for NMOS transistors
968 */
969 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
970 {
971 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
972 }
973
974 /**
975 * @brief Set I/O compensation cell code for PMOS transistors
976 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
977 * @param PMOSCode PMOS compensation code
978 * This code is applied to the I/O compensation cell when the CS bit of the
979 * SYSCFG_CMPCR is set
980 * @retval None
981 */
982 __STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
983 {
984 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
985 }
986
987 /**
988 * @brief Get I/O compensation cell code for PMOS transistors
989 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
990 * @retval Returned value is the I/O compensation cell code for PMOS transistors
991 */
992 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
993 {
994 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
995 }
996
997 #ifdef SYSCFG_CCCR_PCC_MMC
998
999 /**
1000 * @brief Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
1001 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
1002 * @param PMOSCode PMOS compensation code
1003 * This code is applied to the I/O compensation cell when the CS bit of the
1004 * SYSCFG_CMPCR is set
1005 * @retval None
1006 */
1007 __STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
1008 {
1009 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
1010 }
1011
1012 /**
1013 * @brief Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
1014 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
1015 * @retval Returned value is the I/O compensation cell code for PMOS transistors
1016 */
1017 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
1018 {
1019 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
1020 }
1021 #endif /* SYSCFG_CCCR_PCC_MMC */
1022
1023 /**
1024 * @brief Set I/O compensation cell code for NMOS transistors
1025 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
1026 * @param NMOSCode NMOS compensation code
1027 * This code is applied to the I/O compensation cell when the CS bit of the
1028 * SYSCFG_CMPCR is set
1029 * @retval None
1030 */
1031 __STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
1032 {
1033 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
1034 }
1035
1036 /**
1037 * @brief Get I/O compensation cell code for NMOS transistors
1038 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
1039 * @retval Returned value is the I/O compensation cell code for NMOS transistors
1040 */
1041 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
1042 {
1043 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
1044 }
1045
1046 #ifdef SYSCFG_CCCR_NCC_MMC
1047
1048 /**
1049 * @brief Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
1050 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
1051 * @param NMOSCode: NMOS compensation code
1052 * This code is applied to the I/O compensation cell when the CS bit of the
1053 * SYSCFG_CMPCR is set
1054 * @retval None
1055 */
1056 __STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
1057 {
1058 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
1059 }
1060
1061 /**
1062 * @brief Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
1063 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
1064 * @retval Returned value is the I/O compensation cell code for NMOS transistors
1065 */
1066 __STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
1067 {
1068 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
1069 }
1070 #endif /*SYSCFG_CCCR_NCC_MMC*/
1071
1072 #ifdef SYSCFG_PKGR_PKG
1073 /**
1074 * @brief Get the device package
1075 * @rmtoll PKGR PKG LL_SYSCFG_GetPackage
1076 * @retval Returned value can be one of the following values:
1077 * @arg @ref LL_SYSCFG_LQFP100_PACKAGE
1078 * @arg @ref LL_SYSCFG_TQFP144_PACKAGE
1079 * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE
1080 * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE
1081 */
1082 __STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
1083 {
1084 return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
1085 }
1086 #endif /*SYSCFG_PKGR_PKG*/
1087
1088 #ifdef SYSCFG_UR0_RDP
1089 /**
1090 * @brief Get the Flash memory protection level
1091 * @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel
1092 * @retval Returned value can be one of the following values:
1093 * 0xAA : RDP level 0
1094 * 0xCC : RDP level 2
1095 * Any other value : RDP level 1
1096 */
1097 __STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
1098 {
1099 return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
1100 }
1101 /**
1102 * @brief Indicate if the Flash memory bank addresses are inverted or not
1103 * @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped
1104 * @retval State of bit (1 or 0).
1105 */
1106 __STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
1107 {
1108 return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
1109 }
1110
1111 /**
1112 * @brief Get the BOR Threshold Reset Level
1113 * @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel
1114 * @retval Returned value can be one of the following values:
1115 * @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
1116 * @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
1117 * @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
1118 * @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
1119 */
1120 __STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
1121 {
1122 return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
1123 }
1124 /**
1125 * @brief BootCM7 address 0 configuration
1126 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0
1127 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
1128 * @retval None
1129 */
1130 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
1131 {
1132 /* Configure CM7 BOOT ADD0 */
1133 #if defined(DUAL_CORE)
1134 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
1135 #else
1136 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
1137 #endif /*DUAL_CORE*/
1138
1139 }
1140
1141 /**
1142 * @brief Get BootCM7 address 0
1143 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0
1144 * @retval Returned the CM7 Boot Address0
1145 */
1146 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
1147 {
1148 /* Get CM7 BOOT ADD0 */
1149 #if defined(DUAL_CORE)
1150 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
1151 #else
1152 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
1153 #endif /*DUAL_CORE*/
1154 }
1155
1156 /**
1157 * @brief BootCM7 address 1 configuration
1158 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1
1159 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
1160 * @retval None
1161 */
1162 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
1163 {
1164 /* Configure CM7 BOOT ADD1 */
1165 #if defined(DUAL_CORE)
1166 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
1167 #else
1168 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
1169 #endif /*DUAL_CORE*/
1170 }
1171
1172 /**
1173 * @brief Get BootCM7 address 1
1174 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1
1175 * @retval Returned the CM7 Boot Address0
1176 */
1177 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
1178 {
1179 /* Get CM7 BOOT ADD0 */
1180 #if defined(DUAL_CORE)
1181 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
1182 #else
1183 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
1184 #endif /* DUAL_CORE */
1185 }
1186
1187 #if defined(DUAL_CORE)
1188 /**
1189 * @brief BootCM4 address 0 configuration
1190 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_SetCM4BootAddress0
1191 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0
1192 * @retval None
1193 */
1194 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
1195 {
1196 /* Configure CM4 BOOT ADD0 */
1197 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
1198 }
1199
1200 /**
1201 * @brief Get BootCM4 address 0
1202 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_GetCM4BootAddress0
1203 * @retval Returned the CM4 Boot Address0
1204 */
1205 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
1206 {
1207 /* Get CM4 BOOT ADD0 */
1208 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
1209 }
1210
1211 /**
1212 * @brief BootCM4 address 1 configuration
1213 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_SetCM4BootAddress1
1214 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address1
1215 * @retval None
1216 */
1217 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
1218 {
1219 /* Configure CM4 BOOT ADD1 */
1220 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
1221 }
1222
1223 /**
1224 * @brief Get BootCM4 address 1
1225 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_GetCM4BootAddress1
1226 * @retval Returned the CM4 Boot Address0
1227 */
1228 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
1229 {
1230 /* Get CM4 BOOT ADD0 */
1231 return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
1232 }
1233 #endif /*DUAL_CORE*/
1234
1235 /**
1236 * @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase
1237 * @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable
1238 * @retval State of bit (1 or 0).
1239 */
1240 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
1241 {
1242 return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
1243 }
1244
1245 /**
1246 * @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase
1247 * @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable
1248 * @retval State of bit (1 or 0).
1249 */
1250 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
1251 {
1252 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
1253 }
1254
1255 /**
1256 * @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected
1257 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected
1258 * @retval State of bit (1 or 0).
1259 */
1260 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
1261 {
1262 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1263 }
1264
1265 /**
1266 * @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected
1267 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected
1268 * @retval State of bit (1 or 0).
1269 */
1270 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
1271 {
1272 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1273 }
1274
1275 /**
1276 * @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected
1277 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected
1278 * @retval State of bit (1 or 0).
1279 */
1280 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
1281 {
1282 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1283 }
1284
1285 /**
1286 * @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected
1287 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected
1288 * @retval State of bit (1 or 0).
1289 */
1290 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
1291 {
1292 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1293 }
1294
1295 /**
1296 * @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected
1297 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected
1298 * @retval State of bit (1 or 0).
1299 */
1300 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
1301 {
1302 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1303 }
1304
1305 /**
1306 * @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected
1307 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected
1308 * @retval State of bit (1 or 0).
1309 */
1310 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
1311 {
1312 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1313 }
1314
1315 /**
1316 * @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected
1317 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected
1318 * @retval State of bit (1 or 0).
1319 */
1320 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
1321 {
1322 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1323 }
1324
1325 /**
1326 * @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected
1327 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected
1328 * @retval State of bit (1 or 0).
1329 */
1330 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
1331 {
1332 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1333 }
1334
1335 /**
1336 * @brief Get the protected area start address for Flash bank 1
1337 * @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
1338 * @retval Returned the protected area start address for Flash bank 1
1339 */
1340 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
1341 {
1342 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
1343 }
1344
1345 /**
1346 * @brief Get the protected area end address for Flash bank 1
1347 * @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
1348 * @retval Returned the protected area end address for Flash bank 1
1349 */
1350 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
1351 {
1352 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
1353 }
1354
1355 /**
1356 * @brief Get the secured area start address for Flash bank 1
1357 * @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
1358 * @retval Returned the secured area start address for Flash bank 1
1359 */
1360 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
1361 {
1362 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
1363 }
1364
1365 /**
1366 * @brief Get the secured area end address for Flash bank 1
1367 * @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
1368 * @retval Returned the secured area end address for Flash bank 1
1369 */
1370 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
1371 {
1372 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
1373 }
1374
1375 /**
1376 * @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase
1377 * @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable
1378 * @retval State of bit (1 or 0).
1379 */
1380 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
1381 {
1382 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
1383 }
1384
1385 /**
1386 * @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase
1387 * @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable
1388 * @retval State of bit (1 or 0).
1389 */
1390 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
1391 {
1392 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
1393 }
1394
1395 /**
1396 * @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected
1397 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected
1398 * @retval State of bit (1 or 0).
1399 */
1400 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
1401 {
1402 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1403 }
1404
1405 /**
1406 * @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected
1407 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected
1408 * @retval State of bit (1 or 0).
1409 */
1410 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
1411 {
1412 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1413 }
1414
1415 /**
1416 * @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected
1417 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected
1418 * @retval State of bit (1 or 0).
1419 */
1420 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
1421 {
1422 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1423 }
1424
1425 /**
1426 * @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected
1427 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected
1428 * @retval State of bit (1 or 0).
1429 */
1430 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
1431 {
1432 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1433 }
1434
1435 /**
1436 * @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected
1437 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected
1438 * @retval State of bit (1 or 0).
1439 */
1440 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
1441 {
1442 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1443 }
1444
1445 /**
1446 * @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected
1447 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected
1448 * @retval State of bit (1 or 0).
1449 */
1450 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
1451 {
1452 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1453 }
1454
1455 /**
1456 * @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected
1457 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected
1458 * @retval State of bit (1 or 0).
1459 */
1460 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
1461 {
1462 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1463 }
1464
1465 /**
1466 * @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected
1467 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected
1468 * @retval State of bit (1 or 0).
1469 */
1470 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
1471 {
1472 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1473 }
1474
1475 /**
1476 * @brief Get the protected area start address for Flash bank 2
1477 * @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
1478 * @retval Returned the protected area start address for Flash bank 2
1479 */
1480 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
1481 {
1482 return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
1483 }
1484
1485 /**
1486 * @brief Get the protected area end address for Flash bank 2
1487 * @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
1488 * @retval Returned the protected area end address for Flash bank 2
1489 */
1490 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
1491 {
1492 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
1493 }
1494
1495 /**
1496 * @brief Get the secured area start address for Flash bank 2
1497 * @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
1498 * @retval Returned the secured area start address for Flash bank 2
1499 */
1500 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
1501 {
1502 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
1503 }
1504
1505 /**
1506 * @brief Get the secured area end address for Flash bank 2
1507 * @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
1508 * @retval Returned the secured area end address for Flash bank 2
1509 */
1510 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
1511 {
1512 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
1513 }
1514
1515 /**
1516 * @brief Get the Independent Watchdog 1 control mode (Software or Hardware)
1517 * @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode
1518 * @retval Returned value can be one of the following values:
1519 * @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
1520 * @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
1521 */
1522 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
1523 {
1524 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
1525 }
1526
1527 #if defined (DUAL_CORE)
1528 /**
1529 * @brief Get the Independent Watchdog 2 control mode (Software or Hardware)
1530 * @rmtoll UR12 IWDG2M LL_SYSCFG_GetIWDG2ControlMode
1531 * @retval Returned value can be one of the following values:
1532 * @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE
1533 * @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE
1534 */
1535 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
1536 {
1537 return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
1538 }
1539 #endif /* DUAL_CORE */
1540
1541 /**
1542 * @brief Indicates the Secure mode status
1543 * @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled
1544 * @retval State of bit (1 or 0).
1545 */
1546 __STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
1547 {
1548 return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
1549 }
1550
1551 /**
1552 * @brief Indicates if a reset is generated when D1 domain enters DStandby mode
1553 * @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset
1554 * @retval State of bit (1 or 0).
1555 */
1556 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
1557 {
1558 return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
1559 }
1560
1561 /**
1562 * @brief Get the secured DTCM RAM size
1563 * @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize
1564 * @retval Returned value can be one of the following values:
1565 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
1566 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
1567 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
1568 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
1569 */
1570 __STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
1571 {
1572 return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
1573 }
1574
1575 /**
1576 * @brief Indicates if a reset is generated when D1 domain enters DStop mode
1577 * @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset
1578 * @retval State of bit (1 or 0).
1579 */
1580 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
1581 {
1582 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
1583 }
1584
1585 #if defined (DUAL_CORE)
1586 /**
1587 * @brief Indicates if a reset is generated when D2 domain enters DStandby mode
1588 * @rmtoll UR14 D2SBRST LL_SYSCFG_IsD2StandbyGenerateReset
1589 * @retval State of bit (1 or 0).
1590 */
1591 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
1592 {
1593 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
1594 }
1595
1596 /**
1597 * @brief Indicates if a reset is generated when D2 domain enters DStop mode
1598 * @rmtoll UR15 D2STPRST LL_SYSCFG_IsD2StopGenerateReset
1599 * @retval State of bit (1 or 0).
1600 */
1601 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
1602 {
1603 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
1604 }
1605 #endif /* DUAL_CORE */
1606
1607 /**
1608 * @brief Indicates if the independent watchdog is frozen in Standby mode
1609 * @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode
1610 * @retval State of bit (1 or 0).
1611 */
1612 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
1613 {
1614 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
1615 }
1616
1617 /**
1618 * @brief Indicates if the independent watchdog is frozen in Stop mode
1619 * @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode
1620 * @retval State of bit (1 or 0).
1621 */
1622 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
1623 {
1624 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
1625 }
1626
1627 /**
1628 * @brief Indicates if the device private key is programmed
1629 * @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed
1630 * @retval State of bit (1 or 0).
1631 */
1632 __STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
1633 {
1634 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
1635 }
1636
1637 /**
1638 * @brief Indicates if the Product is working on the full voltage range or not
1639 * @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV
1640 * @note When the IOHSLV option bit is set the Product is working below 2.7 V.
1641 * When the IOHSLV option bit is reset the Product is working on the
1642 * full voltage range.
1643 * @retval State of bit (1 or 0).
1644 */
1645 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
1646 {
1647 return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
1648 }
1649 #endif /*SYSCFG_UR0_RDP*/
1650
1651 /**
1652 * @}
1653 */
1654
1655 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1656 * @{
1657 */
1658
1659 /**
1660 * @brief Return the device identifier
1661 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1662 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1663 */
1664 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1665 {
1666 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1667 }
1668
1669 /**
1670 * @brief Return the device revision identifier
1671 * @note This field indicates the revision of the device.
1672 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
1673 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1674 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1675 */
1676 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1677 {
1678 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1679 }
1680
1681 /**
1682 * @brief Enable D1 Domain/CDomain debug during SLEEP mode
1683 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode
1684 * @retval None
1685 */
1686 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
1687 {
1688 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1689 }
1690
1691 /**
1692 * @brief Disable D1 Domain/CDomain debug during SLEEP mode
1693 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode
1694 * @retval None
1695 */
1696 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
1697 {
1698 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1699 }
1700
1701 /**
1702 * @brief Enable D1 Domain/CDomain debug during STOP mode
1703 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode
1704 * @retval None
1705 */
1706 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
1707 {
1708 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1709 }
1710
1711 /**
1712 * @brief Disable D1 Domain/CDomain debug during STOP mode
1713 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode
1714 * @retval None
1715 */
1716 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
1717 {
1718 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1719 }
1720
1721 /**
1722 * @brief Enable D1 Domain/CDomain debug during STANDBY mode
1723 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode
1724 * @retval None
1725 */
1726 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
1727 {
1728 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1729 }
1730
1731 /**
1732 * @brief Disable D1 Domain/CDomain debug during STANDBY mode
1733 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode
1734 * @retval None
1735 */
1736 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
1737 {
1738 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1739 }
1740
1741 #if defined (DUAL_CORE)
1742 /**
1743 * @brief Enable D2 Domain debug during SLEEP mode
1744 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_EnableD2DebugInSleepMode
1745 * @retval None
1746 */
1747 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
1748 {
1749 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1750 }
1751
1752 /**
1753 * @brief Disable D2 Domain debug during SLEEP mode
1754 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_DisableD2DebugInSleepMode
1755 * @retval None
1756 */
1757 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
1758 {
1759 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1760 }
1761
1762 /**
1763 * @brief Enable D2 Domain debug during STOP mode
1764 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_EnableD2DebugInStopMode
1765 * @retval None
1766 */
1767 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
1768 {
1769 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1770 }
1771
1772 /**
1773 * @brief Disable D2 Domain debug during STOP mode
1774 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_DisableD2DebugInStopMode
1775 * @retval None
1776 */
1777 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
1778 {
1779 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1780 }
1781
1782 /**
1783 * @brief Enable D2 Domain debug during STANDBY mode
1784 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_EnableD2DebugInStandbyMode
1785 * @retval None
1786 */
1787 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
1788 {
1789 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1790 }
1791
1792 /**
1793 * @brief Disable D2 Domain debug during STANDBY mode
1794 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_DisableD2DebugInStandbyMode
1795 * @retval None
1796 */
1797 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
1798 {
1799 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1800 }
1801 #endif /* DUAL_CORE */
1802
1803
1804 /**
1805 * @brief Enable D3 Domain/SRDomain debug during STOP mode
1806 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode
1807 * @retval None
1808 */
1809 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
1810 {
1811 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1812 }
1813
1814 /**
1815 * @brief Disable D3 Domain/SRDomain debug during STOP mode
1816 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode
1817 * @retval None
1818 */
1819 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
1820 {
1821 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1822 }
1823
1824 /**
1825 * @brief Enable D3 Domain/SRDomain debug during STANDBY mode
1826 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode
1827 * @retval None
1828 */
1829 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
1830 {
1831 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1832 }
1833
1834 /**
1835 * @brief Disable D3 Domain/SRDomain debug during STANDBY mode
1836 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode
1837 * @retval None
1838 */
1839 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
1840 {
1841 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1842 }
1843
1844 /**
1845 * @brief Enable the trace port clock
1846 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock
1847 * @retval None
1848 */
1849 __STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
1850 {
1851 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
1852 }
1853
1854 /**
1855 * @brief Disable the trace port clock
1856 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock
1857 * @retval None
1858 */
1859 __STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
1860 {
1861 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
1862 }
1863
1864 /**
1865 * @brief Enable the Domain1/CDomain debug clock enable
1866 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock
1867 * @retval None
1868 */
1869 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
1870 {
1871 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
1872 }
1873
1874 /**
1875 * @brief Disable the Domain1/CDomain debug clock enable
1876 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock
1877 * @retval None
1878 */
1879 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
1880 {
1881 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
1882 }
1883
1884 /**
1885 * @brief Enable the Domain3/SRDomain debug clock enable
1886 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock
1887 * @retval None
1888 */
1889 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
1890 {
1891 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
1892 }
1893
1894 /**
1895 * @brief Disable the Domain3/SRDomain debug clock enable
1896 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock
1897 * @retval None
1898 */
1899 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
1900 {
1901 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
1902 }
1903
1904 #define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U
1905 #define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN
1906 /**
1907 * @brief Set the direction of the bi-directional trigger pin TRGIO
1908 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n
1909 * @param PinDirection This parameter can be one of the following values:
1910 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
1911 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
1912 * @retval None
1913 */
1914 __STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
1915 {
1916 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
1917 }
1918
1919 /**
1920 * @brief Get the direction of the bi-directional trigger pin TRGIO
1921 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n
1922 * @retval Returned value can be one of the following values:
1923 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
1924 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
1925 */
1926 __STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
1927 {
1928 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
1929 }
1930
1931 /**
1932 * @brief Freeze APB1 group1 peripherals
1933 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1934 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1935 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1936 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1937 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1938 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1939 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1940 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1941 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1942 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1943 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1944 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1945 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1946 * @param Periphs This parameter can be a combination of the following values:
1947 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1948 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1949 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1950 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1951 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1952 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1953 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1954 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1955 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1956 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1957 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1958 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1959 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1960 * @retval None
1961 */
1962 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1963 {
1964 SET_BIT(DBGMCU->APB1LFZ1, Periphs);
1965 }
1966
1967 /**
1968 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1969 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1970 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1971 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1972 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1973 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1974 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1975 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1976 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1977 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1978 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1979 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1980 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1981 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1982 * @param Periphs This parameter can be a combination of the following values:
1983 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1984 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1985 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1986 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1987 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1988 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1989 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1990 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1991 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1992 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1993 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1994 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1995 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1996 * @retval None
1997 */
1998 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1999 {
2000 CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
2001 }
2002
2003 /**
2004 * @brief Freeze APB1 group2 peripherals
2005 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2006 * @param Periphs This parameter can be a combination of the following values:
2007 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
2008 * @retval None
2009 */
2010 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
2011 {
2012 SET_BIT(DBGMCU->APB1HFZ1, Periphs);
2013 }
2014
2015 /**
2016 * @brief Unfreeze APB1 group2 peripherals
2017 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2018 * @param Periphs This parameter can be a combination of the following values:
2019 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
2020 * @retval None
2021 */
2022 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
2023 {
2024 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
2025 }
2026
2027 /**
2028 * @brief Freeze APB2 peripherals
2029 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2030 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2031 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2032 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2033 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
2034 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
2035 * @param Periphs This parameter can be a combination of the following values:
2036 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
2037 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
2038 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
2039 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
2040 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
2041 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
2042 * @retval None
2043 */
2044 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
2045 {
2046 SET_BIT(DBGMCU->APB2FZ1, Periphs);
2047 }
2048
2049 /**
2050 * @brief Unfreeze APB2 peripherals
2051 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2052 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2053 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2054 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2055 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
2056 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
2057 * @param Periphs This parameter can be a combination of the following values:
2058 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
2059 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
2060 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
2061 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
2062 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
2063 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
2064 * @retval None
2065 */
2066 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
2067 {
2068 CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
2069 }
2070
2071 /**
2072 * @brief Freeze APB3 peripherals
2073 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n
2074 * @param Periphs This parameter can be a combination of the following values:
2075 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
2076 * @retval None
2077 */
2078 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
2079 {
2080 SET_BIT(DBGMCU->APB3FZ1, Periphs);
2081 }
2082
2083 /**
2084 * @brief Unfreeze APB3 peripherals
2085 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
2086 * @param Periphs This parameter can be a combination of the following values:
2087 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
2088 * @retval None
2089 */
2090 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
2091 {
2092 CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
2093 }
2094
2095 /**
2096 * @brief Freeze APB4 peripherals
2097 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2098 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2099 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2100 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2101 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2102 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2103 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2104 * @param Periphs This parameter can be a combination of the following values:
2105 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
2106 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
2107 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
2108 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
2109 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
2110 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
2111 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
2112 * @retval None
2113 */
2114 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
2115 {
2116 SET_BIT(DBGMCU->APB4FZ1, Periphs);
2117 }
2118
2119 /**
2120 * @brief Unfreeze APB4 peripherals
2121 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2122 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2123 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2124 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2125 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2126 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2127 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2128 * @param Periphs This parameter can be a combination of the following values:
2129 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
2130 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
2131 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
2132 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
2133 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
2134 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
2135 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
2136 * @retval None
2137 */
2138 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
2139 {
2140 CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
2141 }
2142 /**
2143 * @}
2144 */
2145
2146 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
2147 * @{
2148 */
2149
2150 /**
2151 * @brief Set FLASH Latency
2152 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
2153 * @param Latency This parameter can be one of the following values:
2154 * @arg @ref LL_FLASH_LATENCY_0
2155 * @arg @ref LL_FLASH_LATENCY_1
2156 * @arg @ref LL_FLASH_LATENCY_2
2157 * @arg @ref LL_FLASH_LATENCY_3
2158 * @arg @ref LL_FLASH_LATENCY_4
2159 * @arg @ref LL_FLASH_LATENCY_5
2160 * @arg @ref LL_FLASH_LATENCY_6
2161 * @arg @ref LL_FLASH_LATENCY_7
2162 * @retval None
2163 */
2164 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
2165 {
2166 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
2167 }
2168
2169 /**
2170 * @brief Get FLASH Latency
2171 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
2172 * @retval Returned value can be one of the following values:
2173 * @arg @ref LL_FLASH_LATENCY_0
2174 * @arg @ref LL_FLASH_LATENCY_1
2175 * @arg @ref LL_FLASH_LATENCY_2
2176 * @arg @ref LL_FLASH_LATENCY_3
2177 * @arg @ref LL_FLASH_LATENCY_4
2178 * @arg @ref LL_FLASH_LATENCY_5
2179 * @arg @ref LL_FLASH_LATENCY_6
2180 * @arg @ref LL_FLASH_LATENCY_7
2181 */
2182 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
2183 {
2184 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
2185 }
2186
2187 /**
2188 * @}
2189 */
2190
2191 #if defined(DUAL_CORE)
2192 /** @defgroup SYSTEM_LL_EF_ART ART
2193 * @{
2194 */
2195
2196 /**
2197 * @brief Enable the Cortex-M4 ART cache.
2198 * @rmtoll ART_CTR EN LL_ART_Enable
2199 * @retval None
2200 */
2201 __STATIC_INLINE void LL_ART_Enable(void)
2202 {
2203 SET_BIT(ART->CTR, ART_CTR_EN);
2204 }
2205
2206 /**
2207 * @brief Disable the Cortex-M4 ART cache.
2208 * @rmtoll ART_CTR EN LL_ART_Disable
2209 * @retval None
2210 */
2211 __STATIC_INLINE void LL_ART_Disable(void)
2212 {
2213 CLEAR_BIT(ART->CTR, ART_CTR_EN);
2214 }
2215
2216 /**
2217 * @brief Check if the Cortex-M4 ART cache is enabled
2218 * @rmtoll ART_CTR EN LL_ART_IsEnabled
2219 * @retval State of bit (1 or 0).
2220 */
2221 __STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
2222 {
2223 return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
2224 }
2225
2226 /**
2227 * @brief Set the Cortex-M4 ART cache Base Address.
2228 * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress
2229 * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
2230 from which the ART accelerator loads code to the cache.
2231 * @retval None
2232 */
2233 __STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
2234 {
2235 MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
2236 }
2237
2238 /**
2239 * @brief Get the Cortex-M4 ART cache Base Address.
2240 * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress
2241 * @retval the Base address of 1 Mbyte address page (cacheable page)
2242 from which the ART accelerator loads code to the cache
2243 */
2244 __STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
2245 {
2246 return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
2247 }
2248 #endif /* DUAL_CORE */
2249
2250 /**
2251 * @}
2252 */
2253
2254 /**
2255 * @}
2256 */
2257
2258 /**
2259 * @}
2260 */
2261
2262 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
2263
2264 /**
2265 * @}
2266 */
2267
2268 #ifdef __cplusplus
2269 }
2270 #endif
2271
2272 #endif /* __STM32H7xx_LL_SYSTEM_H */
2273
2274 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software