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Merge maintenance-8.x.x fixes into master
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal.c
blobf9fa218213f1541793b323bd6003cea137b863d3
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal.c
4 * @author MCD Application Team
5 * @brief HAL module driver.
6 * This is the common part of the HAL initialization
7 *
8 ******************************************************************************
9 * @attention
10 *
11 * Copyright (c) 2017 STMicroelectronics.
12 * All rights reserved.
13 *
14 * This software is licensed under terms that can be found in the LICENSE file
15 * in the root directory of this software component.
16 * If no LICENSE file comes with this software, it is provided AS-IS.
17 *
18 ******************************************************************************
19 @verbatim
20 ==============================================================================
21 ##### How to use this driver #####
22 ==============================================================================
23 [..]
24 The common HAL driver contains a set of generic and common APIs that can be
25 used by the PPP peripheral drivers and the user to start using the HAL.
26 [..]
27 The HAL contains two APIs' categories:
28 (+) Common HAL APIs
29 (+) Services HAL APIs
30
31 @endverbatim
32 ******************************************************************************
33 */
34
35 /* Includes ------------------------------------------------------------------*/
36 #include "stm32h7xx_hal.h"
37
38 /** @addtogroup STM32H7xx_HAL_Driver
39 * @{
40 */
41
42 /** @defgroup HAL HAL
43 * @brief HAL module driver.
44 * @{
45 */
46
47 /* Private typedef -----------------------------------------------------------*/
48 /* Private define ------------------------------------------------------------*/
49 /**
50 * @brief STM32H7xx HAL Driver version number
51 */
52 #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
53 #define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */
54 #define __STM32H7xx_HAL_VERSION_SUB2 (0x04UL) /*!< [15:8] sub2 version */
55 #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
56 #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
57 |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
58 |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
59 |(__STM32H7xx_HAL_VERSION_RC))
60
61 #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
62 #define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */
63
64 /* Private macro -------------------------------------------------------------*/
65 /* Private variables ---------------------------------------------------------*/
66 /* Exported variables --------------------------------------------------------*/
67
68 /** @defgroup HAL_Exported_Variables HAL Exported Variables
69 * @{
70 */
71 __IO uint32_t uwTick;
72 uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
73 HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
74 /**
75 * @}
76 */
77
78 /* Private function prototypes -----------------------------------------------*/
79 /* Private functions ---------------------------------------------------------*/
80
81 /** @addtogroup HAL_Exported_Functions
82 * @{
83 */
84
85 /** @addtogroup HAL_Group1
86 * @brief Initialization and de-initialization functions
87 *
88 @verbatim
89 ===============================================================================
90 ##### Initialization and de-initialization functions #####
91 ===============================================================================
92 [..] This section provides functions allowing to:
93 (+) Initializes the Flash interface the NVIC allocation and initial clock
94 configuration. It initializes the systick also when timeout is needed
95 and the backup domain when enabled.
96 (+) De-Initializes common part of the HAL.
97 (+) Configure The time base source to have 1ms time base with a dedicated
98 Tick interrupt priority.
99 (++) SysTick timer is used by default as source of time base, but user
100 can eventually implement his proper time base source (a general purpose
101 timer for example or other time source), keeping in mind that Time base
102 duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
103 handled in milliseconds basis.
104 (++) Time base configuration function (HAL_InitTick ()) is called automatically
105 at the beginning of the program after reset by HAL_Init() or at any time
106 when clock is configured, by HAL_RCC_ClockConfig().
107 (++) Source of time base is configured to generate interrupts at regular
108 time intervals. Care must be taken if HAL_Delay() is called from a
109 peripheral ISR process, the Tick interrupt line must have higher priority
110 (numerically lower) than the peripheral interrupt. Otherwise the caller
111 ISR process will be blocked.
112 (++) functions affecting time base configurations are declared as __weak
113 to make override possible in case of other implementations in user file.
114 @endverbatim
115 * @{
116 */
117
118 /**
119 * @brief This function is used to initialize the HAL Library; it must be the first
120 * instruction to be executed in the main program (before to call any other
121 * HAL function), it performs the following:
122 * Configures the SysTick to generate an interrupt each 1 millisecond,
123 * which is clocked by the HSI (at this stage, the clock is not yet
124 * configured and thus the system is running from the internal HSI at 16 MHz).
125 * Set NVIC Group Priority to 4.
126 * Calls the HAL_MspInit() callback function defined in user file
127 * "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
128 *
129 * @note SysTick is used as time base for the HAL_Delay() function, the application
130 * need to ensure that the SysTick time base is always set to 1 millisecond
131 * to have correct HAL operation.
132 * @retval HAL status
133 */
134 HAL_StatusTypeDef HAL_Init(void)
135 {
136
137 uint32_t common_system_clock;
138
139 #if defined(DUAL_CORE) && defined(CORE_CM4)
140 /* Configure Cortex-M4 Instruction cache through ART accelerator */
141 __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
142 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
143 __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */
144 #endif /* DUAL_CORE && CORE_CM4 */
145
146 /* Set Interrupt Group Priority */
147 HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
148
149 /* Update the SystemCoreClock global variable */
150 #if defined(RCC_D1CFGR_D1CPRE)
151 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
152 #else
153 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
154 #endif
155
156 /* Update the SystemD2Clock global variable */
157 #if defined(RCC_D1CFGR_HPRE)
158 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
159 #else
160 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
161 #endif
162
163 #if defined(DUAL_CORE) && defined(CORE_CM4)
164 SystemCoreClock = SystemD2Clock;
165 #else
166 SystemCoreClock = common_system_clock;
167 #endif /* DUAL_CORE && CORE_CM4 */
168
169 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
170 if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
171 {
172 return HAL_ERROR;
173 }
174
175 /* Init the low level hardware */
176 HAL_MspInit();
177
178 /* Return function status */
179 return HAL_OK;
180 }
181
182 /**
183 * @brief This function de-Initializes common part of the HAL and stops the systick.
184 * This function is optional.
185 * @retval HAL status
186 */
187 HAL_StatusTypeDef HAL_DeInit(void)
188 {
189 /* Reset of all peripherals */
190 __HAL_RCC_AHB3_FORCE_RESET();
191 __HAL_RCC_AHB3_RELEASE_RESET();
192
193 __HAL_RCC_AHB1_FORCE_RESET();
194 __HAL_RCC_AHB1_RELEASE_RESET();
195
196 __HAL_RCC_AHB2_FORCE_RESET();
197 __HAL_RCC_AHB2_RELEASE_RESET();
198
199 __HAL_RCC_AHB4_FORCE_RESET();
200 __HAL_RCC_AHB4_RELEASE_RESET();
201
202 __HAL_RCC_APB3_FORCE_RESET();
203 __HAL_RCC_APB3_RELEASE_RESET();
204
205 __HAL_RCC_APB1L_FORCE_RESET();
206 __HAL_RCC_APB1L_RELEASE_RESET();
207
208 __HAL_RCC_APB1H_FORCE_RESET();
209 __HAL_RCC_APB1H_RELEASE_RESET();
210
211 __HAL_RCC_APB2_FORCE_RESET();
212 __HAL_RCC_APB2_RELEASE_RESET();
213
214 __HAL_RCC_APB4_FORCE_RESET();
215 __HAL_RCC_APB4_RELEASE_RESET();
216
217 /* De-Init the low level hardware */
218 HAL_MspDeInit();
219
220 /* Return function status */
221 return HAL_OK;
222 }
223
224 /**
225 * @brief Initializes the MSP.
226 * @retval None
227 */
228 __weak void HAL_MspInit(void)
229 {
230 /* NOTE : This function Should not be modified, when the callback is needed,
231 the HAL_MspInit could be implemented in the user file
232 */
233 }
234
235 /**
236 * @brief DeInitializes the MSP.
237 * @retval None
238 */
239 __weak void HAL_MspDeInit(void)
240 {
241 /* NOTE : This function Should not be modified, when the callback is needed,
242 the HAL_MspDeInit could be implemented in the user file
243 */
244 }
245
246 /**
247 * @brief This function configures the source of the time base.
248 * The time source is configured to have 1ms time base with a dedicated
249 * Tick interrupt priority.
250 * @note This function is called automatically at the beginning of program after
251 * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
252 * @note In the default implementation, SysTick timer is the source of time base.
253 * It is used to generate interrupts at regular time intervals.
254 * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
255 * the SysTick interrupt must have higher priority (numerically lower)
256 * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
257 * The function is declared as __weak to be overwritten in case of other
258 * implementation in user file.
259 * @param TickPriority: Tick interrupt priority.
260 * @retval HAL status
261 */
262 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
263 {
264 /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
265 if((uint32_t)uwTickFreq == 0UL)
266 {
267 return HAL_ERROR;
268 }
269
270 /* Configure the SysTick to have interrupt in 1ms time basis*/
271 if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
272 {
273 return HAL_ERROR;
274 }
275
276 /* Configure the SysTick IRQ priority */
277 if (TickPriority < (1UL << __NVIC_PRIO_BITS))
278 {
279 HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
280 uwTickPrio = TickPriority;
281 }
282 else
283 {
284 return HAL_ERROR;
285 }
286
287 /* Return function status */
288 return HAL_OK;
289 }
290
291 /**
292 * @}
293 */
294
295 /** @addtogroup HAL_Group2
296 * @brief HAL Control functions
297 *
298 @verbatim
299 ===============================================================================
300 ##### HAL Control functions #####
301 ===============================================================================
302 [..] This section provides functions allowing to:
303 (+) Provide a tick value in millisecond
304 (+) Provide a blocking delay in millisecond
305 (+) Suspend the time base source interrupt
306 (+) Resume the time base source interrupt
307 (+) Get the HAL API driver version
308 (+) Get the device identifier
309 (+) Get the device revision identifier
310 (+) Enable/Disable Debug module during SLEEP mode
311 (+) Enable/Disable Debug module during STOP mode
312 (+) Enable/Disable Debug module during STANDBY mode
313
314 @endverbatim
315 * @{
316 */
317
318 /**
319 * @brief This function is called to increment a global variable "uwTick"
320 * used as application time base.
321 * @note In the default implementation, this variable is incremented each 1ms
322 * in Systick ISR.
323 * @note This function is declared as __weak to be overwritten in case of other
324 * implementations in user file.
325 * @retval None
326 */
327 __weak void HAL_IncTick(void)
328 {
329 uwTick += (uint32_t)uwTickFreq;
330 }
331
332 /**
333 * @brief Provides a tick value in millisecond.
334 * @note This function is declared as __weak to be overwritten in case of other
335 * implementations in user file.
336 * @retval tick value
337 */
338 __weak uint32_t HAL_GetTick(void)
339 {
340 return uwTick;
341 }
342
343 /**
344 * @brief This function returns a tick priority.
345 * @retval tick priority
346 */
347 uint32_t HAL_GetTickPrio(void)
348 {
349 return uwTickPrio;
350 }
351
352 /**
353 * @brief Set new tick Freq.
354 * @retval Status
355 */
356 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
357 {
358 HAL_StatusTypeDef status = HAL_OK;
359 HAL_TickFreqTypeDef prevTickFreq;
360
361 assert_param(IS_TICKFREQ(Freq));
362
363 if (uwTickFreq != Freq)
364 {
365
366 /* Back up uwTickFreq frequency */
367 prevTickFreq = uwTickFreq;
368
369 /* Update uwTickFreq global variable used by HAL_InitTick() */
370 uwTickFreq = Freq;
371
372 /* Apply the new tick Freq */
373 status = HAL_InitTick(uwTickPrio);
374 if (status != HAL_OK)
375 {
376 /* Restore previous tick frequency */
377 uwTickFreq = prevTickFreq;
378 }
379 }
380
381 return status;
382 }
383
384 /**
385 * @brief Return tick frequency.
386 * @retval Tick frequency.
387 * Value of @ref HAL_TickFreqTypeDef.
388 */
389 HAL_TickFreqTypeDef HAL_GetTickFreq(void)
390 {
391 return uwTickFreq;
392 }
393
394 /**
395 * @brief This function provides minimum delay (in milliseconds) based
396 * on variable incremented.
397 * @note In the default implementation , SysTick timer is the source of time base.
398 * It is used to generate interrupts at regular time intervals where uwTick
399 * is incremented.
400 * @note This function is declared as __weak to be overwritten in case of other
401 * implementations in user file.
402 * @param Delay specifies the delay time length, in milliseconds.
403 * @retval None
404 */
405 __weak void HAL_Delay(uint32_t Delay)
406 {
407 uint32_t tickstart = HAL_GetTick();
408 uint32_t wait = Delay;
409
410 /* Add a freq to guarantee minimum wait */
411 if (wait < HAL_MAX_DELAY)
412 {
413 wait += (uint32_t)(uwTickFreq);
414 }
415
416 while ((HAL_GetTick() - tickstart) < wait)
417 {
418 }
419 }
420
421 /**
422 * @brief Suspend Tick increment.
423 * @note In the default implementation , SysTick timer is the source of time base. It is
424 * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
425 * is called, the SysTick interrupt will be disabled and so Tick increment
426 * is suspended.
427 * @note This function is declared as __weak to be overwritten in case of other
428 * implementations in user file.
429 * @retval None
430 */
431 __weak void HAL_SuspendTick(void)
432 {
433 /* Disable SysTick Interrupt */
434 SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
435 }
436
437 /**
438 * @brief Resume Tick increment.
439 * @note In the default implementation , SysTick timer is the source of time base. It is
440 * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
441 * is called, the SysTick interrupt will be enabled and so Tick increment
442 * is resumed.
443 * @note This function is declared as __weak to be overwritten in case of other
444 * implementations in user file.
445 * @retval None
446 */
447 __weak void HAL_ResumeTick(void)
448 {
449 /* Enable SysTick Interrupt */
450 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
451 }
452
453 /**
454 * @brief Returns the HAL revision
455 * @retval version : 0xXYZR (8bits for each decimal, R for RC)
456 */
457 uint32_t HAL_GetHalVersion(void)
458 {
459 return __STM32H7xx_HAL_VERSION;
460 }
461
462 /**
463 * @brief Returns the device revision identifier.
464 * @retval Device revision identifier
465 */
466 uint32_t HAL_GetREVID(void)
467 {
468 return((DBGMCU->IDCODE) >> 16);
469 }
470
471 /**
472 * @brief Returns the device identifier.
473 * @retval Device identifier
474 */
475 uint32_t HAL_GetDEVID(void)
476 {
477 return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
478 }
479
480 /**
481 * @brief Return the first word of the unique device identifier (UID based on 96 bits)
482 * @retval Device identifier
483 */
484 uint32_t HAL_GetUIDw0(void)
485 {
486 return(READ_REG(*((uint32_t *)UID_BASE)));
487 }
488
489 /**
490 * @brief Return the second word of the unique device identifier (UID based on 96 bits)
491 * @retval Device identifier
492 */
493 uint32_t HAL_GetUIDw1(void)
494 {
495 return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
496 }
497
498 /**
499 * @brief Return the third word of the unique device identifier (UID based on 96 bits)
500 * @retval Device identifier
501 */
502 uint32_t HAL_GetUIDw2(void)
503 {
504 return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
505 }
506
507 /**
508 * @brief Configure the internal voltage reference buffer voltage scale.
509 * @param VoltageScaling specifies the output voltage to achieve
510 * This parameter can be one of the following values:
511 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.5 V.
512 * This requires VDDA equal to or higher than 2.8 V.
513 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.048 V.
514 * This requires VDDA equal to or higher than 2.4 V.
515 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.8 V.
516 * This requires VDDA equal to or higher than 2.1 V.
517 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.5 V.
518 * This requires VDDA equal to or higher than 1.8 V.
519 * @retval None
520 */
521 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
522 {
523 /* Check the parameters */
524 assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
525
526 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
527 }
528
529 /**
530 * @brief Configure the internal voltage reference buffer high impedance mode.
531 * @param Mode specifies the high impedance mode
532 * This parameter can be one of the following values:
533 * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
534 * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
535 * @retval None
536 */
537 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
538 {
539 /* Check the parameters */
540 assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
541
542 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
543 }
544
545 /**
546 * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
547 * @retval None
548 */
549 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
550 {
551 /* Check the parameters */
552 assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
553
554 MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
555 }
556
557 /**
558 * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
559 * @retval HAL_OK/HAL_TIMEOUT
560 */
561 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
562 {
563 uint32_t tickstart;
564
565 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
566
567 /* Get Start Tick*/
568 tickstart = HAL_GetTick();
569
570 /* Wait for VRR bit */
571 while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
572 {
573 if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
574 {
575 return HAL_TIMEOUT;
576 }
577 }
578
579 return HAL_OK;
580 }
581
582 /**
583 * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
584 *
585 * @retval None
586 */
587 void HAL_SYSCFG_DisableVREFBUF(void)
588 {
589 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
590 }
591
592 #if defined(SYSCFG_PMCR_EPIS_SEL)
593 /**
594 * @brief Ethernet PHY Interface Selection either MII or RMII
595 * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface
596 * This parameter can be one of the following values:
597 * @arg SYSCFG_ETH_MII : Select the Media Independent Interface
598 * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
599 * @retval None
600 */
601 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
602 {
603 /* Check the parameter */
604 assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
605
606 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
607 }
608 #endif /* SYSCFG_PMCR_EPIS_SEL */
609
610 /**
611 * @brief Analog Switch control for dual analog pads.
612 * @param SYSCFG_AnalogSwitch: Selects the analog pad
613 * This parameter can be one or a combination of the following values:
614 * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
615 * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch
616 * @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
617 * @arg SYSCFG_SWITCH_PC3: Select PC3 analog switch
618 * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
619 * This parameter can be one or a combination of the following values:
620 * @arg SYSCFG_SWITCH_PA0_OPEN
621 * @arg SYSCFG_SWITCH_PA0_CLOSE
622 * @arg SYSCFG_SWITCH_PA1_OPEN
623 * @arg SYSCFG_SWITCH_PA1_CLOSE
624 * @arg SYSCFG_SWITCH_PC2_OPEN
625 * @arg SYSCFG_SWITCH_PC2_CLOSE
626 * @arg SYSCFG_SWITCH_PC3_OPEN
627 * @arg SYSCFG_SWITCH_PC3_CLOSE
628 * @retval None
629 */
630
631 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
632 {
633 /* Check the parameter */
634 assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
635 assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
636
637 MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
638 }
639
640 #if defined(SYSCFG_PMCR_BOOSTEN)
641 /**
642 * @brief Enables the booster to reduce the total harmonic distortion of the analog
643 * switch when the supply voltage is lower than 2.7 V.
644 * @note Activating the booster allows to guaranty the analog switch AC performance
645 * when the supply voltage is below 2.7 V: in this case, the analog switch
646 * performance is the same on the full voltage range
647 * @retval None
648 */
649 void HAL_SYSCFG_EnableBOOST(void)
650 {
651 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
652 }
653
654 /**
655 * @brief Disables the booster
656 * @note Activating the booster allows to guaranty the analog switch AC performance
657 * when the supply voltage is below 2.7 V: in this case, the analog switch
658 * performance is the same on the full voltage range
659 * @retval None
660 */
661 void HAL_SYSCFG_DisableBOOST(void)
662 {
663 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
664 }
665 #endif /* SYSCFG_PMCR_BOOSTEN */
666
667 #if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0)
668 /**
669 * @brief BootCM7 address 0 configuration
670 * @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
671 * This parameter can be one of the following values:
672 * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
673 * @arg SYSCFG_BOOT_ADDR1: Select the boot address1
674 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
675 * @retval None
676 */
677 void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
678 {
679 /* Check the parameters */
680 assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
681 assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
682 if ( BootRegister == SYSCFG_BOOT_ADDR0 )
683 {
684 /* Configure CM7 BOOT ADD0 */
685 #if defined(DUAL_CORE)
686 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));
687 #else
688 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));
689 #endif /*DUAL_CORE*/
690 }
691 else
692 {
693 /* Configure CM7 BOOT ADD1 */
694 #if defined(DUAL_CORE)
695 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));
696 #else
697 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
698 #endif /*DUAL_CORE*/
699 }
700 }
701 #endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
702
703 #if defined(DUAL_CORE)
704 /**
705 * @brief BootCM4 address 0 configuration
706 * @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
707 * This parameter can be one of the following values:
708 * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
709 * @arg SYSCFG_BOOT_ADDR1: Select the boot address1
710 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1
711 * @retval None
712 */
713 void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
714 {
715 /* Check the parameters */
716 assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
717 assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
718
719 if ( BootRegister == SYSCFG_BOOT_ADDR0 )
720 {
721 /* Configure CM4 BOOT ADD0 */
722 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));
723 }
724
725 else
726 {
727 /* Configure CM4 BOOT ADD1 */
728 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));
729 }
730 }
731
732 /**
733 * @brief Enables the Cortex-M7 boot
734 * @retval None
735 */
736 void HAL_SYSCFG_EnableCM7BOOT(void)
737 {
738 SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);
739 }
740
741 /**
742 * @brief Disables the Cortex-M7 boot
743 * @note Disabling the boot will gate the CPU clock
744 * @retval None
745 */
746 void HAL_SYSCFG_DisableCM7BOOT(void)
747 {
748 CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;
749 }
750
751 /**
752 * @brief Enables the Cortex-M4 boot
753 * @retval None
754 */
755 void HAL_SYSCFG_EnableCM4BOOT(void)
756 {
757 SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
758 }
759
760 /**
761 * @brief Disables the Cortex-M4 boot
762 * @note Disabling the boot will gate the CPU clock
763 * @retval None
764 */
765 void HAL_SYSCFG_DisableCM4BOOT(void)
766 {
767 CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
768 }
769 #endif /*DUAL_CORE*/
770 /**
771 * @brief Enables the I/O Compensation Cell.
772 * @note The I/O compensation cell can be used only when the device supply
773 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
774 * @retval None
775 */
776 void HAL_EnableCompensationCell(void)
777 {
778 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
779 }
780
781 /**
782 * @brief Power-down the I/O Compensation Cell.
783 * @note The I/O compensation cell can be used only when the device supply
784 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
785 * @retval None
786 */
787 void HAL_DisableCompensationCell(void)
788 {
789 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
790 }
791
792
793 /**
794 * @brief To Enable optimize the I/O speed when the product voltage is low.
795 * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
796 * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
797 * higher than 2.5 V might be destructive.
798 * @retval None
799 */
800 void HAL_SYSCFG_EnableIOSpeedOptimize(void)
801 {
802 #if defined(SYSCFG_CCCSR_HSLV)
803 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
804 #else
805 SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
806 #endif /* SYSCFG_CCCSR_HSLV */
807 }
808
809 /**
810 * @brief To Disable optimize the I/O speed when the product voltage is low.
811 * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
812 * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
813 * higher than 2.5 V might be destructive.
814 * @retval None
815 */
816 void HAL_SYSCFG_DisableIOSpeedOptimize(void)
817 {
818 #if defined(SYSCFG_CCCSR_HSLV)
819 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
820 #else
821 CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
822 #endif /* SYSCFG_CCCSR_HSLV */
823 }
824
825 /**
826 * @brief Code selection for the I/O Compensation cell
827 * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
828 * This parameter can be one of the following values:
829 * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
830 * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
831 * @retval None
832 */
833 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
834 {
835 /* Check the parameter */
836 assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
837 MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
838 }
839
840 /**
841 * @brief Code selection for the I/O Compensation cell
842 * @param SYSCFG_PMOSCode: PMOS compensation code
843 * This code is applied to the I/O compensation cell when the CS bit of the
844 * SYSCFG_CMPCR is set
845 * @param SYSCFG_NMOSCode: NMOS compensation code
846 * This code is applied to the I/O compensation cell when the CS bit of the
847 * SYSCFG_CMPCR is set
848 * @retval None
849 */
850 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
851 {
852 /* Check the parameter */
853 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
854 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
855 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
856 }
857
858 #if defined(SYSCFG_CCCR_NCC_MMC)
859 /**
860 * @brief Code selection for the I/O Compensation cell
861 * @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code
862 * This code is applied to the I/O compensation cell when the CS bit of the
863 * SYSCFG_CMPCR is set
864 * @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code
865 * This code is applied to the I/O compensation cell when the CS bit of the
866 * SYSCFG_CMPCR is set
867 * @retval None
868 */
869 void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
870 {
871 /* Check the parameter */
872 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
873 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
874 MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
875 }
876 #endif /* SYSCFG_CCCR_NCC_MMC */
877
878 #if defined(SYSCFG_ADC2ALT_ADC2_ROUT0)
879 /** @brief SYSCFG ADC2 internal input alternate connection macros
880 * @param Adc2AltRout0 This parameter can be a value of :
881 * @arg @ref SYSCFG_ADC2_ROUT0_DAC1_1 DAC1_out1 connected to ADC2 VINP[16]
882 * @arg @ref SYSCFG_ADC2_ROUT0_VBAT4 VBAT/4 connected to ADC2 VINP[16]
883 */
884 void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0)
885 {
886 /* Check the parameters */
887 assert_param(IS_SYSCFG_ADC2ALT_ROUT0(Adc2AltRout0));
888
889 MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0);
890 }
891 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/
892
893 #if defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
894 /** @brief SYSCFG ADC2 internal input alternate connection macros
895 * @param Adc2AltRout1 This parameter can be a value of :
896 * @arg @ref SYSCFG_ADC2_ROUT1_DAC1_2 DAC1_out2 connected to ADC2 VINP[17]
897 * @arg @ref SYSCFG_ADC2_ROUT1_VREFINT VREFINT connected to ADC2 VINP[17]
898 */
899 void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1)
900 {
901 /* Check the parameters */
902 assert_param(IS_SYSCFG_ADC2ALT_ROUT1(Adc2AltRout1));
903
904 MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1);
905 }
906 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
907
908 /**
909 * @brief Enable the Debug Module during Domain1/CDomain SLEEP mode
910 * @retval None
911 */
912 void HAL_DBGMCU_EnableDBGSleepMode(void)
913 {
914 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
915 }
916
917 /**
918 * @brief Disable the Debug Module during Domain1/CDomain SLEEP mode
919 * @retval None
920 */
921 void HAL_DBGMCU_DisableDBGSleepMode(void)
922 {
923 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
924 }
925
926
927 /**
928 * @brief Enable the Debug Module during Domain1/CDomain STOP mode
929 * @retval None
930 */
931 void HAL_DBGMCU_EnableDBGStopMode(void)
932 {
933 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
934 }
935
936 /**
937 * @brief Disable the Debug Module during Domain1/CDomain STOP mode
938 * @retval None
939 */
940 void HAL_DBGMCU_DisableDBGStopMode(void)
941 {
942 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
943 }
944
945 /**
946 * @brief Enable the Debug Module during Domain1/CDomain STANDBY mode
947 * @retval None
948 */
949 void HAL_DBGMCU_EnableDBGStandbyMode(void)
950 {
951 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
952 }
953
954 /**
955 * @brief Disable the Debug Module during Domain1/CDomain STANDBY mode
956 * @retval None
957 */
958 void HAL_DBGMCU_DisableDBGStandbyMode(void)
959 {
960 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
961 }
962
963 #if defined(DUAL_CORE)
964 /**
965 * @brief Enable the Debug Module during Domain1 SLEEP mode
966 * @retval None
967 */
968 void HAL_EnableDomain2DBGSleepMode(void)
969 {
970 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
971 }
972
973 /**
974 * @brief Disable the Debug Module during Domain2 SLEEP mode
975 * @retval None
976 */
977 void HAL_DisableDomain2DBGSleepMode(void)
978 {
979 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
980 }
981
982 /**
983 * @brief Enable the Debug Module during Domain2 STOP mode
984 * @retval None
985 */
986 void HAL_EnableDomain2DBGStopMode(void)
987 {
988 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
989 }
990
991 /**
992 * @brief Disable the Debug Module during Domain2 STOP mode
993 * @retval None
994 */
995 void HAL_DisableDomain2DBGStopMode(void)
996 {
997 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
998 }
999
1000 /**
1001 * @brief Enable the Debug Module during Domain2 STANDBY mode
1002 * @retval None
1003 */
1004 void HAL_EnableDomain2DBGStandbyMode(void)
1005 {
1006 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1007 }
1008
1009 /**
1010 * @brief Disable the Debug Module during Domain2 STANDBY mode
1011 * @retval None
1012 */
1013 void HAL_DisableDomain2DBGStandbyMode(void)
1014 {
1015 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1016 }
1017 #endif /*DUAL_CORE*/
1018
1019 #if defined(DBGMCU_CR_DBG_STOPD3)
1020 /**
1021 * @brief Enable the Debug Module during Domain3/SRDomain STOP mode
1022 * @retval None
1023 */
1024 void HAL_EnableDomain3DBGStopMode(void)
1025 {
1026 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1027 }
1028
1029 /**
1030 * @brief Disable the Debug Module during Domain3/SRDomain STOP mode
1031 * @retval None
1032 */
1033 void HAL_DisableDomain3DBGStopMode(void)
1034 {
1035 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1036 }
1037 #endif /*DBGMCU_CR_DBG_STOPD3*/
1038
1039 #if defined(DBGMCU_CR_DBG_STANDBYD3)
1040 /**
1041 * @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode
1042 * @retval None
1043 */
1044 void HAL_EnableDomain3DBGStandbyMode(void)
1045 {
1046 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1047 }
1048
1049 /**
1050 * @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode
1051 * @retval None
1052 */
1053 void HAL_DisableDomain3DBGStandbyMode(void)
1054 {
1055 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1056 }
1057 #endif /*DBGMCU_CR_DBG_STANDBYD3*/
1058
1059 /**
1060 * @brief Set the FMC Memory Mapping Swapping config.
1061 * @param BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
1062 FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
1063 * @retval HAL state
1064 */
1065 void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
1066 {
1067 /* Check the parameter */
1068 assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
1069 MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
1070 }
1071
1072 /**
1073 * @brief Get FMC Bank mapping mode.
1074 * @retval The FMC Bank mapping mode. This parameter can be
1075 FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
1076 */
1077 uint32_t HAL_GetFMCMemorySwappingConfig(void)
1078 {
1079 return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP);
1080 }
1081
1082 /**
1083 * @brief Configure the EXTI input event line edge
1084 * @note No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
1085 * EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
1086 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1087 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1088 * @param EXTI_Edge: Specifies EXTI line Edge used.
1089 * This parameter can be one of the following values :
1090 * @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
1091 * @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
1092 * @retval None
1093 */
1094 void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
1095 {
1096 /* Check the parameter */
1097 assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
1098 assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
1099
1100 /* Clear Rising Falling edge configuration */
1101 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1102 CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1103
1104 if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
1105 {
1106 SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1107 }
1108 if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
1109 {
1110 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1111 }
1112 }
1113
1114 /**
1115 * @brief Generates a Software interrupt on selected EXTI line.
1116 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1117 * (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
1118 * @retval None
1119 */
1120 void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
1121 {
1122 /* Check the parameters */
1123 assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
1124
1125 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1126 }
1127
1128
1129 /**
1130 * @brief Clears the EXTI's line pending flags for Domain D1
1131 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1132 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1133 * @retval None
1134 */
1135 void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
1136 {
1137 /* Check the parameters */
1138 assert_param(IS_EXTI_D1_LINE(EXTI_Line));
1139 WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1140
1141 }
1142
1143 #if defined(DUAL_CORE)
1144 /**
1145 * @brief Clears the EXTI's line pending flags for Domain D2
1146 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1147 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1148 * @retval None
1149 */
1150 void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
1151 {
1152 /* Check the parameters */
1153 assert_param(IS_EXTI_D2_LINE(EXTI_Line));
1154 WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1155 }
1156
1157 #endif /*DUAL_CORE*/
1158 /**
1159 * @brief Configure the EXTI input event line for Domain D1
1160 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1161 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1162 * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
1163 * This parameter can be one or a combination of the following values :
1164 * @arg EXTI_MODE_IT : Interrupt Mode selected
1165 * @arg EXTI_MODE_EVT : Event Mode selected
1166 * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
1167
1168 * @retval None
1169 */
1170 void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )
1171 {
1172 /* Check the parameter */
1173 assert_param(IS_EXTI_D1_LINE(EXTI_Line));
1174 assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
1175
1176 if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
1177 {
1178 if( EXTI_LineCmd == 0UL)
1179 {
1180 /* Clear EXTI line configuration */
1181 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
1182 }
1183 else
1184 {
1185 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1186 }
1187 }
1188
1189 if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
1190 {
1191 if( EXTI_LineCmd == 0UL)
1192 {
1193 /* Clear EXTI line configuration */
1194 CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1195 }
1196 else
1197 {
1198 SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1199 }
1200 }
1201 }
1202
1203 #if defined(DUAL_CORE)
1204 /**
1205 * @brief Configure the EXTI input event line for Domain D2
1206 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1207 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1208 * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
1209 * This parameter can be one or a combination of the following values :
1210 * @arg EXTI_MODE_IT : Interrupt Mode selected
1211 * @arg EXTI_MODE_EVT : Event Mode selected
1212 * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
1213
1214 * @retval None
1215 */
1216 void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )
1217 {
1218 /* Check the parameter */
1219 assert_param(IS_EXTI_D2_LINE(EXTI_Line));
1220 assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
1221
1222 if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
1223 {
1224 if( EXTI_LineCmd == 0UL)
1225 {
1226 /* Clear EXTI line configuration */
1227 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
1228 }
1229 else
1230 {
1231 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1232 }
1233 }
1234
1235 if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
1236 {
1237 if( EXTI_LineCmd == 0UL)
1238 {
1239 /* Clear EXTI line configuration */
1240 CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1241 }
1242 else
1243 {
1244 SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1245 }
1246 }
1247 }
1248 #endif /*DUAL_CORE*/
1249
1250 /**
1251 * @brief Configure the EXTI input event line for Domain D3
1252 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1253 * (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
1254 * EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
1255 * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
1256 * @param EXTI_ClearSrc: Specifies the clear source of D3 pending event.
1257 * This parameter can be one of the following values :
1258 * @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
1259 * @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
1260 * @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
1261 * @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
1262 * @retval None
1263 */
1264 void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc )
1265 {
1266 __IO uint32_t *pRegv;
1267
1268 /* Check the parameter */
1269 assert_param(IS_EXTI_D3_LINE(EXTI_Line));
1270 assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
1271
1272 if( EXTI_LineCmd == 0UL)
1273 {
1274 /* Clear EXTI line configuration */
1275 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
1276 }
1277 else
1278 {
1279 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1280 }
1281
1282 if(((EXTI_Line>>4)%2UL) == 0UL)
1283 {
1284 pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL));
1285 }
1286 else
1287 {
1288 pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL));
1289 }
1290 MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL)));
1291
1292 }
1293
1294
1295
1296 /**
1297 * @}
1298 */
1299
1300 /**
1301 * @}
1302 */
1303
1304 /**
1305 * @}
1306 */
1307
1308 /**
1309 * @}
1310 */
1311
1312
INAV: Navigation-enabled flight control software