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Merge maintenance-8.x.x fixes into master
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_eth.c
blobb9e26fa7b763a1eb042acdcfc9c82846236b1de8
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_eth.c
4 * @author MCD Application Team
5 * @brief ETH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Ethernet (ETH) peripheral:
8 * + Initialization and deinitialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2017 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### How to use this driver #####
27 ==============================================================================
28 [..]
29 The ETH HAL driver can be used as follows:
30
31 (#)Declare a ETH_HandleTypeDef handle structure, for example:
32 ETH_HandleTypeDef heth;
33
34 (#)Fill parameters of Init structure in heth handle
35
36 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
37
38 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
39 (##) Enable the Ethernet interface clock using
40 (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE()
41 (+++) __HAL_RCC_ETH1TX_CLK_ENABLE()
42 (+++) __HAL_RCC_ETH1RX_CLK_ENABLE()
43
44 (##) Initialize the related GPIO clocks
45 (##) Configure Ethernet pinout
46 (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
47
48 (#) Ethernet data reception is asynchronous, so call the following API
49 to start the listening mode:
50 (##) HAL_ETH_Start():
51 This API starts the MAC and DMA transmission and reception process,
52 without enabling end of transfer interrupts, in this mode user
53 has to poll for data reception by calling HAL_ETH_ReadData()
54 (##) HAL_ETH_Start_IT():
55 This API starts the MAC and DMA transmission and reception process,
56 end of transfer interrupts are enabled in this mode,
57 HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
58
59 (#) When data is received user can call the following API to get received data:
60 (##) HAL_ETH_ReadData(): Read a received packet
61
62 (#) For transmission path, two APIs are available:
63 (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
64 (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
65 HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
66
67 (#) Communication with an external PHY device:
68 (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
69 (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
70
71 (#) Configure the Ethernet MAC after ETH peripheral initialization
72 (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
73 (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
74
75 (#) Configure the Ethernet DMA after ETH peripheral initialization
76 (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
77 (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
78
79 (#) Configure the Ethernet PTP after ETH peripheral initialization
80 (##) Define HAL_ETH_USE_PTP to use PTP APIs.
81 (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef
82 (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef
83 (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers
84 (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers
85 (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers
86 (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission
87 (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp
88 (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp
89
90 -@- The ARP offload feature is not supported in this driver.
91
92 -@- The PTP offload feature is not supported in this driver.
93
94 *** Callback registration ***
95 =============================================
96
97 The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
98 allows the user to configure dynamically the driver callbacks.
99 Use Function HAL_ETH_RegisterCallback() to register an interrupt callback.
100
101 Function HAL_ETH_RegisterCallback() allows to register following callbacks:
102 (+) TxCpltCallback : Tx Complete Callback.
103 (+) RxCpltCallback : Rx Complete Callback.
104 (+) ErrorCallback : Error Callback.
105 (+) PMTCallback : Power Management Callback
106 (+) EEECallback : EEE Callback.
107 (+) WakeUpCallback : Wake UP Callback
108 (+) MspInitCallback : MspInit Callback.
109 (+) MspDeInitCallback: MspDeInit Callback.
110
111 This function takes as parameters the HAL peripheral handle, the Callback ID
112 and a pointer to the user callback function.
113
114 For specific callbacks RxAllocateCallback use dedicated register callbacks:
115 respectively HAL_ETH_RegisterRxAllocateCallback().
116
117 For specific callbacks RxLinkCallback use dedicated register callbacks:
118 respectively HAL_ETH_RegisterRxLinkCallback().
119
120 For specific callbacks TxFreeCallback use dedicated register callbacks:
121 respectively HAL_ETH_RegisterTxFreeCallback().
122
123 For specific callbacks TxPtpCallback use dedicated register callbacks:
124 respectively HAL_ETH_RegisterTxPtpCallback().
125
126 Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default
127 weak function.
128 HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
129 and the Callback ID.
130 This function allows to reset following callbacks:
131 (+) TxCpltCallback : Tx Complete Callback.
132 (+) RxCpltCallback : Rx Complete Callback.
133 (+) ErrorCallback : Error Callback.
134 (+) PMTCallback : Power Management Callback
135 (+) EEECallback : EEE Callback.
136 (+) WakeUpCallback : Wake UP Callback
137 (+) MspInitCallback : MspInit Callback.
138 (+) MspDeInitCallback: MspDeInit Callback.
139
140 For specific callbacks RxAllocateCallback use dedicated unregister callbacks:
141 respectively HAL_ETH_UnRegisterRxAllocateCallback().
142
143 For specific callbacks RxLinkCallback use dedicated unregister callbacks:
144 respectively HAL_ETH_UnRegisterRxLinkCallback().
145
146 For specific callbacks TxFreeCallback use dedicated unregister callbacks:
147 respectively HAL_ETH_UnRegisterTxFreeCallback().
148
149 For specific callbacks TxPtpCallback use dedicated unregister callbacks:
150 respectively HAL_ETH_UnRegisterTxPtpCallback().
151
152 By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
153 all callbacks are set to the corresponding weak functions:
154 examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback().
155 Exception done for MspInit and MspDeInit functions that are
156 reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when
157 these callbacks are null (not registered beforehand).
158 if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit
159 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
160
161 Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
162 Exception done MspInit/MspDeInit that can be registered/unregistered
163 in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
164 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
165 In that case first register the MspInit/MspDeInit user callbacks
166 using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit
167 or HAL_ETH_Init function.
168
169 When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
170 not defined, the callback registration feature is not available and all callbacks
171 are set to the corresponding weak functions.
172
173 @endverbatim
174 ******************************************************************************
175 */
176
177 /* Includes ------------------------------------------------------------------*/
178 #include "stm32h7xx_hal.h"
179
180 /** @addtogroup STM32H7xx_HAL_Driver
181 * @{
182 */
183 #ifdef HAL_ETH_MODULE_ENABLED
184
185 #if defined(ETH)
186
187 /** @defgroup ETH ETH
188 * @brief ETH HAL module driver
189 * @{
190 */
191
192 /* Private typedef -----------------------------------------------------------*/
193 /* Private define ------------------------------------------------------------*/
194 /** @addtogroup ETH_Private_Constants ETH Private Constants
195 * @{
196 */
197 #define ETH_MACCR_MASK 0xFFFB7F7CU
198 #define ETH_MACECR_MASK 0x3F077FFFU
199 #define ETH_MACPFR_MASK 0x800007FFU
200 #define ETH_MACWTR_MASK 0x0000010FU
201 #define ETH_MACTFCR_MASK 0xFFFF00F2U
202 #define ETH_MACRFCR_MASK 0x00000003U
203 #define ETH_MTLTQOMR_MASK 0x00000072U
204 #define ETH_MTLRQOMR_MASK 0x0000007BU
205
206 #define ETH_DMAMR_MASK 0x00007802U
207 #define ETH_DMASBMR_MASK 0x0000D001U
208 #define ETH_DMACCR_MASK 0x00013FFFU
209 #define ETH_DMACTCR_MASK 0x003F1010U
210 #define ETH_DMACRCR_MASK 0x803F0000U
211 #define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
212 ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
213 ETH_MACPCSR_RWKPFE)
214
215 /* Timeout values */
216 #define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
217 ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
218 ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
219
220 #define ETH_MACTSCR_MASK 0x0087FF2FU
221
222 #define ETH_MACSTSUR_VALUE 0xFFFFFFFFU
223 #define ETH_MACSTNUR_VALUE 0xBB9ACA00U
224 #define ETH_SEGMENT_SIZE_DEFAULT 0x218U
225 /**
226 * @}
227 */
228
229 /* Private macros ------------------------------------------------------------*/
230 /** @defgroup ETH_Private_Macros ETH Private Macros
231 * @{
232 */
233 /* Helper macros for TX descriptor handling */
234 #define INCR_TX_DESC_INDEX(inx, offset) do {\
235 (inx) += (offset);\
236 if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
237 (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
238 } while (0)
239
240 /* Helper macros for RX descriptor handling */
241 #define INCR_RX_DESC_INDEX(inx, offset) do {\
242 (inx) += (offset);\
243 if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
244 (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
245 } while (0)
246 /**
247 * @}
248 */
249 /* Private function prototypes -----------------------------------------------*/
250 /** @defgroup ETH_Private_Functions ETH Private Functions
251 * @{
252 */
253 static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf);
254 static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf);
255 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
256 static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
257 static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
258 static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
259 uint32_t ItMode);
260 static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth);
261
262 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
263 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
264 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
265 /**
266 * @}
267 */
268
269 /* Exported functions ---------------------------------------------------------*/
270 /** @defgroup ETH_Exported_Functions ETH Exported Functions
271 * @{
272 */
273
274 /** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
275 * @brief Initialization and Configuration functions
276 *
277 @verbatim
278 ===============================================================================
279 ##### Initialization and Configuration functions #####
280 ===============================================================================
281 [..] This subsection provides a set of functions allowing to initialize and
282 deinitialize the ETH peripheral:
283
284 (+) User must Implement HAL_ETH_MspInit() function in which he configures
285 all related peripherals resources (CLOCK, GPIO and NVIC ).
286
287 (+) Call the function HAL_ETH_Init() to configure the selected device with
288 the selected configuration:
289 (++) MAC address
290 (++) Media interface (MII or RMII)
291 (++) Rx DMA Descriptors Tab
292 (++) Tx DMA Descriptors Tab
293 (++) Length of Rx Buffers
294
295 (+) Call the function HAL_ETH_DeInit() to restore the default configuration
296 of the selected ETH peripheral.
297
298 @endverbatim
299 * @{
300 */
301
302 /**
303 * @brief Initialize the Ethernet peripheral registers.
304 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
305 * the configuration information for ETHERNET module
306 * @retval HAL status
307 */
308 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
309 {
310 uint32_t tickstart;
311
312 if (heth == NULL)
313 {
314 return HAL_ERROR;
315 }
316 if (heth->gState == HAL_ETH_STATE_RESET)
317 {
318 heth->gState = HAL_ETH_STATE_BUSY;
319
320 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
321
322 ETH_InitCallbacksToDefault(heth);
323
324 if (heth->MspInitCallback == NULL)
325 {
326 heth->MspInitCallback = HAL_ETH_MspInit;
327 }
328
329 /* Init the low level hardware */
330 heth->MspInitCallback(heth);
331 #else
332 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
333 HAL_ETH_MspInit(heth);
334
335 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
336 }
337
338 __HAL_RCC_SYSCFG_CLK_ENABLE();
339
340 if (heth->Init.MediaInterface == HAL_ETH_MII_MODE)
341 {
342 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
343 }
344 else
345 {
346 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
347 }
348
349 /* Dummy read to sync with ETH */
350 (void)SYSCFG->PMCR;
351
352 /* Ethernet Software reset */
353 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
354 /* After reset all the registers holds their respective reset values */
355 SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
356
357 /* Get tick */
358 tickstart = HAL_GetTick();
359
360 /* Wait for software reset */
361 while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
362 {
363 if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
364 {
365 /* Set Error Code */
366 heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
367 /* Set State as Error */
368 heth->gState = HAL_ETH_STATE_ERROR;
369 /* Return Error */
370 return HAL_ERROR;
371 }
372 }
373
374 /*------------------ MDIO CSR Clock Range Configuration --------------------*/
375 HAL_ETH_SetMDIOClockRange(heth);
376
377 /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
378 WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
379
380 /*------------------ MAC, MTL and DMA default Configuration ----------------*/
381 ETH_MACDMAConfig(heth);
382
383 /* SET DSL to 64 bit */
384 MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
385
386 /* Set Receive Buffers Length (must be a multiple of 4) */
387 if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
388 {
389 /* Set Error Code */
390 heth->ErrorCode = HAL_ETH_ERROR_PARAM;
391 /* Set State as Error */
392 heth->gState = HAL_ETH_STATE_ERROR;
393 /* Return Error */
394 return HAL_ERROR;
395 }
396 else
397 {
398 MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
399 }
400
401 /*------------------ DMA Tx Descriptors Configuration ----------------------*/
402 ETH_DMATxDescListInit(heth);
403
404 /*------------------ DMA Rx Descriptors Configuration ----------------------*/
405 ETH_DMARxDescListInit(heth);
406
407 /*--------------------- ETHERNET MAC Address Configuration ------------------*/
408 /* Set MAC addr bits 32 to 47 */
409 heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
410 /* Set MAC addr bits 0 to 31 */
411 heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
412 ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
413
414 /* Disable Rx MMC Interrupts */
415 SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
416 ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
417
418 /* Disable Tx MMC Interrupts */
419 SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
420 ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
421
422 heth->ErrorCode = HAL_ETH_ERROR_NONE;
423 heth->gState = HAL_ETH_STATE_READY;
424
425 return HAL_OK;
426 }
427
428 /**
429 * @brief DeInitializes the ETH peripheral.
430 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
431 * the configuration information for ETHERNET module
432 * @retval HAL status
433 */
434 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
435 {
436 /* Set the ETH peripheral state to BUSY */
437 heth->gState = HAL_ETH_STATE_BUSY;
438
439 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
440
441 if (heth->MspDeInitCallback == NULL)
442 {
443 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
444 }
445 /* DeInit the low level hardware */
446 heth->MspDeInitCallback(heth);
447 #else
448
449 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
450 HAL_ETH_MspDeInit(heth);
451
452 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
453
454 /* Set ETH HAL state to Disabled */
455 heth->gState = HAL_ETH_STATE_RESET;
456
457 /* Return function status */
458 return HAL_OK;
459 }
460
461 /**
462 * @brief Initializes the ETH MSP.
463 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
464 * the configuration information for ETHERNET module
465 * @retval None
466 */
467 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
468 {
469 /* Prevent unused argument(s) compilation warning */
470 UNUSED(heth);
471 /* NOTE : This function Should not be modified, when the callback is needed,
472 the HAL_ETH_MspInit could be implemented in the user file
473 */
474 }
475
476 /**
477 * @brief DeInitializes ETH MSP.
478 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
479 * the configuration information for ETHERNET module
480 * @retval None
481 */
482 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
483 {
484 /* Prevent unused argument(s) compilation warning */
485 UNUSED(heth);
486 /* NOTE : This function Should not be modified, when the callback is needed,
487 the HAL_ETH_MspDeInit could be implemented in the user file
488 */
489 }
490
491 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
492 /**
493 * @brief Register a User ETH Callback
494 * To be used instead of the weak predefined callback
495 * @param heth eth handle
496 * @param CallbackID ID of the callback to be registered
497 * This parameter can be one of the following values:
498 * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
499 * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
500 * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID
501 * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
502 * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
503 * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
504 * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
505 * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
506 * @param pCallback pointer to the Callback function
507 * @retval status
508 */
509 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
510 pETH_CallbackTypeDef pCallback)
511 {
512 HAL_StatusTypeDef status = HAL_OK;
513
514 if (pCallback == NULL)
515 {
516 /* Update the error code */
517 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
518 return HAL_ERROR;
519 }
520
521 if (heth->gState == HAL_ETH_STATE_READY)
522 {
523 switch (CallbackID)
524 {
525 case HAL_ETH_TX_COMPLETE_CB_ID :
526 heth->TxCpltCallback = pCallback;
527 break;
528
529 case HAL_ETH_RX_COMPLETE_CB_ID :
530 heth->RxCpltCallback = pCallback;
531 break;
532
533 case HAL_ETH_ERROR_CB_ID :
534 heth->ErrorCallback = pCallback;
535 break;
536
537 case HAL_ETH_PMT_CB_ID :
538 heth->PMTCallback = pCallback;
539 break;
540
541 case HAL_ETH_EEE_CB_ID :
542 heth->EEECallback = pCallback;
543 break;
544
545 case HAL_ETH_WAKEUP_CB_ID :
546 heth->WakeUpCallback = pCallback;
547 break;
548
549 case HAL_ETH_MSPINIT_CB_ID :
550 heth->MspInitCallback = pCallback;
551 break;
552
553 case HAL_ETH_MSPDEINIT_CB_ID :
554 heth->MspDeInitCallback = pCallback;
555 break;
556
557 default :
558 /* Update the error code */
559 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
560 /* Return error status */
561 status = HAL_ERROR;
562 break;
563 }
564 }
565 else if (heth->gState == HAL_ETH_STATE_RESET)
566 {
567 switch (CallbackID)
568 {
569 case HAL_ETH_MSPINIT_CB_ID :
570 heth->MspInitCallback = pCallback;
571 break;
572
573 case HAL_ETH_MSPDEINIT_CB_ID :
574 heth->MspDeInitCallback = pCallback;
575 break;
576
577 default :
578 /* Update the error code */
579 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
580 /* Return error status */
581 status = HAL_ERROR;
582 break;
583 }
584 }
585 else
586 {
587 /* Update the error code */
588 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
589 /* Return error status */
590 status = HAL_ERROR;
591 }
592
593 return status;
594 }
595
596 /**
597 * @brief Unregister an ETH Callback
598 * ETH callback is redirected to the weak predefined callback
599 * @param heth eth handle
600 * @param CallbackID ID of the callback to be unregistered
601 * This parameter can be one of the following values:
602 * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
603 * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
604 * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID
605 * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
606 * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
607 * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
608 * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
609 * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
610 * @retval status
611 */
612 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
613 {
614 HAL_StatusTypeDef status = HAL_OK;
615
616 if (heth->gState == HAL_ETH_STATE_READY)
617 {
618 switch (CallbackID)
619 {
620 case HAL_ETH_TX_COMPLETE_CB_ID :
621 heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
622 break;
623
624 case HAL_ETH_RX_COMPLETE_CB_ID :
625 heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
626 break;
627
628 case HAL_ETH_ERROR_CB_ID :
629 heth->ErrorCallback = HAL_ETH_ErrorCallback;
630 break;
631
632 case HAL_ETH_PMT_CB_ID :
633 heth->PMTCallback = HAL_ETH_PMTCallback;
634 break;
635
636 case HAL_ETH_EEE_CB_ID :
637 heth->EEECallback = HAL_ETH_EEECallback;
638 break;
639
640 case HAL_ETH_WAKEUP_CB_ID :
641 heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
642 break;
643
644 case HAL_ETH_MSPINIT_CB_ID :
645 heth->MspInitCallback = HAL_ETH_MspInit;
646 break;
647
648 case HAL_ETH_MSPDEINIT_CB_ID :
649 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
650 break;
651
652 default :
653 /* Update the error code */
654 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
655 /* Return error status */
656 status = HAL_ERROR;
657 break;
658 }
659 }
660 else if (heth->gState == HAL_ETH_STATE_RESET)
661 {
662 switch (CallbackID)
663 {
664 case HAL_ETH_MSPINIT_CB_ID :
665 heth->MspInitCallback = HAL_ETH_MspInit;
666 break;
667
668 case HAL_ETH_MSPDEINIT_CB_ID :
669 heth->MspDeInitCallback = HAL_ETH_MspDeInit;
670 break;
671
672 default :
673 /* Update the error code */
674 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
675 /* Return error status */
676 status = HAL_ERROR;
677 break;
678 }
679 }
680 else
681 {
682 /* Update the error code */
683 heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
684 /* Return error status */
685 status = HAL_ERROR;
686 }
687
688 return status;
689 }
690 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
691
692 /**
693 * @}
694 */
695
696 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
697 * @brief ETH Transmit and Receive functions
698 *
699 @verbatim
700 ==============================================================================
701 ##### IO operation functions #####
702 ==============================================================================
703 [..]
704 This subsection provides a set of functions allowing to manage the ETH
705 data transfer.
706
707 @endverbatim
708 * @{
709 */
710
711 /**
712 * @brief Enables Ethernet MAC and DMA reception and transmission
713 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
714 * the configuration information for ETHERNET module
715 * @retval HAL status
716 */
717 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
718 {
719 if (heth->gState == HAL_ETH_STATE_READY)
720 {
721 heth->gState = HAL_ETH_STATE_BUSY;
722
723 /* Set number of descriptors to build */
724 heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
725
726 /* Build all descriptors */
727 ETH_UpdateDescriptor(heth);
728
729 /* Enable the MAC transmission */
730 SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
731
732 /* Enable the MAC reception */
733 SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
734
735 /* Set the Flush Transmit FIFO bit */
736 SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
737
738 /* Enable the DMA transmission */
739 SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
740
741 /* Enable the DMA reception */
742 SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
743
744 /* Clear Tx and Rx process stopped flags */
745 heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
746
747 heth->gState = HAL_ETH_STATE_STARTED;
748
749 return HAL_OK;
750 }
751 else
752 {
753 return HAL_ERROR;
754 }
755 }
756
757 /**
758 * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
759 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
760 * the configuration information for ETHERNET module
761 * @retval HAL status
762 */
763 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
764 {
765 if (heth->gState == HAL_ETH_STATE_READY)
766 {
767 heth->gState = HAL_ETH_STATE_BUSY;
768
769 /* save IT mode to ETH Handle */
770 heth->RxDescList.ItMode = 1U;
771
772 /* Set number of descriptors to build */
773 heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
774
775 /* Build all descriptors */
776 ETH_UpdateDescriptor(heth);
777
778 /* Enable the DMA transmission */
779 SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
780
781 /* Enable the DMA reception */
782 SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
783
784 /* Clear Tx and Rx process stopped flags */
785 heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
786
787 /* Set the Flush Transmit FIFO bit */
788 SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
789
790 /* Enable the MAC transmission */
791 SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
792
793 /* Enable the MAC reception */
794 SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
795
796 /* Enable ETH DMA interrupts:
797 - Tx complete interrupt
798 - Rx complete interrupt
799 - Fatal bus interrupt
800 */
801 __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
802 ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE));
803
804 heth->gState = HAL_ETH_STATE_STARTED;
805 return HAL_OK;
806 }
807 else
808 {
809 return HAL_ERROR;
810 }
811 }
812
813 /**
814 * @brief Stop Ethernet MAC and DMA reception/transmission
815 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
816 * the configuration information for ETHERNET module
817 * @retval HAL status
818 */
819 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
820 {
821 if (heth->gState == HAL_ETH_STATE_STARTED)
822 {
823 /* Set the ETH peripheral state to BUSY */
824 heth->gState = HAL_ETH_STATE_BUSY;
825
826 /* Disable the DMA transmission */
827 CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
828
829 /* Disable the DMA reception */
830 CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
831
832 /* Disable the MAC reception */
833 CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
834
835 /* Set the Flush Transmit FIFO bit */
836 SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
837
838 /* Disable the MAC transmission */
839 CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
840
841 heth->gState = HAL_ETH_STATE_READY;
842
843 /* Return function status */
844 return HAL_OK;
845 }
846 else
847 {
848 return HAL_ERROR;
849 }
850 }
851
852 /**
853 * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
854 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
855 * the configuration information for ETHERNET module
856 * @retval HAL status
857 */
858 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
859 {
860 ETH_DMADescTypeDef *dmarxdesc;
861 uint32_t descindex;
862
863 if (heth->gState == HAL_ETH_STATE_STARTED)
864 {
865 /* Set the ETH peripheral state to BUSY */
866 heth->gState = HAL_ETH_STATE_BUSY;
867
868 /* Disable interrupts:
869 - Tx complete interrupt
870 - Rx complete interrupt
871 - Fatal bus interrupt
872 */
873 __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
874 ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE));
875
876 /* Disable the DMA transmission */
877 CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
878
879 /* Disable the DMA reception */
880 CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
881
882 /* Disable the MAC reception */
883 CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
884
885 /* Set the Flush Transmit FIFO bit */
886 SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
887
888 /* Disable the MAC transmission */
889 CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
890
891 /* Clear IOC bit to all Rx descriptors */
892 for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
893 {
894 dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
895 CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
896 }
897
898 heth->RxDescList.ItMode = 0U;
899
900 heth->gState = HAL_ETH_STATE_READY;
901
902 /* Return function status */
903 return HAL_OK;
904 }
905 else
906 {
907 return HAL_ERROR;
908 }
909 }
910
911 /**
912 * @brief Sends an Ethernet Packet in polling mode.
913 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
914 * the configuration information for ETHERNET module
915 * @param pTxConfig: Hold the configuration of packet to be transmitted
916 * @param Timeout: timeout value
917 * @retval HAL status
918 */
919 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout)
920 {
921 uint32_t tickstart;
922 ETH_DMADescTypeDef *dmatxdesc;
923
924 if (pTxConfig == NULL)
925 {
926 heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
927 return HAL_ERROR;
928 }
929
930 if (heth->gState == HAL_ETH_STATE_STARTED)
931 {
932 /* Config DMA Tx descriptor by Tx Packet info */
933 if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
934 {
935 /* Set the ETH error code */
936 heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
937 return HAL_ERROR;
938 }
939
940 /* Ensure completion of descriptor preparation before transmission start */
941 __DSB();
942
943 dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
944
945 /* Incr current tx desc index */
946 INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
947
948 /* Start transmission */
949 /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
950 WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
951
952 tickstart = HAL_GetTick();
953
954 /* Wait for data to be transmitted or timeout occurred */
955 while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
956 {
957 if ((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
958 {
959 heth->ErrorCode |= HAL_ETH_ERROR_DMA;
960 heth->DMAErrorCode = heth->Instance->DMACSR;
961 /* Return function status */
962 return HAL_ERROR;
963 }
964
965 /* Check for the Timeout */
966 if (Timeout != HAL_MAX_DELAY)
967 {
968 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
969 {
970 heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
971 /* Clear TX descriptor so that we can proceed */
972 dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD);
973 return HAL_ERROR;
974 }
975 }
976 }
977
978 /* Return function status */
979 return HAL_OK;
980 }
981 else
982 {
983 return HAL_ERROR;
984 }
985 }
986
987 /**
988 * @brief Sends an Ethernet Packet in interrupt mode.
989 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
990 * the configuration information for ETHERNET module
991 * @param pTxConfig: Hold the configuration of packet to be transmitted
992 * @retval HAL status
993 */
994 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig)
995 {
996 if (pTxConfig == NULL)
997 {
998 heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
999 return HAL_ERROR;
1000 }
1001
1002 if (heth->gState == HAL_ETH_STATE_STARTED)
1003 {
1004 /* Save the packet pointer to release. */
1005 heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData;
1006
1007 /* Config DMA Tx descriptor by Tx Packet info */
1008 if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
1009 {
1010 heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
1011 return HAL_ERROR;
1012 }
1013
1014 /* Ensure completion of descriptor preparation before transmission start */
1015 __DSB();
1016
1017 /* Incr current tx desc index */
1018 INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
1019
1020 /* Start transmission */
1021 /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
1022 WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
1023
1024 return HAL_OK;
1025
1026 }
1027 else
1028 {
1029 return HAL_ERROR;
1030 }
1031 }
1032
1033 /**
1034 * @brief Read a received packet.
1035 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1036 * the configuration information for ETHERNET module
1037 * @param pAppBuff: Pointer to an application buffer to receive the packet.
1038 * @retval HAL status
1039 */
1040 HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
1041 {
1042 uint32_t descidx;
1043 ETH_DMADescTypeDef *dmarxdesc;
1044 uint32_t desccnt = 0U;
1045 uint32_t desccntmax;
1046 uint32_t bufflength;
1047 uint8_t rxdataready = 0U;
1048
1049 if (pAppBuff == NULL)
1050 {
1051 heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
1052 return HAL_ERROR;
1053 }
1054
1055 if (heth->gState != HAL_ETH_STATE_STARTED)
1056 {
1057 return HAL_ERROR;
1058 }
1059
1060 descidx = heth->RxDescList.RxDescIdx;
1061 dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
1062 desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt;
1063
1064 /* Check if descriptor is not owned by DMA */
1065 while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
1066 && (rxdataready == 0U))
1067 {
1068 if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET)
1069 {
1070 /* Get timestamp high */
1071 heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1;
1072 /* Get timestamp low */
1073 heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC0;
1074 }
1075 if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL))
1076 {
1077 /* Check if first descriptor */
1078 if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
1079 {
1080 heth->RxDescList.RxDescCnt = 0;
1081 heth->RxDescList.RxDataLength = 0;
1082 }
1083
1084 /* Get the Frame Length of the received packet */
1085 bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
1086
1087 /* Check if last descriptor */
1088 if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
1089 {
1090 /* Save Last descriptor index */
1091 heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3;
1092
1093 /* Packet ready */
1094 rxdataready = 1;
1095 }
1096
1097 /* Link data */
1098 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1099 /*Call registered Link callback*/
1100 heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
1101 (uint8_t *)dmarxdesc->BackupAddr0, bufflength);
1102 #else
1103 /* Link callback */
1104 HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
1105 (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength);
1106 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1107 heth->RxDescList.RxDescCnt++;
1108 heth->RxDescList.RxDataLength += bufflength;
1109
1110 /* Clear buffer pointer */
1111 dmarxdesc->BackupAddr0 = 0;
1112 }
1113
1114 /* Increment current rx descriptor index */
1115 INCR_RX_DESC_INDEX(descidx, 1U);
1116 /* Get current descriptor address */
1117 dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
1118 desccnt++;
1119 }
1120
1121 heth->RxDescList.RxBuildDescCnt += desccnt;
1122 if ((heth->RxDescList.RxBuildDescCnt) != 0U)
1123 {
1124 /* Update Descriptors */
1125 ETH_UpdateDescriptor(heth);
1126 }
1127
1128 heth->RxDescList.RxDescIdx = descidx;
1129
1130 if (rxdataready == 1U)
1131 {
1132 /* Return received packet */
1133 *pAppBuff = heth->RxDescList.pRxStart;
1134 /* Reset first element */
1135 heth->RxDescList.pRxStart = NULL;
1136
1137 return HAL_OK;
1138 }
1139
1140 /* Packet not ready */
1141 return HAL_ERROR;
1142 }
1143
1144 /**
1145 * @brief This function gives back Rx Desc of the last received Packet
1146 * to the DMA, so ETH DMA will be able to use these descriptors
1147 * to receive next Packets.
1148 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1149 * the configuration information for ETHERNET module
1150 * @retval HAL status
1151 */
1152 static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
1153 {
1154 uint32_t descidx;
1155 uint32_t tailidx;
1156 uint32_t desccount;
1157 ETH_DMADescTypeDef *dmarxdesc;
1158 uint8_t *buff = NULL;
1159 uint8_t allocStatus = 1U;
1160
1161 descidx = heth->RxDescList.RxBuildDescIdx;
1162 dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
1163 desccount = heth->RxDescList.RxBuildDescCnt;
1164
1165 while ((desccount > 0U) && (allocStatus != 0U))
1166 {
1167 /* Check if a buffer's attached the descriptor */
1168 if (READ_REG(dmarxdesc->BackupAddr0) == 0U)
1169 {
1170 /* Get a new buffer. */
1171 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1172 /*Call registered Allocate callback*/
1173 heth->rxAllocateCallback(&buff);
1174 #else
1175 /* Allocate callback */
1176 HAL_ETH_RxAllocateCallback(&buff);
1177 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1178 if (buff == NULL)
1179 {
1180 allocStatus = 0U;
1181 }
1182 else
1183 {
1184 WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff);
1185 WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff);
1186 }
1187 }
1188
1189 if (allocStatus != 0U)
1190 {
1191
1192 if (heth->RxDescList.ItMode != 0U)
1193 {
1194 WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC);
1195 }
1196 else
1197 {
1198 WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V);
1199 }
1200
1201 /* Increment current rx descriptor index */
1202 INCR_RX_DESC_INDEX(descidx, 1U);
1203 /* Get current descriptor address */
1204 dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
1205 desccount--;
1206 }
1207 }
1208
1209 if (heth->RxDescList.RxBuildDescCnt != desccount)
1210 {
1211 /* Set the tail pointer index */
1212 tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT;
1213
1214 /* DMB instruction to avoid race condition */
1215 __DMB();
1216
1217 /* Set the Tail pointer address */
1218 WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (tailidx))));
1219
1220 heth->RxDescList.RxBuildDescIdx = descidx;
1221 heth->RxDescList.RxBuildDescCnt = desccount;
1222 }
1223 }
1224
1225 /**
1226 * @brief Register the Rx alloc callback.
1227 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1228 * the configuration information for ETHERNET module
1229 * @param rxAllocateCallback: pointer to function to alloc buffer
1230 * @retval HAL status
1231 */
1232 HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
1233 pETH_rxAllocateCallbackTypeDef rxAllocateCallback)
1234 {
1235 if (rxAllocateCallback == NULL)
1236 {
1237 /* No buffer to save */
1238 return HAL_ERROR;
1239 }
1240
1241 /* Set function to allocate buffer */
1242 heth->rxAllocateCallback = rxAllocateCallback;
1243
1244 return HAL_OK;
1245 }
1246
1247 /**
1248 * @brief Unregister the Rx alloc callback.
1249 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1250 * the configuration information for ETHERNET module
1251 * @retval HAL status
1252 */
1253 HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth)
1254 {
1255 /* Set function to allocate buffer */
1256 heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback;
1257
1258 return HAL_OK;
1259 }
1260
1261 /**
1262 * @brief Rx Allocate callback.
1263 * @param buff: pointer to allocated buffer
1264 * @retval None
1265 */
1266 __weak void HAL_ETH_RxAllocateCallback(uint8_t **buff)
1267 {
1268 /* Prevent unused argument(s) compilation warning */
1269 UNUSED(buff);
1270 /* NOTE : This function Should not be modified, when the callback is needed,
1271 the HAL_ETH_RxAllocateCallback could be implemented in the user file
1272 */
1273 }
1274
1275 /**
1276 * @brief Rx Link callback.
1277 * @param pStart: pointer to packet start
1278 * @param pEnd: pointer to packet end
1279 * @param buff: pointer to received data
1280 * @param Length: received data length
1281 * @retval None
1282 */
1283 __weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
1284 {
1285 /* Prevent unused argument(s) compilation warning */
1286 UNUSED(pStart);
1287 UNUSED(pEnd);
1288 UNUSED(buff);
1289 UNUSED(Length);
1290 /* NOTE : This function Should not be modified, when the callback is needed,
1291 the HAL_ETH_RxLinkCallback could be implemented in the user file
1292 */
1293 }
1294
1295 /**
1296 * @brief Set the Rx link data function.
1297 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1298 * the configuration information for ETHERNET module
1299 * @param rxLinkCallback: pointer to function to link data
1300 * @retval HAL status
1301 */
1302 HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback)
1303 {
1304 if (rxLinkCallback == NULL)
1305 {
1306 /* No buffer to save */
1307 return HAL_ERROR;
1308 }
1309
1310 /* Set function to link data */
1311 heth->rxLinkCallback = rxLinkCallback;
1312
1313 return HAL_OK;
1314 }
1315
1316 /**
1317 * @brief Unregister the Rx link callback.
1318 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1319 * the configuration information for ETHERNET module
1320 * @retval HAL status
1321 */
1322 HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth)
1323 {
1324 /* Set function to allocate buffer */
1325 heth->rxLinkCallback = HAL_ETH_RxLinkCallback;
1326
1327 return HAL_OK;
1328 }
1329
1330 /**
1331 * @brief Get the error state of the last received packet.
1332 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1333 * the configuration information for ETHERNET module
1334 * @param pErrorCode: pointer to uint32_t to hold the error code
1335 * @retval HAL status
1336 */
1337 HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
1338 {
1339 /* Get error bits. */
1340 *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK);
1341
1342 return HAL_OK;
1343 }
1344
1345 /**
1346 * @brief Set the Tx free function.
1347 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1348 * the configuration information for ETHERNET module
1349 * @param txFreeCallback: pointer to function to release the packet
1350 * @retval HAL status
1351 */
1352 HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback)
1353 {
1354 if (txFreeCallback == NULL)
1355 {
1356 /* No buffer to save */
1357 return HAL_ERROR;
1358 }
1359
1360 /* Set function to free transmmitted packet */
1361 heth->txFreeCallback = txFreeCallback;
1362
1363 return HAL_OK;
1364 }
1365
1366 /**
1367 * @brief Unregister the Tx free callback.
1368 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1369 * the configuration information for ETHERNET module
1370 * @retval HAL status
1371 */
1372 HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth)
1373 {
1374 /* Set function to allocate buffer */
1375 heth->txFreeCallback = HAL_ETH_TxFreeCallback;
1376
1377 return HAL_OK;
1378 }
1379
1380 /**
1381 * @brief Tx Free callback.
1382 * @param buff: pointer to buffer to free
1383 * @retval None
1384 */
1385 __weak void HAL_ETH_TxFreeCallback(uint32_t *buff)
1386 {
1387 /* Prevent unused argument(s) compilation warning */
1388 UNUSED(buff);
1389 /* NOTE : This function Should not be modified, when the callback is needed,
1390 the HAL_ETH_TxFreeCallback could be implemented in the user file
1391 */
1392 }
1393
1394 /**
1395 * @brief Release transmitted Tx packets.
1396 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1397 * the configuration information for ETHERNET module
1398 * @retval HAL status
1399 */
1400 HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
1401 {
1402 ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
1403 uint32_t numOfBuf = dmatxdesclist->BuffersInUse;
1404 uint32_t idx = dmatxdesclist->releaseIndex;
1405 uint8_t pktTxStatus = 1U;
1406 uint8_t pktInUse;
1407 #ifdef HAL_ETH_USE_PTP
1408 ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp;
1409 #endif /* HAL_ETH_USE_PTP */
1410
1411 /* Loop through buffers in use. */
1412 while ((numOfBuf != 0U) && (pktTxStatus != 0U))
1413 {
1414 pktInUse = 1U;
1415 numOfBuf--;
1416 /* If no packet, just examine the next packet. */
1417 if (dmatxdesclist->PacketAddress[idx] == NULL)
1418 {
1419 /* No packet in use, skip to next. */
1420 INCR_TX_DESC_INDEX(idx, 1U);
1421 pktInUse = 0U;
1422 }
1423
1424 if (pktInUse != 0U)
1425 {
1426 /* Determine if the packet has been transmitted. */
1427 if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U)
1428 {
1429 #ifdef HAL_ETH_USE_PTP
1430
1431 /* Disable Ptp transmission */
1432 CLEAR_BIT(heth->Init.TxDesc[idx].DESC2, ETH_DMATXNDESCRF_TTSE);
1433
1434 if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD)
1435 && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS))
1436 {
1437 /* Get timestamp low */
1438 timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0;
1439 /* Get timestamp high */
1440 timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1;
1441 }
1442 else
1443 {
1444 timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX;
1445 }
1446 #endif /* HAL_ETH_USE_PTP */
1447
1448 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1449 /*Call registered callbacks*/
1450 #ifdef HAL_ETH_USE_PTP
1451 /* Handle Ptp */
1452 if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
1453 {
1454 heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
1455 }
1456 #endif /* HAL_ETH_USE_PTP */
1457 /* Release the packet. */
1458 heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]);
1459 #else
1460 /* Call callbacks */
1461 #ifdef HAL_ETH_USE_PTP
1462 /* Handle Ptp */
1463 if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
1464 {
1465 HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
1466 }
1467 #endif /* HAL_ETH_USE_PTP */
1468 /* Release the packet. */
1469 HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]);
1470 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1471
1472 /* Clear the entry in the in-use array. */
1473 dmatxdesclist->PacketAddress[idx] = NULL;
1474
1475 /* Update the transmit relesae index and number of buffers in use. */
1476 INCR_TX_DESC_INDEX(idx, 1U);
1477 dmatxdesclist->BuffersInUse = numOfBuf;
1478 dmatxdesclist->releaseIndex = idx;
1479 }
1480 else
1481 {
1482 /* Get out of the loop! */
1483 pktTxStatus = 0U;
1484 }
1485 }
1486 }
1487 return HAL_OK;
1488 }
1489
1490 #ifdef HAL_ETH_USE_PTP
1491 /**
1492 * @brief Set the Ethernet PTP configuration.
1493 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1494 * the configuration information for ETHERNET module
1495 * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
1496 * the configuration information for PTP
1497 * @retval HAL status
1498 */
1499 HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
1500 {
1501 uint32_t tmpTSCR;
1502 ETH_TimeTypeDef time;
1503
1504 if (ptpconfig == NULL)
1505 {
1506 return HAL_ERROR;
1507 }
1508
1509 /* Mask the Timestamp Trigger interrupt */
1510 CLEAR_BIT(heth->Instance->MACIER, ETH_MACIER_TSIE);
1511
1512 tmpTSCR = ptpconfig->Timestamp |
1513 ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) |
1514 ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) |
1515 ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_MACTSCR_TSCTRLSSR_Pos) |
1516 ((uint32_t)ptpconfig->TimestampV2 << ETH_MACTSCR_TSVER2ENA_Pos) |
1517 ((uint32_t)ptpconfig->TimestampEthernet << ETH_MACTSCR_TSIPENA_Pos) |
1518 ((uint32_t)ptpconfig->TimestampIPv6 << ETH_MACTSCR_TSIPV6ENA_Pos) |
1519 ((uint32_t)ptpconfig->TimestampIPv4 << ETH_MACTSCR_TSIPV4ENA_Pos) |
1520 ((uint32_t)ptpconfig->TimestampEvent << ETH_MACTSCR_TSEVNTENA_Pos) |
1521 ((uint32_t)ptpconfig->TimestampMaster << ETH_MACTSCR_TSMSTRENA_Pos) |
1522 ((uint32_t)ptpconfig->TimestampSnapshots << ETH_MACTSCR_SNAPTYPSEL_Pos) |
1523 ((uint32_t)ptpconfig->TimestampFilter << ETH_MACTSCR_TSENMACADDR_Pos) |
1524 ((uint32_t)ptpconfig->TimestampChecksumCorrection << ETH_MACTSCR_CSC_Pos) |
1525 ((uint32_t)ptpconfig->TimestampStatusMode << ETH_MACTSCR_TXTSSTSM_Pos);
1526
1527 /* Write to MACTSCR */
1528 MODIFY_REG(heth->Instance->MACTSCR, ETH_MACTSCR_MASK, tmpTSCR);
1529
1530 /* Enable Timestamp */
1531 SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA);
1532 WRITE_REG(heth->Instance->MACSSIR, ptpconfig->TimestampSubsecondInc);
1533 WRITE_REG(heth->Instance->MACTSAR, ptpconfig->TimestampAddend);
1534
1535 /* Enable Timestamp */
1536 if (ptpconfig->TimestampAddendUpdate == ENABLE)
1537 {
1538 SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG);
1539 while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0)
1540 {
1541
1542 }
1543 }
1544
1545 /* Enable Update mode */
1546 if (ptpconfig->TimestampUpdateMode == ENABLE)
1547 {
1548 SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT);
1549 }
1550
1551 /* Set PTP Configuration done */
1552 heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED;
1553
1554 /* Set Seconds */
1555 time.Seconds = heth->Instance->MACSTSR;
1556 /* Set NanoSeconds */
1557 time.NanoSeconds = heth->Instance->MACSTNR;
1558
1559 HAL_ETH_PTP_SetTime(heth, &time);
1560
1561 /* Ptp Init */
1562 SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
1563
1564 /* Return function status */
1565 return HAL_OK;
1566 }
1567
1568 /**
1569 * @brief Get the Ethernet PTP configuration.
1570 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1571 * the configuration information for ETHERNET module
1572 * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
1573 * the configuration information for PTP
1574 * @retval HAL status
1575 */
1576 HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
1577 {
1578 if (ptpconfig == NULL)
1579 {
1580 return HAL_ERROR;
1581 }
1582 ptpconfig->Timestamp = READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA);
1583 ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->MACTSCR,
1584 ETH_MACTSCR_TSCFUPDT) >> ETH_MACTSCR_TSUPDT_Pos) > 0U) ? ENABLE : DISABLE;
1585 ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->MACTSCR,
1586 ETH_MACTSCR_TSENALL) >> ETH_MACTSCR_TSENALL_Pos) > 0U) ? ENABLE : DISABLE;
1587 ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->MACTSCR,
1588 ETH_MACTSCR_TSCTRLSSR) >> ETH_MACTSCR_TSCTRLSSR_Pos) > 0U)
1589 ? ENABLE : DISABLE;
1590 ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->MACTSCR,
1591 ETH_MACTSCR_TSVER2ENA) >> ETH_MACTSCR_TSVER2ENA_Pos) > 0U) ? ENABLE : DISABLE;
1592 ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->MACTSCR,
1593 ETH_MACTSCR_TSIPENA) >> ETH_MACTSCR_TSIPENA_Pos) > 0U) ? ENABLE : DISABLE;
1594 ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->MACTSCR,
1595 ETH_MACTSCR_TSIPV6ENA) >> ETH_MACTSCR_TSIPV6ENA_Pos) > 0U) ? ENABLE : DISABLE;
1596 ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->MACTSCR,
1597 ETH_MACTSCR_TSIPV4ENA) >> ETH_MACTSCR_TSIPV4ENA_Pos) > 0U) ? ENABLE : DISABLE;
1598 ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->MACTSCR,
1599 ETH_MACTSCR_TSEVNTENA) >> ETH_MACTSCR_TSEVNTENA_Pos) > 0U) ? ENABLE : DISABLE;
1600 ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->MACTSCR,
1601 ETH_MACTSCR_TSMSTRENA) >> ETH_MACTSCR_TSMSTRENA_Pos) > 0U) ? ENABLE : DISABLE;
1602 ptpconfig->TimestampSnapshots = ((READ_BIT(heth->Instance->MACTSCR,
1603 ETH_MACTSCR_SNAPTYPSEL) >> ETH_MACTSCR_SNAPTYPSEL_Pos) > 0U)
1604 ? ENABLE : DISABLE;
1605 ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->MACTSCR,
1606 ETH_MACTSCR_TSENMACADDR) >> ETH_MACTSCR_TSENMACADDR_Pos) > 0U)
1607 ? ENABLE : DISABLE;
1608 ptpconfig->TimestampChecksumCorrection = ((READ_BIT(heth->Instance->MACTSCR,
1609 ETH_MACTSCR_CSC) >> ETH_MACTSCR_CSC_Pos) > 0U) ? ENABLE : DISABLE;
1610 ptpconfig->TimestampStatusMode = ((READ_BIT(heth->Instance->MACTSCR,
1611 ETH_MACTSCR_TXTSSTSM) >> ETH_MACTSCR_TXTSSTSM_Pos) > 0U)
1612 ? ENABLE : DISABLE;
1613
1614 /* Return function status */
1615 return HAL_OK;
1616 }
1617
1618 /**
1619 * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers.
1620 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1621 * the configuration information for ETHERNET module
1622 * @param time: pointer to a ETH_TimeTypeDef structure that contains
1623 * time to set
1624 * @retval HAL status
1625 */
1626 HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
1627 {
1628 if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
1629 {
1630 /* Set Seconds */
1631 heth->Instance->MACSTSUR = time->Seconds;
1632
1633 /* Set NanoSeconds */
1634 heth->Instance->MACSTNUR = time->NanoSeconds;
1635
1636 /* the system time is updated */
1637 SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
1638
1639 /* Return function status */
1640 return HAL_OK;
1641 }
1642 else
1643 {
1644 /* Return function status */
1645 return HAL_ERROR;
1646 }
1647 }
1648
1649 /**
1650 * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers.
1651 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1652 * the configuration information for ETHERNET module
1653 * @param time: pointer to a ETH_TimeTypeDef structure that contains
1654 * time to get
1655 * @retval HAL status
1656 */
1657 HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
1658 {
1659 if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
1660 {
1661 /* Get Seconds */
1662 time->Seconds = heth->Instance->MACSTSR;
1663 /* Get NanoSeconds */
1664 time->NanoSeconds = heth->Instance->MACSTNR;
1665
1666 /* Return function status */
1667 return HAL_OK;
1668 }
1669 else
1670 {
1671 /* Return function status */
1672 return HAL_ERROR;
1673 }
1674 }
1675
1676 /**
1677 * @brief Update time for the Ethernet PTP registers.
1678 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1679 * the configuration information for ETHERNET module
1680 * @param timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains
1681 * the time update information
1682 * @retval HAL status
1683 */
1684 HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
1685 ETH_TimeTypeDef *timeoffset)
1686 {
1687 if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
1688 {
1689 if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE)
1690 {
1691 /* Set Seconds update */
1692 heth->Instance->MACSTSUR = ETH_MACSTSUR_VALUE - timeoffset->Seconds + 1U;
1693
1694 if (READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCTRLSSR) == ETH_MACTSCR_TSCTRLSSR)
1695 {
1696 /* Set nanoSeconds update */
1697 heth->Instance->MACSTNUR = ETH_MACSTNUR_VALUE - timeoffset->NanoSeconds;
1698 }
1699 else
1700 {
1701 /* Set nanoSeconds update */
1702 heth->Instance->MACSTNUR = ETH_MACSTSUR_VALUE - timeoffset->NanoSeconds + 1U;
1703 }
1704 }
1705 else
1706 {
1707 /* Set Seconds update */
1708 heth->Instance->MACSTSUR = timeoffset->Seconds;
1709 /* Set nanoSeconds update */
1710 heth->Instance->MACSTNUR = timeoffset->NanoSeconds;
1711 }
1712
1713 SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
1714
1715 /* Return function status */
1716 return HAL_OK;
1717 }
1718 else
1719 {
1720 /* Return function status */
1721 return HAL_ERROR;
1722 }
1723 }
1724
1725 /**
1726 * @brief Insert Timestamp in transmission.
1727 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1728 * the configuration information for ETHERNET module
1729 * @retval HAL status
1730 */
1731 HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
1732 {
1733 ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
1734 uint32_t descidx = dmatxdesclist->CurTxDesc;
1735 ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
1736
1737 if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
1738 {
1739 /* Enable Time Stamp transmission */
1740 SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE);
1741
1742 /* Return function status */
1743 return HAL_OK;
1744 }
1745 else
1746 {
1747 /* Return function status */
1748 return HAL_ERROR;
1749 }
1750 }
1751
1752 /**
1753 * @brief Get transmission timestamp.
1754 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1755 * the configuration information for ETHERNET module
1756 * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
1757 * transmission timestamp
1758 * @retval HAL status
1759 */
1760 HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
1761 {
1762 ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
1763 uint32_t idx = dmatxdesclist->releaseIndex;
1764 ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx];
1765
1766 if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
1767 {
1768 /* Get timestamp low */
1769 timestamp->TimeStampLow = dmatxdesc->DESC0;
1770 /* Get timestamp high */
1771 timestamp->TimeStampHigh = dmatxdesc->DESC1;
1772
1773 /* Return function status */
1774 return HAL_OK;
1775 }
1776 else
1777 {
1778 /* Return function status */
1779 return HAL_ERROR;
1780 }
1781 }
1782
1783 /**
1784 * @brief Get receive timestamp.
1785 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1786 * the configuration information for ETHERNET module
1787 * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
1788 * receive timestamp
1789 * @retval HAL status
1790 */
1791 HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
1792 {
1793 if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
1794 {
1795 /* Get timestamp low */
1796 timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow;
1797 /* Get timestamp high */
1798 timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh;
1799
1800 /* Return function status */
1801 return HAL_OK;
1802 }
1803 else
1804 {
1805 /* Return function status */
1806 return HAL_ERROR;
1807 }
1808 }
1809
1810 /**
1811 * @brief Register the Tx Ptp callback.
1812 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1813 * the configuration information for ETHERNET module
1814 * @param txPtpCallback: Function to handle Ptp transmission
1815 * @retval HAL status
1816 */
1817 HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback)
1818 {
1819 if (txPtpCallback == NULL)
1820 {
1821 /* No buffer to save */
1822 return HAL_ERROR;
1823 }
1824 /* Set Function to handle Tx Ptp */
1825 heth->txPtpCallback = txPtpCallback;
1826
1827 return HAL_OK;
1828 }
1829
1830 /**
1831 * @brief Unregister the Tx Ptp callback.
1832 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1833 * the configuration information for ETHERNET module
1834 * @retval HAL status
1835 */
1836 HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth)
1837 {
1838 /* Set function to allocate buffer */
1839 heth->txPtpCallback = HAL_ETH_TxPtpCallback;
1840
1841 return HAL_OK;
1842 }
1843
1844 /**
1845 * @brief Tx Ptp callback.
1846 * @param buff: pointer to application buffer
1847 * @param timestamp: pointer to ETH_TimeStampTypeDef structure that contains
1848 * transmission timestamp
1849 * @retval None
1850 */
1851 __weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
1852 {
1853 /* Prevent unused argument(s) compilation warning */
1854 UNUSED(buff);
1855 /* NOTE : This function Should not be modified, when the callback is needed,
1856 the HAL_ETH_TxPtpCallback could be implemented in the user file
1857 */
1858 }
1859 #endif /* HAL_ETH_USE_PTP */
1860
1861 /**
1862 * @brief This function handles ETH interrupt request.
1863 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
1864 * the configuration information for ETHERNET module
1865 * @retval HAL status
1866 */
1867 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
1868 {
1869 uint32_t mac_flag = READ_REG(heth->Instance->MACISR);
1870 uint32_t dma_flag = READ_REG(heth->Instance->DMACSR);
1871 uint32_t dma_itsource = READ_REG(heth->Instance->DMACIER);
1872 uint32_t exti_d1_flag = READ_REG(EXTI_D1->PR3);
1873 #if defined(DUAL_CORE)
1874 uint32_t exti_d2_flag = READ_REG(EXTI_D2->PR3);
1875 #endif /* DUAL_CORE */
1876
1877 /* Packet received */
1878 if (((dma_flag & ETH_DMACSR_RI) != 0U) && ((dma_itsource & ETH_DMACIER_RIE) != 0U))
1879 {
1880 /* Clear the Eth DMA Rx IT pending bits */
1881 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
1882
1883 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1884 /*Call registered Receive complete callback*/
1885 heth->RxCpltCallback(heth);
1886 #else
1887 /* Receive complete callback */
1888 HAL_ETH_RxCpltCallback(heth);
1889 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1890 }
1891
1892 /* Packet transmitted */
1893 if (((dma_flag & ETH_DMACSR_TI) != 0U) && ((dma_itsource & ETH_DMACIER_TIE) != 0U))
1894 {
1895 /* Clear the Eth DMA Tx IT pending bits */
1896 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
1897
1898 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1899 /*Call registered Transmit complete callback*/
1900 heth->TxCpltCallback(heth);
1901 #else
1902 /* Transfer complete callback */
1903 HAL_ETH_TxCpltCallback(heth);
1904 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1905 }
1906
1907 /* ETH DMA Error */
1908 if (((dma_flag & ETH_DMACSR_AIS) != 0U) && ((dma_itsource & ETH_DMACIER_AIE) != 0U))
1909 {
1910 heth->ErrorCode |= HAL_ETH_ERROR_DMA;
1911 /* if fatal bus error occurred */
1912 if ((dma_flag & ETH_DMACSR_FBE) != 0U)
1913 {
1914 /* Get DMA error code */
1915 heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
1916
1917 /* Disable all interrupts */
1918 __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
1919
1920 /* Set HAL state to ERROR */
1921 heth->gState = HAL_ETH_STATE_ERROR;
1922 }
1923 else
1924 {
1925 /* Get DMA error status */
1926 heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
1927 ETH_DMACSR_RBU | ETH_DMACSR_AIS));
1928
1929 /* Clear the interrupt summary flag */
1930 __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
1931 ETH_DMACSR_RBU | ETH_DMACSR_AIS));
1932 }
1933 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1934 /* Call registered Error callback*/
1935 heth->ErrorCallback(heth);
1936 #else
1937 /* Ethernet DMA Error callback */
1938 HAL_ETH_ErrorCallback(heth);
1939 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1940 }
1941
1942 /* ETH MAC Error IT */
1943 if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
1944 ((mac_flag & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
1945 {
1946 heth->ErrorCode |= HAL_ETH_ERROR_MAC;
1947
1948 /* Get MAC Rx Tx status and clear Status register pending bit */
1949 heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
1950
1951 heth->gState = HAL_ETH_STATE_ERROR;
1952
1953 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1954 /* Call registered Error callback*/
1955 heth->ErrorCallback(heth);
1956 #else
1957 /* Ethernet Error callback */
1958 HAL_ETH_ErrorCallback(heth);
1959 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1960 heth->MACErrorCode = (uint32_t)(0x0U);
1961 }
1962
1963 /* ETH PMT IT */
1964 if ((mac_flag & ETH_MAC_PMT_IT) != 0U)
1965 {
1966 /* Get MAC Wake-up source and clear the status register pending bit */
1967 heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
1968
1969 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1970 /* Call registered PMT callback*/
1971 heth->PMTCallback(heth);
1972 #else
1973 /* Ethernet PMT callback */
1974 HAL_ETH_PMTCallback(heth);
1975 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1976
1977 heth->MACWakeUpEvent = (uint32_t)(0x0U);
1978 }
1979
1980 /* ETH EEE IT */
1981 if ((mac_flag & ETH_MAC_LPI_IT) != 0U)
1982 {
1983 /* Get MAC LPI interrupt source and clear the status register pending bit */
1984 heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU);
1985
1986 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1987 /* Call registered EEE callback*/
1988 heth->EEECallback(heth);
1989 #else
1990 /* Ethernet EEE callback */
1991 HAL_ETH_EEECallback(heth);
1992 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1993
1994 heth->MACLPIEvent = (uint32_t)(0x0U);
1995 }
1996
1997 #if defined(DUAL_CORE)
1998 if (HAL_GetCurrentCPUID() == CM7_CPUID)
1999 {
2000 /* check ETH WAKEUP exti flag */
2001 if ((exti_d1_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
2002 {
2003 /* Clear ETH WAKEUP Exti pending bit */
2004 __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
2005 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
2006 /* Call registered WakeUp callback*/
2007 heth->WakeUpCallback(heth);
2008 #else
2009 /* ETH WAKEUP callback */
2010 HAL_ETH_WakeUpCallback(heth);
2011 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2012 }
2013 }
2014 else
2015 {
2016 /* check ETH WAKEUP exti flag */
2017 if ((exti_d2_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
2018 {
2019 /* Clear ETH WAKEUP Exti pending bit */
2020 __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
2021 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
2022 /* Call registered WakeUp callback*/
2023 heth->WakeUpCallback(heth);
2024 #else
2025 /* ETH WAKEUP callback */
2026 HAL_ETH_WakeUpCallback(heth);
2027 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2028 }
2029 }
2030 #else /* DUAL_CORE not defined */
2031 /* check ETH WAKEUP exti flag */
2032 if ((exti_d1_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
2033 {
2034 /* Clear ETH WAKEUP Exti pending bit */
2035 __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
2036 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
2037 /* Call registered WakeUp callback*/
2038 heth->WakeUpCallback(heth);
2039 #else
2040 /* ETH WAKEUP callback */
2041 HAL_ETH_WakeUpCallback(heth);
2042 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2043 }
2044 #endif /* DUAL_CORE */
2045 }
2046
2047 /**
2048 * @brief Tx Transfer completed callbacks.
2049 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2050 * the configuration information for ETHERNET module
2051 * @retval None
2052 */
2053 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
2054 {
2055 /* Prevent unused argument(s) compilation warning */
2056 UNUSED(heth);
2057 /* NOTE : This function Should not be modified, when the callback is needed,
2058 the HAL_ETH_TxCpltCallback could be implemented in the user file
2059 */
2060 }
2061
2062 /**
2063 * @brief Rx Transfer completed callbacks.
2064 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2065 * the configuration information for ETHERNET module
2066 * @retval None
2067 */
2068 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
2069 {
2070 /* Prevent unused argument(s) compilation warning */
2071 UNUSED(heth);
2072 /* NOTE : This function Should not be modified, when the callback is needed,
2073 the HAL_ETH_RxCpltCallback could be implemented in the user file
2074 */
2075 }
2076
2077 /**
2078 * @brief Ethernet transfer error callbacks
2079 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2080 * the configuration information for ETHERNET module
2081 * @retval None
2082 */
2083 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
2084 {
2085 /* Prevent unused argument(s) compilation warning */
2086 UNUSED(heth);
2087 /* NOTE : This function Should not be modified, when the callback is needed,
2088 the HAL_ETH_ErrorCallback could be implemented in the user file
2089 */
2090 }
2091
2092 /**
2093 * @brief Ethernet Power Management module IT callback
2094 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2095 * the configuration information for ETHERNET module
2096 * @retval None
2097 */
2098 __weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
2099 {
2100 /* Prevent unused argument(s) compilation warning */
2101 UNUSED(heth);
2102 /* NOTE : This function Should not be modified, when the callback is needed,
2103 the HAL_ETH_PMTCallback could be implemented in the user file
2104 */
2105 }
2106
2107 /**
2108 * @brief Energy Efficient Etherent IT callback
2109 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2110 * the configuration information for ETHERNET module
2111 * @retval None
2112 */
2113 __weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
2114 {
2115 /* Prevent unused argument(s) compilation warning */
2116 UNUSED(heth);
2117 /* NOTE : This function Should not be modified, when the callback is needed,
2118 the HAL_ETH_EEECallback could be implemented in the user file
2119 */
2120 }
2121
2122 /**
2123 * @brief ETH WAKEUP interrupt callback
2124 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2125 * the configuration information for ETHERNET module
2126 * @retval None
2127 */
2128 __weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
2129 {
2130 /* Prevent unused argument(s) compilation warning */
2131 UNUSED(heth);
2132 /* NOTE : This function Should not be modified, when the callback is needed,
2133 the HAL_ETH_WakeUpCallback could be implemented in the user file
2134 */
2135 }
2136
2137 /**
2138 * @brief Read a PHY register
2139 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2140 * the configuration information for ETHERNET module
2141 * @param PHYAddr: PHY port address, must be a value from 0 to 31
2142 * @param PHYReg: PHY register address, must be a value from 0 to 31
2143 * @param pRegValue: parameter to hold read value
2144 * @retval HAL status
2145 */
2146 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
2147 uint32_t *pRegValue)
2148 {
2149 uint32_t tickstart;
2150 uint32_t tmpreg;
2151
2152 /* Check for the Busy flag */
2153 if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
2154 {
2155 return HAL_ERROR;
2156 }
2157
2158 /* Get the MACMDIOAR value */
2159 WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
2160
2161 /* Prepare the MDIO Address Register value
2162 - Set the PHY device address
2163 - Set the PHY register address
2164 - Set the read mode
2165 - Set the MII Busy bit */
2166
2167 MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
2168 MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
2169 MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
2170 SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
2171
2172 /* Write the result value into the MDII Address register */
2173 WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
2174
2175 tickstart = HAL_GetTick();
2176
2177 /* Wait for the Busy flag */
2178 while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
2179 {
2180 if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
2181 {
2182 return HAL_ERROR;
2183 }
2184 }
2185
2186 /* Get MACMIIDR value */
2187 WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
2188
2189 return HAL_OK;
2190 }
2191
2192 /**
2193 * @brief Writes to a PHY register.
2194 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2195 * the configuration information for ETHERNET module
2196 * @param PHYAddr: PHY port address, must be a value from 0 to 31
2197 * @param PHYReg: PHY register address, must be a value from 0 to 31
2198 * @param RegValue: the value to write
2199 * @retval HAL status
2200 */
2201 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
2202 uint32_t RegValue)
2203 {
2204 uint32_t tickstart;
2205 uint32_t tmpreg;
2206
2207 /* Check for the Busy flag */
2208 if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
2209 {
2210 return HAL_ERROR;
2211 }
2212
2213 /* Get the MACMDIOAR value */
2214 WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
2215
2216 /* Prepare the MDIO Address Register value
2217 - Set the PHY device address
2218 - Set the PHY register address
2219 - Set the write mode
2220 - Set the MII Busy bit */
2221
2222 MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
2223 MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
2224 MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
2225 SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
2226
2227 /* Give the value to the MII data register */
2228 WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
2229
2230 /* Write the result value into the MII Address register */
2231 WRITE_REG(ETH->MACMDIOAR, tmpreg);
2232
2233 tickstart = HAL_GetTick();
2234
2235 /* Wait for the Busy flag */
2236 while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
2237 {
2238 if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
2239 {
2240 return HAL_ERROR;
2241 }
2242 }
2243
2244 return HAL_OK;
2245 }
2246
2247 /**
2248 * @}
2249 */
2250
2251 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
2252 * @brief ETH control functions
2253 *
2254 @verbatim
2255 ==============================================================================
2256 ##### Peripheral Control functions #####
2257 ==============================================================================
2258 [..]
2259 This subsection provides a set of functions allowing to control the ETH
2260 peripheral.
2261
2262 @endverbatim
2263 * @{
2264 */
2265 /**
2266 * @brief Get the configuration of the MAC and MTL subsystems.
2267 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2268 * the configuration information for ETHERNET module
2269 * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
2270 * the configuration of the MAC.
2271 * @retval HAL Status
2272 */
2273 HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
2274 {
2275 if (macconf == NULL)
2276 {
2277 return HAL_ERROR;
2278 }
2279
2280 /* Get MAC parameters */
2281 macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
2282 macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE;
2283 macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
2284 macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
2285 macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U)
2286 ? ENABLE : DISABLE;
2287 macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
2288 macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR,
2289 ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
2290 macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
2291 macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
2292 macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
2293 macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
2294 macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE;
2295 macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE;
2296 macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
2297 macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
2298 macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
2299 macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR,
2300 ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
2301 macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
2302 macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
2303 macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
2304
2305 macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
2306 macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
2307 macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
2308 macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR,
2309 ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
2310 macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U)
2311 ? ENABLE : DISABLE;
2312 macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
2313
2314 macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
2315 macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
2316
2317 macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE;
2318 macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
2319 macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
2320 macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
2321 macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
2322 macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U)
2323 ? ENABLE : DISABLE;
2324
2325 macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
2326
2327 macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
2328 macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
2329 ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
2330 macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
2331 macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
2332 ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
2333
2334 return HAL_OK;
2335 }
2336
2337 /**
2338 * @brief Get the configuration of the DMA.
2339 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2340 * the configuration information for ETHERNET module
2341 * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
2342 * the configuration of the ETH DMA.
2343 * @retval HAL Status
2344 */
2345 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
2346 {
2347 if (dmaconf == NULL)
2348 {
2349 return HAL_ERROR;
2350 }
2351
2352 dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE;
2353 dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
2354 dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB) >> 15) > 0U) ? ENABLE : DISABLE;
2355
2356 dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR | ETH_DMAMR_PR | ETH_DMAMR_DA));
2357
2358 dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL) >> 16) > 0U) ? ENABLE : DISABLE;
2359 dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
2360
2361 dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE;
2362 dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL);
2363
2364 dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE;
2365 dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
2366 dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
2367
2368 return HAL_OK;
2369 }
2370
2371 /**
2372 * @brief Set the MAC configuration.
2373 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2374 * the configuration information for ETHERNET module
2375 * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains
2376 * the configuration of the MAC.
2377 * @retval HAL status
2378 */
2379 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
2380 {
2381 if (macconf == NULL)
2382 {
2383 return HAL_ERROR;
2384 }
2385
2386 if (heth->gState == HAL_ETH_STATE_READY)
2387 {
2388 ETH_SetMACConfig(heth, macconf);
2389
2390 return HAL_OK;
2391 }
2392 else
2393 {
2394 return HAL_ERROR;
2395 }
2396 }
2397
2398 /**
2399 * @brief Set the ETH DMA configuration.
2400 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2401 * the configuration information for ETHERNET module
2402 * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
2403 * the configuration of the ETH DMA.
2404 * @retval HAL status
2405 */
2406 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
2407 {
2408 if (dmaconf == NULL)
2409 {
2410 return HAL_ERROR;
2411 }
2412
2413 if (heth->gState == HAL_ETH_STATE_READY)
2414 {
2415 ETH_SetDMAConfig(heth, dmaconf);
2416
2417 return HAL_OK;
2418 }
2419 else
2420 {
2421 return HAL_ERROR;
2422 }
2423 }
2424
2425 /**
2426 * @brief Configures the Clock range of ETH MDIO interface.
2427 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2428 * the configuration information for ETHERNET module
2429 * @retval None
2430 */
2431 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
2432 {
2433 uint32_t hclk;
2434 uint32_t tmpreg;
2435
2436 /* Get the ETHERNET MACMDIOAR value */
2437 tmpreg = (heth->Instance)->MACMDIOAR;
2438
2439 /* Clear CSR Clock Range bits */
2440 tmpreg &= ~ETH_MACMDIOAR_CR;
2441
2442 /* Get hclk frequency value */
2443 hclk = HAL_RCC_GetHCLKFreq();
2444
2445 /* Set CR bits depending on hclk value */
2446 if (hclk < 35000000U)
2447 {
2448 /* CSR Clock Range between 0-35 MHz */
2449 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
2450 }
2451 else if (hclk < 60000000U)
2452 {
2453 /* CSR Clock Range between 35-60 MHz */
2454 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
2455 }
2456 else if (hclk < 100000000U)
2457 {
2458 /* CSR Clock Range between 60-100 MHz */
2459 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
2460 }
2461 else if (hclk < 150000000U)
2462 {
2463 /* CSR Clock Range between 100-150 MHz */
2464 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
2465 }
2466 else if (hclk < 250000000U)
2467 {
2468 /* CSR Clock Range between 150-250 MHz */
2469 tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
2470 }
2471 else /* (hclk >= 250000000U) */
2472 {
2473 /* CSR Clock >= 250 MHz */
2474 tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV124);
2475 }
2476
2477 /* Configure the CSR Clock Range */
2478 (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
2479 }
2480
2481 /**
2482 * @brief Set the ETH MAC (L2) Filters configuration.
2483 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2484 * the configuration information for ETHERNET module
2485 * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
2486 * the configuration of the ETH MAC filters.
2487 * @retval HAL status
2488 */
2489 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig)
2490 {
2491 uint32_t filterconfig;
2492
2493 if (pFilterConfig == NULL)
2494 {
2495 return HAL_ERROR;
2496 }
2497
2498 filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
2499 ((uint32_t)pFilterConfig->HashUnicast << 1) |
2500 ((uint32_t)pFilterConfig->HashMulticast << 2) |
2501 ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
2502 ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
2503 ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) |
2504 ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
2505 ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
2506 ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
2507 ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
2508 pFilterConfig->ControlPacketsFilter);
2509
2510 MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
2511
2512 return HAL_OK;
2513 }
2514
2515 /**
2516 * @brief Get the ETH MAC (L2) Filters configuration.
2517 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2518 * the configuration information for ETHERNET module
2519 * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
2520 * the configuration of the ETH MAC filters.
2521 * @retval HAL status
2522 */
2523 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
2524 {
2525 if (pFilterConfig == NULL)
2526 {
2527 return HAL_ERROR;
2528 }
2529
2530 pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE;
2531 pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE;
2532 pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE;
2533 pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
2534 ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
2535 pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
2536 pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) > 0U) ? ENABLE : DISABLE;
2537 pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
2538 pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
2539 ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
2540 pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
2541 pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U)
2542 ? ENABLE : DISABLE;
2543 pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
2544
2545 return HAL_OK;
2546 }
2547
2548 /**
2549 * @brief Set the source MAC Address to be matched.
2550 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2551 * the configuration information for ETHERNET module
2552 * @param AddrNbr: The MAC address to configure
2553 * This parameter must be a value of the following:
2554 * ETH_MAC_ADDRESS1
2555 * ETH_MAC_ADDRESS2
2556 * ETH_MAC_ADDRESS3
2557 * @param pMACAddr: Pointer to MAC address buffer data (6 bytes)
2558 * @retval HAL status
2559 */
2560 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
2561 const uint8_t *pMACAddr)
2562 {
2563 uint32_t macaddrlr;
2564 uint32_t macaddrhr;
2565
2566 if (pMACAddr == NULL)
2567 {
2568 return HAL_ERROR;
2569 }
2570
2571 /* Get mac addr high reg offset */
2572 macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr);
2573 /* Get mac addr low reg offset */
2574 macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr);
2575
2576 /* Set MAC addr bits 32 to 47 */
2577 (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
2578 /* Set MAC addr bits 0 to 31 */
2579 (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
2580 ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
2581
2582 /* Enable address and set source address bit */
2583 (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
2584
2585 return HAL_OK;
2586 }
2587
2588 /**
2589 * @brief Set the ETH Hash Table Value.
2590 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2591 * the configuration information for ETHERNET module
2592 * @param pHashTable: pointer to a table of two 32 bit values, that contains
2593 * the 64 bits of the hash table.
2594 * @retval HAL status
2595 */
2596 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
2597 {
2598 if (pHashTable == NULL)
2599 {
2600 return HAL_ERROR;
2601 }
2602
2603 heth->Instance->MACHT0R = pHashTable[0];
2604 heth->Instance->MACHT1R = pHashTable[1];
2605
2606 return HAL_OK;
2607 }
2608
2609 /**
2610 * @brief Set the VLAN Identifier for Rx packets
2611 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2612 * the configuration information for ETHERNET module
2613 * @param ComparisonBits: 12 or 16 bit comparison mode
2614 must be a value of @ref ETH_VLAN_Tag_Comparison
2615 * @param VLANIdentifier: VLAN Identifier value
2616 * @retval None
2617 */
2618 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
2619 {
2620 if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
2621 {
2622 MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL, VLANIdentifier);
2623 CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
2624 }
2625 else
2626 {
2627 MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID, VLANIdentifier);
2628 SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
2629 }
2630 }
2631
2632 /**
2633 * @brief Enters the Power down mode.
2634 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2635 * the configuration information for ETHERNET module
2636 * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
2637 * that contains the Power Down configuration
2638 * @retval None.
2639 */
2640 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig)
2641 {
2642 uint32_t powerdownconfig;
2643
2644 powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
2645 ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
2646 ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
2647 ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
2648 ETH_MACPCSR_PWRDWN);
2649
2650 /* Enable PMT interrupt */
2651 __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
2652
2653 MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig);
2654 }
2655
2656 /**
2657 * @brief Exits from the Power down mode.
2658 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2659 * the configuration information for ETHERNET module
2660 * @retval None.
2661 */
2662 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
2663 {
2664 /* clear wake up sources */
2665 CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST |
2666 ETH_MACPCSR_RWKPFE);
2667
2668 if (READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != (uint32_t)RESET)
2669 {
2670 /* Exit power down mode */
2671 CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
2672 }
2673
2674 /* Disable PMT interrupt */
2675 __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE);
2676 }
2677
2678 /**
2679 * @brief Set the WakeUp filter.
2680 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2681 * the configuration information for ETHERNET module
2682 * @param pFilter: pointer to filter registers values
2683 * @param Count: number of filter registers, must be from 1 to 8.
2684 * @retval None.
2685 */
2686 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
2687 {
2688 uint32_t regindex;
2689
2690 if (pFilter == NULL)
2691 {
2692 return HAL_ERROR;
2693 }
2694
2695 /* Reset Filter Pointer */
2696 SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
2697
2698 /* Wake up packet filter config */
2699 for (regindex = 0; regindex < Count; regindex++)
2700 {
2701 /* Write filter regs */
2702 WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
2703 }
2704
2705 return HAL_OK;
2706 }
2707
2708 /**
2709 * @}
2710 */
2711
2712 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
2713 * @brief ETH State and Errors functions
2714 *
2715 @verbatim
2716 ==============================================================================
2717 ##### Peripheral State and Errors functions #####
2718 ==============================================================================
2719 [..]
2720 This subsection provides a set of functions allowing to return the State of
2721 ETH communication process, return Peripheral Errors occurred during communication
2722 process
2723
2724
2725 @endverbatim
2726 * @{
2727 */
2728
2729 /**
2730 * @brief Returns the ETH state.
2731 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2732 * the configuration information for ETHERNET module
2733 * @retval HAL state
2734 */
2735 HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth)
2736 {
2737 return heth->gState;
2738 }
2739
2740 /**
2741 * @brief Returns the ETH error code
2742 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2743 * the configuration information for ETHERNET module
2744 * @retval ETH Error Code
2745 */
2746 uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth)
2747 {
2748 return heth->ErrorCode;
2749 }
2750
2751 /**
2752 * @brief Returns the ETH DMA error code
2753 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2754 * the configuration information for ETHERNET module
2755 * @retval ETH DMA Error Code
2756 */
2757 uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth)
2758 {
2759 return heth->DMAErrorCode;
2760 }
2761
2762 /**
2763 * @brief Returns the ETH MAC error code
2764 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2765 * the configuration information for ETHERNET module
2766 * @retval ETH MAC Error Code
2767 */
2768 uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth)
2769 {
2770 return heth->MACErrorCode;
2771 }
2772
2773 /**
2774 * @brief Returns the ETH MAC WakeUp event source
2775 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2776 * the configuration information for ETHERNET module
2777 * @retval ETH MAC WakeUp event source
2778 */
2779 uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
2780 {
2781 return heth->MACWakeUpEvent;
2782 }
2783
2784 /**
2785 * @brief Returns the ETH Tx Buffers in use number
2786 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2787 * the configuration information for ETHERNET module
2788 * @retval ETH Tx Buffers in use number
2789 */
2790 uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth)
2791 {
2792 return heth->TxDescList.BuffersInUse;
2793 }
2794 /**
2795 * @}
2796 */
2797
2798 /**
2799 * @}
2800 */
2801
2802 /** @addtogroup ETH_Private_Functions ETH Private Functions
2803 * @{
2804 */
2805
2806 static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
2807 {
2808 uint32_t macregval;
2809
2810 /*------------------------ MACCR Configuration --------------------*/
2811 macregval = (macconf->InterPacketGapVal |
2812 macconf->SourceAddrControl |
2813 ((uint32_t)macconf->ChecksumOffload << 27) |
2814 ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
2815 ((uint32_t)macconf->Support2KPacket << 22) |
2816 ((uint32_t)macconf->CRCStripTypePacket << 21) |
2817 ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
2818 ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
2819 ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
2820 ((uint32_t)macconf->JumboPacket << 16) |
2821 macconf->Speed |
2822 macconf->DuplexMode |
2823 ((uint32_t)macconf->LoopbackMode << 12) |
2824 ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
2825 ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
2826 ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
2827 ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
2828 macconf->BackOffLimit |
2829 ((uint32_t)macconf->DeferralCheck << 4) |
2830 macconf->PreambleLength);
2831
2832 /* Write to MACCR */
2833 MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
2834
2835 /*------------------------ MACECR Configuration --------------------*/
2836 macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
2837 ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
2838 ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
2839 ((uint32_t)macconf->SlowProtocolDetect << 17) |
2840 ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) |
2841 macconf->GiantPacketSizeLimit);
2842
2843 /* Write to MACECR */
2844 MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
2845
2846 /*------------------------ MACWTR Configuration --------------------*/
2847 macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
2848 macconf->WatchdogTimeout);
2849
2850 /* Write to MACWTR */
2851 MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
2852
2853 /*------------------------ MACTFCR Configuration --------------------*/
2854 macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
2855 macconf->PauseLowThreshold |
2856 ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) |
2857 (macconf->PauseTime << 16));
2858
2859 /* Write to MACTFCR */
2860 MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
2861
2862 /*------------------------ MACRFCR Configuration --------------------*/
2863 macregval = ((uint32_t)macconf->ReceiveFlowControl |
2864 ((uint32_t)macconf->UnicastPausePacketDetect << 1));
2865
2866 /* Write to MACRFCR */
2867 MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
2868
2869 /*------------------------ MTLTQOMR Configuration --------------------*/
2870 /* Write to MTLTQOMR */
2871 MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
2872
2873 /*------------------------ MTLRQOMR Configuration --------------------*/
2874 macregval = (macconf->ReceiveQueueMode |
2875 ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
2876 ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
2877 ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
2878
2879 /* Write to MTLRQOMR */
2880 MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
2881 }
2882
2883 static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
2884 {
2885 uint32_t dmaregval;
2886
2887 /*------------------------ DMAMR Configuration --------------------*/
2888 MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
2889
2890 /*------------------------ DMASBMR Configuration --------------------*/
2891 dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
2892 dmaconf->BurstMode |
2893 ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
2894
2895 MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
2896
2897 /*------------------------ DMACCR Configuration --------------------*/
2898 dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
2899 dmaconf->MaximumSegmentSize);
2900 MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
2901
2902 /*------------------------ DMACTCR Configuration --------------------*/
2903 dmaregval = (dmaconf->TxDMABurstLength |
2904 ((uint32_t)dmaconf->SecondPacketOperate << 4) |
2905 ((uint32_t)dmaconf->TCPSegmentation << 12));
2906
2907 MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
2908
2909 /*------------------------ DMACRCR Configuration --------------------*/
2910 dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) |
2911 dmaconf->RxDMABurstLength);
2912
2913 /* Write to DMACRCR */
2914 MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
2915 }
2916
2917 /**
2918 * @brief Configures Ethernet MAC and DMA with default parameters.
2919 * called by HAL_ETH_Init() API.
2920 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2921 * the configuration information for ETHERNET module
2922 * @retval HAL status
2923 */
2924 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
2925 {
2926 ETH_MACConfigTypeDef macDefaultConf;
2927 ETH_DMAConfigTypeDef dmaDefaultConf;
2928
2929 /*--------------- ETHERNET MAC registers default Configuration --------------*/
2930 macDefaultConf.AutomaticPadCRCStrip = ENABLE;
2931 macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
2932 macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
2933 macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
2934 macDefaultConf.ChecksumOffload = ENABLE;
2935 macDefaultConf.CRCCheckingRxPackets = ENABLE;
2936 macDefaultConf.CRCStripTypePacket = ENABLE;
2937 macDefaultConf.DeferralCheck = DISABLE;
2938 macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
2939 macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
2940 macDefaultConf.ExtendedInterPacketGap = DISABLE;
2941 macDefaultConf.ExtendedInterPacketGapVal = 0x0U;
2942 macDefaultConf.ForwardRxErrorPacket = DISABLE;
2943 macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
2944 macDefaultConf.GiantPacketSizeLimit = 0x618U;
2945 macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
2946 macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
2947 macDefaultConf.Jabber = ENABLE;
2948 macDefaultConf.JumboPacket = DISABLE;
2949 macDefaultConf.LoopbackMode = DISABLE;
2950 macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
2951 macDefaultConf.PauseTime = 0x0U;
2952 macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
2953 macDefaultConf.ProgrammableWatchdog = DISABLE;
2954 macDefaultConf.ReceiveFlowControl = DISABLE;
2955 macDefaultConf.ReceiveOwn = ENABLE;
2956 macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
2957 macDefaultConf.RetryTransmission = ENABLE;
2958 macDefaultConf.SlowProtocolDetect = DISABLE;
2959 macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
2960 macDefaultConf.Speed = ETH_SPEED_100M;
2961 macDefaultConf.Support2KPacket = DISABLE;
2962 macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
2963 macDefaultConf.TransmitFlowControl = DISABLE;
2964 macDefaultConf.UnicastPausePacketDetect = DISABLE;
2965 macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
2966 macDefaultConf.Watchdog = ENABLE;
2967 macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB;
2968 macDefaultConf.ZeroQuantaPause = ENABLE;
2969
2970 /* MAC default configuration */
2971 ETH_SetMACConfig(heth, &macDefaultConf);
2972
2973 /*--------------- ETHERNET DMA registers default Configuration --------------*/
2974 dmaDefaultConf.AddressAlignedBeats = ENABLE;
2975 dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
2976 dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
2977 dmaDefaultConf.FlushRxPacket = DISABLE;
2978 dmaDefaultConf.PBLx8Mode = DISABLE;
2979 dmaDefaultConf.RebuildINCRxBurst = DISABLE;
2980 dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
2981 dmaDefaultConf.SecondPacketOperate = DISABLE;
2982 dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
2983 dmaDefaultConf.TCPSegmentation = DISABLE;
2984 dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT;
2985
2986 /* DMA default configuration */
2987 ETH_SetDMAConfig(heth, &dmaDefaultConf);
2988 }
2989
2990 /**
2991 * @brief Initializes the DMA Tx descriptors.
2992 * called by HAL_ETH_Init() API.
2993 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
2994 * the configuration information for ETHERNET module
2995 * @retval None
2996 */
2997 static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
2998 {
2999 ETH_DMADescTypeDef *dmatxdesc;
3000 uint32_t i;
3001
3002 /* Fill each DMATxDesc descriptor with the right values */
3003 for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
3004 {
3005 dmatxdesc = heth->Init.TxDesc + i;
3006
3007 WRITE_REG(dmatxdesc->DESC0, 0x0U);
3008 WRITE_REG(dmatxdesc->DESC1, 0x0U);
3009 WRITE_REG(dmatxdesc->DESC2, 0x0U);
3010 WRITE_REG(dmatxdesc->DESC3, 0x0U);
3011
3012 WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
3013
3014 }
3015
3016 heth->TxDescList.CurTxDesc = 0;
3017
3018 /* Set Transmit Descriptor Ring Length */
3019 WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U));
3020
3021 /* Set Transmit Descriptor List Address */
3022 WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
3023
3024 /* Set Transmit Descriptor Tail pointer */
3025 WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
3026 }
3027
3028 /**
3029 * @brief Initializes the DMA Rx descriptors in chain mode.
3030 * called by HAL_ETH_Init() API.
3031 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
3032 * the configuration information for ETHERNET module
3033 * @retval None
3034 */
3035 static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
3036 {
3037 ETH_DMADescTypeDef *dmarxdesc;
3038 uint32_t i;
3039
3040 for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
3041 {
3042 dmarxdesc = heth->Init.RxDesc + i;
3043
3044 WRITE_REG(dmarxdesc->DESC0, 0x0U);
3045 WRITE_REG(dmarxdesc->DESC1, 0x0U);
3046 WRITE_REG(dmarxdesc->DESC2, 0x0U);
3047 WRITE_REG(dmarxdesc->DESC3, 0x0U);
3048 WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
3049 WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
3050
3051 /* Set Rx descritors addresses */
3052 WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
3053
3054 }
3055
3056 WRITE_REG(heth->RxDescList.RxDescIdx, 0U);
3057 WRITE_REG(heth->RxDescList.RxDescCnt, 0U);
3058 WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U);
3059 WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U);
3060 WRITE_REG(heth->RxDescList.ItMode, 0U);
3061
3062 /* Set Receive Descriptor Ring Length */
3063 WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
3064
3065 /* Set Receive Descriptor List Address */
3066 WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
3067
3068 /* Set Receive Descriptor Tail pointer Address */
3069 WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U))));
3070 }
3071
3072 /**
3073 * @brief Prepare Tx DMA descriptor before transmission.
3074 * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
3075 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
3076 * the configuration information for ETHERNET module
3077 * @param pTxConfig: Tx packet configuration
3078 * @param ItMode: Enable or disable Tx EOT interrupt
3079 * @retval Status
3080 */
3081 static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
3082 uint32_t ItMode)
3083 {
3084 ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
3085 uint32_t descidx = dmatxdesclist->CurTxDesc;
3086 uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
3087 uint32_t idx;
3088 uint32_t descnbr = 0;
3089 ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
3090
3091 ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
3092 uint32_t bd_count = 0;
3093 uint32_t primask_bit;
3094
3095 /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
3096 if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
3097 || (dmatxdesclist->PacketAddress[descidx] != NULL))
3098 {
3099 return HAL_ETH_ERROR_BUSY;
3100 }
3101
3102 /***************************************************************************/
3103 /***************** Context descriptor configuration (Optional) **********/
3104 /***************************************************************************/
3105 /* If VLAN tag is enabled for this packet */
3106 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
3107 {
3108 /* Set vlan tag value */
3109 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
3110 /* Set vlan tag valid bit */
3111 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
3112 /* Set the descriptor as the vlan input source */
3113 SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
3114
3115 /* if inner VLAN is enabled */
3116 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET)
3117 {
3118 /* Set inner vlan tag value */
3119 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
3120 /* Set inner vlan tag valid bit */
3121 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
3122
3123 /* Set Vlan Tag control */
3124 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
3125
3126 /* Set the descriptor as the inner vlan input source */
3127 SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
3128 /* Enable double VLAN processing */
3129 SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
3130 }
3131 }
3132
3133 /* if tcp segmentation is enabled for this packet */
3134 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
3135 {
3136 /* Set MSS value */
3137 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
3138 /* Set MSS valid bit */
3139 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
3140 }
3141
3142 if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
3143 || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET))
3144 {
3145 /* Set as context descriptor */
3146 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
3147 /* Ensure rest of descriptor is written to RAM before the OWN bit */
3148 __DMB();
3149 /* Set own bit */
3150 SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
3151 /* Increment current tx descriptor index */
3152 INCR_TX_DESC_INDEX(descidx, 1U);
3153 /* Get current descriptor address */
3154 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
3155
3156 descnbr += 1U;
3157
3158 /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
3159 if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
3160 {
3161 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
3162 /* Ensure rest of descriptor is written to RAM before the OWN bit */
3163 __DMB();
3164 /* Clear own bit */
3165 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
3166
3167 return HAL_ETH_ERROR_BUSY;
3168 }
3169 }
3170
3171 /***************************************************************************/
3172 /***************** Normal descriptors configuration *****************/
3173 /***************************************************************************/
3174
3175 descnbr += 1U;
3176
3177 /* Set header or buffer 1 address */
3178 WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
3179 /* Set header or buffer 1 Length */
3180 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
3181
3182 if (txbuffer->next != NULL)
3183 {
3184 txbuffer = txbuffer->next;
3185 /* Set buffer 2 address */
3186 WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
3187 /* Set buffer 2 Length */
3188 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
3189 }
3190 else
3191 {
3192 WRITE_REG(dmatxdesc->DESC1, 0x0U);
3193 /* Set buffer 2 Length */
3194 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
3195 }
3196
3197 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
3198 {
3199 /* Set TCP Header length */
3200 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
3201 /* Set TCP payload length */
3202 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
3203 /* Set TCP Segmentation Enabled bit */
3204 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
3205 }
3206 else
3207 {
3208 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
3209
3210 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
3211 {
3212 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
3213 }
3214
3215 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET)
3216 {
3217 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
3218 }
3219 }
3220
3221 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
3222 {
3223 /* Set Vlan Tag control */
3224 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
3225 }
3226
3227 /* Mark it as First Descriptor */
3228 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
3229 /* Mark it as NORMAL descriptor */
3230 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
3231 /* Ensure rest of descriptor is written to RAM before the OWN bit */
3232 __DMB();
3233 /* set OWN bit of FIRST descriptor */
3234 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
3235
3236 /* If source address insertion/replacement is enabled for this packet */
3237 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET)
3238 {
3239 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
3240 }
3241
3242 /* only if the packet is split into more than one descriptors > 1 */
3243 while (txbuffer->next != NULL)
3244 {
3245 /* Clear the LD bit of previous descriptor */
3246 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
3247 /* Increment current tx descriptor index */
3248 INCR_TX_DESC_INDEX(descidx, 1U);
3249 /* Get current descriptor address */
3250 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
3251
3252 /* Clear the FD bit of new Descriptor */
3253 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
3254
3255 /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
3256 if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
3257 || (dmatxdesclist->PacketAddress[descidx] != NULL))
3258 {
3259 descidx = firstdescidx;
3260 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
3261
3262 /* clear previous desc own bit */
3263 for (idx = 0; idx < descnbr; idx ++)
3264 {
3265 /* Ensure rest of descriptor is written to RAM before the OWN bit */
3266 __DMB();
3267
3268 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
3269
3270 /* Increment current tx descriptor index */
3271 INCR_TX_DESC_INDEX(descidx, 1U);
3272 /* Get current descriptor address */
3273 dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
3274 }
3275
3276 return HAL_ETH_ERROR_BUSY;
3277 }
3278
3279 descnbr += 1U;
3280
3281 /* Get the next Tx buffer in the list */
3282 txbuffer = txbuffer->next;
3283
3284 /* Set header or buffer 1 address */
3285 WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
3286 /* Set header or buffer 1 Length */
3287 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
3288
3289 if (txbuffer->next != NULL)
3290 {
3291 /* Get the next Tx buffer in the list */
3292 txbuffer = txbuffer->next;
3293 /* Set buffer 2 address */
3294 WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
3295 /* Set buffer 2 Length */
3296 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
3297 }
3298 else
3299 {
3300 WRITE_REG(dmatxdesc->DESC1, 0x0U);
3301 /* Set buffer 2 Length */
3302 MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
3303 }
3304
3305 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
3306 {
3307 /* Set TCP payload length */
3308 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
3309 /* Set TCP Segmentation Enabled bit */
3310 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
3311 }
3312 else
3313 {
3314 /* Set the packet length */
3315 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
3316
3317 if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
3318 {
3319 /* Checksum Insertion Control */
3320 MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
3321 }
3322 }
3323
3324 bd_count += 1U;
3325
3326 /* Ensure rest of descriptor is written to RAM before the OWN bit */
3327 __DMB();
3328 /* Set Own bit */
3329 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
3330 /* Mark it as NORMAL descriptor */
3331 CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
3332 }
3333
3334 if (ItMode != ((uint32_t)RESET))
3335 {
3336 /* Set Interrupt on completion bit */
3337 SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
3338 }
3339 else
3340 {
3341 /* Clear Interrupt on completion bit */
3342 CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
3343 }
3344
3345 /* Mark it as LAST descriptor */
3346 SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
3347 /* Save the current packet address to expose it to the application */
3348 dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
3349
3350 dmatxdesclist->CurTxDesc = descidx;
3351
3352 /* Enter critical section */
3353 primask_bit = __get_PRIMASK();
3354 __set_PRIMASK(1);
3355
3356 dmatxdesclist->BuffersInUse += bd_count + 1U;
3357
3358 /* Exit critical section: restore previous priority mask */
3359 __set_PRIMASK(primask_bit);
3360
3361 /* Return function status */
3362 return HAL_ETH_ERROR_NONE;
3363 }
3364
3365 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
3366 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
3367 {
3368 /* Init the ETH Callback settings */
3369 heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
3370 heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
3371 heth->ErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */
3372 heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */
3373 heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */
3374 heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */
3375 heth->rxLinkCallback = HAL_ETH_RxLinkCallback; /* Legacy weak RxLinkCallback */
3376 heth->txFreeCallback = HAL_ETH_TxFreeCallback; /* Legacy weak TxFreeCallback */
3377 #ifdef HAL_ETH_USE_PTP
3378 heth->txPtpCallback = HAL_ETH_TxPtpCallback; /* Legacy weak TxPtpCallback */
3379 #endif /* HAL_ETH_USE_PTP */
3380 heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */
3381 }
3382 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
3383
3384 /**
3385 * @}
3386 */
3387
3388 /**
3389 * @}
3390 */
3391
3392 #endif /* ETH */
3393
3394 #endif /* HAL_ETH_MODULE_ENABLED */
3395
3396 /**
3397 * @}
3398 */
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