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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_i2s.c
blob864ea4b1989a28c50726e1d43b45a786ad2c56a1
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_i2s.c
4 * @author MCD Application Team
5 * @brief I2S HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 @verbatim
12 ===============================================================================
13 ##### How to use this driver #####
14 ===============================================================================
15 [..]
16 The I2S HAL driver can be used as follow:
17
18 (#) Declare a I2S_HandleTypeDef handle structure.
19 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
20 (##) Enable the SPIx interface clock.
21 (##) I2S pins configuration:
22 (+++) Enable the clock for the I2S GPIOs.
23 (+++) Configure these I2S pins as alternate function pull-up.
24 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
25 and HAL_I2S_Receive_IT() APIs).
26 (+++) Configure the I2Sx interrupt priority.
27 (+++) Enable the NVIC I2S IRQ handle.
28 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
29 and HAL_I2S_Receive_DMA() APIs:
30 (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
31 (+++) Enable the DMAx interface clock.
32 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
33 (+++) Configure the DMA Tx/Rx Stream/Channel.
34 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
35 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
36 DMA Tx/Rx Stream/Channel.
37
38 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
39 using HAL_I2S_Init() function.
40
41 -@- The specific I2S interrupts (Transmission complete interrupt,
42 RXNE interrupt and Error Interrupts) will be managed using the macros
43 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
44
45 (+@) External clock source is configured after setting correctly
46 the define constant EXTERNAL_CLOCK_VALUE in the stm32h7xx_hal_conf.h file.
47
48 (#) Three mode of operations are available within this driver :
49
50 *** Polling mode IO operation ***
51 =================================
52 [..]
53 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
54 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
55
56 *** Interrupt mode IO operation ***
57 ===================================
58 [..]
59 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
60 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
61 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
62 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
63 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
64 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
65 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
66 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
67 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
68 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
69 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
70 add his own code by customization of function pointer HAL_I2S_ErrorCallback
71
72 *** DMA mode IO operation ***
73 ==============================
74 [..]
75 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
76 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
77 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
78 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
79 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
80 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
81 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
82 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
83 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
84 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
85 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
86 add his own code by customization of function pointer HAL_I2S_ErrorCallback
87 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
88 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
89 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
90
91 *** I2S HAL driver macros list ***
92 ===================================
93 [..]
94 Below the list of most used macros in I2S HAL driver.
95
96 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
97 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
98 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
99 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
100 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
101
102 [..]
103 (@) You can refer to the I2S HAL driver header file for more useful macros
104
105 *** I2S HAL driver macros list ***
106 ===================================
107 [..]
108 Callback registration:
109
110 (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1UL
111 allows the user to configure dynamically the driver callbacks.
112 Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
113
114 Function HAL_I2S_RegisterCallback() allows to register following callbacks:
115 (+) TxCpltCallback : I2S Tx Completed callback
116 (+) RxCpltCallback : I2S Rx Completed callback
117 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
118 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
119 (+) ErrorCallback : I2S Error callback
120 (+) MspInitCallback : I2S Msp Init callback
121 (+) MspDeInitCallback : I2S Msp DeInit callback
122 This function takes as parameters the HAL peripheral handle, the Callback ID
123 and a pointer to the user callback function.
124
125
126 (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
127 weak function.
128 HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
129 and the Callback ID.
130 This function allows to reset following callbacks:
131 (+) TxCpltCallback : I2S Tx Completed callback
132 (+) RxCpltCallback : I2S Rx Completed callback
133 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
134 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
135 (+) ErrorCallback : I2S Error callback
136 (+) MspInitCallback : I2S Msp Init callback
137 (+) MspDeInitCallback : I2S Msp DeInit callback
138
139 By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
140 all callbacks are set to the corresponding weak functions:
141 examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
142 Exception done for MspInit and MspDeInit functions that are
143 reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
144 these callbacks are null (not registered beforehand).
145 If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
146 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
147
148 Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
149 Exception done MspInit/MspDeInit functions that can be registered/unregistered
150 in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
151 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
152 Then, the user first registers the MspInit/MspDeInit user callbacks
153 using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
154 or HAL_I2S_Init() function.
155
156 When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
157 not defined, the callback registering feature is not available
158 and weak (surcharged) callbacks are used.
159
160
161 @endverbatim
162 ******************************************************************************
163 * @attention
164 *
165 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
166 * All rights reserved.</center></h2>
167 *
168 * This software component is licensed by ST under BSD 3-Clause license,
169 * the "License"; You may not use this file except in compliance with the
170 * License. You may obtain a copy of the License at:
171 * opensource.org/licenses/BSD-3-Clause
172 *
173 ******************************************************************************
174 */
175
176 /* Includes ------------------------------------------------------------------*/
177 #include "stm32h7xx_hal.h"
178
179 #ifdef HAL_I2S_MODULE_ENABLED
180
181 /** @addtogroup STM32H7xx_HAL_Driver
182 * @{
183 */
184
185 /** @defgroup I2S I2S
186 * @brief I2S HAL module driver
187 * @{
188 */
189
190 /* Private typedef -----------------------------------------------------------*/
191 /* Private define ------------------------------------------------------------*/
192 #define I2S_TIMEOUT 0xFFFFUL
193
194 /* Private macro -------------------------------------------------------------*/
195 /* Private variables ---------------------------------------------------------*/
196 /* Private function prototypes -----------------------------------------------*/
197 /** @defgroup I2S_Private_Functions I2S Private Functions
198 * @{
199 */
200 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
201 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
202 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
203 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
204 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
205 static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s);
206 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s);
207 static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s);
208 static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s);
209 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
210 uint32_t Timeout);
211 /**
212 * @}
213 */
214
215 /* Exported functions ---------------------------------------------------------*/
216
217 /** @defgroup I2S_Exported_Functions I2S Exported Functions
218 * @{
219 */
220
221 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
222 * @brief Initialization and Configuration functions
223 *
224 @verbatim
225 ===============================================================================
226 ##### Initialization and de-initialization functions #####
227 ===============================================================================
228 [..] This subsection provides a set of functions allowing to initialize and
229 de-initialize the I2Sx peripheral in simplex mode:
230
231 (+) User must Implement HAL_I2S_MspInit() function in which he configures
232 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
233
234 (+) Call the function HAL_I2S_Init() to configure the selected device with
235 the selected configuration:
236 (++) Mode
237 (++) Standard
238 (++) Data Format
239 (++) MCLK Output
240 (++) Audio frequency
241 (++) Polarity
242
243 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
244 of the selected I2Sx peripheral.
245 @endverbatim
246 * @{
247 */
248
249 /**
250 * @brief Initializes the I2S according to the specified parameters
251 * in the I2S_InitTypeDef and create the associated handle.
252 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
253 * the configuration information for I2S module
254 * @retval HAL status
255 */
256 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
257 {
258 uint32_t i2sdiv;
259 uint32_t i2sodd;
260 uint32_t packetlength;
261 uint32_t tmp;
262 uint32_t i2sclk;
263 uint32_t ispcm;
264
265 /* Check the I2S handle allocation */
266 if (hi2s == NULL)
267 {
268 return HAL_ERROR;
269 }
270
271 /* Check the I2S parameters */
272 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
273 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
274 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
275 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
276 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
277 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
278 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
279 assert_param(IS_I2S_FIRST_BIT(hi2s->Init.FirstBit));
280 assert_param(IS_I2S_WS_INVERSION(hi2s->Init.WSInversion));
281 assert_param(IS_I2S_DATA_24BIT_ALIGNMENT(hi2s->Init.Data24BitAlignment));
282 assert_param(IS_I2S_MASTER_KEEP_IO_STATE(hi2s->Init.MasterKeepIOState));
283
284 if (hi2s->State == HAL_I2S_STATE_RESET)
285 {
286 /* Allocate lock resource and initialize it */
287 hi2s->Lock = HAL_UNLOCKED;
288
289 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
290 /* Init the I2S Callback settings */
291 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
292 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
293 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
294 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
295 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
296
297 if (hi2s->MspInitCallback == NULL)
298 {
299 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
300 }
301
302 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
303 hi2s->MspInitCallback(hi2s);
304 #else
305 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
306 HAL_I2S_MspInit(hi2s);
307 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
308 }
309
310 hi2s->State = HAL_I2S_STATE_BUSY;
311
312 /* Disable the selected I2S peripheral */
313 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
314 {
315 /* Disable I2S peripheral */
316 __HAL_I2S_DISABLE(hi2s);
317 }
318
319 /* Clear I2S configuration register */
320 CLEAR_REG(hi2s->Instance->I2SCFGR);
321
322 if (IS_I2S_MASTER(hi2s->Init.Mode))
323 {
324 /*------------------------- I2SDIV and ODD Calculation ---------------------*/
325 /* If the requested audio frequency is not the default, compute the prescaler */
326 if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
327 {
328 /* Check the frame length (For the Prescaler computing) ********************/
329 if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
330 {
331 /* Channel length is 32 bits */
332 packetlength = 2UL;
333 }
334 else
335 {
336 /* Channel length is 16 bits */
337 packetlength = 1UL;
338 }
339
340 /* Check if PCM standard is used */
341 if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||
342 (hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))
343 {
344 ispcm = 1UL;
345 }
346 else
347 {
348 ispcm = 0UL;
349 }
350
351 /* Get the source clock value: based on System Clock value */
352 #if defined (SPI_SPI6I2S_SUPPORT)
353 if (hi2s->Instance == SPI6)
354 {
355 /* SPI6 source clock */
356 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
357 }
358 else
359 {
360 /* SPI1,SPI2 and SPI3 share the same source clock */
361 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
362 }
363 #else
364 /* SPI1,SPI2 and SPI3 share the same source clock */
365 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
366 #endif
367
368 /* Compute the Real divider depending on the MCLK output state, with a floating point */
369 if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
370 {
371 /* MCLK output is enabled */
372 tmp = (uint32_t)((((i2sclk / (256UL >> ispcm)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
373 }
374 else
375 {
376 /* MCLK output is disabled */
377 tmp = (uint32_t)((((i2sclk / ((32UL >> ispcm) * packetlength)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
378 }
379
380 /* Remove the flatting point */
381 tmp = tmp / 10UL;
382
383 /* Check the parity of the divider */
384 i2sodd = (uint32_t)(tmp & (uint32_t)1UL);
385
386 /* Compute the i2sdiv prescaler */
387 i2sdiv = (uint32_t)((tmp - i2sodd) / 2UL);
388 }
389 else
390 {
391 /* Set the default values */
392 i2sdiv = 2UL;
393 i2sodd = 0UL;
394 }
395
396 /* Test if the obtain values are forbidden or out of range */
397 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
398 {
399 /* Set the error code */
400 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
401 return HAL_ERROR;
402 }
403
404 /* Force i2smod to 1 just to be sure that (2xi2sdiv + i2sodd) is always higher than 0 */
405 if (i2sdiv == 0UL)
406 {
407 i2sodd = 1UL;
408 }
409
410 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD),
411 ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
412 }
413
414 /*-------------------------- I2Sx I2SCFGR Configuration --------------------*/
415 /* Configure I2SMOD, I2SCFG, I2SSTD, PCMSYNC, DATLEN ,CHLEN ,CKPOL, WSINV, DATAFMT, I2SDIV, ODD and MCKOE bits bits */
416 /* And configure the I2S with the I2S_InitStruct values */
417 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG | \
418 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | \
419 SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | \
420 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_WSINV | \
421 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_MCKOE),
422 (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
423 hi2s->Init.Standard | hi2s->Init.DataFormat | \
424 hi2s->Init.CPOL | hi2s->Init.WSInversion | \
425 hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
426 /*Clear status register*/
427 WRITE_REG(hi2s->Instance->IFCR, 0x0FF8);
428
429 /*---------------------------- I2Sx CFG2 Configuration ----------------------*/
430
431 /* Unlock the AF configuration to configure CFG2 register*/
432 CLEAR_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK);
433
434 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST, hi2s->Init.FirstBit);
435
436 /* Insure that AFCNTR is managed only by Master */
437 if (IS_I2S_MASTER(hi2s->Init.Mode))
438 {
439 /* Alternate function GPIOs control */
440 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState));
441 }
442
443 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
444 hi2s->State = HAL_I2S_STATE_READY;
445
446 return HAL_OK;
447 }
448
449 /**
450 * @brief DeInitializes the I2S peripheral
451 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
452 * the configuration information for I2S module
453 * @retval HAL status
454 */
455 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
456 {
457 /* Check the I2S handle allocation */
458 if (hi2s == NULL)
459 {
460 return HAL_ERROR;
461 }
462
463 /* Check the parameters */
464 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
465
466 hi2s->State = HAL_I2S_STATE_BUSY;
467
468 /* Disable the I2S Peripheral Clock */
469 __HAL_I2S_DISABLE(hi2s);
470
471 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
472 if (hi2s->MspDeInitCallback == NULL)
473 {
474 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
475 }
476
477 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
478 hi2s->MspDeInitCallback(hi2s);
479 #else
480 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
481 HAL_I2S_MspDeInit(hi2s);
482 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
483
484 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
485 hi2s->State = HAL_I2S_STATE_RESET;
486
487 /* Release Lock */
488 __HAL_UNLOCK(hi2s);
489
490 return HAL_OK;
491 }
492
493 /**
494 * @brief I2S MSP Init
495 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
496 * the configuration information for I2S module
497 * @retval None
498 */
499 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
500 {
501 /* Prevent unused argument(s) compilation warning */
502 UNUSED(hi2s);
503
504 /* NOTE : This function Should not be modified, when the callback is needed,
505 the HAL_I2S_MspInit could be implemented in the user file
506 */
507 }
508
509 /**
510 * @brief I2S MSP DeInit
511 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
512 * the configuration information for I2S module
513 * @retval None
514 */
515 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
516 {
517 /* Prevent unused argument(s) compilation warning */
518 UNUSED(hi2s);
519
520 /* NOTE : This function Should not be modified, when the callback is needed,
521 the HAL_I2S_MspDeInit could be implemented in the user file
522 */
523 }
524
525 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
526 /**
527 * @brief Register a User I2S Callback
528 * To be used instead of the weak predefined callback
529 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
530 * the configuration information for the specified I2S.
531 * @param CallbackID ID of the callback to be registered
532 * @param pCallback pointer to the Callback function
533 * @retval HAL status
534 */
535 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
536 {
537 HAL_StatusTypeDef status = HAL_OK;
538
539 if (pCallback == NULL)
540 {
541 /* Update the error code */
542 hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
543
544 return HAL_ERROR;
545 }
546 /* Process locked */
547 __HAL_LOCK(hi2s);
548
549 if (HAL_I2S_STATE_READY == hi2s->State)
550 {
551 switch (CallbackID)
552 {
553 case HAL_I2S_TX_COMPLETE_CB_ID :
554 hi2s->TxCpltCallback = pCallback;
555 break;
556
557 case HAL_I2S_RX_COMPLETE_CB_ID :
558 hi2s->RxCpltCallback = pCallback;
559 break;
560
561 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
562 hi2s->TxHalfCpltCallback = pCallback;
563 break;
564
565 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
566 hi2s->RxHalfCpltCallback = pCallback;
567 break;
568
569 case HAL_I2S_ERROR_CB_ID :
570 hi2s->ErrorCallback = pCallback;
571 break;
572
573 case HAL_I2S_MSPINIT_CB_ID :
574 hi2s->MspInitCallback = pCallback;
575 break;
576
577 case HAL_I2S_MSPDEINIT_CB_ID :
578 hi2s->MspDeInitCallback = pCallback;
579 break;
580
581 default :
582 /* Update the error code */
583 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
584
585 /* Return error status */
586 status = HAL_ERROR;
587 break;
588 }
589 }
590 else if (HAL_I2S_STATE_RESET == hi2s->State)
591 {
592 switch (CallbackID)
593 {
594 case HAL_I2S_MSPINIT_CB_ID :
595 hi2s->MspInitCallback = pCallback;
596 break;
597
598 case HAL_I2S_MSPDEINIT_CB_ID :
599 hi2s->MspDeInitCallback = pCallback;
600 break;
601
602 default :
603 /* Update the error code */
604 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
605
606 /* Return error status */
607 status = HAL_ERROR;
608 break;
609 }
610 }
611 else
612 {
613 /* Update the error code */
614 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
615
616 /* Return error status */
617 status = HAL_ERROR;
618 }
619
620 /* Release Lock */
621 __HAL_UNLOCK(hi2s);
622 return status;
623 }
624
625 /**
626 * @brief Unregister an I2S Callback
627 * I2S callback is redirected to the weak predefined callback
628 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
629 * the configuration information for the specified I2S.
630 * @param CallbackID ID of the callback to be unregistered
631 * @retval HAL status
632 */
633 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
634 {
635 HAL_StatusTypeDef status = HAL_OK;
636
637 /* Process locked */
638 __HAL_LOCK(hi2s);
639
640 if (HAL_I2S_STATE_READY == hi2s->State)
641 {
642 switch (CallbackID)
643 {
644 case HAL_I2S_TX_COMPLETE_CB_ID :
645 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
646 break;
647
648 case HAL_I2S_RX_COMPLETE_CB_ID :
649 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
650 break;
651
652 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
653 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
654 break;
655
656 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
657 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
658 break;
659
660 case HAL_I2S_ERROR_CB_ID :
661 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
662 break;
663
664 case HAL_I2S_MSPINIT_CB_ID :
665 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
666 break;
667
668 case HAL_I2S_MSPDEINIT_CB_ID :
669 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
670 break;
671
672 default :
673 /* Update the error code */
674 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
675
676 /* Return error status */
677 status = HAL_ERROR;
678 break;
679 }
680 }
681 else if (HAL_I2S_STATE_RESET == hi2s->State)
682 {
683 switch (CallbackID)
684 {
685 case HAL_I2S_MSPINIT_CB_ID :
686 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
687 break;
688
689 case HAL_I2S_MSPDEINIT_CB_ID :
690 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
691 break;
692
693 default :
694 /* Update the error code */
695 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
696
697 /* Return error status */
698 status = HAL_ERROR;
699 break;
700 }
701 }
702 else
703 {
704 /* Update the error code */
705 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
706
707 /* Return error status */
708 status = HAL_ERROR;
709 }
710
711 /* Release Lock */
712 __HAL_UNLOCK(hi2s);
713 return status;
714 }
715 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
716 /**
717 * @}
718 */
719
720 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
721 * @brief Data transfers functions
722 *
723 @verbatim
724 ===============================================================================
725 ##### IO operation functions #####
726 ===============================================================================
727 [..]
728 This subsection provides a set of functions allowing to manage the I2S data
729 transfers.
730
731 (#) There are two modes of transfer:
732 (++) Blocking mode : The communication is performed in the polling mode.
733 The status of all data processing is returned by the same function
734 after finishing transfer.
735 (++) No-Blocking mode : The communication is performed using Interrupts
736 or DMA. These functions return the status of the transfer startup.
737 The end of the data processing will be indicated through the
738 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
739 using DMA mode.
740
741 (#) Blocking mode functions are :
742 (++) HAL_I2S_Transmit()
743 (++) HAL_I2S_Receive()
744
745 (#) No-Blocking mode functions with Interrupt are :
746 (++) HAL_I2S_Transmit_IT()
747 (++) HAL_I2S_Receive_IT()
748
749 (#) No-Blocking mode functions with DMA are :
750 (++) HAL_I2S_Transmit_DMA()
751 (++) HAL_I2S_Receive_DMA()
752
753 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
754 (++) HAL_I2S_TxCpltCallback()
755 (++) HAL_I2S_RxCpltCallback()
756 (++) HAL_I2S_ErrorCallback()
757
758 @endverbatim
759 * @{
760 */
761
762 /**
763 * @brief Transmit an amount of data in blocking mode
764 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
765 * the configuration information for I2S module
766 * @param pData a 16-bit pointer to data buffer.
767 * @param Size number of data sample to be sent:
768 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
769 * configuration phase, the Size parameter means the number of 16-bit data length
770 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
771 * the Size parameter means the number of 16-bit data length.
772 * @param Timeout Timeout duration
773 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
774 * between Master and Slave(example: audio streaming).
775 * @retval HAL status
776 */
777 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
778 {
779 #if defined (__GNUC__)
780 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
781 #endif /* __GNUC__ */
782
783 if ((pData == NULL) || (Size == 0UL))
784 {
785 return HAL_ERROR;
786 }
787
788 /* Process Locked */
789 __HAL_LOCK(hi2s);
790
791 if (hi2s->State != HAL_I2S_STATE_READY)
792 {
793 __HAL_UNLOCK(hi2s);
794 return HAL_BUSY;
795 }
796
797 /* Set state and reset error code */
798 hi2s->State = HAL_I2S_STATE_BUSY_TX;
799 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
800 hi2s->pTxBuffPtr = pData;
801 hi2s->TxXferSize = Size;
802 hi2s->TxXferCount = Size;
803
804 /* Initialize fields not used in handle to zero */
805 hi2s->pRxBuffPtr = NULL;
806 hi2s->RxXferSize = (uint16_t) 0UL;
807 hi2s->RxXferCount = (uint16_t) 0UL;
808
809 /* Check if the I2S is already enabled */
810 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
811 {
812 /* Enable I2S peripheral */
813 __HAL_I2S_ENABLE(hi2s);
814 }
815
816 /* Start the transfer */
817 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
818
819
820 /* Wait until TXP flag is set */
821 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK)
822 {
823 /* Set the error code */
824 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
825 hi2s->State = HAL_I2S_STATE_READY;
826 __HAL_UNLOCK(hi2s);
827 return HAL_ERROR;
828 }
829
830 while (hi2s->TxXferCount > 0UL)
831 {
832 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
833 {
834 /* Transmit data in 32 Bit mode */
835 hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
836 hi2s->pTxBuffPtr += 2;
837 hi2s->TxXferCount--;
838 }
839 else
840 {
841 /* Transmit data in 16 Bit mode */
842 #if defined (__GNUC__)
843 *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
844 #else
845 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
846 #endif /* __GNUC__ */
847
848 hi2s->pTxBuffPtr++;
849 hi2s->TxXferCount--;
850 }
851
852 /* Wait until TXP flag is set */
853 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK)
854 {
855 /* Set the error code */
856 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
857 hi2s->State = HAL_I2S_STATE_READY;
858 __HAL_UNLOCK(hi2s);
859 return HAL_ERROR;
860 }
861
862 /* Check if an underrun occurs */
863 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
864 {
865 /* Clear underrun flag */
866 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
867
868 /* Set the error code */
869 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
870 }
871 }
872
873 hi2s->State = HAL_I2S_STATE_READY;
874 __HAL_UNLOCK(hi2s);
875 return HAL_OK;
876 }
877
878 /**
879 * @brief Receive an amount of data in blocking mode
880 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
881 * the configuration information for I2S module
882 * @param pData a 16-bit pointer to data buffer.
883 * @param Size number of data sample to be sent:
884 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
885 * configuration phase, the Size parameter means the number of 16-bit data length
886 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
887 * the Size parameter means the number of 16-bit data length.
888 * @param Timeout Timeout duration
889 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
890 * between Master and Slave(example: audio streaming).
891 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
892 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
893 * @retval HAL status
894 */
895 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
896 {
897 #if defined (__GNUC__)
898 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
899 #endif /* __GNUC__ */
900
901 if ((pData == NULL) || (Size == 0UL))
902 {
903 return HAL_ERROR;
904 }
905
906 /* Process Locked */
907 __HAL_LOCK(hi2s);
908
909 if (hi2s->State != HAL_I2S_STATE_READY)
910 {
911 __HAL_UNLOCK(hi2s);
912 return HAL_BUSY;
913 }
914
915 /* Set state and reset error code */
916 hi2s->State = HAL_I2S_STATE_BUSY_RX;
917 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
918 hi2s->pRxBuffPtr = pData;
919 hi2s->RxXferSize = Size;
920 hi2s->RxXferCount = Size;
921
922 /* Initialize fields not used in handle to zero */
923 hi2s->pTxBuffPtr = NULL;
924 hi2s->TxXferSize = (uint16_t) 0UL;
925 hi2s->TxXferCount = (uint16_t) 0UL;
926
927 /* Check if the I2S is already enabled */
928 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
929 {
930 /* Enable I2S peripheral */
931 __HAL_I2S_ENABLE(hi2s);
932 }
933
934 /* Start the transfer */
935 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
936
937 /* Receive data */
938 while (hi2s->RxXferCount > 0UL)
939 {
940 /* Wait until RXNE flag is set */
941 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, Timeout) != HAL_OK)
942 {
943 /* Set the error code */
944 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
945 hi2s->State = HAL_I2S_STATE_READY;
946 __HAL_UNLOCK(hi2s);
947 return HAL_ERROR;
948 }
949
950 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
951 {
952 /* Receive data in 32 Bit mode */
953 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
954 hi2s->pRxBuffPtr += 2;
955 hi2s->RxXferCount--;
956 }
957 else
958 {
959 /* Receive data in 16 Bit mode */
960 #if defined (__GNUC__)
961 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
962 #else
963 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
964 #endif /* __GNUC__ */
965 hi2s->pRxBuffPtr++;
966 hi2s->RxXferCount--;
967 }
968
969 /* Check if an overrun occurs */
970 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
971 {
972 /* Clear overrun flag */
973 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
974
975 /* Set the error code */
976 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
977 }
978 }
979
980 hi2s->State = HAL_I2S_STATE_READY;
981 __HAL_UNLOCK(hi2s);
982 return HAL_OK;
983 }
984
985 /**
986 * @brief Transmit an amount of data in non-blocking mode with Interrupt
987 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
988 * the configuration information for I2S module
989 * @param pData a 16-bit pointer to data buffer.
990 * @param Size number of data sample to be sent:
991 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
992 * configuration phase, the Size parameter means the number of 16-bit data length
993 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
994 * the Size parameter means the number of 16-bit data length.
995 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
996 * between Master and Slave(example: audio streaming).
997 * @retval HAL status
998 */
999 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1000 {
1001 if ((pData == NULL) || (Size == 0UL))
1002 {
1003 return HAL_ERROR;
1004 }
1005
1006 /* Process Locked */
1007 __HAL_LOCK(hi2s);
1008
1009 if (hi2s->State != HAL_I2S_STATE_READY)
1010 {
1011 __HAL_UNLOCK(hi2s);
1012 return HAL_BUSY;
1013 }
1014
1015 /* Set state and reset error code */
1016 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1017 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1018 hi2s->pTxBuffPtr = (uint16_t *)pData;
1019 hi2s->TxXferSize = Size;
1020 hi2s->TxXferCount = Size;
1021
1022 /* Initialize fields not used in handle to zero */
1023 hi2s->pRxBuffPtr = NULL;
1024 hi2s->RxXferSize = (uint16_t) 0UL;
1025 hi2s->RxXferCount = (uint16_t) 0UL;
1026
1027 /* Set the function for IT treatment */
1028 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1029 {
1030 hi2s->TxISR = I2S_Transmit_32Bit_IT;
1031 }
1032 else
1033 {
1034 hi2s->TxISR = I2S_Transmit_16Bit_IT;
1035 }
1036
1037 /* Check if the I2S is already enabled */
1038 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1039 {
1040 /* Enable I2S peripheral */
1041 __HAL_I2S_ENABLE(hi2s);
1042 }
1043
1044 /* Enable TXP and UDR interrupt */
1045 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_UDR));
1046
1047 /* Enable TIFRE interrupt if the mode is Slave */
1048 if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
1049 {
1050 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1051 }
1052
1053 /* Start the transfer */
1054 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1055
1056 __HAL_UNLOCK(hi2s);
1057 return HAL_OK;
1058 }
1059
1060 /**
1061 * @brief Receive an amount of data in non-blocking mode with Interrupt
1062 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1063 * the configuration information for I2S module
1064 * @param pData a 16-bit pointer to the Receive data buffer.
1065 * @param Size number of data sample to be sent:
1066 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1067 * configuration phase, the Size parameter means the number of 16-bit data length
1068 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1069 * the Size parameter means the number of 16-bit data length.
1070 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1071 * between Master and Slave(example: audio streaming).
1072 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
1073 * between Master and Slave otherwise the I2S interrupt should be optimized.
1074 * @retval HAL status
1075 */
1076 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1077 {
1078 if ((pData == NULL) || (Size == 0UL))
1079 {
1080 return HAL_ERROR;
1081 }
1082
1083 /* Process Locked */
1084 __HAL_LOCK(hi2s);
1085
1086 if (hi2s->State != HAL_I2S_STATE_READY)
1087 {
1088 __HAL_UNLOCK(hi2s);
1089 return HAL_BUSY;
1090 }
1091
1092 /* Set state and reset error code */
1093 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1094 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1095 hi2s->pRxBuffPtr = pData;
1096 hi2s->RxXferSize = Size;
1097 hi2s->RxXferCount = Size;
1098
1099 /* Initialize fields not used in handle to zero */
1100 hi2s->pTxBuffPtr = NULL;
1101 hi2s->TxXferSize = (uint16_t) 0UL;
1102 hi2s->TxXferCount = (uint16_t) 0UL;
1103
1104 /* Set the function for IT treatment */
1105 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1106 {
1107 hi2s->RxISR = I2S_Receive_32Bit_IT;
1108 }
1109 else
1110 {
1111 hi2s->RxISR = I2S_Receive_16Bit_IT;
1112 }
1113
1114 /* Check if the I2S is already enabled */
1115 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1116 {
1117 /* Enable I2S peripheral */
1118 __HAL_I2S_ENABLE(hi2s);
1119 }
1120 /* Enable RXNE and ERR interrupt */
1121 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_OVR));
1122
1123 /* Enable TIFRE interrupt if the mode is Slave */
1124 if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
1125 {
1126 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1127 }
1128
1129 /* Start the transfer */
1130 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1131
1132 __HAL_UNLOCK(hi2s);
1133 return HAL_OK;
1134 }
1135
1136 /**
1137 * @brief Transmit an amount of data in non-blocking mode with DMA
1138 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1139 * the configuration information for I2S module
1140 * @param pData a 16-bit pointer to the Transmit data buffer.
1141 * @param Size number of data sample to be sent:
1142 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1143 * configuration phase, the Size parameter means the number of 16-bit data length
1144 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1145 * the Size parameter means the number of 16-bit data length.
1146 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1147 * between Master and Slave(example: audio streaming).
1148 * @retval HAL status
1149 */
1150 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1151 {
1152 if ((pData == NULL) || (Size == 0UL))
1153 {
1154 return HAL_ERROR;
1155 }
1156
1157 /* Process Locked */
1158 __HAL_LOCK(hi2s);
1159
1160 if (hi2s->State != HAL_I2S_STATE_READY)
1161 {
1162 __HAL_UNLOCK(hi2s);
1163 return HAL_BUSY;
1164 }
1165
1166 /* Set state and reset error code */
1167 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1168 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1169 hi2s->pTxBuffPtr = pData;
1170 hi2s->TxXferSize = Size;
1171 hi2s->TxXferCount = Size;
1172
1173 /* Init field not used in handle to zero */
1174 hi2s->pRxBuffPtr = NULL;
1175 hi2s->RxXferSize = (uint16_t)0UL;
1176 hi2s->RxXferCount = (uint16_t)0UL;
1177
1178 /* Set the I2S Tx DMA Half transfer complete callback */
1179 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
1180
1181 /* Set the I2S Tx DMA transfer complete callback */
1182 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
1183
1184 /* Set the DMA error callback */
1185 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
1186
1187 /* Enable the Tx DMA Stream/Channel */
1188 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
1189 {
1190 /* Update SPI error code */
1191 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1192 hi2s->State = HAL_I2S_STATE_READY;
1193
1194 __HAL_UNLOCK(hi2s);
1195 return HAL_ERROR;
1196 }
1197
1198 /* Check if the I2S Tx request is already enabled */
1199 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
1200 {
1201 /* Enable Tx DMA Request */
1202 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1203 }
1204
1205 /* Check if the I2S is already enabled */
1206 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1207 {
1208 /* Enable I2S peripheral */
1209 __HAL_I2S_ENABLE(hi2s);
1210 }
1211
1212 /* Start the transfer */
1213 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1214
1215 __HAL_UNLOCK(hi2s);
1216 return HAL_OK;
1217 }
1218
1219 /**
1220 * @brief Receive an amount of data in non-blocking mode with DMA
1221 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1222 * the configuration information for I2S module
1223 * @param pData a 16-bit pointer to the Receive data buffer.
1224 * @param Size number of data sample to be sent:
1225 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1226 * configuration phase, the Size parameter means the number of 16-bit data length
1227 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1228 * the Size parameter means the number of 16-bit data length.
1229 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1230 * between Master and Slave(example: audio streaming).
1231 * @retval HAL status
1232 */
1233 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1234 {
1235 if ((pData == NULL) || (Size == 0UL))
1236 {
1237 return HAL_ERROR;
1238 }
1239
1240 /* Process Locked */
1241 __HAL_LOCK(hi2s);
1242
1243 if (hi2s->State != HAL_I2S_STATE_READY)
1244 {
1245 __HAL_UNLOCK(hi2s);
1246 return HAL_BUSY;
1247 }
1248
1249 /* Set state and reset error code */
1250 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1251 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1252 hi2s->pRxBuffPtr = pData;
1253 hi2s->RxXferSize = Size;
1254 hi2s->RxXferCount = Size;
1255
1256 /* Init field not used in handle to zero */
1257 hi2s->pTxBuffPtr = NULL;
1258 hi2s->TxXferSize = (uint16_t)0UL;
1259 hi2s->TxXferCount = (uint16_t)0UL;
1260
1261
1262 /* Set the I2S Rx DMA Half transfer complete callback */
1263 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
1264
1265 /* Set the I2S Rx DMA transfer complete callback */
1266 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
1267
1268 /* Set the DMA error callback */
1269 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
1270
1271 /* Enable the Rx DMA Stream/Channel */
1272 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
1273 {
1274 /* Update SPI error code */
1275 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1276 hi2s->State = HAL_I2S_STATE_READY;
1277
1278 __HAL_UNLOCK(hi2s);
1279 return HAL_ERROR;
1280 }
1281
1282 /* Check if the I2S Rx request is already enabled */
1283 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
1284 {
1285 /* Enable Rx DMA Request */
1286 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1287 }
1288
1289 /* Check if the I2S is already enabled */
1290 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1291 {
1292 /* Enable I2S peripheral */
1293 __HAL_I2S_ENABLE(hi2s);
1294 }
1295
1296 /* Start the transfer */
1297 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1298
1299 __HAL_UNLOCK(hi2s);
1300 return HAL_OK;
1301 }
1302
1303 /**
1304 * @brief Pauses the audio DMA Stream/Channel playing from the Media.
1305 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1306 * the configuration information for I2S module
1307 * @retval HAL status
1308 */
1309 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
1310 {
1311 /* Process Locked */
1312 __HAL_LOCK(hi2s);
1313
1314 uint32_t tickstart;
1315
1316 /* Get tick */
1317 tickstart = HAL_GetTick();
1318
1319
1320 /* Check if the I2S peripheral is in master mode */
1321 if (IS_I2S_MASTER(hi2s->Init.Mode))
1322 {
1323 /* Check if there is a transfer on-going */
1324 if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL)
1325 {
1326 /* Set error code to no on going transfer */
1327 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NO_OGT);
1328 hi2s->State = HAL_I2S_STATE_READY;
1329
1330 __HAL_UNLOCK(hi2s);
1331 return HAL_ERROR;
1332 }
1333
1334 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSUSP);
1335
1336 while (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) != 0UL)
1337 {
1338 if ((((HAL_GetTick() - tickstart) >= I2S_TIMEOUT) && (I2S_TIMEOUT != HAL_MAX_DELAY)) || (I2S_TIMEOUT == 0U))
1339 {
1340 /* Set the I2S State ready */
1341 hi2s->State = HAL_I2S_STATE_READY;
1342
1343 /* Process Unlocked */
1344 __HAL_UNLOCK(hi2s);
1345
1346 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
1347 hi2s->State = HAL_I2S_STATE_READY;
1348 return HAL_TIMEOUT;
1349 }
1350 }
1351
1352 /* Disable I2S peripheral */
1353 __HAL_I2S_DISABLE(hi2s);
1354
1355 hi2s->State = HAL_I2S_STATE_READY;
1356
1357 /* Process Unlocked */
1358 __HAL_UNLOCK(hi2s);
1359
1360 return HAL_OK;
1361 }
1362 else
1363 {
1364 /* Set error code to not supported */
1365 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NOT_SUPPORTED);
1366 hi2s->State = HAL_I2S_STATE_READY;
1367
1368 /* Process Unlocked */
1369 __HAL_UNLOCK(hi2s);
1370
1371 return HAL_ERROR;
1372 }
1373 }
1374
1375 /**
1376 * @brief Resumes the audio DMA Stream/Channel playing from the Media.
1377 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1378 * the configuration information for I2S module
1379 * @retval HAL status
1380 */
1381 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
1382 {
1383 /* Process Locked */
1384 __HAL_LOCK(hi2s);
1385
1386 if (hi2s->State != HAL_I2S_STATE_READY)
1387 {
1388 hi2s->State = HAL_I2S_STATE_READY;
1389
1390 __HAL_UNLOCK(hi2s);
1391 return HAL_ERROR;
1392 }
1393
1394 /* Set state and reset error code */
1395 hi2s->State = HAL_I2S_STATE_BUSY;
1396 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1397
1398 /* Enable I2S peripheral */
1399 __HAL_I2S_ENABLE(hi2s);
1400
1401 /* Start the transfer */
1402 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1403
1404 /* Process Unlocked */
1405 __HAL_UNLOCK(hi2s);
1406
1407 return HAL_OK;
1408 }
1409
1410 /**
1411 * @brief Stops the audio DMA Stream/Channel playing from the Media.
1412 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1413 * the configuration information for I2S module
1414 * @retval HAL status
1415 */
1416 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
1417 {
1418 HAL_StatusTypeDef errorcode = HAL_OK;
1419 /* The Lock is not implemented on this API to allow the user application
1420 to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1421 when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
1422 and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1423 */
1424
1425 /* Disable the I2S Tx/Rx DMA requests */
1426 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1427 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1428
1429 /* Abort the I2S DMA tx Stream/Channel */
1430 if (hi2s->hdmatx != NULL)
1431 {
1432 /* Disable the I2S DMA tx Stream/Channel */
1433 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
1434 {
1435 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1436 errorcode = HAL_ERROR;
1437 }
1438 }
1439
1440 /* Abort the I2S DMA rx Stream/Channel */
1441 if (hi2s->hdmarx != NULL)
1442 {
1443 /* Disable the I2S DMA rx Stream/Channel */
1444 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
1445 {
1446 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1447 errorcode = HAL_ERROR;
1448 }
1449 }
1450
1451 /* Disable I2S peripheral */
1452 __HAL_I2S_DISABLE(hi2s);
1453
1454 hi2s->State = HAL_I2S_STATE_READY;
1455
1456 return errorcode;
1457 }
1458
1459 /**
1460 * @brief This function handles I2S interrupt request.
1461 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1462 * the configuration information for I2S module
1463 * @retval None
1464 */
1465 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
1466 {
1467 uint32_t itsource = hi2s->Instance->IER;
1468 uint32_t itflag = hi2s->Instance->SR;
1469 uint32_t trigger = itsource & itflag;
1470
1471 /* I2S in mode Receiver ------------------------------------------------*/
1472 if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) && HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP))
1473 {
1474 hi2s->RxISR(hi2s);
1475 }
1476
1477 /* I2S in mode Transmitter -----------------------------------------------*/
1478 if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) == RESET) && HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP))
1479 {
1480 hi2s->TxISR(hi2s);
1481 }
1482
1483 /* I2S interrupt error ----------------------------------------------------*/
1484 if ((trigger & (I2S_FLAG_OVR| I2S_FLAG_UDR | I2S_FLAG_FRE)) != 0UL)
1485 {
1486 /* I2S Overrun error interrupt occurred ---------------------------------*/
1487 if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
1488 {
1489 /* Disable RXP and ERR interrupt */
1490 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
1491
1492 /* Set the error code and execute error callback*/
1493 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1494 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1495 }
1496
1497 /* I2S Underrun error interrupt occurred --------------------------------*/
1498 if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
1499 {
1500 /* Disable TXP and ERR interrupt */
1501 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
1502
1503 /* Set the error code and execute error callback*/
1504 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
1505 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
1506 }
1507
1508 /* I2S Frame error interrupt occurred -----------------------------------*/
1509 if (I2S_CHECK_FLAG(itflag, I2S_FLAG_FRE) != RESET)
1510 {
1511 /* Disable FRE and ERR interrupt */
1512 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_FRE | I2S_IT_ERR));
1513
1514 /* Set the error code and execute error callback*/
1515 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_FRE);
1516 __HAL_I2S_CLEAR_FREFLAG(hi2s);
1517 }
1518
1519 /* Set the I2S State ready */
1520 hi2s->State = HAL_I2S_STATE_READY;
1521
1522 /* Call user error callback */
1523 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1524 hi2s->ErrorCallback(hi2s);
1525 #else
1526 HAL_I2S_ErrorCallback(hi2s);
1527 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1528 }
1529 }
1530
1531 /**
1532 * @brief Tx Transfer Half completed callbacks
1533 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1534 * the configuration information for I2S module
1535 * @retval None
1536 */
1537 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1538 {
1539 /* Prevent unused argument(s) compilation warning */
1540 UNUSED(hi2s);
1541
1542 /* NOTE : This function Should not be modified, when the callback is needed,
1543 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
1544 */
1545 }
1546
1547 /**
1548 * @brief Tx Transfer completed callbacks
1549 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1550 * the configuration information for I2S module
1551 * @retval None
1552 */
1553 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
1554 {
1555 /* Prevent unused argument(s) compilation warning */
1556 UNUSED(hi2s);
1557
1558 /* NOTE : This function Should not be modified, when the callback is needed,
1559 the HAL_I2S_TxCpltCallback could be implemented in the user file
1560 */
1561 }
1562
1563 /**
1564 * @brief Rx Transfer half completed callbacks
1565 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1566 * the configuration information for I2S module
1567 * @retval None
1568 */
1569 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1570 {
1571 /* Prevent unused argument(s) compilation warning */
1572 UNUSED(hi2s);
1573
1574 /* NOTE : This function Should not be modified, when the callback is needed,
1575 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
1576 */
1577 }
1578
1579 /**
1580 * @brief Rx Transfer completed callbacks
1581 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1582 * the configuration information for I2S module
1583 * @retval None
1584 */
1585 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
1586 {
1587 /* Prevent unused argument(s) compilation warning */
1588 UNUSED(hi2s);
1589
1590 /* NOTE : This function Should not be modified, when the callback is needed,
1591 the HAL_I2S_RxCpltCallback could be implemented in the user file
1592 */
1593 }
1594
1595 /**
1596 * @brief I2S error callbacks
1597 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1598 * the configuration information for I2S module
1599 * @retval None
1600 */
1601 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
1602 {
1603 /* Prevent unused argument(s) compilation warning */
1604 UNUSED(hi2s);
1605
1606 /* NOTE : This function Should not be modified, when the callback is needed,
1607 the HAL_I2S_ErrorCallback could be implemented in the user file
1608 */
1609 }
1610
1611 /**
1612 * @}
1613 */
1614
1615 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
1616 * @brief Peripheral State functions
1617 *
1618 @verbatim
1619 ===============================================================================
1620 ##### Peripheral State and Errors functions #####
1621 ===============================================================================
1622 [..]
1623 This subsection permits to get in run-time the status of the peripheral
1624 and the data flow.
1625
1626 @endverbatim
1627 * @{
1628 */
1629
1630 /**
1631 * @brief Return the I2S state
1632 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1633 * the configuration information for I2S module
1634 * @retval HAL state
1635 */
1636 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
1637 {
1638 return hi2s->State;
1639 }
1640
1641 /**
1642 * @brief Return the I2S error code
1643 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1644 * the configuration information for I2S module
1645 * @retval I2S Error Code
1646 */
1647 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
1648 {
1649 return hi2s->ErrorCode;
1650 }
1651 /**
1652 * @}
1653 */
1654
1655
1656 /**
1657 * @brief DMA I2S transmit process complete callback
1658 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1659 * the configuration information for the specified DMA module.
1660 * @retval None
1661 */
1662 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
1663 {
1664 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1665
1666 /* if DMA is configured in DMA_NORMAL Mode */
1667 if (hdma->Init.Mode == DMA_NORMAL)
1668 {
1669 /* Disable Tx DMA Request */
1670 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1671
1672 hi2s->TxXferCount = (uint16_t) 0UL;
1673 hi2s->State = HAL_I2S_STATE_READY;
1674 }
1675 /* Call user Tx complete callback */
1676 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1677 hi2s->TxCpltCallback(hi2s);
1678 #else
1679 HAL_I2S_TxCpltCallback(hi2s);
1680 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1681 }
1682
1683 /**
1684 * @brief DMA I2S transmit process half complete callback
1685 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1686 * the configuration information for the specified DMA module.
1687 * @retval None
1688 */
1689 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
1690 {
1691 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1692
1693 /* Call user Tx half complete callback */
1694 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1695 hi2s->TxHalfCpltCallback(hi2s);
1696 #else
1697 HAL_I2S_TxHalfCpltCallback(hi2s);
1698 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1699 }
1700
1701 /**
1702 * @brief DMA I2S receive process complete callback
1703 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1704 * the configuration information for the specified DMA module.
1705 * @retval None
1706 */
1707 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
1708 {
1709 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1710
1711 /* if DMA is configured in DMA_NORMAL Mode */
1712 if (hdma->Init.Mode == DMA_NORMAL)
1713 {
1714 /* Disable Rx DMA Request */
1715 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1716 hi2s->RxXferCount = (uint16_t)0UL;
1717 hi2s->State = HAL_I2S_STATE_READY;
1718 }
1719 /* Call user Rx complete callback */
1720 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1721 hi2s->RxCpltCallback(hi2s);
1722 #else
1723 HAL_I2S_RxCpltCallback(hi2s);
1724 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1725 }
1726
1727 /**
1728 * @brief DMA I2S receive process half complete callback
1729 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1730 * the configuration information for the specified DMA module.
1731 * @retval None
1732 */
1733 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
1734 {
1735 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1736
1737 /* Call user Rx half complete callback */
1738 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1739 hi2s->RxHalfCpltCallback(hi2s);
1740 #else
1741 HAL_I2S_RxHalfCpltCallback(hi2s);
1742 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1743 }
1744
1745 /**
1746 * @brief DMA I2S communication error callback
1747 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1748 * the configuration information for the specified DMA module.
1749 * @retval None
1750 */
1751 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
1752 {
1753 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1754
1755 /* Disable Rx and Tx DMA Request */
1756 CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
1757 hi2s->TxXferCount = (uint16_t) 0UL;
1758 hi2s->RxXferCount = (uint16_t) 0UL;
1759
1760 hi2s->State = HAL_I2S_STATE_READY;
1761
1762 /* Set the error code and execute error callback*/
1763 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1764 /* Call user error callback */
1765 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1766 hi2s->ErrorCallback(hi2s);
1767 #else
1768 HAL_I2S_ErrorCallback(hi2s);
1769 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1770 }
1771
1772 /**
1773 * @brief Manage the transmission 16-bit in Interrupt context
1774 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1775 * the configuration information for I2S module
1776 * @retval None
1777 */
1778 static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
1779 {
1780 /* Transmit data */
1781 #if defined (__GNUC__)
1782 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
1783
1784 *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
1785 #else
1786 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
1787 #endif /* __GNUC__ */
1788 hi2s->pTxBuffPtr++;
1789 hi2s->TxXferCount--;
1790
1791 if (hi2s->TxXferCount == 0UL)
1792 {
1793 /* Disable TXE and ERR interrupt */
1794 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
1795
1796 hi2s->State = HAL_I2S_STATE_READY;
1797 /* Call user Tx complete callback */
1798 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1799 hi2s->TxCpltCallback(hi2s);
1800 #else
1801 HAL_I2S_TxCpltCallback(hi2s);
1802 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1803 }
1804 }
1805
1806 /**
1807 * @brief Manage the transmission 32-bit in Interrupt context
1808 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1809 * the configuration information for I2S module
1810 * @retval None
1811 */
1812 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s)
1813 {
1814 /* Transmit data */
1815 hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
1816 hi2s->pTxBuffPtr += 2;
1817 hi2s->TxXferCount--;
1818
1819 if (hi2s->TxXferCount == 0UL)
1820 {
1821 /* Disable TXE and ERR interrupt */
1822 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
1823
1824 hi2s->State = HAL_I2S_STATE_READY;
1825 /* Call user Tx complete callback */
1826 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1827 hi2s->TxCpltCallback(hi2s);
1828 #else
1829 HAL_I2S_TxCpltCallback(hi2s);
1830 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1831 }
1832 }
1833
1834 /**
1835 * @brief Manage the reception 16-bit in Interrupt context
1836 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1837 * the configuration information for I2S module
1838 * @retval None
1839 */
1840 static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s)
1841 {
1842 /* Receive data */
1843 #if defined (__GNUC__)
1844 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
1845
1846 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
1847 #else
1848 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
1849 #endif /* __GNUC__ */
1850 hi2s->pRxBuffPtr++;
1851 hi2s->RxXferCount--;
1852
1853 if (hi2s->RxXferCount == 0UL)
1854 {
1855 /* Disable RXNE and ERR interrupt */
1856 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
1857
1858 hi2s->State = HAL_I2S_STATE_READY;
1859 /* Call user Rx complete callback */
1860 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1861 hi2s->RxCpltCallback(hi2s);
1862 #else
1863 HAL_I2S_RxCpltCallback(hi2s);
1864 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1865 }
1866 }
1867
1868 /**
1869 * @brief Manage the reception 32-bit in Interrupt context
1870 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1871 * the configuration information for I2S module
1872 * @retval None
1873 */
1874 static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s)
1875 {
1876 /* Receive data */
1877 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
1878 hi2s->pRxBuffPtr += 2;
1879 hi2s->RxXferCount--;
1880
1881 if (hi2s->RxXferCount == 0UL)
1882 {
1883 /* Disable RXNE and ERR interrupt */
1884 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
1885
1886 hi2s->State = HAL_I2S_STATE_READY;
1887 /* Call user Rx complete callback */
1888 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
1889 hi2s->RxCpltCallback(hi2s);
1890 #else
1891 HAL_I2S_RxCpltCallback(hi2s);
1892 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1893 }
1894 }
1895
1896 /**
1897 * @brief This function handles I2S Communication Timeout.
1898 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1899 * the configuration information for I2S module
1900 * @param Flag Flag checked
1901 * @param State Value of the flag expected
1902 * @param Timeout Duration of the timeout
1903 * @retval HAL status
1904 */
1905 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
1906 {
1907 uint32_t tickstart;
1908
1909 /* Get tick */
1910 tickstart = HAL_GetTick();
1911
1912 /* Wait until flag is set to status*/
1913 while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
1914 {
1915 if (Timeout != HAL_MAX_DELAY)
1916 {
1917 if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0UL))
1918 {
1919 /* Set the I2S State ready */
1920 hi2s->State = HAL_I2S_STATE_READY;
1921
1922 /* Process Unlocked */
1923 __HAL_UNLOCK(hi2s);
1924
1925 return HAL_TIMEOUT;
1926 }
1927 }
1928 }
1929 return HAL_OK;
1930 }
1931
1932 /**
1933 * @}
1934 */
1935
1936 /**
1937 * @}
1938 */
1939
1940 /**
1941 * @}
1942 */
1943
1944 #endif /* HAL_I2S_MODULE_ENABLED */
1945
1946 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software