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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_pwr.c
blob5f09f92264ec89abfd0e2f0d0c279dae14ab3bea
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization and de-initialization functions.
9 * + Peripheral Control functions.
10 * + Interrupt Handling functions.
11 @verbatim
12 ==============================================================================
13 ##### PWR peripheral overview #####
14 ==============================================================================
15 [..]
16 (#) The Power control (PWR) provides an overview of the supply architecture
17 for the different power domains and of the supply configuration
18 controller.
19 In the H7 family, the number of power domains is different between
20 device lines. This difference is due to characteristics of each device.
21
22 (#) Domain architecture overview for the different H7 lines:
23 (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
24 These devices have 3 power domains (D1, D2 and D3).
25 The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
26 peripherals. The D2 domain contains peripherals and a CPU
27 (Cortex-M4). The D3 domain contains the system control, I/O logic
28 and low-power peripherals.
29 (+) STM32H743, STM32H753, STM32H742 and STM32H750 devices have 3 power
30 domains (D1, D2 and D3).
31 The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
32 peripherals. The D2 domain contains peripherals. The D3 domains
33 contains the system control, I/O logic and low-power peripherals.
34 (+) STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx devices have 2
35 power domains (CD and SRD).
36 The core domain (CD) contains a CPU (Cortex-M7), a Flash
37 memory and peripherals. The SmartRun domain contains the system
38 control, I/O logic and low-power peripherals.
39
40 (#) Every entity have low power mode as decribed below :
41 (#) The CPU low power modes are :
42 (+) CPU CRUN.
43 (+) CPU CSLEEP.
44 (+) CPU CSTOP.
45 (#) The domain low power modes are :
46 (+) DRUN.
47 (+) DSTOP.
48 (+) DSTANDBY.
49 (#) The SYSTEM low power modes are :
50 (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
51 Standby. In Run* mode, the performance is limited and the
52 system supply configuration shall be programmed. The system
53 enters Run mode only when the ACTVOSRDY bit in PWR control
54 status register 1 (PWR_CSR1) is set to 1.
55 (+) RUN.
56 (+) STOP.
57 (+) STANDBY.
58
59 ==============================================================================
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Power management peripheral is active by default at startup level in
64 STM32h7xx lines.
65
66 (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
67 to enable/disable access to the backup domain (RTC registers, RTC backup
68 data registers and backup SRAM).
69
70 (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
71 mode and voltage threshold) in order to set up the Power Voltage Detector,
72 then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start
73 and stop the PVD detection.
74 (+) PVD level could be one of the following values :
75 (++) 1V95
76 (++) 2V1
77 (++) 2V25
78 (++) 2V4
79 (++) 2V55
80 (++) 2V7
81 (++) 2V85
82 (++) External voltage level
83
84 (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
85 with the right parameter to configure the wake up pin polarity (Low or
86 High) and to enable and disable it.
87
88 (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
89 mode. Wake-up from SLEEP mode could be following to an event or an
90 interrupt according to low power mode intrinsic request called (__WFI()
91 or __WFE()).
92 Please ensure to clear all CPU pending events by calling
93 HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
94 in SLEEP mode with __WFE() entry.
95
96 (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
97 mode for single core devices. For dual core devices, this API will enter
98 the domain (containing Cortex-Mx that executing this function) in DSTOP
99 mode. According to the used parameter, user could select the regulator to
100 be kept actif in low power mode and wake-up event type.
101 Please ensure to clear all CPU pending events by calling
102 HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
103 in CSTOP mode with __WFE() entry.
104
105 (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
106 STANDBY mode for single core devices. For dual core devices, this API
107 will enter the domain (containing Cortex-Mx that executing this function)
108 in DSTANDBY mode.
109
110 (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
111 enable and disable the Cortex-Mx re-entring in SLEEP mode after an
112 interruption handling is over.
113
114 (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
115 to configure the Cortex-Mx to wake-up after any pending event / interrupt
116 even if it's disabled or has insufficient priority to cause exception
117 entry.
118
119 (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
120 request.
121
122 *** PWR HAL driver macros list ***
123 =============================================
124 [..]
125 Below the list of most used macros in PWR HAL driver.
126
127 (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
128 regulator output voltage.
129 (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags.
130 (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
131
132 @endverbatim
133 ******************************************************************************
134 * @attention
135 *
136 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
137 * All rights reserved.</center></h2>
138 *
139 * This software component is licensed by ST under BSD 3-Clause license,
140 * the "License"; You may not use this file except in compliance with the
141 * License. You may obtain a copy of the License at:
142 * opensource.org/licenses/BSD-3-Clause
143 *
144 ******************************************************************************
145 */
146
147 /* Includes ------------------------------------------------------------------*/
148 #include "stm32h7xx_hal.h"
149
150 /** @addtogroup STM32H7xx_HAL_Driver
151 * @{
152 */
153
154 /** @defgroup PWR PWR
155 * @brief PWR HAL module driver
156 * @{
157 */
158
159 #ifdef HAL_PWR_MODULE_ENABLED
160
161 /* Private typedef -----------------------------------------------------------*/
162 /* Private define ------------------------------------------------------------*/
163
164 /** @addtogroup PWR_Private_Constants PWR Private Constants
165 * @{
166 */
167
168 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
169 * @{
170 */
171 #if !defined (DUAL_CORE)
172 #define PVD_MODE_IT (0x00010000U)
173 #define PVD_MODE_EVT (0x00020000U)
174 #endif /* !defined (DUAL_CORE) */
175
176 #define PVD_RISING_EDGE (0x00000001U)
177 #define PVD_FALLING_EDGE (0x00000002U)
178 #define PVD_RISING_FALLING_EDGE (0x00000003U)
179 /**
180 * @}
181 */
182
183 /**
184 * @}
185 */
186
187 /* Private macro -------------------------------------------------------------*/
188 /* Private variables ---------------------------------------------------------*/
189 /* Private function prototypes -----------------------------------------------*/
190 /* Private functions ---------------------------------------------------------*/
191
192 /** @defgroup PWR_Exported_Functions PWR Exported Functions
193 * @{
194 */
195
196 /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
197 * @brief Initialization and De-Initialization functions
198 *
199 @verbatim
200 ===============================================================================
201 ##### Initialization and De-Initialization Functions #####
202 ===============================================================================
203 [..]
204 This section provides functions allowing to deinitialize power peripheral.
205
206 [..]
207 After system reset, the backup domain (RTC registers, RTC backup data
208 registers and backup SRAM) is protected against possible unwanted write
209 accesses.
210 The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
211 domain.
212 The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
213 domain.
214
215 @endverbatim
216 * @{
217 */
218
219 /**
220 * @brief Deinitialize the HAL PWR peripheral registers to their default reset
221 * values.
222 * @note This functionality is not available in this product.
223 * The prototype is kept just to maintain compatibility with other
224 * products.
225 * @retval None.
226 */
227 void HAL_PWR_DeInit (void)
228 {
229 }
230
231 /**
232 * @brief Enable access to the backup domain (RTC registers, RTC backup data
233 * registers and backup SRAM).
234 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
235 * Backup Domain Access should be kept enabled.
236 * @retval None.
237 */
238 void HAL_PWR_EnableBkUpAccess (void)
239 {
240 /* Enable access to RTC and backup registers */
241 SET_BIT (PWR->CR1, PWR_CR1_DBP);
242 }
243
244 /**
245 * @brief Disable access to the backup domain (RTC registers, RTC backup data
246 * registers and backup SRAM).
247 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
248 * Backup Domain Access should be kept enabled.
249 * @retval None.
250 */
251 void HAL_PWR_DisableBkUpAccess (void)
252 {
253 /* Disable access to RTC and backup registers */
254 CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
255 }
256 /**
257 * @}
258 */
259
260 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
261 * @brief Power Control functions
262 *
263 @verbatim
264 ===============================================================================
265 ##### Peripheral Control Functions #####
266 ===============================================================================
267 [..]
268 This section provides functions allowing to control power peripheral.
269
270 *** PVD configuration ***
271 =========================
272 [..]
273 (+) The PVD is used to monitor the VDD power supply by comparing it to a
274 threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
275 register).
276
277 (+) A PVDO flag is available to indicate if VDD is higher or lower
278 than the PVD threshold. This event is internally connected to the EXTI
279 line 16 to generate an interrupt if enabled.
280 It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
281
282 (+) The PVD is stopped in STANDBY mode.
283
284 *** Wake-up pin configuration ***
285 =================================
286 [..]
287 (+) Wake-up pin is used to wake up the system from STANDBY mode.
288 The pin pull is configurable through the WKUPEPR register to be in
289 No-pull, Pull-up and Pull-down.
290 The pin polarity is configurable through the WKUPEPR register to be
291 active on rising or falling edges.
292
293 (+) There are up to six Wake-up pin in the STM32H7 devices family.
294
295 *** Low Power modes configuration ***
296 =====================================
297 [..]
298 The device present 3 principles low-power modes features:
299 (+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining
300 active (Powered and Clocked).
301
302 (+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the
303 regulator is running. The Main regulator or the LP
304 regulator could be selected.
305
306 (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
307 supply regulator is powered off.
308
309 *** SLEEP mode ***
310 ==================
311 [..]
312 (+) Entry:
313 The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
314 SLEEPEntry) function.
315
316 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
317 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
318
319 -@@- The Regulator parameter is not used for the STM32H7 family
320 and is kept as parameter just to maintain compatibility with the
321 lower power families (STM32L).
322
323 (+) Exit:
324 Any peripheral interrupt acknowledged by the nested vectored interrupt
325 controller (NVIC) can wake up the device from SLEEP mode.
326
327 *** STOP mode ***
328 =================
329 [..]
330 In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
331 the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
332 register contents are preserved.
333 The voltage regulator can be configured either in normal or low-power mode.
334 To minimize the consumption in STOP mode, FLASH can be powered off before
335 entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
336 It can be switched on again by software after exiting the STOP mode using
337 the HAL_PWREx_DisableFlashPowerDown() function.
338
339 (+) Entry:
340 The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
341 STOPEntry) function with:
342
343 (++) Regulator:
344 (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
345 (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
346
347 (++) STOPEntry:
348 (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
349 (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
350
351 (+) Exit:
352 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
353
354 *** STANDBY mode ***
355 ====================
356 [..]
357 (+)
358 The system STANDBY mode allows to achieve the lowest power consumption.
359 It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
360 disabled. The system is consequently powered off. The PLL, the HSI
361 oscillator and the HSE oscillator are also switched off. SRAM and register
362 contents are lost except for the RTC registers, RTC backup registers,
363 backup SRAM and standby circuitry.
364
365 [..]
366 The voltage regulator is OFF.
367
368 (++) Entry:
369 (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
370 function.
371
372 (++) Exit:
373 (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
374 RTC wakeup, tamper event, time stamp event, external reset in NRST
375 pin, IWDG reset.
376
377 *** Auto-wakeup (AWU) from low-power mode ***
378 =============================================
379 [..]
380 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
381 RTC Wakeup event, a tamper event or a time-stamp event, without
382 depending on an external interrupt (Auto-wakeup mode).
383
384 (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
385
386 (++) To wake up from the STOP mode with an RTC alarm event, it is
387 necessary to configure the RTC to generate the RTC alarm using the
388 HAL_RTC_SetAlarm_IT() function.
389
390 (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
391 it is necessary to configure the RTC to detect the tamper or time
392 stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
393 HAL_RTCEx_SetTamper_IT() functions.
394
395 (++) To wake up from the STOP mode with an RTC WakeUp event, it is
396 necessary to configure the RTC to generate the RTC WakeUp event
397 using the HAL_RTCEx_SetWakeUpTimer_IT() function.
398
399 @endverbatim
400 * @{
401 */
402
403 /**
404 * @brief Configure the event mode and the voltage threshold detected by the
405 * Programmable Voltage Detector(PVD).
406 * @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
407 * the configuration information for the PVD.
408 * @note Refer to the electrical characteristics of your device datasheet for
409 * more details about the voltage threshold corresponding to each
410 * detection level.
411 * @note For dual core devices, please ensure to configure the EXTI lines for
412 * the different Cortex-Mx through PWR_Exported_Macro provided by this
413 * driver. All combination are allowed: wake up only Cortex-M7, wake up
414 * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
415 * @retval None.
416 */
417 void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
418 {
419 /* Check the PVD configuration parameter */
420 if (sConfigPVD == NULL)
421 {
422 return;
423 }
424
425 /* Check the parameters */
426 assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
427 assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
428
429 /* Set PLS[7:5] bits according to PVDLevel value */
430 MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
431
432 /* Clear previous config */
433 #if !defined (DUAL_CORE)
434 __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
435 __HAL_PWR_PVD_EXTI_DISABLE_IT ();
436 #endif /* !defined (DUAL_CORE) */
437
438 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
439 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
440
441 #if !defined (DUAL_CORE)
442 /* Interrupt mode configuration */
443 if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
444 {
445 __HAL_PWR_PVD_EXTI_ENABLE_IT ();
446 }
447
448 /* Event mode configuration */
449 if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
450 {
451 __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
452 }
453 #endif /* !defined (DUAL_CORE) */
454
455 /* Rising edge configuration */
456 if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
457 {
458 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
459 }
460
461 /* Falling edge configuration */
462 if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
463 {
464 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
465 }
466 }
467
468 /**
469 * @brief Enable the Programmable Voltage Detector (PVD).
470 * @retval None.
471 */
472 void HAL_PWR_EnablePVD (void)
473 {
474 /* Enable the power voltage detector */
475 SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
476 }
477
478 /**
479 * @brief Disable the Programmable Voltage Detector (PVD).
480 * @retval None.
481 */
482 void HAL_PWR_DisablePVD (void)
483 {
484 /* Disable the power voltage detector */
485 CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
486 }
487
488 /**
489 * @brief Enable the WakeUp PINx functionality.
490 * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
491 * This parameter can be one of the following legacy values, which
492 * sets the default (rising edge):
493 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
494 * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
495 * or one of the following values where the user can explicitly states
496 * the enabled pin and the chosen polarity:
497 * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
498 * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
499 * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
500 * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
501 * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
502 * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
503 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
504 * @retval None.
505 */
506 void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
507 {
508 /* Check the parameters */
509 assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
510
511 /*
512 Enable and Specify the Wake-Up pin polarity and the pull configuration
513 for the event detection (rising or falling edge).
514 */
515 MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
516 }
517
518 /**
519 * @brief Disable the WakeUp PINx functionality.
520 * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable.
521 * This parameter can be one of the following values:
522 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
523 * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
524 * PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
525 * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
526 * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
527 * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
528 * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
529 * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
530 * @retval None.
531 */
532 void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
533 {
534 /* Check the parameters */
535 assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
536
537 /* Disable the wake up pin selected */
538 CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
539 }
540
541 /**
542 * @brief Enter the current core in SLEEP mode (CSLEEP).
543 * @param Regulator : Specifies the regulator state in SLEEP mode.
544 * This parameter can be one of the following values:
545 * @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON.
546 * @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
547 * regulator ON.
548 * @note This parameter is not used for the STM32H7 family and is kept as
549 * parameter just to maintain compatibility with the lower power
550 * families.
551 * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
552 * intrinsic instruction.
553 * This parameter can be one of the following values:
554 * @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
555 * @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
556 * @note Ensure to clear pending events before calling this API through
557 * HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
558 * @retval None.
559 */
560 void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
561 {
562 UNUSED(Regulator);
563
564 /* Check the parameters */
565 assert_param (IS_PWR_REGULATOR (Regulator));
566 assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
567
568 /* Clear SLEEPDEEP bit of Cortex System Control Register */
569 CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
570
571 /* Select SLEEP mode entry */
572 if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
573 {
574 /* Request Wait For Interrupt */
575 __WFI ();
576 }
577 else
578 {
579 /* Request Wait For Event */
580 __WFE ();
581 }
582 }
583
584 /**
585 * @brief Enter STOP mode.
586 * @note For single core devices, this API will enter the system in STOP mode
587 * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is
588 * cleared.
589 * For dual core devices, this API will enter the domain (containing
590 * Cortex-Mx that executing this function) in DSTOP mode. If all
591 * Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
592 * cleared, all the system will enter in STOP mode.
593 * @param Regulator : Specifies the regulator state in STOP mode.
594 * This parameter can be one of the following values:
595 * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
596 * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
597 * regulator ON.
598 * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
599 * intrinsic instruction.
600 * This parameter can be one of the following values:
601 * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
602 * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
603 * @note In System STOP mode, all I/O pins keep the same state as in Run mode.
604 * @note When exiting System STOP mode by issuing an interrupt or a wakeup
605 * event, the HSI RC oscillator is selected as default system wakeup
606 * clock.
607 * @note In System STOP mode, when the voltage regulator operates in low
608 * power mode, an additional startup delay is incurred when the system
609 * is waking up. By keeping the internal regulator ON during STOP mode,
610 * the consumption is higher although the startup time is reduced.
611 * @retval None.
612 */
613 void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
614 {
615 /* Check the parameters */
616 assert_param (IS_PWR_REGULATOR (Regulator));
617 assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
618
619 /* Select the regulator state in STOP mode */
620 MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
621
622 /* Configure the PWR mode for the different Domains */
623 #if defined (DUAL_CORE)
624 /* Check CPU ID */
625 if (HAL_GetCurrentCPUID () == CM7_CPUID)
626 {
627 /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
628 CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
629 }
630 else
631 {
632 /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
633 CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
634 }
635 #else /* Single core devices */
636 /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
637 CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
638
639 #if defined (PWR_CPUCR_PDDS_D2)
640 /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
641 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
642 #endif /* PWR_CPUCR_PDDS_D2 */
643 #endif /* defined (DUAL_CORE) */
644
645 /* Set SLEEPDEEP bit of Cortex System Control Register */
646 SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
647
648 /* Ensure that all instructions are done before entering STOP mode */
649 __DSB ();
650 __ISB ();
651
652 /* Select STOP mode entry */
653 if (STOPEntry == PWR_STOPENTRY_WFI)
654 {
655 /* Request Wait For Interrupt */
656 __WFI ();
657 }
658 else
659 {
660 /* Request Wait For Event */
661 __WFE ();
662 }
663
664 /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
665 CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
666 }
667
668 /**
669 * @brief Enter STANDBY mode.
670 * @note For single core devices, this API will enter the system in STANDBY
671 * mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
672 * regiter is cleared.
673 * For dual core devices, this API will enter the domain (containing
674 * Cortex-Mx that executing this function) in DSTANDBY mode. If all
675 * Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
676 * is cleared, all the system will enter in STANDBY mode.
677 * @note The system enters Standby mode only when all domains are in DSTANDBY.
678 * @note When the System exit STANDBY mode by issuing an interrupt or a
679 * wakeup event, the HSI RC oscillator is selected as system clock.
680 * @retval None.
681 */
682 void HAL_PWR_EnterSTANDBYMode (void)
683 {
684 /* Configure the PWR mode for the different Domains */
685 #if defined (DUAL_CORE)
686 /* Check CPU ID */
687 if (HAL_GetCurrentCPUID () == CM7_CPUID)
688 {
689 /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
690 SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
691 SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
692 }
693 else
694 {
695 /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
696 SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
697 SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
698 }
699 #else /* Single core devices */
700 /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
701 SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
702
703 #if defined (PWR_CPUCR_PDDS_D2)
704 /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
705 SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
706 #endif /* PWR_CPUCR_PDDS_D2 */
707 #endif /* defined (DUAL_CORE) */
708
709 /* Set SLEEPDEEP bit of Cortex System Control Register */
710 SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
711
712 /* Ensure that all instructions are done before entering STOP mode */
713 __DSB ();
714 __ISB ();
715
716 /* This option is used to ensure that store operations are completed */
717 #if defined (__CC_ARM)
718 __force_stores();
719 #endif /* defined (__CC_ARM) */
720
721 /* Request Wait For Interrupt */
722 __WFI ();
723 }
724
725 /**
726 * @brief Indicate Sleep-On-Exit feature when returning from Handler mode to
727 * Thread mode.
728 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
729 * processor re-enters SLEEP mode when an interruption handling is over.
730 * Setting this bit is useful when the processor is expected to run
731 * only on interruptions handling.
732 * @retval None.
733 */
734 void HAL_PWR_EnableSleepOnExit (void)
735 {
736 /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
737 SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
738 }
739
740 /**
741 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to
742 * Thread mode.
743 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
744 * processor re-enters SLEEP mode when an interruption handling is over.
745 * @retval None
746 */
747 void HAL_PWR_DisableSleepOnExit (void)
748 {
749 /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
750 CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
751 }
752
753 /**
754 * @brief Enable CORTEX SEVONPEND feature.
755 * @note Sets SEVONPEND bit of SCR register. When this bit is set, any
756 * pending event / interrupt even if it's disabled or has insufficient
757 * priority to cause exception entry wakes up the Cortex-Mx.
758 * @retval None.
759 */
760 void HAL_PWR_EnableSEVOnPend (void)
761 {
762 /* Set SEVONPEND bit of Cortex-Mx System Control Register */
763 SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
764 }
765
766 /**
767 * @brief Disable CORTEX SEVONPEND feature.
768 * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only
769 * enabled pending causes exception entry wakes up the Cortex-Mx.
770 * @retval None.
771 */
772 void HAL_PWR_DisableSEVOnPend (void)
773 {
774 /* Clear SEVONPEND bit of Cortex System Control Register */
775 CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
776 }
777 /**
778 * @}
779 */
780
781 /** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
782 * @brief Interrupt Handling functions
783 *
784 @verbatim
785 ===============================================================================
786 ##### Interrupt Handling Functions #####
787 ===============================================================================
788 [..]
789 This section provides functions allowing to handle the PVD pending
790 interrupts.
791
792 @endverbatim
793 * @{
794 */
795
796 /**
797 * @brief This function handles the PWR PVD interrupt request.
798 * @note This API should be called under the PVD_AVD_IRQHandler().
799 * @retval None.
800 */
801 void HAL_PWR_PVD_IRQHandler (void)
802 {
803 #if defined (DUAL_CORE)
804 /* Check Cortex-Mx ID */
805 if (HAL_GetCurrentCPUID () == CM7_CPUID)
806 {
807 /* Check PWR EXTI D1 flag */
808 if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
809 {
810 /* Clear PWR EXTI D1 pending bit */
811 __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
812
813 /* PWR PVD interrupt user callback */
814 HAL_PWR_PVDCallback ();
815 }
816 }
817 else
818 {
819 /* Check PWR EXTI D2 flag */
820 if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
821 {
822 /* Clear PWR EXTI D2 pending bit */
823 __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
824
825 /* PWR PVD interrupt user callback */
826 HAL_PWR_PVDCallback ();
827 }
828 }
829 #else /* Single core devices */
830 /* PVD EXTI line interrupt detected */
831 if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
832 {
833 /* Clear PWR EXTI pending bit */
834 __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
835
836 /* PWR PVD interrupt user callback */
837 HAL_PWR_PVDCallback ();
838 }
839 #endif /* defined (DUAL_CORE) */
840 }
841
842 /**
843 * @brief PWR PVD interrupt callback.
844 * @retval None.
845 */
846 __weak void HAL_PWR_PVDCallback (void)
847 {
848 /* NOTE : This function should not be modified, when the callback is needed,
849 the HAL_PWR_PVDCallback can be implemented in the user file
850 */
851 }
852
853 /**
854 * @}
855 */
856
857 /**
858 * @}
859 */
860
861 #endif /* HAL_PWR_MODULE_ENABLED */
862 /**
863 * @}
864 */
865
866 /**
867 * @}
868 */
869
870 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software