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Merge maintenance-8.x.x fixes into master
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_adc.c
blob2ecaf6ccb6cae5b0e5897bc2368ea3b309737420
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h7xx_ll_adc.h"
22 #include "stm32h7xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency */
64 /* Unit: CPU cycles. */
65 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
66 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
67 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68
69 /**
70 * @}
71 */
72
73 /* Private macros ------------------------------------------------------------*/
74
75 /** @addtogroup ADC_LL_Private_Macros
76 * @{
77 */
78
79 /* Check of parameters for configuration of ADC hierarchical scope: */
80 /* common to several ADC instances. */
81 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
82 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
83 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
84 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
85 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
97 )
98
99 /* Check of parameters for configuration of ADC hierarchical scope: */
100 /* ADC instance. */
101 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
102 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B) \
103 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \
104 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
105 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
107 )
108
109 #define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \
110 ( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
111 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \
112 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \
113 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \
114 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \
115 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \
116 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \
117 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \
118 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \
119 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \
120 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \
121 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \
122 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \
123 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \
124 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \
125 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \
126 )
127
128 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
129 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
131 )
132
133 /* Check of parameters for configuration of ADC hierarchical scope: */
134 /* ADC group regular */
135 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
136 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) \
158 )
159
160 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
161 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
162 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
163 )
164
165 #define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \
166 ( ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
167 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
168 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
169 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER) \
170 )
171
172 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
173 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
174 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
175 )
176
177 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
178 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
179 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
180 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
181 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
182 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
183 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
184 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
185 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
186 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
187 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
188 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
189 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
190 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
191 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
192 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
193 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
194 )
195
196 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
197 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
198 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
199 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
200 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
201 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
202 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
203 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
204 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
205 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
206 )
207
208 /* Check of parameters for configuration of ADC hierarchical scope: */
209 /* ADC group injected */
210 #if defined(STM32H745xx) || defined(STM32H745xG) || defined(STM32H742xx) || defined(STM32H743xx) || defined(STM32H747xG) || defined(STM32H747xx) || defined(STM32H750xx) || defined(STM32H753xx) || defined(STM32H755xx) || defined(STM32H757xx)
211 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
212 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
216 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
217 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
218 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
219 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
220 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
221 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
225 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
226 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
227 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
228 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
229 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
230 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
231 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \
232 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \
233 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \
234 )
235 #else
236 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
237 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
238 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
239 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
240 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
241 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
242 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
243 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
244 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
245 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
246 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
247 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
248 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
249 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
250 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
251 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
252 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
253 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
254 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \
255 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \
256 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \
257 )
258 #endif
259
260 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
261 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
262 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
263 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
264 )
265
266 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
267 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
268 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
269 )
270
271 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
272 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
273 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
274 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
275 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
276 )
277
278 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
279 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
280 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
281 )
282
283 /* Check of parameters for configuration of ADC hierarchical scope: */
284 /* multimode. */
285 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
286 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
287 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
288 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
289 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
290 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
291 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
292 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
293 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
294 )
295
296 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
297 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
298 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \
299 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \
300 )
301 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
302 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) \
303 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) \
304 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) \
305 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) \
306 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS) \
307 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) \
308 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS) \
309 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
310 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) \
311 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \
312 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) \
313 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
314 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
315 )
316
317 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
318 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
319 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
320 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
321 )
322
323 /**
324 * @}
325 */
326
327
328 /* Private function prototypes -----------------------------------------------*/
329
330 /* Exported functions --------------------------------------------------------*/
331 /** @addtogroup ADC_LL_Exported_Functions
332 * @{
333 */
334
335 /** @addtogroup ADC_LL_EF_Init
336 * @{
337 */
338
339 /**
340 * @brief De-initialize registers of all ADC instances belonging to
341 * the same ADC common instance to their default reset values.
342 * @note This function is performing a hard reset, using high level
343 * clock source RCC ADC reset.
344 * Caution: On this STM32 series, if several ADC instances are available
345 * on the selected device, RCC ADC reset will reset
346 * all ADC instances belonging to the common ADC instance.
347 * To de-initialize only 1 ADC instance, use
348 * function @ref LL_ADC_DeInit().
349 * @param ADCxy_COMMON ADC common instance
350 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
351 * @retval An ErrorStatus enumeration value:
352 * - SUCCESS: ADC common registers are de-initialized
353 * - ERROR: not applicable
354 */
355 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
356 {
357 /* Check the parameters */
358 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
359
360 if (ADCxy_COMMON == ADC12_COMMON)
361 {
362 /* Force reset of ADC clock (core clock) */
363 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12);
364
365 /* Release reset of ADC clock (core clock) */
366 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
367 }
368 else
369 {
370 #if defined (ADC3)
371 /* Force reset of ADC clock (core clock) */
372 LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_ADC3);
373
374 /* Release reset of ADC clock (core clock) */
375 LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_ADC3);
376 #endif
377 }
378
379 return SUCCESS;
380 }
381
382 /**
383 * @brief Initialize some features of ADC common parameters
384 * (all ADC instances belonging to the same ADC common instance)
385 * and multimode (for devices with several ADC instances available).
386 * @note The setting of ADC common parameters is conditioned to
387 * ADC instances state:
388 * All ADC instances belonging to the same ADC common instance
389 * must be disabled.
390 * @param ADCxy_COMMON ADC common instance
391 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
392 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
393 * @retval An ErrorStatus enumeration value:
394 * - SUCCESS: ADC common registers are initialized
395 * - ERROR: ADC common registers are not initialized
396 */
397 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
398 {
399 ErrorStatus status = SUCCESS;
400
401 /* Check the parameters */
402 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
403 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
404
405 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
406 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
407 {
408 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
409 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
410 }
411
412 /* Note: Hardware constraint (refer to description of functions */
413 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
414 /* On this STM32 series, setting of these features is conditioned to */
415 /* ADC state: */
416 /* All ADC instances of the ADC common group must be disabled. */
417 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
418 {
419 /* Configuration of ADC hierarchical scope: */
420 /* - common to several ADC */
421 /* (all ADC instances belonging to the same ADC common instance) */
422 /* - Set ADC clock (conversion clock) */
423 /* - multimode (if several ADC instances available on the */
424 /* selected device) */
425 /* - Set ADC multimode configuration */
426 /* - Set ADC multimode DMA transfer */
427 /* - Set ADC multimode: delay between 2 sampling phases */
428 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
429 {
430 MODIFY_REG(ADCxy_COMMON->CCR,
431 ADC_CCR_CKMODE
432 | ADC_CCR_PRESC
433 | ADC_CCR_DUAL
434 | ADC_CCR_DAMDF
435 | ADC_CCR_DELAY
436 ,
437 ADC_CommonInitStruct->CommonClock
438 | ADC_CommonInitStruct->Multimode
439 | ADC_CommonInitStruct->MultiDMATransfer
440 | ADC_CommonInitStruct->MultiTwoSamplingDelay
441 );
442 }
443 else
444 {
445 MODIFY_REG(ADCxy_COMMON->CCR,
446 ADC_CCR_CKMODE
447 | ADC_CCR_PRESC
448 | ADC_CCR_DUAL
449 | ADC_CCR_DAMDF
450 | ADC_CCR_DELAY
451 ,
452 ADC_CommonInitStruct->CommonClock
453 | LL_ADC_MULTI_INDEPENDENT
454 );
455 }
456 }
457 else
458 {
459 /* Initialization error: One or several ADC instances belonging to */
460 /* the same ADC common instance are not disabled. */
461 status = ERROR;
462 }
463
464 return status;
465 }
466
467 /**
468 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
469 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
470 * whose fields will be set to default values.
471 * @retval None
472 */
473 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
474 {
475 /* Set ADC_CommonInitStruct fields to default values */
476 /* Set fields of ADC common */
477 /* (all ADC instances belonging to the same ADC common instance) */
478 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
479
480 /* Set fields of ADC multimode */
481 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
482 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
483 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5;
484 }
485
486 /**
487 * @brief De-initialize registers of the selected ADC instance
488 * to their default reset values.
489 * @note To reset all ADC instances quickly (perform a hard reset),
490 * use function @ref LL_ADC_CommonDeInit().
491 * @note If this functions returns error status, it means that ADC instance
492 * is in an unknown state.
493 * In this case, perform a hard reset using high level
494 * clock source RCC ADC reset.
495 * Caution: On this STM32 series, if several ADC instances are available
496 * on the selected device, RCC ADC reset will reset
497 * all ADC instances belonging to the common ADC instance.
498 * Refer to function @ref LL_ADC_CommonDeInit().
499 * @param ADCx ADC instance
500 * @retval An ErrorStatus enumeration value:
501 * - SUCCESS: ADC registers are de-initialized
502 * - ERROR: ADC registers are not de-initialized
503 */
504 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
505 {
506 ErrorStatus status = SUCCESS;
507
508 __IO uint32_t timeout_cpu_cycles = 0UL;
509
510 /* Check the parameters */
511 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
512
513 /* Disable ADC instance if not already disabled. */
514 if (LL_ADC_IsEnabled(ADCx) == 1UL)
515 {
516 /* Stop potential ADC conversion on going on ADC group regular. */
517 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
518 {
519 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
520 {
521 LL_ADC_REG_StopConversion(ADCx);
522 }
523 }
524
525 /* Stop potential ADC conversion on going on ADC group injected. */
526 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
527 {
528 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
529 {
530 LL_ADC_INJ_StopConversion(ADCx);
531 }
532 }
533
534 /* Wait for ADC conversions are effectively stopped */
535 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
536 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
537 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
538 {
539 timeout_cpu_cycles--;
540 if (timeout_cpu_cycles == 0UL)
541 {
542 /* Time-out error */
543 status = ERROR;
544 break;
545 }
546 }
547
548 /* Flush group injected contexts queue (register JSQR): */
549 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
550 /* contexts queue is maintained with the last active context). */
551 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
552
553 /* Disable the ADC instance */
554 LL_ADC_Disable(ADCx);
555
556 /* Wait for ADC instance is effectively disabled */
557 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
558 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
559 {
560 timeout_cpu_cycles--;
561 if (timeout_cpu_cycles == 0UL)
562 {
563 /* Time-out error */
564 status = ERROR;
565 break;
566 }
567 }
568 }
569
570 /* Check whether ADC state is compliant with expected state */
571 if (READ_BIT(ADCx->CR,
572 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
573 | ADC_CR_ADDIS | ADC_CR_ADEN)
574 )
575 == 0UL)
576 {
577 /* ========== Reset ADC registers ========== */
578 /* Reset register IER */
579 CLEAR_BIT(ADCx->IER,
580 (LL_ADC_IT_ADRDY
581 | LL_ADC_IT_EOC
582 | LL_ADC_IT_EOS
583 | LL_ADC_IT_OVR
584 | LL_ADC_IT_EOSMP
585 | LL_ADC_IT_JEOC
586 | LL_ADC_IT_JEOS
587 | LL_ADC_IT_JQOVF
588 | LL_ADC_IT_AWD1
589 | LL_ADC_IT_AWD2
590 | LL_ADC_IT_AWD3
591 )
592 );
593
594 /* Reset register ISR */
595 SET_BIT(ADCx->ISR,
596 (LL_ADC_FLAG_ADRDY
597 | LL_ADC_FLAG_EOC
598 | LL_ADC_FLAG_EOS
599 | LL_ADC_FLAG_OVR
600 | LL_ADC_FLAG_EOSMP
601 | LL_ADC_FLAG_JEOC
602 | LL_ADC_FLAG_JEOS
603 | LL_ADC_FLAG_JQOVF
604 | LL_ADC_FLAG_AWD1
605 | LL_ADC_FLAG_AWD2
606 | LL_ADC_FLAG_AWD3
607 )
608 );
609
610 /* Reset register CR */
611 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
612 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
613 /* access mode "read-set": no direct reset applicable. */
614 /* - Reset Calibration mode to default setting (single ended). */
615 /* - Disable ADC internal voltage regulator. */
616 /* - Enable ADC deep power down. */
617 /* Note: ADC internal voltage regulator disable and ADC deep power */
618 /* down enable are conditioned to ADC state disabled: */
619 /* already done above. */
620 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
621 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
622
623 /* Reset register CFGR */
624 CLEAR_BIT(ADCx->CFGR,
625 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
626 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
627 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
628 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
629 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_RES
630 | ADC_CFGR_DMNGT)
631 );
632
633 SET_BIT(ADCx->CFGR, ADC_CFGR_JQDIS);
634
635 /* Reset register CFGR2 */
636 CLEAR_BIT(ADCx->CFGR2,
637 (ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1
638 | ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2
639 | ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS
640 | ADC_CFGR2_OVSS | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
641 );
642
643 /* Reset register SMPR1 */
644 CLEAR_BIT(ADCx->SMPR1,
645 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
646 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
647 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
648 );
649
650 /* Reset register SMPR2 */
651 CLEAR_BIT(ADCx->SMPR2,
652 (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17
653 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14
654 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11
655 | ADC_SMPR2_SMP10)
656 );
657
658 /* Reset register TR1 */
659 #if defined(ADC_VER_V5_V90)
660 if (ADCx == ADC3)
661 {
662 /* Reset register TR1 */
663 MODIFY_REG(ADCx->LTR1_TR1, ADC3_TR1_AWDFILT | ADC3_TR1_HT1 | ADC3_TR1_LT1, ADC3_TR1_HT1);
664
665 /* Reset register TR2 */
666 MODIFY_REG(ADCx->HTR1_TR2, ADC3_TR2_HT2 | ADC3_TR2_LT2, ADC3_TR2_HT2);
667
668 /* Reset register TR3 */
669 MODIFY_REG(ADCx->RES1_TR3, ADC3_TR3_HT3 | ADC3_TR3_LT3, ADC3_TR3_HT3);
670 }
671 else
672 {
673 CLEAR_BIT(ADCx->LTR1_TR1, ADC_LTR_LT);
674 SET_BIT(ADCx->HTR1_TR2, ADC_HTR_HT);
675
676 CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_LTR_LT);
677 SET_BIT(ADCx->HTR2_CALFACT, ADC_HTR_HT);
678 CLEAR_BIT(ADCx->LTR3_RES10, ADC_LTR_LT);
679 SET_BIT(ADCx->HTR3_RES11, ADC_HTR_HT);
680 }
681 #else
682 CLEAR_BIT(ADCx->LTR1, ADC_LTR_LT);
683 SET_BIT(ADCx->HTR1, ADC_HTR_HT);
684
685 CLEAR_BIT(ADCx->LTR2, ADC_LTR_LT);
686 SET_BIT(ADCx->HTR2, ADC_HTR_HT);
687 CLEAR_BIT(ADCx->LTR3, ADC_LTR_LT);
688 SET_BIT(ADCx->HTR3, ADC_HTR_HT);
689 #endif
690
691 /* Reset register SQR1 */
692 CLEAR_BIT(ADCx->SQR1,
693 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
694 | ADC_SQR1_SQ1 | ADC_SQR1_L)
695 );
696
697 /* Reset register SQR2 */
698 CLEAR_BIT(ADCx->SQR2,
699 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
700 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
701 );
702
703 /* Reset register SQR3 */
704 CLEAR_BIT(ADCx->SQR3,
705 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
706 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
707 );
708
709 /* Reset register SQR4 */
710 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
711
712 /* Reset register JSQR */
713 CLEAR_BIT(ADCx->JSQR,
714 (ADC_JSQR_JL
715 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
716 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
717 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
718 );
719
720 /* Reset register DR */
721 /* Note: bits in access mode read only, no direct reset applicable */
722
723 /* Reset register OFR1 */
724 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_SSATE);
725 /* Reset register OFR2 */
726 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_SSATE);
727 /* Reset register OFR3 */
728 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_SSATE);
729 /* Reset register OFR4 */
730 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_SSATE);
731
732 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
733 /* Note: bits in access mode read only, no direct reset applicable */
734
735 /* Reset register AWD2CR */
736 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
737
738 /* Reset register AWD3CR */
739 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
740
741 /* Reset register DIFSEL */
742 #if defined(ADC_VER_V5_V90)
743 if (ADCx == ADC3)
744 {
745 CLEAR_BIT(ADCx->LTR2_DIFSEL, ADC_DIFSEL_DIFSEL);
746
747 /* Reset register CALFACT */
748 CLEAR_BIT(ADCx->HTR2_CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
749 }
750 else
751 {
752 CLEAR_BIT(ADCx->DIFSEL_RES12, ADC_DIFSEL_DIFSEL);
753
754 /* Reset register CALFACT */
755 CLEAR_BIT(ADCx->CALFACT_RES13, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
756
757 /* Reset register CALFACT2 */
758 CLEAR_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT);
759 }
760 #else
761 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
762
763 /* Reset register CALFACT */
764 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
765
766 /* Reset register CALFACT2 */
767 CLEAR_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT);
768 #endif
769 }
770 else
771 {
772 /* ADC instance is in an unknown state */
773 /* Need to performing a hard reset of ADC instance, using high level */
774 /* clock source RCC ADC reset. */
775 /* Caution: On this STM32 series, if several ADC instances are available */
776 /* on the selected device, RCC ADC reset will reset */
777 /* all ADC instances belonging to the common ADC instance. */
778 /* Caution: On this STM32 series, if several ADC instances are available */
779 /* on the selected device, RCC ADC reset will reset */
780 /* all ADC instances belonging to the common ADC instance. */
781 status = ERROR;
782 }
783
784 return status;
785 }
786
787 /**
788 * @brief Initialize some features of ADC instance.
789 * @note These parameters have an impact on ADC scope: ADC instance.
790 * Affects both group regular and group injected (availability
791 * of ADC group injected depends on STM32 families).
792 * Refer to corresponding unitary functions into
793 * @ref ADC_LL_EF_Configuration_ADC_Instance .
794 * @note The setting of these parameters by function @ref LL_ADC_Init()
795 * is conditioned to ADC state:
796 * ADC instance must be disabled.
797 * This condition is applied to all ADC features, for efficiency
798 * and compatibility over all STM32 families. However, the different
799 * features can be set under different ADC state conditions
800 * (setting possible with ADC enabled without conversion on going,
801 * ADC enabled with conversion on going, ...)
802 * Each feature can be updated afterwards with a unitary function
803 * and potentially with ADC in a different state than disabled,
804 * refer to description of each function for setting
805 * conditioned to ADC state.
806 * @note After using this function, some other features must be configured
807 * using LL unitary functions.
808 * The minimum configuration remaining to be done is:
809 * - Set ADC group regular or group injected sequencer:
810 * map channel on the selected sequencer rank.
811 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
812 * - Set ADC channel sampling time
813 * Refer to function LL_ADC_SetChannelSamplingTime();
814 * @param ADCx ADC instance
815 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
816 * @retval An ErrorStatus enumeration value:
817 * - SUCCESS: ADC registers are initialized
818 * - ERROR: ADC registers are not initialized
819 */
820 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
821 {
822 ErrorStatus status = SUCCESS;
823
824 /* Check the parameters */
825 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
826
827 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
828 assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(ADC_InitStruct->LeftBitShift));
829 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
830
831 /* Note: Hardware constraint (refer to description of this function): */
832 /* ADC instance must be disabled. */
833 if (LL_ADC_IsEnabled(ADCx) == 0UL)
834 {
835 /* Configuration of ADC hierarchical scope: */
836 /* - ADC instance */
837 /* - Set ADC data resolution */
838 /* - Set ADC conversion data alignment */
839 /* - Set ADC low power mode */
840 #if defined(ADC_VER_V5_V90)
841 if(ADCx==ADC3)
842 {
843 MODIFY_REG(ADCx->CFGR,
844 ADC3_CFGR_RES
845 | ADC_CFGR_AUTDLY
846 ,
847 ((__LL_ADC12_RESOLUTION_TO_ADC3(ADC_InitStruct->Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL)
848 | ADC_InitStruct->LowPowerMode
849 );
850 }
851 else
852 {
853 MODIFY_REG(ADCx->CFGR,
854 ADC_CFGR_RES
855 | ADC_CFGR_AUTDLY
856 ,
857 ADC_InitStruct->Resolution
858 | ADC_InitStruct->LowPowerMode
859 );
860 }
861 #else
862 MODIFY_REG(ADCx->CFGR,
863 ADC_CFGR_RES
864 | ADC_CFGR_AUTDLY
865 ,
866 ADC_InitStruct->Resolution
867 | ADC_InitStruct->LowPowerMode
868 );
869 #endif
870
871 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift);
872 }
873 else
874 {
875 /* Initialization error: ADC instance is not disabled. */
876 status = ERROR;
877 }
878 return status;
879 }
880
881 /**
882 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
883 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
884 * whose fields will be set to default values.
885 * @retval None
886 */
887 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
888 {
889 /* Set ADC_InitStruct fields to default values */
890 /* Set fields of ADC instance */
891 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_16B;
892 ADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE;
893 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
894
895 }
896
897 /**
898 * @brief Initialize some features of ADC group regular.
899 * @note These parameters have an impact on ADC scope: ADC group regular.
900 * Refer to corresponding unitary functions into
901 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
902 * (functions with prefix "REG").
903 * @note The setting of these parameters by function @ref LL_ADC_Init()
904 * is conditioned to ADC state:
905 * ADC instance must be disabled.
906 * This condition is applied to all ADC features, for efficiency
907 * and compatibility over all STM32 families. However, the different
908 * features can be set under different ADC state conditions
909 * (setting possible with ADC enabled without conversion on going,
910 * ADC enabled with conversion on going, ...)
911 * Each feature can be updated afterwards with a unitary function
912 * and potentially with ADC in a different state than disabled,
913 * refer to description of each function for setting
914 * conditioned to ADC state.
915 * @note After using this function, other features must be configured
916 * using LL unitary functions.
917 * The minimum configuration remaining to be done is:
918 * - Set ADC group regular or group injected sequencer:
919 * map channel on the selected sequencer rank.
920 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
921 * - Set ADC channel sampling time
922 * Refer to function LL_ADC_SetChannelSamplingTime();
923 * @param ADCx ADC instance
924 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
925 * @retval An ErrorStatus enumeration value:
926 * - SUCCESS: ADC registers are initialized
927 * - ERROR: ADC registers are not initialized
928 */
929 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
930 {
931 ErrorStatus status = SUCCESS;
932
933 /* Check the parameters */
934 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
935 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
936 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
937 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
938 {
939 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
940
941 /* ADC group regular continuous mode and discontinuous mode */
942 /* can not be enabled simultenaeously */
943 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
944 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
945 }
946 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
947 assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode));
948 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
949
950 /* Note: Hardware constraint (refer to description of this function): */
951 /* ADC instance must be disabled. */
952 if (LL_ADC_IsEnabled(ADCx) == 0UL)
953 {
954 /* Configuration of ADC hierarchical scope: */
955 /* - ADC group regular */
956 /* - Set ADC group regular trigger source */
957 /* - Set ADC group regular sequencer length */
958 /* - Set ADC group regular sequencer discontinuous mode */
959 /* - Set ADC group regular continuous mode */
960 /* - Set ADC group regular conversion data transfer: no transfer or */
961 /* transfer by DMA, and DMA requests mode */
962 /* - Set ADC group regular overrun behavior */
963 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
964 /* setting of trigger source to SW start. */
965 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
966 {
967 MODIFY_REG(ADCx->CFGR,
968 ADC_CFGR_EXTSEL
969 | ADC_CFGR_EXTEN
970 | ADC_CFGR_DISCEN
971 | ADC_CFGR_DISCNUM
972 | ADC_CFGR_CONT
973 | ADC_CFGR_DMNGT
974 | ADC_CFGR_OVRMOD
975 ,
976 ADC_REG_InitStruct->TriggerSource
977 | ADC_REG_InitStruct->SequencerDiscont
978 | ADC_REG_InitStruct->ContinuousMode
979 | ADC_REG_InitStruct->DataTransferMode
980 | ADC_REG_InitStruct->Overrun
981 );
982 }
983 else
984 {
985 MODIFY_REG(ADCx->CFGR,
986 ADC_CFGR_EXTSEL
987 | ADC_CFGR_EXTEN
988 | ADC_CFGR_DISCEN
989 | ADC_CFGR_DISCNUM
990 | ADC_CFGR_CONT
991 | ADC_CFGR_DMNGT
992 | ADC_CFGR_OVRMOD
993 ,
994 ADC_REG_InitStruct->TriggerSource
995 | LL_ADC_REG_SEQ_DISCONT_DISABLE
996 | ADC_REG_InitStruct->ContinuousMode
997 | ADC_REG_InitStruct->DataTransferMode
998 | ADC_REG_InitStruct->Overrun
999 );
1000 }
1001
1002 /* Set ADC group regular sequencer length and scan direction */
1003 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1004 }
1005 else
1006 {
1007 /* Initialization error: ADC instance is not disabled. */
1008 status = ERROR;
1009 }
1010 return status;
1011 }
1012
1013 /**
1014 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1015 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1016 * whose fields will be set to default values.
1017 * @retval None
1018 */
1019 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1020 {
1021 /* Set ADC_REG_InitStruct fields to default values */
1022 /* Set fields of ADC group regular */
1023 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1024 /* setting of trigger source to SW start. */
1025 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1026 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1027 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1028 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1029 ADC_REG_InitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
1030 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
1031 }
1032
1033 /**
1034 * @brief Initialize some features of ADC group injected.
1035 * @note These parameters have an impact on ADC scope: ADC group injected.
1036 * Refer to corresponding unitary functions into
1037 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1038 * (functions with prefix "INJ").
1039 * @note The setting of these parameters by function @ref LL_ADC_Init()
1040 * is conditioned to ADC state:
1041 * ADC instance must be disabled.
1042 * This condition is applied to all ADC features, for efficiency
1043 * and compatibility over all STM32 families. However, the different
1044 * features can be set under different ADC state conditions
1045 * (setting possible with ADC enabled without conversion on going,
1046 * ADC enabled with conversion on going, ...)
1047 * Each feature can be updated afterwards with a unitary function
1048 * and potentially with ADC in a different state than disabled,
1049 * refer to description of each function for setting
1050 * conditioned to ADC state.
1051 * @note After using this function, other features must be configured
1052 * using LL unitary functions.
1053 * The minimum configuration remaining to be done is:
1054 * - Set ADC group injected sequencer:
1055 * map channel on the selected sequencer rank.
1056 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1057 * - Set ADC channel sampling time
1058 * Refer to function LL_ADC_SetChannelSamplingTime();
1059 * @param ADCx ADC instance
1060 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1061 * @retval An ErrorStatus enumeration value:
1062 * - SUCCESS: ADC registers are initialized
1063 * - ERROR: ADC registers are not initialized
1064 */
1065 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1066 {
1067 ErrorStatus status = SUCCESS;
1068
1069 /* Check the parameters */
1070 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1071 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
1072 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1073 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1074 {
1075 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1076 }
1077 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1078
1079 /* Note: Hardware constraint (refer to description of this function): */
1080 /* ADC instance must be disabled. */
1081 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1082 {
1083 /* Configuration of ADC hierarchical scope: */
1084 /* - ADC group injected */
1085 /* - Set ADC group injected trigger source */
1086 /* - Set ADC group injected sequencer length */
1087 /* - Set ADC group injected sequencer discontinuous mode */
1088 /* - Set ADC group injected conversion trigger: independent or */
1089 /* from ADC group regular */
1090 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1091 /* setting of trigger source to SW start. */
1092 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1093 {
1094 MODIFY_REG(ADCx->CFGR,
1095 ADC_CFGR_JDISCEN
1096 | ADC_CFGR_JAUTO
1097 ,
1098 ADC_INJ_InitStruct->SequencerDiscont
1099 | ADC_INJ_InitStruct->TrigAuto
1100 );
1101 }
1102 else
1103 {
1104 MODIFY_REG(ADCx->CFGR,
1105 ADC_CFGR_JDISCEN
1106 | ADC_CFGR_JAUTO
1107 ,
1108 LL_ADC_REG_SEQ_DISCONT_DISABLE
1109 | ADC_INJ_InitStruct->TrigAuto
1110 );
1111 }
1112
1113 MODIFY_REG(ADCx->JSQR,
1114 ADC_JSQR_JEXTSEL
1115 | ADC_JSQR_JEXTEN
1116 | ADC_JSQR_JL
1117 ,
1118 ADC_INJ_InitStruct->TriggerSource
1119 | ADC_INJ_InitStruct->SequencerLength
1120 );
1121 }
1122 else
1123 {
1124 /* Initialization error: ADC instance is not disabled. */
1125 status = ERROR;
1126 }
1127 return status;
1128 }
1129
1130 /**
1131 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1132 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1133 * whose fields will be set to default values.
1134 * @retval None
1135 */
1136 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1137 {
1138 /* Set ADC_INJ_InitStruct fields to default values */
1139 /* Set fields of ADC group injected */
1140 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1141 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1142 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1143 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1144 }
1145
1146 /**
1147 * @}
1148 */
1149
1150 /**
1151 * @}
1152 */
1153
1154 /**
1155 * @}
1156 */
1157
1158 #endif /* ADC1 || ADC2 || ADC3 */
1159
1160 /**
1161 * @}
1162 */
1163
1164 #endif /* USE_FULL_LL_DRIVER */
1165
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