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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_dma.c
blobd71df5dced924df243c3bebb9cd6c65a47c65a8a
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_dma.h"
23 #include "stm32h7xx_ll_bus.h"
24
25 /** @addtogroup STM32H7xx_LL_Driver
26 * @{
27 */
28
29 #if defined (DMA1) || defined (DMA2)
30
31 /** @addtogroup DMA_LL
32 * @{
33 */
34
35 /* Private types -------------------------------------------------------------*/
36 /* Private variables ---------------------------------------------------------*/
37 /* Private constants ---------------------------------------------------------*/
38 /* Private macros ------------------------------------------------------------*/
39 /** @addtogroup DMA_LL_Private_Macros
40 * @{
41 */
42 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
43 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
44 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
45
46 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
47 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
48 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
49
50 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
51 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
52
53 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
54 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
55
56 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
57 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
58 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
59
60 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
61 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
62 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
63
64 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
65
66 #if defined(ADC3)
67 #define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_ADC3))
68 #else
69 #define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX))
70 #endif /* ADC3 */
71
72 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
73 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
74 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
75 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
76
77 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
78 (((STREAM) == LL_DMA_STREAM_0) || \
79 ((STREAM) == LL_DMA_STREAM_1) || \
80 ((STREAM) == LL_DMA_STREAM_2) || \
81 ((STREAM) == LL_DMA_STREAM_3) || \
82 ((STREAM) == LL_DMA_STREAM_4) || \
83 ((STREAM) == LL_DMA_STREAM_5) || \
84 ((STREAM) == LL_DMA_STREAM_6) || \
85 ((STREAM) == LL_DMA_STREAM_7) || \
86 ((STREAM) == LL_DMA_STREAM_ALL))) || \
87 (((INSTANCE) == DMA2) && \
88 (((STREAM) == LL_DMA_STREAM_0) || \
89 ((STREAM) == LL_DMA_STREAM_1) || \
90 ((STREAM) == LL_DMA_STREAM_2) || \
91 ((STREAM) == LL_DMA_STREAM_3) || \
92 ((STREAM) == LL_DMA_STREAM_4) || \
93 ((STREAM) == LL_DMA_STREAM_5) || \
94 ((STREAM) == LL_DMA_STREAM_6) || \
95 ((STREAM) == LL_DMA_STREAM_7) || \
96 ((STREAM) == LL_DMA_STREAM_ALL))))
97
98 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
99 ((STATE) == LL_DMA_FIFOMODE_ENABLE))
100
101 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
102 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
103 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
104 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
105
106 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
107 ((BURST) == LL_DMA_MBURST_INC4) || \
108 ((BURST) == LL_DMA_MBURST_INC8) || \
109 ((BURST) == LL_DMA_MBURST_INC16))
110
111 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
112 ((BURST) == LL_DMA_PBURST_INC4) || \
113 ((BURST) == LL_DMA_PBURST_INC8) || \
114 ((BURST) == LL_DMA_PBURST_INC16))
115
116 /**
117 * @}
118 */
119
120 /* Private function prototypes -----------------------------------------------*/
121
122 /* Exported functions --------------------------------------------------------*/
123 /** @addtogroup DMA_LL_Exported_Functions
124 * @{
125 */
126
127 /** @addtogroup DMA_LL_EF_Init
128 * @{
129 */
130
131 /**
132 * @brief De-initialize the DMA registers to their default reset values.
133 * @param DMAx DMAx Instance
134 * @param Stream This parameter can be one of the following values:
135 * @arg @ref LL_DMA_STREAM_0
136 * @arg @ref LL_DMA_STREAM_1
137 * @arg @ref LL_DMA_STREAM_2
138 * @arg @ref LL_DMA_STREAM_3
139 * @arg @ref LL_DMA_STREAM_4
140 * @arg @ref LL_DMA_STREAM_5
141 * @arg @ref LL_DMA_STREAM_6
142 * @arg @ref LL_DMA_STREAM_7
143 * @arg @ref LL_DMA_STREAM_ALL
144 * @retval An ErrorStatus enumeration value:
145 * - SUCCESS: DMA registers are de-initialized
146 * - ERROR: DMA registers are not de-initialized
147 */
148 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
149 {
150 DMA_Stream_TypeDef *tmp;
151 ErrorStatus status = SUCCESS;
152
153 /* Check the DMA Instance DMAx and Stream parameters */
154 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
155
156 if (Stream == LL_DMA_STREAM_ALL)
157 {
158 if (DMAx == DMA1)
159 {
160 /* Force reset of DMA clock */
161 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
162
163 /* Release reset of DMA clock */
164 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
165 }
166 else if (DMAx == DMA2)
167 {
168 /* Force reset of DMA clock */
169 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
170
171 /* Release reset of DMA clock */
172 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
173 }
174 else
175 {
176 status = ERROR;
177 }
178 }
179 else
180 {
181 /* Disable the selected Stream */
182 LL_DMA_DisableStream(DMAx, Stream);
183
184 /* Get the DMA Stream Instance */
185 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
186
187 /* Reset DMAx_Streamy configuration register */
188 LL_DMA_WriteReg(tmp, CR, 0U);
189
190 /* Reset DMAx_Streamy remaining bytes register */
191 LL_DMA_WriteReg(tmp, NDTR, 0U);
192
193 /* Reset DMAx_Streamy peripheral address register */
194 LL_DMA_WriteReg(tmp, PAR, 0U);
195
196 /* Reset DMAx_Streamy memory address register */
197 LL_DMA_WriteReg(tmp, M0AR, 0U);
198
199 /* Reset DMAx_Streamy memory address register */
200 LL_DMA_WriteReg(tmp, M1AR, 0U);
201
202 /* Reset DMAx_Streamy FIFO control register */
203 LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
204
205 /* Reset Channel register field for DMAx Stream */
206 LL_DMA_SetPeriphRequest(DMAx, Stream, LL_DMAMUX1_REQ_MEM2MEM);
207
208 if (Stream == LL_DMA_STREAM_0)
209 {
210 /* Reset the Stream0 pending flags */
211 DMAx->LIFCR = 0x0000003FU;
212 }
213 else if (Stream == LL_DMA_STREAM_1)
214 {
215 /* Reset the Stream1 pending flags */
216 DMAx->LIFCR = 0x00000F40U;
217 }
218 else if (Stream == LL_DMA_STREAM_2)
219 {
220 /* Reset the Stream2 pending flags */
221 DMAx->LIFCR = 0x003F0000U;
222 }
223 else if (Stream == LL_DMA_STREAM_3)
224 {
225 /* Reset the Stream3 pending flags */
226 DMAx->LIFCR = 0x0F400000U;
227 }
228 else if (Stream == LL_DMA_STREAM_4)
229 {
230 /* Reset the Stream4 pending flags */
231 DMAx->HIFCR = 0x0000003FU;
232 }
233 else if (Stream == LL_DMA_STREAM_5)
234 {
235 /* Reset the Stream5 pending flags */
236 DMAx->HIFCR = 0x00000F40U;
237 }
238 else if (Stream == LL_DMA_STREAM_6)
239 {
240 /* Reset the Stream6 pending flags */
241 DMAx->HIFCR = 0x003F0000U;
242 }
243 else if (Stream == LL_DMA_STREAM_7)
244 {
245 /* Reset the Stream7 pending flags */
246 DMAx->HIFCR = 0x0F400000U;
247 }
248 else
249 {
250 status = ERROR;
251 }
252 }
253
254 return (uint32_t)status;
255 }
256
257 /**
258 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
259 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
260 * @arg @ref __LL_DMA_GET_INSTANCE
261 * @arg @ref __LL_DMA_GET_STREAM
262 * @param DMAx DMAx Instance
263 * @param Stream This parameter can be one of the following values:
264 * @arg @ref LL_DMA_STREAM_0
265 * @arg @ref LL_DMA_STREAM_1
266 * @arg @ref LL_DMA_STREAM_2
267 * @arg @ref LL_DMA_STREAM_3
268 * @arg @ref LL_DMA_STREAM_4
269 * @arg @ref LL_DMA_STREAM_5
270 * @arg @ref LL_DMA_STREAM_6
271 * @arg @ref LL_DMA_STREAM_7
272 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
273 * @retval An ErrorStatus enumeration value:
274 * - SUCCESS: DMA registers are initialized
275 * - ERROR: Not applicable
276 */
277 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
278 {
279 /* Check the DMA Instance DMAx and Stream parameters */
280 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
281
282 /* Check the DMA parameters from DMA_InitStruct */
283 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
284 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
285 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
286 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
287 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
288 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
289 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
290 assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest));
291 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
292 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
293
294 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
295 when FIFO mode is enabled */
296 if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
297 {
298 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
299 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
300 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
301 }
302
303 /*---------------------------- DMAx SxCR Configuration ------------------------
304 * Configure DMAx_Streamy: data transfer direction, data transfer mode,
305 * peripheral and memory increment mode,
306 * data size alignment and priority level with parameters :
307 * - Direction: DMA_SxCR_DIR[1:0] bits
308 * - Mode: DMA_SxCR_CIRC bit
309 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
310 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
311 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
312 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
313 * - Priority: DMA_SxCR_PL[1:0] bits
314 */
315 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
316 DMA_InitStruct->Mode | \
317 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
318 DMA_InitStruct->MemoryOrM2MDstIncMode | \
319 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
320 DMA_InitStruct->MemoryOrM2MDstDataSize | \
321 DMA_InitStruct->Priority
322 );
323
324 if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
325 {
326 /*---------------------------- DMAx SxFCR Configuration ------------------------
327 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
328 * - FIFOMode: DMA_SxFCR_DMDIS bit
329 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
330 */
331 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
332
333 /*---------------------------- DMAx SxCR Configuration --------------------------
334 * Configure DMAx_Streamy: memory burst transfer with parameters :
335 * - MemBurst: DMA_SxCR_MBURST[1:0] bits
336 */
337 LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst);
338
339 /*---------------------------- DMAx SxCR Configuration --------------------------
340 * Configure DMAx_Streamy: peripheral burst transfer with parameters :
341 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
342 */
343 LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst);
344 }
345
346 /*-------------------------- DMAx SxM0AR Configuration --------------------------
347 * Configure the memory or destination base address with parameter :
348 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
349 */
350 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
351
352 /*-------------------------- DMAx SxPAR Configuration ---------------------------
353 * Configure the peripheral or source base address with parameter :
354 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
355 */
356 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
357
358 /*--------------------------- DMAx SxNDTR Configuration -------------------------
359 * Configure the peripheral base address with parameter :
360 * - NbData: DMA_SxNDT[15:0] bits
361 */
362 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
363
364 /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
365 * Configure the peripheral base address with parameter :
366 * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits
367 */
368 LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest);
369
370 return (uint32_t)SUCCESS;
371 }
372
373 /**
374 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
375 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
376 * @retval None
377 */
378 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
379 {
380 /* Set DMA_InitStruct fields to default values */
381 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
382 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
383 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
384 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
385 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
386 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
387 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
388 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
389 DMA_InitStruct->NbData = 0x00000000U;
390 DMA_InitStruct->PeriphRequest = LL_DMAMUX1_REQ_MEM2MEM;
391 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
392 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
393 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
394 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
395 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
396 }
397
398 /**
399 * @}
400 */
401
402 /**
403 * @}
404 */
405
406 /**
407 * @}
408 */
409
410 #endif /* DMA1 || DMA2 */
411
412 /**
413 * @}
414 */
415
416 #endif /* USE_FULL_LL_DRIVER */
417
418 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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