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Merge maintenance-8.x.x fixes into master
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_spi.c
blobd17fc72afd2c9498a728ce72710b5826fbd269ec
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h7xx_ll_spi.h"
22 #include "stm32h7xx_ll_bus.h"
23 #include "stm32h7xx_ll_rcc.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #ifndef assert_param
28 #define assert_param(expr) ((void)0U)
29 #endif
30 #endif /* USE_FULL_ASSERT */
31
32 /** @addtogroup STM32H7xx_LL_Driver
33 * @{
34 */
35
36 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
37
38 /** @addtogroup SPI_LL
39 * @{
40 */
41
42 /* Private types -------------------------------------------------------------*/
43 /* Private variables ---------------------------------------------------------*/
44 /* Private constants ---------------------------------------------------------*/
45 /* Private macros ------------------------------------------------------------*/
46 /** @addtogroup SPI_LL_Private_Macros
47 * @{
48 */
49
50 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \
51 ((__VALUE__) == LL_SPI_MODE_SLAVE))
52
53 #define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \
54 ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \
55 ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \
56 ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \
57 ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \
58 ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \
59 ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \
60 ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \
61 ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \
62 ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \
63 ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \
64 ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \
65 ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \
66 ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \
67 ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \
68 ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
69
70 #define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \
71 ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \
72 ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \
73 ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \
74 ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \
75 ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \
76 ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \
77 ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \
78 ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \
79 ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \
80 ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \
81 ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \
82 ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \
83 ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \
84 ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \
85 ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
86
87 #define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \
88 ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
89
90 #define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \
91 ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
92
93 #define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \
94 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \
95 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
96
97 #define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \
98 ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \
99 ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
100
101 #define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \
102 ((__VALUE__) == LL_SPI_PROTOCOL_TI))
103
104 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \
105 ((__VALUE__) == LL_SPI_PHASE_2EDGE))
106
107 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \
108 ((__VALUE__) == LL_SPI_POLARITY_HIGH))
109
110 #define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \
111 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \
112 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \
113 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \
114 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \
115 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \
116 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \
117 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
118
119 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \
120 ((__VALUE__) == LL_SPI_MSB_FIRST))
121
122 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \
123 ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \
124 ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \
125 ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \
126 ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
127
128 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \
129 ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \
130 ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \
131 ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \
132 ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \
133 ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \
134 ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \
135 ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \
136 ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \
137 ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \
138 ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \
139 ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \
140 ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \
141 ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \
142 ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \
143 ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \
144 ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \
145 ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \
146 ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \
147 ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \
148 ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \
149 ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \
150 ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \
151 ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \
152 ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \
153 ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \
154 ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \
155 ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \
156 ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
157
158 #define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \
159 ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \
160 ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \
161 ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \
162 ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \
163 ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \
164 ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \
165 ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \
166 ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \
167 ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \
168 ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \
169 ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \
170 ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \
171 ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \
172 ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \
173 ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
174
175 #define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \
176 ((__VALUE__) == LL_SPI_CRC_5BIT) || \
177 ((__VALUE__) == LL_SPI_CRC_6BIT) || \
178 ((__VALUE__) == LL_SPI_CRC_7BIT) || \
179 ((__VALUE__) == LL_SPI_CRC_8BIT) || \
180 ((__VALUE__) == LL_SPI_CRC_9BIT) || \
181 ((__VALUE__) == LL_SPI_CRC_10BIT) || \
182 ((__VALUE__) == LL_SPI_CRC_11BIT) || \
183 ((__VALUE__) == LL_SPI_CRC_12BIT) || \
184 ((__VALUE__) == LL_SPI_CRC_13BIT) || \
185 ((__VALUE__) == LL_SPI_CRC_14BIT) || \
186 ((__VALUE__) == LL_SPI_CRC_15BIT) || \
187 ((__VALUE__) == LL_SPI_CRC_16BIT) || \
188 ((__VALUE__) == LL_SPI_CRC_17BIT) || \
189 ((__VALUE__) == LL_SPI_CRC_18BIT) || \
190 ((__VALUE__) == LL_SPI_CRC_19BIT) || \
191 ((__VALUE__) == LL_SPI_CRC_20BIT) || \
192 ((__VALUE__) == LL_SPI_CRC_21BIT) || \
193 ((__VALUE__) == LL_SPI_CRC_22BIT) || \
194 ((__VALUE__) == LL_SPI_CRC_23BIT) || \
195 ((__VALUE__) == LL_SPI_CRC_24BIT) || \
196 ((__VALUE__) == LL_SPI_CRC_25BIT) || \
197 ((__VALUE__) == LL_SPI_CRC_26BIT) || \
198 ((__VALUE__) == LL_SPI_CRC_27BIT) || \
199 ((__VALUE__) == LL_SPI_CRC_28BIT) || \
200 ((__VALUE__) == LL_SPI_CRC_29BIT) || \
201 ((__VALUE__) == LL_SPI_CRC_30BIT) || \
202 ((__VALUE__) == LL_SPI_CRC_31BIT) || \
203 ((__VALUE__) == LL_SPI_CRC_32BIT))
204
205 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \
206 ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \
207 ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
208
209 #define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \
210 ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \
211 ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \
212 ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
213
214 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \
215 ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
216
217 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
218
219 /**
220 * @}
221 */
222
223 /* Private function prototypes -----------------------------------------------*/
224
225 /* Exported functions --------------------------------------------------------*/
226 /** @addtogroup SPI_LL_Exported_Functions
227 * @{
228 */
229
230 /** @addtogroup SPI_LL_EF_Init
231 * @{
232 */
233
234 /**
235 * @brief De-initialize the SPI registers to their default reset values.
236 * @param SPIx SPI Instance
237 * @retval An ErrorStatus enumeration value:
238 * - SUCCESS: SPI registers are de-initialized
239 * - ERROR: SPI registers are not de-initialized
240 */
241 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
242 {
243 ErrorStatus status = ERROR;
244
245 /* Check the parameters */
246 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
247
248 #if defined(SPI1)
249 if (SPIx == SPI1)
250 {
251 /* Force reset of SPI clock */
252 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
253
254 /* Release reset of SPI clock */
255 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
256
257 /* Update the return status */
258 status = SUCCESS;
259 }
260 #endif /* SPI1 */
261 #if defined(SPI2)
262 if (SPIx == SPI2)
263 {
264 /* Force reset of SPI clock */
265 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
266
267 /* Release reset of SPI clock */
268 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
269
270 /* Update the return status */
271 status = SUCCESS;
272 }
273 #endif /* SPI2 */
274 #if defined(SPI3)
275 if (SPIx == SPI3)
276 {
277 /* Force reset of SPI clock */
278 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
279
280 /* Release reset of SPI clock */
281 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
282
283 /* Update the return status */
284 status = SUCCESS;
285 }
286 #endif /* SPI3 */
287 #if defined(SPI4)
288 if (SPIx == SPI4)
289 {
290 /* Force reset of SPI clock */
291 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
292
293 /* Release reset of SPI clock */
294 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
295
296 /* Update the return status */
297 status = SUCCESS;
298 }
299 #endif /* SPI4 */
300 #if defined(SPI5)
301 if (SPIx == SPI5)
302 {
303 /* Force reset of SPI clock */
304 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
305
306 /* Release reset of SPI clock */
307 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
308
309 /* Update the return status */
310 status = SUCCESS;
311 }
312 #endif /* SPI5 */
313 #if defined(SPI6)
314 if (SPIx == SPI6)
315 {
316 /* Force reset of SPI clock */
317 LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6);
318
319 /* Release reset of SPI clock */
320 LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6);
321
322 /* Update the return status */
323 status = SUCCESS;
324 }
325 #endif /* SPI6 */
326
327 return status;
328 }
329
330 /**
331 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
332 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled
333 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
334 * Otherwise, ERROR result will be returned.
335 * @param SPIx SPI Instance
336 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
337 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
338 */
339 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
340 {
341 ErrorStatus status = ERROR;
342 uint32_t tmp_nss;
343 uint32_t tmp_mode;
344 uint32_t tmp_nss_polarity;
345
346 /* Check the SPI Instance SPIx*/
347 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
348
349 /* Check the SPI parameters from SPI_InitStruct*/
350 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
351 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
352 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
353 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
354 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
355 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
356 assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
357 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
358 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
359
360 /* Check the SPI instance is not enabled */
361 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
362 {
363 /*---------------------------- SPIx CFG1 Configuration ------------------------
364 * Configure SPIx CFG1 with parameters:
365 * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits
366 * - CRC Computation Enable : SPI_CFG1_CRCEN bit
367 * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
368 */
369 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
370 SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
371
372 tmp_nss = SPI_InitStruct->NSS;
373 tmp_mode = SPI_InitStruct->Mode;
374 tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx);
375
376 /* Checks to setup Internal SS signal level and avoid a MODF Error */
377 if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \
378 (tmp_mode == LL_SPI_MODE_MASTER)) || \
379 ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \
380 (tmp_mode == LL_SPI_MODE_SLAVE))))
381 {
382 LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
383 }
384
385 /*---------------------------- SPIx CFG2 Configuration ------------------------
386 * Configure SPIx CFG2 with parameters:
387 * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
388 * - ClockPolarity : SPI_CFG2_CPOL bit
389 * - ClockPhase : SPI_CFG2_CPHA bit
390 * - BitOrder : SPI_CFG2_LSBFRST bit
391 * - Master/Slave Mode : SPI_CFG2_MASTER bit
392 * - SPI Mode : SPI_CFG2_COMM[1:0] bits
393 */
394 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
395 SPI_CFG2_CPOL | SPI_CFG2_CPHA |
396 SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM,
397 SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
398 SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
399 SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
400
401 /*---------------------------- SPIx CR1 Configuration ------------------------
402 * Configure SPIx CR1 with parameter:
403 * - Half Duplex Direction : SPI_CR1_HDDIR bit
404 */
405 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
406
407 /*---------------------------- SPIx CRCPOLY Configuration ----------------------
408 * Configure SPIx CRCPOLY with parameter:
409 * - CRCPoly : CRCPOLY[31:0] bits
410 */
411 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
412 {
413 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
414 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
415 }
416
417 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
418 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
419
420 status = SUCCESS;
421 }
422
423 return status;
424 }
425
426 /**
427 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
428 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
429 * whose fields will be set to default values.
430 * @retval None
431 */
432 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
433 {
434 /* Set SPI_InitStruct fields to default values */
435 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
436 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
437 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
438 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
439 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
440 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
441 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
442 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
443 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
444 SPI_InitStruct->CRCPoly = 7UL;
445 }
446
447 /**
448 * @}
449 */
450
451 /**
452 * @}
453 */
454
455 /**
456 * @}
457 */
458 /** @addtogroup I2S_LL
459 * @{
460 */
461
462 /* Private types -------------------------------------------------------------*/
463 /* Private variables ---------------------------------------------------------*/
464 /* Private constants ---------------------------------------------------------*/
465 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
466 * @{
467 */
468 /* I2S registers Masks */
469 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
470 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_CKPOL | \
471 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_MCKOE | \
472 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
473
474 /**
475 * @}
476 */
477 /* Private macros ------------------------------------------------------------*/
478 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
479 * @{
480 */
481
482 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) || \
483 ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) || \
484 ((__VALUE__) == LL_I2S_DATAFORMAT_24B) || \
485 ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \
486 ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
487
488 #define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) || \
489 ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
490
491 #define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) || \
492 ((__VALUE__) == LL_I2S_POLARITY_HIGH))
493
494 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) || \
495 ((__VALUE__) == LL_I2S_STANDARD_MSB) || \
496 ((__VALUE__) == LL_I2S_STANDARD_LSB) || \
497 ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) || \
498 ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
499
500 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) || \
501 ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) || \
502 ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) || \
503 ((__VALUE__) == LL_I2S_MODE_MASTER_TX) || \
504 ((__VALUE__) == LL_I2S_MODE_MASTER_RX) || \
505 ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
506
507 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) || \
508 ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
509
510 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) && \
511 ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) || \
512 ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
513
514 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL)
515
516 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) || \
517 ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
518
519 #define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) || \
520 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) || \
521 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) || \
522 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) || \
523 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) || \
524 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) || \
525 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) || \
526 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
527
528 #define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) || \
529 ((__VALUE__) == LL_I2S_MSB_FIRST))
530 /**
531 * @}
532 */
533
534 /* Private function prototypes -----------------------------------------------*/
535
536 /* Exported functions --------------------------------------------------------*/
537 /** @addtogroup I2S_LL_Exported_Functions
538 * @{
539 */
540
541 /** @addtogroup I2S_LL_EF_Init
542 * @{
543 */
544
545 /**
546 * @brief De-initialize the SPI/I2S registers to their default reset values.
547 * @param SPIx SPI Instance
548 * @retval An ErrorStatus enumeration value:
549 * - SUCCESS: SPI registers are de-initialized
550 * - ERROR: SPI registers are not de-initialized
551 */
552 ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
553 {
554 return LL_SPI_DeInit(SPIx);
555 }
556
557 /**
558 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
559 * @note As some bits in I2S configuration registers can only be written when the SPI is disabled
560 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
561 * Otherwise, ERROR result will be returned.
562 * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results
563 * in wrong programming.
564 * @param SPIx SPI Instance
565 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
566 * @retval An ErrorStatus enumeration value:
567 * - SUCCESS: SPI registers are Initialized
568 * - ERROR: SPI registers are not Initialized
569 */
570 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct)
571 {
572 uint32_t i2sdiv = 0UL;
573 uint32_t i2sodd = 0UL;
574 uint32_t packetlength = 1UL;
575 uint32_t ispcm = 0UL;
576 uint32_t tmp;
577 uint32_t sourceclock = 0UL;
578
579 ErrorStatus status = ERROR;
580
581 /* Prevent unused argument(s) compilation warning */
582 UNUSED(sourceclock);
583
584 /* Check the I2S parameters */
585 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
586 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
587 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
588 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
589 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
590 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
591 assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity));
592
593 /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled.
594 * In this case, it is useless to check if the I2SMOD bit is set to 0 because
595 * this bit I2SMOD only serves to select the desired mode.
596 */
597 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
598 {
599 /*---------------------------- SPIx I2SCFGR Configuration --------------------
600 * Configure SPIx I2SCFGR with parameters:
601 * - Mode : SPI_I2SCFGR_I2SCFG[2:0] bits
602 * - Standard : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
603 * - DataFormat : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits
604 * - ClockPolarity : SPI_I2SCFGR_CKPOL bit
605 * - MCLKOutput : SPI_I2SPR_MCKOE bit
606 * - I2S mode : SPI_I2SCFGR_I2SMOD bit
607 */
608
609 /* Write to SPIx I2SCFGR */
610 MODIFY_REG(SPIx->I2SCFGR,
611 I2S_I2SCFGR_CLEAR_MASK,
612 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
613 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
614 I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD);
615
616 /*---------------------------- SPIx I2SCFGR Configuration ----------------------
617 * Configure SPIx I2SCFGR with parameters:
618 * - AudioFreq : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits
619 */
620
621 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
622 * else, default values are used: i2sodd = 0U, i2sdiv = 0U.
623 */
624 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
625 {
626 /* Check the frame length (For the Prescaler computing)
627 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
628 */
629 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
630 {
631 /* Packet length is 32 bits */
632 packetlength = 2UL;
633 }
634
635 /* Check if PCM standard is used */
636 if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) ||
637 (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG))
638 {
639 ispcm = 1UL;
640 }
641
642 /* Get the I2S (SPI) source clock value */
643 #if defined (SPI_SPI6I2S_SUPPORT)
644 if (SPIx == SPI6)
645 {
646 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE);
647 }
648 else
649 {
650 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
651 }
652 #else
653 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
654 #endif /* SPI_SPI6I2S_SUPPORT */
655
656 /* Compute the Real divider depending on the MCLK output state with a fixed point */
657 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
658 {
659 /* MCLK output is enabled */
660 tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
661 }
662 else
663 {
664 /* MCLK output is disabled */
665 tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
666 }
667
668 /* Remove the fixed point */
669 tmp = tmp / 16UL;
670
671 /* Check the parity of the divider */
672 i2sodd = tmp & 0x1UL;
673
674 /* Compute the i2sdiv prescaler */
675 i2sdiv = tmp / 2UL;
676 }
677
678 /* Test if the obtain values are forbidden or out of range */
679 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
680 {
681 /* Set the default values */
682 i2sdiv = 0UL;
683 i2sodd = 0UL;
684 }
685
686 /* Write to SPIx I2SCFGR register the computed value */
687 MODIFY_REG(SPIx->I2SCFGR,
688 SPI_I2SCFGR_ODD | SPI_I2SCFGR_I2SDIV,
689 (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos));
690
691 status = SUCCESS;
692 }
693
694 return status;
695 }
696
697 /**
698 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
699 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
700 * whose fields will be set to default values.
701 * @retval None
702 */
703 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
704 {
705 /*--------------- Reset I2S init structure parameters values -----------------*/
706 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
707 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
708 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
709 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
710 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
711 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
712 }
713
714 /**
715 * @brief Set linear and parity prescaler.
716 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
717 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
718 * @param SPIx SPI Instance
719 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
720 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
721 * @param PrescalerParity This parameter can be one of the following values:
722 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
723 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
724 * @retval None
725 */
726 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
727 {
728 /* Check the I2S parameters */
729 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
730 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
731 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
732
733 /* Write to SPIx I2SPR */
734 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) |
735 (PrescalerParity << SPI_I2SCFGR_ODD_Pos));
736 }
737
738 /**
739 * @}
740 */
741
742 /**
743 * @}
744 */
745
746 /**
747 * @}
748 */
749
750 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
751
752 /**
753 * @}
754 */
755 #endif /* USE_FULL_LL_DRIVER */
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