?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_usb.c
blob18ed741cab39bf2702b82504e843e05502f421bc
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_usb.c
4 * @author MCD Application Team
5 * @brief USB Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the USB Peripheral Controller:
9 * + Initialization/de-initialization functions
10 * + I/O operation functions
11 * + Peripheral Control functions
12 * + Peripheral State functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### How to use this driver #####
17 ==============================================================================
18 [..]
19 (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
20
21 (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
22
23 (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
24
25 @endverbatim
26 ******************************************************************************
27 * @attention
28 *
29 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
30 * All rights reserved.</center></h2>
31 *
32 * This software component is licensed by ST under BSD 3-Clause license,
33 * the "License"; You may not use this file except in compliance with the
34 * License. You may obtain a copy of the License at:
35 * opensource.org/licenses/BSD-3-Clause
36 *
37 ******************************************************************************
38 */
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32h7xx_hal.h"
42
43 /** @addtogroup STM32H7xx_LL_USB_DRIVER
44 * @{
45 */
46
47 #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
48 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
49 /* Private typedef -----------------------------------------------------------*/
50 /* Private define ------------------------------------------------------------*/
51 /* Private macro -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53 /* Private function prototypes -----------------------------------------------*/
54 /* Private functions ---------------------------------------------------------*/
55 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
56 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
57
58 /* Exported functions --------------------------------------------------------*/
59 /** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
60 * @{
61 */
62
63 /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
64 * @brief Initialization and Configuration functions
65 *
66 @verbatim
67 ===============================================================================
68 ##### Initialization/de-initialization functions #####
69 ===============================================================================
70
71 @endverbatim
72 * @{
73 */
74
75 /**
76 * @brief Initializes the USB Core
77 * @param USBx USB Instance
78 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
79 * the configuration information for the specified USBx peripheral.
80 * @retval HAL status
81 */
82 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
83 {
84 HAL_StatusTypeDef ret;
85
86 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
87 {
88 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
89
90 /* Init The ULPI Interface */
91 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
92
93 /* Select vbus source */
94 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
95 if (cfg.use_external_vbus == 1U)
96 {
97 USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
98 }
99 /* Reset after a PHY select */
100 ret = USB_CoreReset(USBx);
101 }
102 else /* FS interface (embedded Phy) */
103 {
104 /* Select FS Embedded PHY */
105 USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
106
107 /* Reset after a PHY select and set Host mode */
108 ret = USB_CoreReset(USBx);
109
110 if (cfg.battery_charging_enable == 0U)
111 {
112 /* Activate the USB Transceiver */
113 USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
114 }
115 else
116 {
117 /* Deactivate the USB Transceiver */
118 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
119 }
120 }
121
122 if (cfg.dma_enable == 1U)
123 {
124 USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
125 USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
126 }
127
128 return ret;
129 }
130
131
132 /**
133 * @brief Set the USB turnaround time
134 * @param USBx USB Instance
135 * @param hclk: AHB clock frequency
136 * @retval USB turnaround time In PHY Clocks number
137 */
138 HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
139 uint32_t hclk, uint8_t speed)
140 {
141 uint32_t UsbTrd;
142
143 /* The USBTRD is configured according to the tables below, depending on AHB frequency
144 used by application. In the low AHB frequency range it is used to stretch enough the USB response
145 time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
146 latency to the Data FIFO */
147 if (speed == USBD_FS_SPEED)
148 {
149 if ((hclk >= 14200000U) && (hclk < 15000000U))
150 {
151 /* hclk Clock Range between 14.2-15 MHz */
152 UsbTrd = 0xFU;
153 }
154 else if ((hclk >= 15000000U) && (hclk < 16000000U))
155 {
156 /* hclk Clock Range between 15-16 MHz */
157 UsbTrd = 0xEU;
158 }
159 else if ((hclk >= 16000000U) && (hclk < 17200000U))
160 {
161 /* hclk Clock Range between 16-17.2 MHz */
162 UsbTrd = 0xDU;
163 }
164 else if ((hclk >= 17200000U) && (hclk < 18500000U))
165 {
166 /* hclk Clock Range between 17.2-18.5 MHz */
167 UsbTrd = 0xCU;
168 }
169 else if ((hclk >= 18500000U) && (hclk < 20000000U))
170 {
171 /* hclk Clock Range between 18.5-20 MHz */
172 UsbTrd = 0xBU;
173 }
174 else if ((hclk >= 20000000U) && (hclk < 21800000U))
175 {
176 /* hclk Clock Range between 20-21.8 MHz */
177 UsbTrd = 0xAU;
178 }
179 else if ((hclk >= 21800000U) && (hclk < 24000000U))
180 {
181 /* hclk Clock Range between 21.8-24 MHz */
182 UsbTrd = 0x9U;
183 }
184 else if ((hclk >= 24000000U) && (hclk < 27700000U))
185 {
186 /* hclk Clock Range between 24-27.7 MHz */
187 UsbTrd = 0x8U;
188 }
189 else if ((hclk >= 27700000U) && (hclk < 32000000U))
190 {
191 /* hclk Clock Range between 27.7-32 MHz */
192 UsbTrd = 0x7U;
193 }
194 else /* if(hclk >= 32000000) */
195 {
196 /* hclk Clock Range between 32-200 MHz */
197 UsbTrd = 0x6U;
198 }
199 }
200 else if (speed == USBD_HS_SPEED)
201 {
202 UsbTrd = USBD_HS_TRDT_VALUE;
203 }
204 else
205 {
206 UsbTrd = USBD_DEFAULT_TRDT_VALUE;
207 }
208
209 USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
210 USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
211
212 return HAL_OK;
213 }
214
215 /**
216 * @brief USB_EnableGlobalInt
217 * Enables the controller's Global Int in the AHB Config reg
218 * @param USBx Selected device
219 * @retval HAL status
220 */
221 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
222 {
223 USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
224 return HAL_OK;
225 }
226
227 /**
228 * @brief USB_DisableGlobalInt
229 * Disable the controller's Global Int in the AHB Config reg
230 * @param USBx Selected device
231 * @retval HAL status
232 */
233 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
234 {
235 USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
236 return HAL_OK;
237 }
238
239 /**
240 * @brief USB_SetCurrentMode : Set functional mode
241 * @param USBx Selected device
242 * @param mode current core mode
243 * This parameter can be one of these values:
244 * @arg USB_DEVICE_MODE: Peripheral mode
245 * @arg USB_HOST_MODE: Host mode
246 * @arg USB_DRD_MODE: Dual Role Device mode
247 * @retval HAL status
248 */
249 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
250 {
251 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
252
253 if (mode == USB_HOST_MODE)
254 {
255 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
256 }
257 else if (mode == USB_DEVICE_MODE)
258 {
259 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
260 }
261 else
262 {
263 return HAL_ERROR;
264 }
265 HAL_Delay(50U);
266
267 return HAL_OK;
268 }
269
270 /**
271 * @brief USB_DevInit : Initializes the USB_OTG controller registers
272 * for device mode
273 * @param USBx Selected device
274 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
275 * the configuration information for the specified USBx peripheral.
276 * @retval HAL status
277 */
278 HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
279 {
280 HAL_StatusTypeDef ret = HAL_OK;
281 uint32_t USBx_BASE = (uint32_t)USBx;
282 uint32_t i;
283
284 for (i = 0U; i < 15U; i++)
285 {
286 USBx->DIEPTXF[i] = 0U;
287 }
288
289 /* VBUS Sensing setup */
290 if (cfg.vbus_sensing_enable == 0U)
291 {
292 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
293
294 /* Deactivate VBUS Sensing B */
295 USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
296
297 /* B-peripheral session valid override enable */
298 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
299 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
300 }
301 else
302 {
303 /* Enable HW VBUS sensing */
304 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
305 }
306
307 /* Restart the Phy Clock */
308 USBx_PCGCCTL = 0U;
309
310 /* Device mode configuration */
311 USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
312
313 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
314 {
315 if (cfg.speed == USBD_HS_SPEED)
316 {
317 /* Set Core speed to High speed mode */
318 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
319 }
320 else
321 {
322 /* Set Core speed to Full speed mode */
323 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
324 }
325 }
326 else
327 {
328 /* Set Core speed to Full speed mode */
329 (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
330 }
331
332 /* Flush the FIFOs */
333 if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
334 {
335 ret = HAL_ERROR;
336 }
337
338 if (USB_FlushRxFifo(USBx) != HAL_OK)
339 {
340 ret = HAL_ERROR;
341 }
342
343 /* Clear all pending Device Interrupts */
344 USBx_DEVICE->DIEPMSK = 0U;
345 USBx_DEVICE->DOEPMSK = 0U;
346 USBx_DEVICE->DAINTMSK = 0U;
347
348 for (i = 0U; i < cfg.dev_endpoints; i++)
349 {
350 if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
351 {
352 if (i == 0U)
353 {
354 USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
355 }
356 else
357 {
358 USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
359 }
360 }
361 else
362 {
363 USBx_INEP(i)->DIEPCTL = 0U;
364 }
365
366 USBx_INEP(i)->DIEPTSIZ = 0U;
367 USBx_INEP(i)->DIEPINT = 0xFB7FU;
368 }
369
370 for (i = 0U; i < cfg.dev_endpoints; i++)
371 {
372 if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
373 {
374 if (i == 0U)
375 {
376 USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
377 }
378 else
379 {
380 USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
381 }
382 }
383 else
384 {
385 USBx_OUTEP(i)->DOEPCTL = 0U;
386 }
387
388 USBx_OUTEP(i)->DOEPTSIZ = 0U;
389 USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
390 }
391
392 USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
393
394 /* Disable all interrupts. */
395 USBx->GINTMSK = 0U;
396
397 /* Clear any pending interrupts */
398 USBx->GINTSTS = 0xBFFFFFFFU;
399
400 /* Enable the common interrupts */
401 if (cfg.dma_enable == 0U)
402 {
403 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
404 }
405
406 /* Enable interrupts matching to the Device mode ONLY */
407 USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
408 USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
409 USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
410 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
411
412 if (cfg.Sof_enable != 0U)
413 {
414 USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
415 }
416
417 if (cfg.vbus_sensing_enable == 1U)
418 {
419 USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
420 }
421
422 return ret;
423 }
424
425 /**
426 * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
427 * @param USBx Selected device
428 * @param num FIFO number
429 * This parameter can be a value from 1 to 15
430 15 means Flush all Tx FIFOs
431 * @retval HAL status
432 */
433 HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
434 {
435 uint32_t count = 0U;
436
437 USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
438
439 do
440 {
441 if (++count > 200000U)
442 {
443 return HAL_TIMEOUT;
444 }
445 }
446 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
447
448 return HAL_OK;
449 }
450
451 /**
452 * @brief USB_FlushRxFifo : Flush Rx FIFO
453 * @param USBx Selected device
454 * @retval HAL status
455 */
456 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
457 {
458 uint32_t count = 0;
459
460 USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
461
462 do
463 {
464 if (++count > 200000U)
465 {
466 return HAL_TIMEOUT;
467 }
468 }
469 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
470
471 return HAL_OK;
472 }
473
474 /**
475 * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register
476 * depending the PHY type and the enumeration speed of the device.
477 * @param USBx Selected device
478 * @param speed device speed
479 * This parameter can be one of these values:
480 * @arg USB_OTG_SPEED_HIGH: High speed mode
481 * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
482 * @arg USB_OTG_SPEED_FULL: Full speed mode
483 * @retval Hal status
484 */
485 HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
486 {
487 uint32_t USBx_BASE = (uint32_t)USBx;
488
489 USBx_DEVICE->DCFG |= speed;
490 return HAL_OK;
491 }
492
493 /**
494 * @brief USB_GetDevSpeed Return the Dev Speed
495 * @param USBx Selected device
496 * @retval speed device speed
497 * This parameter can be one of these values:
498 * @arg PCD_SPEED_HIGH: High speed mode
499 * @arg PCD_SPEED_FULL: Full speed mode
500 */
501 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
502 {
503 uint32_t USBx_BASE = (uint32_t)USBx;
504 uint8_t speed;
505 uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
506
507 if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
508 {
509 speed = USBD_HS_SPEED;
510 }
511 else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
512 (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
513 {
514 speed = USBD_FS_SPEED;
515 }
516 else
517 {
518 speed = 0xFU;
519 }
520
521 return speed;
522 }
523
524 /**
525 * @brief Activate and configure an endpoint
526 * @param USBx Selected device
527 * @param ep pointer to endpoint structure
528 * @retval HAL status
529 */
530 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
531 {
532 uint32_t USBx_BASE = (uint32_t)USBx;
533 uint32_t epnum = (uint32_t)ep->num;
534
535 if (ep->is_in == 1U)
536 {
537 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
538
539 if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
540 {
541 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
542 ((uint32_t)ep->type << 18) | (epnum << 22) |
543 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
544 USB_OTG_DIEPCTL_USBAEP;
545 }
546 }
547 else
548 {
549 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
550
551 if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
552 {
553 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
554 ((uint32_t)ep->type << 18) |
555 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
556 USB_OTG_DOEPCTL_USBAEP;
557 }
558 }
559 return HAL_OK;
560 }
561
562 /**
563 * @brief Activate and configure a dedicated endpoint
564 * @param USBx Selected device
565 * @param ep pointer to endpoint structure
566 * @retval HAL status
567 */
568 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
569 {
570 uint32_t USBx_BASE = (uint32_t)USBx;
571 uint32_t epnum = (uint32_t)ep->num;
572
573 /* Read DEPCTLn register */
574 if (ep->is_in == 1U)
575 {
576 if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
577 {
578 USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
579 ((uint32_t)ep->type << 18) | (epnum << 22) |
580 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
581 USB_OTG_DIEPCTL_USBAEP;
582 }
583
584 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
585 }
586 else
587 {
588 if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
589 {
590 USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
591 ((uint32_t)ep->type << 18) | (epnum << 22) |
592 USB_OTG_DOEPCTL_USBAEP;
593 }
594
595 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
596 }
597
598 return HAL_OK;
599 }
600
601 /**
602 * @brief De-activate and de-initialize an endpoint
603 * @param USBx Selected device
604 * @param ep pointer to endpoint structure
605 * @retval HAL status
606 */
607 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
608 {
609 uint32_t USBx_BASE = (uint32_t)USBx;
610 uint32_t epnum = (uint32_t)ep->num;
611
612 /* Read DEPCTLn register */
613 if (ep->is_in == 1U)
614 {
615 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
616 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
617 USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
618 USB_OTG_DIEPCTL_MPSIZ |
619 USB_OTG_DIEPCTL_TXFNUM |
620 USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
621 USB_OTG_DIEPCTL_EPTYP);
622 }
623 else
624 {
625 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
626 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
627 USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
628 USB_OTG_DOEPCTL_MPSIZ |
629 USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
630 USB_OTG_DOEPCTL_EPTYP);
631 }
632
633 return HAL_OK;
634 }
635
636 /**
637 * @brief De-activate and de-initialize a dedicated endpoint
638 * @param USBx Selected device
639 * @param ep pointer to endpoint structure
640 * @retval HAL status
641 */
642 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
643 {
644 uint32_t USBx_BASE = (uint32_t)USBx;
645 uint32_t epnum = (uint32_t)ep->num;
646
647 /* Read DEPCTLn register */
648 if (ep->is_in == 1U)
649 {
650 USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
651 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
652 }
653 else
654 {
655 USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
656 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
657 }
658
659 return HAL_OK;
660 }
661
662 /**
663 * @brief USB_EPStartXfer : setup and starts a transfer over an EP
664 * @param USBx Selected device
665 * @param ep pointer to endpoint structure
666 * @param dma USB dma enabled or disabled
667 * This parameter can be one of these values:
668 * 0 : DMA feature not used
669 * 1 : DMA feature used
670 * @retval HAL status
671 */
672 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
673 {
674 uint32_t USBx_BASE = (uint32_t)USBx;
675 uint32_t epnum = (uint32_t)ep->num;
676 uint16_t pktcnt;
677
678 /* IN endpoint */
679 if (ep->is_in == 1U)
680 {
681 /* Zero Length Packet? */
682 if (ep->xfer_len == 0U)
683 {
684 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
685 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
686 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
687 }
688 else
689 {
690 /* Program the transfer size and packet count
691 * as follows: xfersize = N * maxpacket +
692 * short_packet pktcnt = N + (short_packet
693 * exist ? 1 : 0)
694 */
695 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
696 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
697 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
698 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
699
700 if (ep->type == EP_TYPE_ISOC)
701 {
702 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
703 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
704 }
705 }
706
707 if (dma == 1U)
708 {
709 if ((uint32_t)ep->dma_addr != 0U)
710 {
711 USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
712 }
713
714 if (ep->type == EP_TYPE_ISOC)
715 {
716 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
717 {
718 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
719 }
720 else
721 {
722 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
723 }
724 }
725
726 /* EP enable, IN data in FIFO */
727 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
728 }
729 else
730 {
731 /* EP enable, IN data in FIFO */
732 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
733
734 if (ep->type != EP_TYPE_ISOC)
735 {
736 /* Enable the Tx FIFO Empty Interrupt for this EP */
737 if (ep->xfer_len > 0U)
738 {
739 USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
740 }
741 }
742 else
743 {
744 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
745 {
746 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
747 }
748 else
749 {
750 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
751 }
752
753 (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
754 }
755 }
756 }
757 else /* OUT endpoint */
758 {
759 /* Program the transfer size and packet count as follows:
760 * pktcnt = N
761 * xfersize = N * maxpacket
762 */
763 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
764 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
765
766 if (ep->xfer_len == 0U)
767 {
768 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
769 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
770 }
771 else
772 {
773 pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
774 USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
775 USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
776 }
777
778 if (dma == 1U)
779 {
780 if ((uint32_t)ep->xfer_buff != 0U)
781 {
782 USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
783 }
784 }
785
786 if (ep->type == EP_TYPE_ISOC)
787 {
788 if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
789 {
790 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
791 }
792 else
793 {
794 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
795 }
796 }
797 /* EP enable */
798 USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
799 }
800
801 return HAL_OK;
802 }
803
804 /**
805 * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
806 * @param USBx Selected device
807 * @param ep pointer to endpoint structure
808 * @param dma USB dma enabled or disabled
809 * This parameter can be one of these values:
810 * 0 : DMA feature not used
811 * 1 : DMA feature used
812 * @retval HAL status
813 */
814 HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
815 {
816 uint32_t USBx_BASE = (uint32_t)USBx;
817 uint32_t epnum = (uint32_t)ep->num;
818
819 /* IN endpoint */
820 if (ep->is_in == 1U)
821 {
822 /* Zero Length Packet? */
823 if (ep->xfer_len == 0U)
824 {
825 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
826 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
827 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
828 }
829 else
830 {
831 /* Program the transfer size and packet count
832 * as follows: xfersize = N * maxpacket +
833 * short_packet pktcnt = N + (short_packet
834 * exist ? 1 : 0)
835 */
836 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
837 USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
838
839 if (ep->xfer_len > ep->maxpacket)
840 {
841 ep->xfer_len = ep->maxpacket;
842 }
843 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
844 USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
845 }
846
847 if (dma == 1U)
848 {
849 if ((uint32_t)ep->dma_addr != 0U)
850 {
851 USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
852 }
853
854 /* EP enable, IN data in FIFO */
855 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
856 }
857 else
858 {
859 /* EP enable, IN data in FIFO */
860 USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
861
862 /* Enable the Tx FIFO Empty Interrupt for this EP */
863 if (ep->xfer_len > 0U)
864 {
865 USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
866 }
867 }
868 }
869 else /* OUT endpoint */
870 {
871 /* Program the transfer size and packet count as follows:
872 * pktcnt = N
873 * xfersize = N * maxpacket
874 */
875 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
876 USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
877
878 if (ep->xfer_len > 0U)
879 {
880 ep->xfer_len = ep->maxpacket;
881 }
882
883 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
884 USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
885
886 if (dma == 1U)
887 {
888 if ((uint32_t)ep->xfer_buff != 0U)
889 {
890 USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
891 }
892 }
893
894 /* EP enable */
895 USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
896 }
897
898 return HAL_OK;
899 }
900
901 /**
902 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
903 * with the EP/channel
904 * @param USBx Selected device
905 * @param src pointer to source buffer
906 * @param ch_ep_num endpoint or host channel number
907 * @param len Number of bytes to write
908 * @param dma USB dma enabled or disabled
909 * This parameter can be one of these values:
910 * 0 : DMA feature not used
911 * 1 : DMA feature used
912 * @retval HAL status
913 */
914 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
915 {
916 uint32_t USBx_BASE = (uint32_t)USBx;
917 uint32_t *pSrc = (uint32_t *)src;
918 uint32_t count32b, i;
919
920 if (dma == 0U)
921 {
922 count32b = ((uint32_t)len + 3U) / 4U;
923 for (i = 0U; i < count32b; i++)
924 {
925 USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
926 pSrc++;
927 }
928 }
929
930 return HAL_OK;
931 }
932
933 /**
934 * @brief USB_ReadPacket : read a packet from the RX FIFO
935 * @param USBx Selected device
936 * @param dest source pointer
937 * @param len Number of bytes to read
938 * @retval pointer to destination buffer
939 */
940 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
941 {
942 uint32_t USBx_BASE = (uint32_t)USBx;
943 uint32_t *pDest = (uint32_t *)dest;
944 uint32_t i;
945 uint32_t count32b = ((uint32_t)len + 3U) / 4U;
946
947 for (i = 0U; i < count32b; i++)
948 {
949 __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
950 pDest++;
951 }
952
953 return ((void *)pDest);
954 }
955
956 /**
957 * @brief USB_EPSetStall : set a stall condition over an EP
958 * @param USBx Selected device
959 * @param ep pointer to endpoint structure
960 * @retval HAL status
961 */
962 HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
963 {
964 uint32_t USBx_BASE = (uint32_t)USBx;
965 uint32_t epnum = (uint32_t)ep->num;
966
967 if (ep->is_in == 1U)
968 {
969 if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
970 {
971 USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
972 }
973 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
974 }
975 else
976 {
977 if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
978 {
979 USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
980 }
981 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
982 }
983
984 return HAL_OK;
985 }
986
987 /**
988 * @brief USB_EPClearStall : Clear a stall condition over an EP
989 * @param USBx Selected device
990 * @param ep pointer to endpoint structure
991 * @retval HAL status
992 */
993 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
994 {
995 uint32_t USBx_BASE = (uint32_t)USBx;
996 uint32_t epnum = (uint32_t)ep->num;
997
998 if (ep->is_in == 1U)
999 {
1000 USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
1001 if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
1002 {
1003 USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
1004 }
1005 }
1006 else
1007 {
1008 USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
1009 if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
1010 {
1011 USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
1012 }
1013 }
1014 return HAL_OK;
1015 }
1016
1017 /**
1018 * @brief USB_StopDevice : Stop the usb device mode
1019 * @param USBx Selected device
1020 * @retval HAL status
1021 */
1022 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
1023 {
1024 HAL_StatusTypeDef ret;
1025 uint32_t USBx_BASE = (uint32_t)USBx;
1026 uint32_t i;
1027
1028 /* Clear Pending interrupt */
1029 for (i = 0U; i < 15U; i++)
1030 {
1031 USBx_INEP(i)->DIEPINT = 0xFB7FU;
1032 USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
1033 }
1034
1035 /* Clear interrupt masks */
1036 USBx_DEVICE->DIEPMSK = 0U;
1037 USBx_DEVICE->DOEPMSK = 0U;
1038 USBx_DEVICE->DAINTMSK = 0U;
1039
1040 /* Flush the FIFO */
1041 ret = USB_FlushRxFifo(USBx);
1042 if (ret != HAL_OK)
1043 {
1044 return ret;
1045 }
1046
1047 ret = USB_FlushTxFifo(USBx, 0x10U);
1048 if (ret != HAL_OK)
1049 {
1050 return ret;
1051 }
1052
1053 return ret;
1054 }
1055
1056 /**
1057 * @brief USB_SetDevAddress : Stop the usb device mode
1058 * @param USBx Selected device
1059 * @param address new device address to be assigned
1060 * This parameter can be a value from 0 to 255
1061 * @retval HAL status
1062 */
1063 HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
1064 {
1065 uint32_t USBx_BASE = (uint32_t)USBx;
1066
1067 USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
1068 USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
1069
1070 return HAL_OK;
1071 }
1072
1073 /**
1074 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
1075 * @param USBx Selected device
1076 * @retval HAL status
1077 */
1078 HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
1079 {
1080 uint32_t USBx_BASE = (uint32_t)USBx;
1081
1082 USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
1083 HAL_Delay(3U);
1084
1085 return HAL_OK;
1086 }
1087
1088 /**
1089 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
1090 * @param USBx Selected device
1091 * @retval HAL status
1092 */
1093 HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
1094 {
1095 uint32_t USBx_BASE = (uint32_t)USBx;
1096
1097 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
1098 HAL_Delay(3U);
1099
1100 return HAL_OK;
1101 }
1102
1103 /**
1104 * @brief USB_ReadInterrupts: return the global USB interrupt status
1105 * @param USBx Selected device
1106 * @retval HAL status
1107 */
1108 uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
1109 {
1110 uint32_t tmpreg;
1111
1112 tmpreg = USBx->GINTSTS;
1113 tmpreg &= USBx->GINTMSK;
1114
1115 return tmpreg;
1116 }
1117
1118 /**
1119 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
1120 * @param USBx Selected device
1121 * @retval HAL status
1122 */
1123 uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
1124 {
1125 uint32_t USBx_BASE = (uint32_t)USBx;
1126 uint32_t tmpreg;
1127
1128 tmpreg = USBx_DEVICE->DAINT;
1129 tmpreg &= USBx_DEVICE->DAINTMSK;
1130
1131 return ((tmpreg & 0xffff0000U) >> 16);
1132 }
1133
1134 /**
1135 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
1136 * @param USBx Selected device
1137 * @retval HAL status
1138 */
1139 uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
1140 {
1141 uint32_t USBx_BASE = (uint32_t)USBx;
1142 uint32_t tmpreg;
1143
1144 tmpreg = USBx_DEVICE->DAINT;
1145 tmpreg &= USBx_DEVICE->DAINTMSK;
1146
1147 return ((tmpreg & 0xFFFFU));
1148 }
1149
1150 /**
1151 * @brief Returns Device OUT EP Interrupt register
1152 * @param USBx Selected device
1153 * @param epnum endpoint number
1154 * This parameter can be a value from 0 to 15
1155 * @retval Device OUT EP Interrupt register
1156 */
1157 uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
1158 {
1159 uint32_t USBx_BASE = (uint32_t)USBx;
1160 uint32_t tmpreg;
1161
1162 tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
1163 tmpreg &= USBx_DEVICE->DOEPMSK;
1164
1165 return tmpreg;
1166 }
1167
1168 /**
1169 * @brief Returns Device IN EP Interrupt register
1170 * @param USBx Selected device
1171 * @param epnum endpoint number
1172 * This parameter can be a value from 0 to 15
1173 * @retval Device IN EP Interrupt register
1174 */
1175 uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
1176 {
1177 uint32_t USBx_BASE = (uint32_t)USBx;
1178 uint32_t tmpreg, msk, emp;
1179
1180 msk = USBx_DEVICE->DIEPMSK;
1181 emp = USBx_DEVICE->DIEPEMPMSK;
1182 msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
1183 tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
1184
1185 return tmpreg;
1186 }
1187
1188 /**
1189 * @brief USB_ClearInterrupts: clear a USB interrupt
1190 * @param USBx Selected device
1191 * @param interrupt interrupt flag
1192 * @retval None
1193 */
1194 void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
1195 {
1196 USBx->GINTSTS |= interrupt;
1197 }
1198
1199 /**
1200 * @brief Returns USB core mode
1201 * @param USBx Selected device
1202 * @retval return core mode : Host or Device
1203 * This parameter can be one of these values:
1204 * 0 : Host
1205 * 1 : Device
1206 */
1207 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
1208 {
1209 return ((USBx->GINTSTS) & 0x1U);
1210 }
1211
1212 /**
1213 * @brief Activate EP0 for Setup transactions
1214 * @param USBx Selected device
1215 * @retval HAL status
1216 */
1217 HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
1218 {
1219 uint32_t USBx_BASE = (uint32_t)USBx;
1220
1221 /* Set the MPS of the IN EP0 to 64 bytes */
1222 USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
1223
1224 USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
1225
1226 return HAL_OK;
1227 }
1228
1229 /**
1230 * @brief Prepare the EP0 to start the first control setup
1231 * @param USBx Selected device
1232 * @param dma USB dma enabled or disabled
1233 * This parameter can be one of these values:
1234 * 0 : DMA feature not used
1235 * 1 : DMA feature used
1236 * @param psetup pointer to setup packet
1237 * @retval HAL status
1238 */
1239 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
1240 {
1241 uint32_t USBx_BASE = (uint32_t)USBx;
1242 uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
1243
1244 if (gSNPSiD > USB_OTG_CORE_ID_300A)
1245 {
1246 if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
1247 {
1248 return HAL_OK;
1249 }
1250 }
1251
1252 USBx_OUTEP(0U)->DOEPTSIZ = 0U;
1253 USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
1254 USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
1255 USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
1256
1257 if (dma == 1U)
1258 {
1259 USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
1260 /* EP enable */
1261 USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
1262 }
1263
1264 return HAL_OK;
1265 }
1266
1267 /**
1268 * @brief Reset the USB Core (needed after USB clock settings change)
1269 * @param USBx Selected device
1270 * @retval HAL status
1271 */
1272 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
1273 {
1274 uint32_t count = 0U;
1275
1276 /* Wait for AHB master IDLE state. */
1277 do
1278 {
1279 if (++count > 200000U)
1280 {
1281 return HAL_TIMEOUT;
1282 }
1283 }
1284 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
1285
1286 /* Core Soft Reset */
1287 count = 0U;
1288 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
1289
1290 do
1291 {
1292 if (++count > 200000U)
1293 {
1294 return HAL_TIMEOUT;
1295 }
1296 }
1297 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
1298
1299 return HAL_OK;
1300 }
1301
1302 /**
1303 * @brief USB_HostInit : Initializes the USB OTG controller registers
1304 * for Host mode
1305 * @param USBx Selected device
1306 * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
1307 * the configuration information for the specified USBx peripheral.
1308 * @retval HAL status
1309 */
1310 HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
1311 {
1312 uint32_t USBx_BASE = (uint32_t)USBx;
1313 uint32_t i;
1314
1315 /* Restart the Phy Clock */
1316 USBx_PCGCCTL = 0U;
1317
1318 /* Disable VBUS sensing */
1319 USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
1320
1321 /* Disable Battery chargin detector */
1322 USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
1323
1324
1325 if ((USBx->CID & (0x1U << 8)) != 0U)
1326 {
1327 if (cfg.speed == USB_OTG_SPEED_FULL)
1328 {
1329 /* Force Device Enumeration to FS/LS mode only */
1330 USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
1331 }
1332 else
1333 {
1334 /* Set default Max speed support */
1335 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
1336 }
1337 }
1338 else
1339 {
1340 /* Set default Max speed support */
1341 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
1342 }
1343
1344 /* Make sure the FIFOs are flushed. */
1345 (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
1346 (void)USB_FlushRxFifo(USBx);
1347
1348 /* Clear all pending HC Interrupts */
1349 for (i = 0U; i < cfg.Host_channels; i++)
1350 {
1351 USBx_HC(i)->HCINT = 0xFFFFFFFFU;
1352 USBx_HC(i)->HCINTMSK = 0U;
1353 }
1354
1355 /* Enable VBUS driving */
1356 (void)USB_DriveVbus(USBx, 1U);
1357
1358 HAL_Delay(200U);
1359
1360 /* Disable all interrupts. */
1361 USBx->GINTMSK = 0U;
1362
1363 /* Clear any pending interrupts */
1364 USBx->GINTSTS = 0xFFFFFFFFU;
1365
1366 if ((USBx->CID & (0x1U << 8)) != 0U)
1367 {
1368 /* set Rx FIFO size */
1369 USBx->GRXFSIZ = 0x200U;
1370 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
1371 USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
1372 }
1373 else
1374 {
1375 /* set Rx FIFO size */
1376 USBx->GRXFSIZ = 0x80U;
1377 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
1378 USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
1379 }
1380
1381 /* Enable the common interrupts */
1382 if (cfg.dma_enable == 0U)
1383 {
1384 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
1385 }
1386
1387 /* Enable interrupts matching to the Host mode ONLY */
1388 USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
1389 USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
1390 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
1391
1392 return HAL_OK;
1393 }
1394
1395 /**
1396 * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
1397 * HCFG register on the PHY type and set the right frame interval
1398 * @param USBx Selected device
1399 * @param freq clock frequency
1400 * This parameter can be one of these values:
1401 * HCFG_48_MHZ : Full Speed 48 MHz Clock
1402 * HCFG_6_MHZ : Low Speed 6 MHz Clock
1403 * @retval HAL status
1404 */
1405 HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
1406 {
1407 uint32_t USBx_BASE = (uint32_t)USBx;
1408
1409 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
1410 USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
1411
1412 if (freq == HCFG_48_MHZ)
1413 {
1414 USBx_HOST->HFIR = 48000U;
1415 }
1416 else if (freq == HCFG_6_MHZ)
1417 {
1418 USBx_HOST->HFIR = 6000U;
1419 }
1420 else
1421 {
1422 /* ... */
1423 }
1424
1425 return HAL_OK;
1426 }
1427
1428 /**
1429 * @brief USB_OTG_ResetPort : Reset Host Port
1430 * @param USBx Selected device
1431 * @retval HAL status
1432 * @note (1)The application must wait at least 10 ms
1433 * before clearing the reset bit.
1434 */
1435 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
1436 {
1437 uint32_t USBx_BASE = (uint32_t)USBx;
1438
1439 __IO uint32_t hprt0 = 0U;
1440
1441 hprt0 = USBx_HPRT0;
1442
1443 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1444 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1445
1446 USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
1447 HAL_Delay(100U); /* See Note #1 */
1448 USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
1449 HAL_Delay(10U);
1450
1451 return HAL_OK;
1452 }
1453
1454 /**
1455 * @brief USB_DriveVbus : activate or de-activate vbus
1456 * @param state VBUS state
1457 * This parameter can be one of these values:
1458 * 0 : VBUS Active
1459 * 1 : VBUS Inactive
1460 * @retval HAL status
1461 */
1462 HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
1463 {
1464 uint32_t USBx_BASE = (uint32_t)USBx;
1465 __IO uint32_t hprt0 = 0U;
1466
1467 hprt0 = USBx_HPRT0;
1468
1469 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1470 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1471
1472 if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
1473 {
1474 USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
1475 }
1476 if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
1477 {
1478 USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
1479 }
1480 return HAL_OK;
1481 }
1482
1483 /**
1484 * @brief Return Host Core speed
1485 * @param USBx Selected device
1486 * @retval speed : Host speed
1487 * This parameter can be one of these values:
1488 * @arg HCD_SPEED_HIGH: High speed mode
1489 * @arg HCD_SPEED_FULL: Full speed mode
1490 * @arg HCD_SPEED_LOW: Low speed mode
1491 */
1492 uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
1493 {
1494 uint32_t USBx_BASE = (uint32_t)USBx;
1495 __IO uint32_t hprt0 = 0U;
1496
1497 hprt0 = USBx_HPRT0;
1498 return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
1499 }
1500
1501 /**
1502 * @brief Return Host Current Frame number
1503 * @param USBx Selected device
1504 * @retval current frame number
1505 */
1506 uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
1507 {
1508 uint32_t USBx_BASE = (uint32_t)USBx;
1509
1510 return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
1511 }
1512
1513 /**
1514 * @brief Initialize a host channel
1515 * @param USBx Selected device
1516 * @param ch_num Channel number
1517 * This parameter can be a value from 1 to 15
1518 * @param epnum Endpoint number
1519 * This parameter can be a value from 1 to 15
1520 * @param dev_address Current device address
1521 * This parameter can be a value from 0 to 255
1522 * @param speed Current device speed
1523 * This parameter can be one of these values:
1524 * @arg USB_OTG_SPEED_HIGH: High speed mode
1525 * @arg USB_OTG_SPEED_FULL: Full speed mode
1526 * @arg USB_OTG_SPEED_LOW: Low speed mode
1527 * @param ep_type Endpoint Type
1528 * This parameter can be one of these values:
1529 * @arg EP_TYPE_CTRL: Control type
1530 * @arg EP_TYPE_ISOC: Isochronous type
1531 * @arg EP_TYPE_BULK: Bulk type
1532 * @arg EP_TYPE_INTR: Interrupt type
1533 * @param mps Max Packet Size
1534 * This parameter can be a value from 0 to32K
1535 * @retval HAL state
1536 */
1537 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
1538 uint8_t ch_num,
1539 uint8_t epnum,
1540 uint8_t dev_address,
1541 uint8_t speed,
1542 uint8_t ep_type,
1543 uint16_t mps)
1544 {
1545 HAL_StatusTypeDef ret = HAL_OK;
1546 uint32_t USBx_BASE = (uint32_t)USBx;
1547 uint32_t HCcharEpDir, HCcharLowSpeed;
1548
1549 /* Clear old interrupt conditions for this host channel. */
1550 USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
1551
1552 /* Enable channel interrupts required for this transfer. */
1553 switch (ep_type)
1554 {
1555 case EP_TYPE_CTRL:
1556 case EP_TYPE_BULK:
1557 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1558 USB_OTG_HCINTMSK_STALLM |
1559 USB_OTG_HCINTMSK_TXERRM |
1560 USB_OTG_HCINTMSK_DTERRM |
1561 USB_OTG_HCINTMSK_AHBERR |
1562 USB_OTG_HCINTMSK_NAKM;
1563
1564 if ((epnum & 0x80U) == 0x80U)
1565 {
1566 USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1567 }
1568 else
1569 {
1570 if ((USBx->CID & (0x1U << 8)) != 0U)
1571 {
1572 USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
1573 }
1574 }
1575 break;
1576
1577 case EP_TYPE_INTR:
1578 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1579 USB_OTG_HCINTMSK_STALLM |
1580 USB_OTG_HCINTMSK_TXERRM |
1581 USB_OTG_HCINTMSK_DTERRM |
1582 USB_OTG_HCINTMSK_NAKM |
1583 USB_OTG_HCINTMSK_AHBERR |
1584 USB_OTG_HCINTMSK_FRMORM;
1585
1586 if ((epnum & 0x80U) == 0x80U)
1587 {
1588 USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1589 }
1590
1591 break;
1592
1593 case EP_TYPE_ISOC:
1594 USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
1595 USB_OTG_HCINTMSK_ACKM |
1596 USB_OTG_HCINTMSK_AHBERR |
1597 USB_OTG_HCINTMSK_FRMORM;
1598
1599 if ((epnum & 0x80U) == 0x80U)
1600 {
1601 USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
1602 }
1603 break;
1604
1605 default:
1606 ret = HAL_ERROR;
1607 break;
1608 }
1609
1610 /* Enable the top level host channel interrupt. */
1611 USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
1612
1613 /* Make sure host channel interrupts are enabled. */
1614 USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
1615
1616 /* Program the HCCHAR register */
1617 if ((epnum & 0x80U) == 0x80U)
1618 {
1619 HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
1620 }
1621 else
1622 {
1623 HCcharEpDir = 0U;
1624 }
1625
1626 if (speed == HPRT0_PRTSPD_LOW_SPEED)
1627 {
1628 HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
1629 }
1630 else
1631 {
1632 HCcharLowSpeed = 0U;
1633 }
1634
1635 USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
1636 ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
1637 (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
1638 ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
1639
1640 if (ep_type == EP_TYPE_INTR)
1641 {
1642 USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
1643 }
1644
1645 return ret;
1646 }
1647
1648 /**
1649 * @brief Start a transfer over a host channel
1650 * @param USBx Selected device
1651 * @param hc pointer to host channel structure
1652 * @param dma USB dma enabled or disabled
1653 * This parameter can be one of these values:
1654 * 0 : DMA feature not used
1655 * 1 : DMA feature used
1656 * @retval HAL state
1657 */
1658 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
1659 {
1660 uint32_t USBx_BASE = (uint32_t)USBx;
1661 uint32_t ch_num = (uint32_t)hc->ch_num;
1662 static __IO uint32_t tmpreg = 0U;
1663 uint8_t is_oddframe;
1664 uint16_t len_words;
1665 uint16_t num_packets;
1666 uint16_t max_hc_pkt_count = 256U;
1667
1668 if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
1669 {
1670 if ((dma == 0U) && (hc->do_ping == 1U))
1671 {
1672 (void)USB_DoPing(USBx, hc->ch_num);
1673 return HAL_OK;
1674 }
1675 else if (dma == 1U)
1676 {
1677 USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
1678 hc->do_ping = 0U;
1679 }
1680 else
1681 {
1682 /* ... */
1683 }
1684 }
1685
1686 /* Compute the expected number of packets associated to the transfer */
1687 if (hc->xfer_len > 0U)
1688 {
1689 num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
1690
1691 if (num_packets > max_hc_pkt_count)
1692 {
1693 num_packets = max_hc_pkt_count;
1694 hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
1695 }
1696 }
1697 else
1698 {
1699 num_packets = 1U;
1700 }
1701 if (hc->ep_is_in != 0U)
1702 {
1703 hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
1704 }
1705
1706 /* Initialize the HCTSIZn register */
1707 USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
1708 (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
1709 (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
1710
1711 if (dma != 0U)
1712 {
1713 /* xfer_buff MUST be 32-bits aligned */
1714 USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
1715 }
1716
1717 is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
1718 USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
1719 USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
1720
1721 /* Set host channel enable */
1722 tmpreg = USBx_HC(ch_num)->HCCHAR;
1723 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
1724
1725 /* make sure to set the correct ep direction */
1726 if (hc->ep_is_in != 0U)
1727 {
1728 tmpreg |= USB_OTG_HCCHAR_EPDIR;
1729 }
1730 else
1731 {
1732 tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
1733 }
1734 tmpreg |= USB_OTG_HCCHAR_CHENA;
1735 USBx_HC(ch_num)->HCCHAR = tmpreg;
1736
1737 if (dma == 0U) /* Slave mode */
1738 {
1739 if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
1740 {
1741 switch (hc->ep_type)
1742 {
1743 /* Non periodic transfer */
1744 case EP_TYPE_CTRL:
1745 case EP_TYPE_BULK:
1746
1747 len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
1748
1749 /* check if there is enough space in FIFO space */
1750 if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
1751 {
1752 /* need to process data in nptxfempty interrupt */
1753 USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
1754 }
1755 break;
1756
1757 /* Periodic transfer */
1758 case EP_TYPE_INTR:
1759 case EP_TYPE_ISOC:
1760 len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
1761 /* check if there is enough space in FIFO space */
1762 if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
1763 {
1764 /* need to process data in ptxfempty interrupt */
1765 USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
1766 }
1767 break;
1768
1769 default:
1770 break;
1771 }
1772
1773 /* Write packet into the Tx FIFO. */
1774 (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
1775 }
1776 }
1777
1778 return HAL_OK;
1779 }
1780
1781 /**
1782 * @brief Read all host channel interrupts status
1783 * @param USBx Selected device
1784 * @retval HAL state
1785 */
1786 uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
1787 {
1788 uint32_t USBx_BASE = (uint32_t)USBx;
1789
1790 return ((USBx_HOST->HAINT) & 0xFFFFU);
1791 }
1792
1793 /**
1794 * @brief Halt a host channel
1795 * @param USBx Selected device
1796 * @param hc_num Host Channel number
1797 * This parameter can be a value from 1 to 15
1798 * @retval HAL state
1799 */
1800 HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
1801 {
1802 uint32_t USBx_BASE = (uint32_t)USBx;
1803 uint32_t hcnum = (uint32_t)hc_num;
1804 uint32_t count = 0U;
1805 uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
1806
1807 /* Check for space in the request queue to issue the halt. */
1808 if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
1809 {
1810 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1811
1812 if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
1813 {
1814 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1815 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1816 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1817 do
1818 {
1819 if (++count > 1000U)
1820 {
1821 break;
1822 }
1823 }
1824 while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1825 }
1826 else
1827 {
1828 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1829 }
1830 }
1831 else
1832 {
1833 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1834
1835 if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
1836 {
1837 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1838 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1839 USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1840 do
1841 {
1842 if (++count > 1000U)
1843 {
1844 break;
1845 }
1846 }
1847 while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1848 }
1849 else
1850 {
1851 USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1852 }
1853 }
1854
1855 return HAL_OK;
1856 }
1857
1858 /**
1859 * @brief Initiate Do Ping protocol
1860 * @param USBx Selected device
1861 * @param hc_num Host Channel number
1862 * This parameter can be a value from 1 to 15
1863 * @retval HAL state
1864 */
1865 HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
1866 {
1867 uint32_t USBx_BASE = (uint32_t)USBx;
1868 uint32_t chnum = (uint32_t)ch_num;
1869 uint32_t num_packets = 1U;
1870 uint32_t tmpreg;
1871
1872 USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
1873 USB_OTG_HCTSIZ_DOPING;
1874
1875 /* Set host channel enable */
1876 tmpreg = USBx_HC(chnum)->HCCHAR;
1877 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
1878 tmpreg |= USB_OTG_HCCHAR_CHENA;
1879 USBx_HC(chnum)->HCCHAR = tmpreg;
1880
1881 return HAL_OK;
1882 }
1883
1884 /**
1885 * @brief Stop Host Core
1886 * @param USBx Selected device
1887 * @retval HAL state
1888 */
1889 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
1890 {
1891 uint32_t USBx_BASE = (uint32_t)USBx;
1892 uint32_t count = 0U;
1893 uint32_t value;
1894 uint32_t i;
1895
1896 (void)USB_DisableGlobalInt(USBx);
1897
1898 /* Flush FIFO */
1899 (void)USB_FlushTxFifo(USBx, 0x10U);
1900 (void)USB_FlushRxFifo(USBx);
1901
1902 /* Flush out any leftover queued requests. */
1903 for (i = 0U; i <= 15U; i++)
1904 {
1905 value = USBx_HC(i)->HCCHAR;
1906 value |= USB_OTG_HCCHAR_CHDIS;
1907 value &= ~USB_OTG_HCCHAR_CHENA;
1908 value &= ~USB_OTG_HCCHAR_EPDIR;
1909 USBx_HC(i)->HCCHAR = value;
1910 }
1911
1912 /* Halt all channels to put them into a known state. */
1913 for (i = 0U; i <= 15U; i++)
1914 {
1915 value = USBx_HC(i)->HCCHAR;
1916 value |= USB_OTG_HCCHAR_CHDIS;
1917 value |= USB_OTG_HCCHAR_CHENA;
1918 value &= ~USB_OTG_HCCHAR_EPDIR;
1919 USBx_HC(i)->HCCHAR = value;
1920
1921 do
1922 {
1923 if (++count > 1000U)
1924 {
1925 break;
1926 }
1927 }
1928 while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1929 }
1930
1931 /* Clear any pending Host interrupts */
1932 USBx_HOST->HAINT = 0xFFFFFFFFU;
1933 USBx->GINTSTS = 0xFFFFFFFFU;
1934
1935 (void)USB_EnableGlobalInt(USBx);
1936
1937 return HAL_OK;
1938 }
1939
1940 /**
1941 * @brief USB_ActivateRemoteWakeup active remote wakeup signalling
1942 * @param USBx Selected device
1943 * @retval HAL status
1944 */
1945 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
1946 {
1947 uint32_t USBx_BASE = (uint32_t)USBx;
1948
1949 if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
1950 {
1951 /* active Remote wakeup signalling */
1952 USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
1953 }
1954
1955 return HAL_OK;
1956 }
1957
1958 /**
1959 * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
1960 * @param USBx Selected device
1961 * @retval HAL status
1962 */
1963 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
1964 {
1965 uint32_t USBx_BASE = (uint32_t)USBx;
1966
1967 /* active Remote wakeup signalling */
1968 USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
1969
1970 return HAL_OK;
1971 }
1972 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
1973
1974
1975 /**
1976 * @}
1977 */
1978
1979 /**
1980 * @}
1981 */
1982 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
1983 #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
1984
1985 /**
1986 * @}
1987 */
1988
1989 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software