src/main/drivers/accgyro/accgyro_mpu.h

   1 /*
   2  * This file is part of Cleanflight.
   3  *
   4  * Cleanflight is free software: you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 3 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Cleanflight is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with Cleanflight.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #pragma once
  19
  20 #include "drivers/sensor.h"
  21 #include "drivers/accgyro/accgyro.h"
  22
  23 #define MPU6000_WHO_AM_I_CONST              (0x68)
  24 #define MPU6500_WHO_AM_I_CONST              (0x70)
  25 #define MPU9250_WHO_AM_I_CONST              (0x71)
  26 #define MPU9255_WHO_AM_I_CONST              (0x73)
  27 #define ICM20601_WHO_AM_I_CONST             (0xAC)
  28 #define ICM20602_WHO_AM_I_CONST             (0x12)
  29 #define ICM20608G_WHO_AM_I_CONST            (0xAF)
  30 #define ICM20689_WHO_AM_I_CONST             (0x98)
  31 #define ICM42605_WHO_AM_I_CONST             (0x42)
  32 #define ICM42688P_WHO_AM_I_CONST            (0x47)
  33
  34
  35 // RA = Register Address
  36
  37 #define MPU_RA_XG_OFFS_TC       0x00    //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
  38 #define MPU_RA_YG_OFFS_TC       0x01    //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
  39 #define MPU_RA_ZG_OFFS_TC       0x02    //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
  40 #define MPU_RA_X_FINE_GAIN      0x03    //[7:0] X_FINE_GAIN
  41 #define MPU_RA_Y_FINE_GAIN      0x04    //[7:0] Y_FINE_GAIN
  42 #define MPU_RA_Z_FINE_GAIN      0x05    //[7:0] Z_FINE_GAIN
  43 #define MPU_RA_XA_OFFS_H        0x06    //[15:0] XA_OFFS
  44 #define MPU_RA_XA_OFFS_L_TC     0x07
  45 #define MPU_RA_YA_OFFS_H        0x08    //[15:0] YA_OFFS
  46 #define MPU_RA_YA_OFFS_L_TC     0x09
  47 #define MPU_RA_ZA_OFFS_H        0x0A    //[15:0] ZA_OFFS
  48 #define MPU_RA_ZA_OFFS_L_TC     0x0B
  49 #define MPU_RA_PRODUCT_ID       0x0C    // Product ID Register
  50 #define MPU_RA_XG_OFFS_USRH     0x13    //[15:0] XG_OFFS_USR
  51 #define MPU_RA_XG_OFFS_USRL     0x14
  52 #define MPU_RA_YG_OFFS_USRH     0x15    //[15:0] YG_OFFS_USR
  53 #define MPU_RA_YG_OFFS_USRL     0x16
  54 #define MPU_RA_ZG_OFFS_USRH     0x17    //[15:0] ZG_OFFS_USR
  55 #define MPU_RA_ZG_OFFS_USRL     0x18
  56 #define MPU_RA_SMPLRT_DIV       0x19
  57 #define MPU_RA_CONFIG           0x1A
  58 #define MPU_RA_GYRO_CONFIG      0x1B
  59 #define MPU_RA_ACCEL_CONFIG     0x1C
  60 #define MPU_RA_FF_THR           0x1D
  61 #define MPU_RA_FF_DUR           0x1E
  62 #define MPU_RA_MOT_THR          0x1F
  63 #define MPU_RA_MOT_DUR          0x20
  64 #define MPU_RA_ZRMOT_THR        0x21
  65 #define MPU_RA_ZRMOT_DUR        0x22
  66 #define MPU_RA_FIFO_EN          0x23
  67 #define MPU_RA_I2C_MST_CTRL     0x24
  68 #define MPU_RA_I2C_SLV0_ADDR    0x25
  69 #define MPU_RA_I2C_SLV0_REG     0x26
  70 #define MPU_RA_I2C_SLV0_CTRL    0x27
  71 #define MPU_RA_I2C_SLV1_ADDR    0x28
  72 #define MPU_RA_I2C_SLV1_REG     0x29
  73 #define MPU_RA_I2C_SLV1_CTRL    0x2A
  74 #define MPU_RA_I2C_SLV2_ADDR    0x2B
  75 #define MPU_RA_I2C_SLV2_REG     0x2C
  76 #define MPU_RA_I2C_SLV2_CTRL    0x2D
  77 #define MPU_RA_I2C_SLV3_ADDR    0x2E
  78 #define MPU_RA_I2C_SLV3_REG     0x2F
  79 #define MPU_RA_I2C_SLV3_CTRL    0x30
  80 #define MPU_RA_I2C_SLV4_ADDR    0x31
  81 #define MPU_RA_I2C_SLV4_REG     0x32
  82 #define MPU_RA_I2C_SLV4_DO      0x33
  83 #define MPU_RA_I2C_SLV4_CTRL    0x34
  84 #define MPU_RA_I2C_SLV4_DI      0x35
  85 #define MPU_RA_I2C_MST_STATUS   0x36
  86 #define MPU_RA_INT_PIN_CFG      0x37
  87 #define MPU_RA_INT_ENABLE       0x38
  88 #define MPU_RA_DMP_INT_STATUS   0x39
  89 #define MPU_RA_INT_STATUS       0x3A
  90 #define MPU_RA_ACCEL_XOUT_H     0x3B
  91 #define MPU_RA_ACCEL_XOUT_L     0x3C
  92 #define MPU_RA_ACCEL_YOUT_H     0x3D
  93 #define MPU_RA_ACCEL_YOUT_L     0x3E
  94 #define MPU_RA_ACCEL_ZOUT_H     0x3F
  95 #define MPU_RA_ACCEL_ZOUT_L     0x40
  96 #define MPU_RA_TEMP_OUT_H       0x41
  97 #define MPU_RA_TEMP_OUT_L       0x42
  98 #define MPU_RA_GYRO_XOUT_H      0x43
  99 #define MPU_RA_GYRO_XOUT_L      0x44
 100 #define MPU_RA_GYRO_YOUT_H      0x45
 101 #define MPU_RA_GYRO_YOUT_L      0x46
 102 #define MPU_RA_GYRO_ZOUT_H      0x47
 103 #define MPU_RA_GYRO_ZOUT_L      0x48
 104 #define MPU_RA_EXT_SENS_DATA_00 0x49
 105 #define MPU_RA_MOT_DETECT_STATUS    0x61
 106 #define MPU_RA_I2C_SLV0_DO      0x63
 107 #define MPU_RA_I2C_SLV1_DO      0x64
 108 #define MPU_RA_I2C_SLV2_DO      0x65
 109 #define MPU_RA_I2C_SLV3_DO      0x66
 110 #define MPU_RA_I2C_MST_DELAY_CTRL   0x67
 111 #define MPU_RA_SIGNAL_PATH_RESET    0x68
 112 #define MPU_RA_MOT_DETECT_CTRL      0x69
 113 #define MPU_RA_USER_CTRL        0x6A
 114 #define MPU_RA_PWR_MGMT_1       0x6B
 115 #define MPU_RA_PWR_MGMT_2       0x6C
 116 #define MPU_RA_BANK_SEL         0x6D
 117 #define MPU_RA_MEM_START_ADDR   0x6E
 118 #define MPU_RA_MEM_R_W          0x6F
 119 #define MPU_RA_DMP_CFG_1        0x70
 120 #define MPU_RA_DMP_CFG_2        0x71
 121 #define MPU_RA_FIFO_COUNTH      0x72
 122 #define MPU_RA_FIFO_COUNTL      0x73
 123 #define MPU_RA_FIFO_R_W         0x74
 124 #define MPU_RA_WHO_AM_I         0x75
 125
 126 // RF = Register Flag
 127 #define MPU_RF_DATA_RDY_EN (1 << 0)
 128
 129 #define MPU_DLPF_10HZ           0x05
 130 #define MPU_DLPF_20HZ           0x04
 131 #define MPU_DLPF_42HZ           0x03
 132 #define MPU_DLPF_98HZ           0x02
 133 #define MPU_DLPF_188HZ          0x01
 134 #define MPU_DLPF_256HZ          0x00
 135
 136 typedef struct mpuConfiguration_s {
 137     uint8_t gyroReadXRegister; // Y and Z must registers follow this, 2 words each
 138 } mpuConfiguration_t;
 139
 140 typedef struct __attribute__ ((__packed__)) mpuContextData_s {
 141     uint16_t    chipMagicNumber;
 142     uint8_t     lastReadStatus;
 143     uint8_t     __padding;
 144     uint8_t     accRaw[6];  // MPU_RA_ACCEL_XOUT_H
 145     uint8_t     tempRaw[2]; // MPU_RA_TEMP_OUT_H
 146     uint8_t     gyroRaw[6]; // MPU_RA_GYRO_XOUT_H
 147 } mpuContextData_t;
 148
 149 enum gyro_fsr_e {
 150     INV_FSR_250DPS = 0,
 151     INV_FSR_500DPS,
 152     INV_FSR_1000DPS,
 153     INV_FSR_2000DPS,
 154     NUM_GYRO_FSR
 155 };
 156
 157 enum fchoice_b {
 158     FCB_DISABLED = 0,
 159     FCB_8800_32,
 160     FCB_3600_32
 161 };
 162
 163 enum clock_sel_e {
 164     INV_CLK_INTERNAL = 0,
 165     INV_CLK_PLL,
 166     NUM_CLK
 167 };
 168
 169 enum accel_fsr_e {
 170     INV_FSR_2G = 0,
 171     INV_FSR_4G,
 172     INV_FSR_8G,
 173     INV_FSR_16G,
 174     NUM_ACCEL_FSR
 175 };
 176
 177 struct gyroDev_s;
 178 struct accDev_s;
 179
 180 const gyroFilterAndRateConfig_t * mpuChooseGyroConfig(uint8_t desiredLpf, uint16_t desiredRateHz);
 181 bool mpuGyroRead(struct gyroDev_s *gyro);
 182 bool mpuGyroReadScratchpad(struct gyroDev_s *gyro);
 183 bool mpuAccReadScratchpad(struct accDev_s *acc);
 184 bool mpuTemperatureReadScratchpad(struct gyroDev_s *gyro, int16_t * data);