src/main/drivers/timer_def_at32f43x.h

   1 /*
   2  * This file is part of INAV.
   3  *
   4  * INAV is free software: you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 3 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * INAV is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with INAV.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #pragma once
  19
  20 #define timerDMASafeType_t  uint32_t
  21
  22 #define DEF_TIM_DMAMAP__D(dma, stream, channel)         DMA_TAG(dma, stream, channel)
  23 #define DEF_TIM_DMAMAP__NONE                            DMA_NONE
  24
  25 // Define TIM device/DMA/MUX
  26 #define DEF_TIM(tim, ch, pin, usage, flags, dmavar)     {               \
  27      tim,                                                               \
  28      IO_TAG(pin),                                                       \
  29      DEF_TIM_CHNL_ ## ch,                                               \
  30      DEF_TIM_OUTPUT(ch) | flags,                                        \
  31      IOCFG_AF_PP,                                                       \
  32      DEF_TIM_AF(TCH_## tim ## _ ## ch, pin),                            \
  33      usage,                                                             \
  34      DEF_TIM_DMAMAP(dmavar, tim ## _ ## ch),                            \
  35      DEF_TIM_DMA_REQUEST(tim ## _ ## ch)                                \
  36   }
  37
  38 // AF mappings
  39 #define DEF_TIM_AF(timch, pin)        CONCAT(DEF_TIM_AF__, DEF_TIM_AF__ ## pin ## __ ## timch)
  40 // MUX mappings
  41 #define DEF_TIM_AF__D(af_n, tim_n)    GPIO_MUX_ ## af_n
  42
  43 #define DEF_TIM_DMA_REQUEST(timch) \
  44     CONCAT(DEF_TIM_DMA_REQ__, DEF_TIM_TCH2BTCH(timch))
  45
  46
  47 /* add the DMA mappings here */
  48 // D(DMAx, Stream, Channel)
  49 // at32f43x has DMAMUX that allow arbitrary assignment of peripherals to streams.
  50 #define DEF_TIM_DMA_FULL \
  51     D(1, 1, 0), D(1, 2, 0), D(1, 3, 0), D(1, 4, 0), D(1, 5, 0), D(1, 6, 0), D(1, 7, 0), \
  52     D(2, 1, 0), D(2, 2, 0), D(2, 3, 0), D(2, 4, 0), D(2, 5, 0), D(2, 6, 0), D(2, 7, 0)
  53
  54 #define DEF_TIM_DMA__BTCH_TMR1_CH1    DEF_TIM_DMA_FULL
  55 #define DEF_TIM_DMA__BTCH_TMR1_CH2    DEF_TIM_DMA_FULL
  56 #define DEF_TIM_DMA__BTCH_TMR1_CH3    DEF_TIM_DMA_FULL
  57 #define DEF_TIM_DMA__BTCH_TMR1_CH4    DEF_TIM_DMA_FULL
  58
  59 #define DEF_TIM_DMA__BTCH_TMR2_CH1    DEF_TIM_DMA_FULL
  60 #define DEF_TIM_DMA__BTCH_TMR2_CH2    DEF_TIM_DMA_FULL
  61 #define DEF_TIM_DMA__BTCH_TMR2_CH3    DEF_TIM_DMA_FULL
  62 #define DEF_TIM_DMA__BTCH_TMR2_CH4    DEF_TIM_DMA_FULL
  63
  64 #define DEF_TIM_DMA__BTCH_TMR3_CH1    DEF_TIM_DMA_FULL
  65 #define DEF_TIM_DMA__BTCH_TMR3_CH2    DEF_TIM_DMA_FULL
  66 #define DEF_TIM_DMA__BTCH_TMR3_CH3    DEF_TIM_DMA_FULL
  67 #define DEF_TIM_DMA__BTCH_TMR3_CH4    DEF_TIM_DMA_FULL
  68
  69 #define DEF_TIM_DMA__BTCH_TMR4_CH1    DEF_TIM_DMA_FULL
  70 #define DEF_TIM_DMA__BTCH_TMR4_CH2    DEF_TIM_DMA_FULL
  71 #define DEF_TIM_DMA__BTCH_TMR4_CH3    DEF_TIM_DMA_FULL
  72 #define DEF_TIM_DMA__BTCH_TMR4_CH4    DEF_TIM_DMA_FULL
  73
  74 #define DEF_TIM_DMA__BTCH_TMR5_CH1    DEF_TIM_DMA_FULL
  75 #define DEF_TIM_DMA__BTCH_TMR5_CH2    DEF_TIM_DMA_FULL
  76 #define DEF_TIM_DMA__BTCH_TMR5_CH3    DEF_TIM_DMA_FULL
  77 #define DEF_TIM_DMA__BTCH_TMR5_CH4    DEF_TIM_DMA_FULL
  78
  79 #define DEF_TIM_DMA__BTCH_TMR8_CH1    DEF_TIM_DMA_FULL
  80 #define DEF_TIM_DMA__BTCH_TMR8_CH2    DEF_TIM_DMA_FULL
  81 #define DEF_TIM_DMA__BTCH_TMR8_CH3    DEF_TIM_DMA_FULL
  82 #define DEF_TIM_DMA__BTCH_TMR8_CH4    DEF_TIM_DMA_FULL
  83
  84 #define DEF_TIM_DMA__BTCH_TMR15_CH1   DEF_TIM_DMA_FULL
  85 #define DEF_TIM_DMA__BTCH_TMR15_CH2   NONE
  86
  87 #define DEF_TIM_DMA__BTCH_TMR16_CH1   DEF_TIM_DMA_FULL
  88
  89 #define DEF_TIM_DMA__BTCH_TMR17_CH1   DEF_TIM_DMA_FULL
  90
  91 #define DEF_TIM_DMA__BTCH_TMR20_CH1   DEF_TIM_DMA_FULL
  92 #define DEF_TIM_DMA__BTCH_TMR20_CH2   DEF_TIM_DMA_FULL
  93 #define DEF_TIM_DMA__BTCH_TMR20_CH3   DEF_TIM_DMA_FULL
  94 #define DEF_TIM_DMA__BTCH_TMR20_CH4   DEF_TIM_DMA_FULL
  95
  96 #define DEF_TIM_DMA__BTCH_TMR9_CH1    NONE
  97 #define DEF_TIM_DMA__BTCH_TMR9_CH2    NONE
  98
  99 #define DEF_TIM_DMA__BTCH_TMR10_CH1   NONE
 100 #define DEF_TIM_DMA__BTCH_TMR11_CH1   NONE
 101
 102 #define DEF_TIM_DMA__BTCH_TMR12_CH1   NONE
 103 #define DEF_TIM_DMA__BTCH_TMR12_CH2   NONE
 104 #define DEF_TIM_DMA__BTCH_TMR13_CH1   NONE
 105 #define DEF_TIM_DMA__BTCH_TMR14_CH1   NONE
 106
 107 // TIM_UP table
 108 #define DEF_TIM_DMA__BTCH_TMR1_UP     DEF_TIM_DMA_FULL
 109 #define DEF_TIM_DMA__BTCH_TMR2_UP     DEF_TIM_DMA_FULL
 110 #define DEF_TIM_DMA__BTCH_TMR3_UP     DEF_TIM_DMA_FULL
 111 #define DEF_TIM_DMA__BTCH_TMR4_UP     DEF_TIM_DMA_FULL
 112 #define DEF_TIM_DMA__BTCH_TMR5_UP     DEF_TIM_DMA_FULL
 113 #define DEF_TIM_DMA__BTCH_TMR6_UP     DEF_TIM_DMA_FULL
 114 #define DEF_TIM_DMA__BTCH_TMR7_UP     DEF_TIM_DMA_FULL
 115 #define DEF_TIM_DMA__BTCH_TMR8_UP     DEF_TIM_DMA_FULL
 116 #define DEF_TIM_DMA__BTCH_TMR9_UP     DEF_TIM_DMA_FULL
 117 #define DEF_TIM_DMA__BTCH_TMR10_UP    DEF_TIM_DMA_FULL
 118 #define DEF_TIM_DMA__BTCH_TMR11_UP    DEF_TIM_DMA_FULL
 119 #define DEF_TIM_DMA__BTCH_TMR12_UP    DEF_TIM_DMA_FULL
 120 #define DEF_TIM_DMA__BTCH_TMR13_UP    DEF_TIM_DMA_FULL
 121 #define DEF_TIM_DMA__BTCH_TMR14_UP    DEF_TIM_DMA_FULL
 122
 123 #define DMA_REQUEST_NONE 255
 124
 125 #define DEF_TIM_DMA_REQ__BTCH_TMR1_CH1    DMAMUX_DMAREQ_ID_TMR1_CH1
 126 #define DEF_TIM_DMA_REQ__BTCH_TMR1_CH2    DMAMUX_DMAREQ_ID_TMR1_CH2
 127 #define DEF_TIM_DMA_REQ__BTCH_TMR1_CH3    DMAMUX_DMAREQ_ID_TMR1_CH3
 128 #define DEF_TIM_DMA_REQ__BTCH_TMR1_CH4    DMAMUX_DMAREQ_ID_TMR1_CH4
 129
 130 #define DEF_TIM_DMA_REQ__BTCH_TMR2_CH1    DMAMUX_DMAREQ_ID_TMR2_CH1
 131 #define DEF_TIM_DMA_REQ__BTCH_TMR2_CH2    DMAMUX_DMAREQ_ID_TMR2_CH2
 132 #define DEF_TIM_DMA_REQ__BTCH_TMR2_CH3    DMAMUX_DMAREQ_ID_TMR2_CH3
 133 #define DEF_TIM_DMA_REQ__BTCH_TMR2_CH4    DMAMUX_DMAREQ_ID_TMR2_CH4
 134
 135 #define DEF_TIM_DMA_REQ__BTCH_TMR3_CH1    DMAMUX_DMAREQ_ID_TMR3_CH1
 136 #define DEF_TIM_DMA_REQ__BTCH_TMR3_CH2    DMAMUX_DMAREQ_ID_TMR3_CH2
 137 #define DEF_TIM_DMA_REQ__BTCH_TMR3_CH3    DMAMUX_DMAREQ_ID_TMR3_CH3
 138 #define DEF_TIM_DMA_REQ__BTCH_TMR3_CH4    DMAMUX_DMAREQ_ID_TMR3_CH4
 139
 140 #define DEF_TIM_DMA_REQ__BTCH_TMR4_CH1    DMAMUX_DMAREQ_ID_TMR4_CH1
 141 #define DEF_TIM_DMA_REQ__BTCH_TMR4_CH2    DMAMUX_DMAREQ_ID_TMR4_CH2
 142 #define DEF_TIM_DMA_REQ__BTCH_TMR4_CH3    DMAMUX_DMAREQ_ID_TMR4_CH3
 143 #define DEF_TIM_DMA_REQ__BTCH_TMR4_CH4    DMAMUX_DMAREQ_ID_TMR4_CH4
 144
 145 #define DEF_TIM_DMA_REQ__BTCH_TMR5_CH1    DMAMUX_DMAREQ_ID_TMR5_CH1
 146 #define DEF_TIM_DMA_REQ__BTCH_TMR5_CH2    DMAMUX_DMAREQ_ID_TMR5_CH2
 147 #define DEF_TIM_DMA_REQ__BTCH_TMR5_CH3    DMAMUX_DMAREQ_ID_TMR5_CH3
 148 #define DEF_TIM_DMA_REQ__BTCH_TMR5_CH4    DMAMUX_DMAREQ_ID_TMR5_CH4
 149
 150 #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH1    DMAMUX_DMAREQ_ID_TMR8_CH1
 151 #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH2    DMAMUX_DMAREQ_ID_TMR8_CH2
 152 #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH3    DMAMUX_DMAREQ_ID_TMR8_CH3
 153 #define DEF_TIM_DMA_REQ__BTCH_TMR8_CH4    DMAMUX_DMAREQ_ID_TMR8_CH4
 154
 155 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH1   DMAMUX_DMAREQ_ID_TMR20_CH1
 156 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH2   DMAMUX_DMAREQ_ID_TMR20_CH2
 157 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH3   DMAMUX_DMAREQ_ID_TMR20_CH3
 158 #define DEF_TIM_DMA_REQ__BTCH_TMR20_CH4   DMAMUX_DMAREQ_ID_TMR20_CH4
 159
 160 // TIM_UP request table
 161 #define DEF_TIM_DMA_REQ__BTCH_TMR1_UP     DMAMUX_DMAREQ_ID_TMR1_OVERFLOW
 162 #define DEF_TIM_DMA_REQ__BTCH_TMR2_UP     DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
 163 #define DEF_TIM_DMA_REQ__BTCH_TMR3_UP     DMAMUX_DMAREQ_ID_TMR3_OVERFLOW
 164 #define DEF_TIM_DMA_REQ__BTCH_TMR4_UP     DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
 165 #define DEF_TIM_DMA_REQ__BTCH_TMR5_UP     DMAMUX_DMAREQ_ID_TMR5_OVERFLOW
 166 #define DEF_TIM_DMA_REQ__BTCH_TMR8_UP     DMAMUX_DMAREQ_ID_TMR8_OVERFLOW
 167 #define DEF_TIM_DMA_REQ__BTCH_TMR20_UP    DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
 168
 169
 170 // AF table
 171 //GPIOA
 172 #define DEF_TIM_AF__PA0__TCH_TMR2_CH1     D(1, 2)    //A MUX1 1
 173 #define DEF_TIM_AF__PA1__TCH_TMR2_CH2     D(1, 2)    //A MUX1 2
 174 #define DEF_TIM_AF__PA2__TCH_TMR2_CH3     D(1, 2)
 175 #define DEF_TIM_AF__PA3__TCH_TMR2_CH4     D(1, 2)
 176 #define DEF_TIM_AF__PA5__TCH_TMR2_CH1     D(1, 2)
 177 #define DEF_TIM_AF__PA7__TCH_TMR1_CH1N    D(1, 1)
 178 #define DEF_TIM_AF__PA8__TCH_TMR1_CH1     D(1, 1)
 179 #define DEF_TIM_AF__PA9__TCH_TMR1_CH2     D(1, 1)
 180 #define DEF_TIM_AF__PA10__TCH_TMR1_CH3    D(1, 1)
 181 #define DEF_TIM_AF__PA11__TCH_TMR1_CH4    D(1, 1)
 182 #define DEF_TIM_AF__PA15__TCH_TMR2_CH1    D(1, 2)
 183
 184 #define DEF_TIM_AF__PA0__TCH_TMR5_CH1     D(2, 5)
 185 #define DEF_TIM_AF__PA1__TCH_TMR5_CH2     D(2, 5)
 186 #define DEF_TIM_AF__PA2__TCH_TMR5_CH3     D(2, 5)
 187 #define DEF_TIM_AF__PA3__TCH_TMR5_CH4     D(2, 5)
 188 #define DEF_TIM_AF__PA6__TCH_TMR3_CH1     D(2, 3)
 189 #define DEF_TIM_AF__PA7__TCH_TMR3_CH2     D(2, 3)
 190
 191 #define DEF_TIM_AF__PA2__TCH_TMR9_CH1     D(3, 9)
 192 #define DEF_TIM_AF__PA3__TCH_TMR9_CH2     D(3, 9)
 193 #define DEF_TIM_AF__PA5__TCH_TMR8_CH1N    D(3, 8)
 194 #define DEF_TIM_AF__PA7__TCH_TMR8_CH1N    D(3, 8)
 195
 196 #define DEF_TIM_AF__PA6__TCH_TMR13_CH1    D(9, 13)
 197 #define DEF_TIM_AF__PA7__TCH_TMR14_CH1    D(9, 14)
 198
 199 //GPIOB
 200 #define DEF_TIM_AF__PB0__TCH_TMR1_CH2N    D(1, 1)
 201 #define DEF_TIM_AF__PB1__TCH_TMR1_CH3N    D(1, 1)
 202 #define DEF_TIM_AF__PB2__TCH_TMR2_CH4     D(1, 2)
 203 #define DEF_TIM_AF__PB3__TCH_TMR2_CH2     D(1, 2)
 204 #define DEF_TIM_AF__PB8__TCH_TMR2_CH1     D(1, 2)
 205 #define DEF_TIM_AF__PB9__TCH_TMR2_CH2     D(1, 2)
 206 #define DEF_TIM_AF__PB10__TCH_TMR2_CH3    D(1, 2)
 207 #define DEF_TIM_AF__PB11__TCH_TMR2_CH4    D(1, 2)
 208 #define DEF_TIM_AF__PB13__TCH_TMR1_CH1N   D(1, 1)
 209 #define DEF_TIM_AF__PB14__TCH_TMR1_CH2N   D(1, 1)
 210 #define DEF_TIM_AF__PB15__TCH_TMR1_CH3N   D(1, 1)
 211
 212 #define DEF_TIM_AF__PB0__TCH_TMR3_CH3     D(2, 3)
 213 #define DEF_TIM_AF__PB1__TCH_TMR3_CH4     D(2, 3)
 214 #define DEF_TIM_AF__PB2__TCH_TMR20_CH1    D(2, 20)
 215 #define DEF_TIM_AF__PB4__TCH_TMR3_CH1     D(2, 3)
 216 #define DEF_TIM_AF__PB5__TCH_TMR3_CH2     D(2, 3)
 217 #define DEF_TIM_AF__PB6__TCH_TMR4_CH1     D(2, 4)
 218 #define DEF_TIM_AF__PB7__TCH_TMR4_CH2     D(2, 4)
 219 #define DEF_TIM_AF__PB8__TCH_TMR4_CH3     D(2, 4)
 220 #define DEF_TIM_AF__PB9__TCH_TMR4_CH4     D(2, 4)
 221 #define DEF_TIM_AF__PB11__TCH_TMR5_CH4     D(2, 5)
 222 #define DEF_TIM_AF__PB12__TCH_TMR5_CH1     D(2, 5)
 223
 224 #define DEF_TIM_AF__PB0__TCH_TMR8_CH2N    D(3, 8)
 225 #define DEF_TIM_AF__PB1__TCH_TMR8_CH3N    D(3, 8)
 226 #define DEF_TIM_AF__PB8__TCH_TMR10_CH1    D(3, 10)
 227 #define DEF_TIM_AF__PB9__TCH_TMR11_CH1    D(3, 11)
 228 #define DEF_TIM_AF__PB14__TCH_TMR8_CH2N   D(3, 8)
 229 #define DEF_TIM_AF__PB15__TCH_TMR8_CH3N   D(3, 8)
 230
 231 #define DEF_TIM_AF__PB14__TCH_TMR12_CH1   D(9, 12)
 232 #define DEF_TIM_AF__PB15__TCH_TMR12_CH2   D(9, 12)
 233
 234 //GPIOC
 235 #define DEF_TIM_AF__PC2__TCH_TMR20_CH2    D(2, 20)
 236 #define DEF_TIM_AF__PC6__TCH_TMR3_CH1     D(2, 3)
 237 #define DEF_TIM_AF__PC7__TCH_TMR3_CH2     D(2, 3)
 238 #define DEF_TIM_AF__PC8__TCH_TMR3_CH3     D(2, 3)
 239 #define DEF_TIM_AF__PC9__TCH_TMR3_CH4     D(2, 3)
 240 #define DEF_TIM_AF__PC10__TCH_TMR5_CH2    D(2, 5)
 241 #define DEF_TIM_AF__PC11__TCH_TMR5_CH3    D(2, 5)
 242
 243 #define DEF_TIM_AF__PC4__TCH_TMR9_CH1     D(3, 9)
 244 #define DEF_TIM_AF__PC5__TCH_TMR9_CH2     D(3, 9)
 245 #define DEF_TIM_AF__PC6__TCH_TMR8_CH1     D(3, 8)
 246 #define DEF_TIM_AF__PC7__TCH_TMR8_CH2     D(3, 8)
 247 #define DEF_TIM_AF__PC8__TCH_TMR8_CH3     D(3, 8)
 248 #define DEF_TIM_AF__PC9__TCH_TMR8_CH4     D(3, 8)
 249 #define DEF_TIM_AF__PC12__TCH_TMR11_CH1   D(3, 11)
 250
 251 //GPIOD
 252 #define DEF_TIM_AF__PD12__TCH_TMR4_CH1    D(2, 4)
 253 #define DEF_TIM_AF__PD13__TCH_TMR4_CH2    D(2, 4)
 254 #define DEF_TIM_AF__PD14__TCH_TMR4_CH3    D(2, 4)
 255 #define DEF_TIM_AF__PD15__TCH_TMR4_CH4    D(2, 4)
 256
 257 //GPIOE
 258 #define DEF_TIM_AF__PE8__TCH_TMR1_CH1N    D(1, 1)
 259 #define DEF_TIM_AF__PE9__TCH_TMR1_CH1     D(1, 1)
 260 #define DEF_TIM_AF__PE10__TCH_TMR1_CH2N   D(1, 1)
 261 #define DEF_TIM_AF__PE11__TCH_TMR1_CH2    D(1, 1)
 262 #define DEF_TIM_AF__PE12__TCH_TMR1_CH3N   D(1, 1)
 263 #define DEF_TIM_AF__PE13__TCH_TMR1_CH3    D(1, 1)
 264 #define DEF_TIM_AF__PE14__TCH_TMR1_CH4    D(1, 1)
 265
 266 #define DEF_TIM_AF__PE3__TCH_TMR3_CH1     D(3, 3)
 267 #define DEF_TIM_AF__PE4__TCH_TMR3_CH2     D(3, 3)
 268 #define DEF_TIM_AF__PE5__TCH_TMR3_CH3     D(3, 3)
 269 #define DEF_TIM_AF__PE6__TCH_TMR3_CH4     D(3, 3)
 270
 271 #define DEF_TIM_AF__PE5__TCH_TMR9_CH1     D(3, 9)
 272 #define DEF_TIM_AF__PE6__TCH_TMR9_CH2     D(3, 9)
 273
 274 #define DEF_TIM_AF__PE1__TCH_TMR20_CH4     D(6, 20)
 275 #define DEF_TIM_AF__PE2__TCH_TMR20_CH1     D(6, 20)
 276 #define DEF_TIM_AF__PE3__TCH_TMR20_CH2     D(6, 20)
 277 #define DEF_TIM_AF__PE4__TCH_TMR20_CH1N     D(6, 20)
 278 #define DEF_TIM_AF__PE5__TCH_TMR20_CH2N     D(6, 20)
 279 #define DEF_TIM_AF__PE6__TCH_TMR20_CH3N     D(6, 20)
 280
 281 //GPIOF
 282 #define DEF_TIM_AF__PF2__TCH_TMR20_CH3      D(2, 20)
 283 #define DEF_TIM_AF__PF3__TCH_TMR20_CH4      D(2, 20)
 284 #define DEF_TIM_AF__PF4__TCH_TMR20_CH1N      D(2, 20)
 285 #define DEF_TIM_AF__PF5__TCH_TMR20_CH2N     D(2, 20)
 286 #define DEF_TIM_AF__PF6__TCH_TMR20_CH4      D(2, 20)
 287 #define DEF_TIM_AF__PF10__TCH_TMR5_CH4      D(2, 5)
 288 #define DEF_TIM_AF__PF12__TCH_TMR20_CH1     D(2, 20)
 289 #define DEF_TIM_AF__PF13__TCH_TMR20_CH2     D(2, 20)
 290 #define DEF_TIM_AF__PF14__TCH_TMR20_CH3     D(2, 20)
 291 #define DEF_TIM_AF__PF15__TCH_TMR20_CH4     D(2, 20)
 292
 293 #define DEF_TIM_AF__PF6__TCH_TMR10_CH1    D(3, 10)
 294 #define DEF_TIM_AF__PF7__TCH_TMR11_CH1    D(3, 11)
 295
 296 #define DEF_TIM_AF__PF8__TCH_TMR13_CH1    D(9, 13)
 297 #define DEF_TIM_AF__PF9__TCH_TMR14_CH1    D(9, 14)
 298
 299 // GPIOG
 300 #define DEF_TIM_AF__PG0__TCH_TMR20_CH1N    D(2, 20)
 301 #define DEF_TIM_AF__PG1__TCH_TMR20_CH2N    D(2, 20)
 302 #define DEF_TIM_AF__PG2__TCH_TMR20_CH3N    D(2, 20)
 303
 304 //GPIOH
 305 #define DEF_TIM_AF__PH2__TCH_TMR5_CH1    D(2, 5)
 306 #define DEF_TIM_AF__PH3__TCH_TMR5_CH2    D(2, 5)
 307