src/main/drivers/timer_def_stm32h7xx.h

   1 /*
   2  * This file is part of INAV.
   3  *
   4  * INAV is free software: you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 3 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * INAV is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with INAV.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #pragma once
  19
  20 #define timerDMASafeType_t  uint32_t
  21
  22 #define DEF_TIM_DMAMAP__D(dma, stream, request) DMA_TAG(dma, stream, request)
  23 #define DEF_TIM_DMAMAP__NONE                    DMA_NONE
  24
  25 #define DEF_TIM(tim, ch, pin, usage, flags, dmavar) {   \
  26     tim,                                                \
  27     IO_TAG(pin),                                        \
  28     DEF_TIM_CHNL_ ## ch,                                \
  29     DEF_TIM_OUTPUT(ch) | flags,                         \
  30     IOCFG_AF_PP,                                        \
  31     DEF_TIM_AF(TCH_## tim ## _ ## ch, pin),             \
  32     usage,                                              \
  33     DEF_TIM_DMAMAP(dmavar, tim ## _ ## ch)              \
  34 }
  35
  36 // AF mappings
  37 #define DEF_TIM_AF(timch, pin)        CONCAT(DEF_TIM_AF__, DEF_TIM_AF__ ## pin ## __ ## timch)
  38 #define DEF_TIM_AF__D(af_n, tim_n)    GPIO_AF ## af_n ## _TIM ## tim_n
  39
  40 /* H7 Stream Mappings */
  41 // D(DMAx, Stream)
  42
  43 // H7 has DMAMUX that allow arbitrary assignment of peripherals to streams.
  44
  45 #define DEF_TIM_DMA_FULL(req) \
  46     D(1, 0, req), D(1, 1, req), D(1, 2, req), D(1, 3, req), D(1, 4, req), D(1, 5, req), D(1, 6, req), D(1, 7, req), \
  47     D(2, 0, req), D(2, 1, req), D(2, 2, req), D(2, 3, req), D(2, 4, req), D(2, 5, req), D(2, 6, req), D(2, 7, req)
  48
  49 #define DEF_TIM_DMA__BTCH_TIM1_CH1    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM1_CH1)
  50 #define DEF_TIM_DMA__BTCH_TIM1_CH2    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM1_CH2)
  51 #define DEF_TIM_DMA__BTCH_TIM1_CH3    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM1_CH3)
  52 #define DEF_TIM_DMA__BTCH_TIM1_CH4    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM1_CH4)
  53
  54 #define DEF_TIM_DMA__BTCH_TIM2_CH1    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM2_CH1)
  55 #define DEF_TIM_DMA__BTCH_TIM2_CH2    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM2_CH2)
  56 #define DEF_TIM_DMA__BTCH_TIM2_CH3    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM2_CH3)
  57 #define DEF_TIM_DMA__BTCH_TIM2_CH4    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM2_CH4)
  58
  59 #define DEF_TIM_DMA__BTCH_TIM3_CH1    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM3_CH1)
  60 #define DEF_TIM_DMA__BTCH_TIM3_CH2    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM3_CH2)
  61 #define DEF_TIM_DMA__BTCH_TIM3_CH3    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM3_CH3)
  62 #define DEF_TIM_DMA__BTCH_TIM3_CH4    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM3_CH4)
  63
  64 #define DEF_TIM_DMA__BTCH_TIM4_CH1    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM4_CH1)
  65 #define DEF_TIM_DMA__BTCH_TIM4_CH2    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM4_CH2)
  66 #define DEF_TIM_DMA__BTCH_TIM4_CH3    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM4_CH3)
  67 #define DEF_TIM_DMA__BTCH_TIM4_CH4    NONE
  68
  69 #define DEF_TIM_DMA__BTCH_TIM5_CH1    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM5_CH1)
  70 #define DEF_TIM_DMA__BTCH_TIM5_CH2    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM5_CH2)
  71 #define DEF_TIM_DMA__BTCH_TIM5_CH3    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM5_CH3)
  72 #define DEF_TIM_DMA__BTCH_TIM5_CH4    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM5_CH4)
  73
  74 #define DEF_TIM_DMA__BTCH_TIM8_CH1    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM8_CH1)
  75 #define DEF_TIM_DMA__BTCH_TIM8_CH2    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM8_CH2)
  76 #define DEF_TIM_DMA__BTCH_TIM8_CH3    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM8_CH3)
  77 #define DEF_TIM_DMA__BTCH_TIM8_CH4    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM8_CH4)
  78
  79 #define DEF_TIM_DMA__BTCH_TIM12_CH1   NONE
  80 #define DEF_TIM_DMA__BTCH_TIM12_CH2   NONE
  81
  82 #define DEF_TIM_DMA__BTCH_TIM13_CH1   NONE
  83
  84 #define DEF_TIM_DMA__BTCH_TIM14_CH1   NONE
  85
  86 #define DEF_TIM_DMA__BTCH_TIM15_CH1   DEF_TIM_DMA_FULL(DMA_REQUEST_TIM15_CH1)
  87 #define DEF_TIM_DMA__BTCH_TIM15_CH2   NONE
  88
  89 #define DEF_TIM_DMA__BTCH_TIM16_CH1   DEF_TIM_DMA_FULL(DMA_REQUEST_TIM16_CH1)
  90
  91 #define DEF_TIM_DMA__BTCH_TIM17_CH1   DEF_TIM_DMA_FULL(DMA_REQUEST_TIM17_CH1)
  92
  93 // TIM_UP table
  94 #define DEF_TIM_DMA__BTCH_TIM1_UP     DEF_TIM_DMA_FULL(DMA_REQUEST_TIM1_UP)
  95 #define DEF_TIM_DMA__BTCH_TIM2_UP     DEF_TIM_DMA_FULL(DMA_REQUEST_TIM2_UP)
  96 #define DEF_TIM_DMA__BTCH_TIM3_UP     DEF_TIM_DMA_FULL(DMA_REQUEST_TIM3_UP)
  97 #define DEF_TIM_DMA__BTCH_TIM4_UP     DEF_TIM_DMA_FULL(DMA_REQUEST_TIM4_UP)
  98 #define DEF_TIM_DMA__BTCH_TIM5_UP     DEF_TIM_DMA_FULL(DMA_REQUEST_TIM5_UP)
  99 #define DEF_TIM_DMA__BTCH_TIM6_UP     DEF_TIM_DMA_FULL(DMA_REQUEST_TIM6_UP)
 100 #define DEF_TIM_DMA__BTCH_TIM7_UP     DEF_TIM_DMA_FULL(DMA_REQUEST_TIM7_UP)
 101 #define DEF_TIM_DMA__BTCH_TIM8_UP     DEF_TIM_DMA_FULL(DMA_REQUEST_TIM8_UP)
 102 #define DEF_TIM_DMA__BTCH_TIM12_UP    NONE
 103 #define DEF_TIM_DMA__BTCH_TIM13_UP    NONE
 104 #define DEF_TIM_DMA__BTCH_TIM14_UP    NONE
 105 #define DEF_TIM_DMA__BTCH_TIM15_UP    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM15_UP)
 106 #define DEF_TIM_DMA__BTCH_TIM16_UP    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM16_UP)
 107 #define DEF_TIM_DMA__BTCH_TIM17_UP    DEF_TIM_DMA_FULL(DMA_REQUEST_TIM17_UP)
 108
 109 // AF table
 110
 111 // AF table
 112
 113 //PORTA
 114 #define DEF_TIM_AF__PA0__TCH_TIM2_CH1     D(1, 2)
 115 #define DEF_TIM_AF__PA1__TCH_TIM2_CH2     D(1, 2)
 116 #define DEF_TIM_AF__PA2__TCH_TIM2_CH3     D(1, 2)
 117 #define DEF_TIM_AF__PA3__TCH_TIM2_CH4     D(1, 2)
 118 #define DEF_TIM_AF__PA5__TCH_TIM2_CH1     D(1, 2)
 119 #define DEF_TIM_AF__PA7__TCH_TIM1_CH1N    D(1, 1)
 120 #define DEF_TIM_AF__PA8__TCH_TIM1_CH1     D(1, 1)
 121 #define DEF_TIM_AF__PA9__TCH_TIM1_CH2     D(1, 1)
 122 #define DEF_TIM_AF__PA10__TCH_TIM1_CH3    D(1, 1)
 123 #define DEF_TIM_AF__PA11__TCH_TIM1_CH4    D(1, 1)
 124 #define DEF_TIM_AF__PA15__TCH_TIM2_CH1    D(1, 2)
 125
 126 #define DEF_TIM_AF__PA0__TCH_TIM5_CH1     D(2, 5)
 127 #define DEF_TIM_AF__PA1__TCH_TIM5_CH2     D(2, 5)
 128 #define DEF_TIM_AF__PA2__TCH_TIM5_CH3     D(2, 5)
 129 #define DEF_TIM_AF__PA3__TCH_TIM5_CH4     D(2, 5)
 130 #define DEF_TIM_AF__PA6__TCH_TIM3_CH1     D(2, 3)
 131 #define DEF_TIM_AF__PA7__TCH_TIM3_CH2     D(2, 3)
 132
 133 #define DEF_TIM_AF__PA5__TCH_TIM8_CH1N    D(3, 8)
 134 #define DEF_TIM_AF__PA7__TCH_TIM8_CH1N    D(3, 8)
 135
 136 #define DEF_TIM_AF__PA6__TCH_TIM13_CH1    D(9, 13)
 137 #define DEF_TIM_AF__PA7__TCH_TIM14_CH1    D(9, 14)
 138
 139 #define DEF_TIM_AF__PA1__TCH_TIM15_CH1N   D(4, 15)
 140 #define DEF_TIM_AF__PA2__TCH_TIM15_CH1    D(4, 15)
 141 #define DEF_TIM_AF__PA3__TCH_TIM15_CH2    D(4, 15)
 142
 143 //PORTB
 144 #define DEF_TIM_AF__PB0__TCH_TIM1_CH2N    D(1, 1)
 145 #define DEF_TIM_AF__PB1__TCH_TIM1_CH3N    D(1, 1)
 146 #define DEF_TIM_AF__PB3__TCH_TIM2_CH2     D(1, 2)
 147 #define DEF_TIM_AF__PB6__TCH_TIM16_CH1N   D(1, 16)
 148 #define DEF_TIM_AF__PB7__TCH_TIM17_CH1N   D(1, 17)
 149 #define DEF_TIM_AF__PB8__TCH_TIM16_CH1    D(1, 16)
 150 #define DEF_TIM_AF__PB9__TCH_TIM17_CH1    D(1, 17)
 151 #define DEF_TIM_AF__PB10__TCH_TIM2_CH3    D(1, 2)
 152 #define DEF_TIM_AF__PB11__TCH_TIM2_CH4    D(1, 2)
 153 #define DEF_TIM_AF__PB13__TCH_TIM1_CH1N   D(1, 1)
 154 #define DEF_TIM_AF__PB14__TCH_TIM1_CH2N   D(1, 1)
 155 #define DEF_TIM_AF__PB15__TCH_TIM1_CH3N   D(1, 1)
 156
 157 #define DEF_TIM_AF__PB0__TCH_TIM3_CH3     D(2, 3)
 158 #define DEF_TIM_AF__PB1__TCH_TIM3_CH4     D(2, 3)
 159 #define DEF_TIM_AF__PB4__TCH_TIM3_CH1     D(2, 3)
 160 #define DEF_TIM_AF__PB5__TCH_TIM3_CH2     D(2, 3)
 161 #define DEF_TIM_AF__PB6__TCH_TIM4_CH1     D(2, 4)
 162 #define DEF_TIM_AF__PB7__TCH_TIM4_CH2     D(2, 4)
 163 #define DEF_TIM_AF__PB8__TCH_TIM4_CH3     D(2, 4)
 164 #define DEF_TIM_AF__PB9__TCH_TIM4_CH4     D(2, 4)
 165
 166 #define DEF_TIM_AF__PB14__TCH_TIM12_CH1   D(2, 12)
 167 #define DEF_TIM_AF__PB15__TCH_TIM12_CH2   D(2, 12)
 168
 169 //PORTC
 170 #define DEF_TIM_AF__PC6__TCH_TIM3_CH1     D(2, 3)
 171 #define DEF_TIM_AF__PC7__TCH_TIM3_CH2     D(2, 3)
 172 #define DEF_TIM_AF__PC8__TCH_TIM3_CH3     D(2, 3)
 173 #define DEF_TIM_AF__PC9__TCH_TIM3_CH4     D(2, 3)
 174
 175 #define DEF_TIM_AF__PC6__TCH_TIM8_CH1     D(3, 8)
 176 #define DEF_TIM_AF__PC7__TCH_TIM8_CH2     D(3, 8)
 177 #define DEF_TIM_AF__PC8__TCH_TIM8_CH3     D(3, 8)
 178 #define DEF_TIM_AF__PC9__TCH_TIM8_CH4     D(3, 8)
 179
 180 //PORTD
 181 #define DEF_TIM_AF__PD12__TCH_TIM4_CH1    D(2, 4)
 182 #define DEF_TIM_AF__PD13__TCH_TIM4_CH2    D(2, 4)
 183 #define DEF_TIM_AF__PD14__TCH_TIM4_CH3    D(2, 4)
 184 #define DEF_TIM_AF__PD15__TCH_TIM4_CH4    D(2, 4)
 185
 186 //PORTE
 187 #define DEF_TIM_AF__PE8__TCH_TIM1_CH1N    D(1, 1)
 188 #define DEF_TIM_AF__PE9__TCH_TIM1_CH1     D(1, 1)
 189 #define DEF_TIM_AF__PE10__TCH_TIM1_CH2N   D(1, 1)
 190 #define DEF_TIM_AF__PE11__TCH_TIM1_CH2    D(1, 1)
 191 #define DEF_TIM_AF__PE12__TCH_TIM1_CH3N   D(1, 1)
 192 #define DEF_TIM_AF__PE13__TCH_TIM1_CH3    D(1, 1)
 193 #define DEF_TIM_AF__PE14__TCH_TIM1_CH4    D(1, 1)
 194
 195 #define DEF_TIM_AF__PE4__TCH_TIM15_CH1N   D(4, 15)
 196 #define DEF_TIM_AF__PE5__TCH_TIM15_CH1    D(4, 15)
 197 #define DEF_TIM_AF__PE6__TCH_TIM15_CH2    D(4, 15)
 198
 199 //PORTF
 200 #define DEF_TIM_AF__PF6__TCH_TIM16_CH1    D(1, 16)
 201 #define DEF_TIM_AF__PF7__TCH_TIM17_CH1    D(1, 17)
 202 #define DEF_TIM_AF__PF8__TCH_TIM16_CH1N   D(1, 16)
 203 #define DEF_TIM_AF__PF9__TCH_TIM17_CH1N   D(1, 17)
 204
 205 #define DEF_TIM_AF__PF8__TCH_TIM13_CH1N   D(9, 13)
 206 #define DEF_TIM_AF__PF9__TCH_TIM14_CH1N   D(9, 14)
 207
 208 //PORTH
 209 #define DEF_TIM_AF__PH6__TCH_TIM12_CH1    D(2, 12)
 210 #define DEF_TIM_AF__PH9__TCH_TIM12_CH2    D(2, 12)
 211 #define DEF_TIM_AF__PH10__TCH_TIM5_CH1    D(2, 5)
 212 #define DEF_TIM_AF__PH11__TCH_TIM5_CH2    D(2, 5)
 213 #define DEF_TIM_AF__PH12__TCH_TIM5_CH3    D(2, 5)
 214 #define DEF_TIM_AF__PH13__TCH_TIM8_CH1N   D(3, 8)
 215 #define DEF_TIM_AF__PH14__TCH_TIM8_CH2N   D(3, 8)
 216 #define DEF_TIM_AF__PH15__TCH_TIM8_CH3N   D(3, 8)
 217
 218 //PORTI
 219 #define DEF_TIM_AF__PI0__TCH_TIM5_CH4     D(2, 5)
 220
 221 #define DEF_TIM_AF__PI2__TCH_TIM8_CH4     D(3, 8)
 222 #define DEF_TIM_AF__PI5__TCH_TIM8_CH1     D(3, 8)
 223 #define DEF_TIM_AF__PI6__TCH_TIM8_CH2     D(3, 8)
 224 #define DEF_TIM_AF__PI7__TCH_TIM8_CH3     D(3, 8)