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[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_can.h
blobddb1a074026412a1fd8f442c16d9dc1c0cf4c2a8
1 /**
2 **************************************************************************
3 * @file at32f435_437_can.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 can header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_CAN_H
29 #define __AT32F435_437_CAN_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup CAN
44 * @{
45 */
46
47
48 /** @defgroup CAN_timeout_count
49 * @{
50 */
51
52 #define FZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for fzc bit */
53 #define DZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for dzc bit */
54
55 /**
56 * @}
57 */
58
59 /** @defgroup CAN_flags_definition
60 * @brief can flag
61 * @{
62 */
63
64 #define CAN_EAF_FLAG ((uint32_t)0x01) /*!< error active flag */
65 #define CAN_EPF_FLAG ((uint32_t)0x02) /*!< error passive flag */
66 #define CAN_BOF_FLAG ((uint32_t)0x03) /*!< bus-off flag */
67 #define CAN_ETR_FLAG ((uint32_t)0x04) /*!< error type record flag */
68 #define CAN_EOIF_FLAG ((uint32_t)0x05) /*!< error occur interrupt flag */
69 #define CAN_TM0TCF_FLAG ((uint32_t)0x06) /*!< transmit mailbox 0 transmission completed flag */
70 #define CAN_TM1TCF_FLAG ((uint32_t)0x07) /*!< transmit mailbox 1 transmission completed flag */
71 #define CAN_TM2TCF_FLAG ((uint32_t)0x08) /*!< transmit mailbox 2 transmission completed flag */
72 #define CAN_RF0MN_FLAG ((uint32_t)0x09) /*!< receive fifo 0 message num flag */
73 #define CAN_RF0FF_FLAG ((uint32_t)0x0A) /*!< receive fifo 0 full flag */
74 #define CAN_RF0OF_FLAG ((uint32_t)0x0B) /*!< receive fifo 0 overflow flag */
75 #define CAN_RF1MN_FLAG ((uint32_t)0x0C) /*!< receive fifo 1 message num flag */
76 #define CAN_RF1FF_FLAG ((uint32_t)0x0D) /*!< receive fifo 1 full flag */
77 #define CAN_RF1OF_FLAG ((uint32_t)0x0E) /*!< receive fifo 1 overflow flag */
78 #define CAN_QDZIF_FLAG ((uint32_t)0x0F) /*!< quit doze mode interrupt flag */
79 #define CAN_EDZC_FLAG ((uint32_t)0x10) /*!< enter doze mode confirm flag */
80 #define CAN_TMEF_FLAG ((uint32_t)0x11) /*!< transmit mailbox empty flag */
81
82 /**
83 * @}
84 */
85
86 /** @defgroup CAN_interrupts_definition
87 * @brief can interrupt
88 * @{
89 */
90
91 #define CAN_TCIEN_INT ((uint32_t)0x00000001) /*!< transmission complete interrupt */
92 #define CAN_RF0MIEN_INT ((uint32_t)0x00000002) /*!< receive fifo 0 message interrupt */
93 #define CAN_RF0FIEN_INT ((uint32_t)0x00000004) /*!< receive fifo 0 full interrupt */
94 #define CAN_RF0OIEN_INT ((uint32_t)0x00000008) /*!< receive fifo 0 overflow interrupt */
95 #define CAN_RF1MIEN_INT ((uint32_t)0x00000010) /*!< receive fifo 1 message interrupt */
96 #define CAN_RF1FIEN_INT ((uint32_t)0x00000020) /*!< receive fifo 1 full interrupt */
97 #define CAN_RF1OIEN_INT ((uint32_t)0x00000040) /*!< receive fifo 1 overflow interrupt */
98 #define CAN_EAIEN_INT ((uint32_t)0x00000100) /*!< error active interrupt */
99 #define CAN_EPIEN_INT ((uint32_t)0x00000200) /*!< error passive interrupt */
100 #define CAN_BOIEN_INT ((uint32_t)0x00000400) /*!< bus-off interrupt */
101 #define CAN_ETRIEN_INT ((uint32_t)0x00000800) /*!< error type record interrupt */
102 #define CAN_EOIEN_INT ((uint32_t)0x00008000) /*!< error occur interrupt */
103 #define CAN_QDZIEN_INT ((uint32_t)0x00010000) /*!< quit doze mode interrupt */
104 #define CAN_EDZIEN_INT ((uint32_t)0x00020000) /*!< enter doze mode confirm interrupt */
105
106 /**
107 * @}
108 */
109
110 /**
111 * @brief can flag clear operation macro definition val
112 */
113 #define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
114 #define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
115 #define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
116 #define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
117 #define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
118 #define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
119 #define CAN_TSTS_TM0CT_VAL ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
120 #define CAN_TSTS_TM1CT_VAL ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
121 #define CAN_TSTS_TM2CT_VAL ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
122 #define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
123 #define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
124 #define CAN_RF0_RF0R_VAL ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
125 #define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
126 #define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
127 #define CAN_RF1_RF1R_VAL ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
128
129 /** @defgroup CAN_exported_types
130 * @{
131 */
132
133 /**
134 * @brief can filter fifo
135 */
136 typedef enum
137 {
138 CAN_FILTER_FIFO0 = 0x00, /*!< filter fifo 0 assignment for filter x */
139 CAN_FILTER_FIFO1 = 0x01 /*!< filter fifo 1 assignment for filter x */
140 } can_filter_fifo_type;
141
142 /**
143 * @brief can filter mode
144 */
145 typedef enum
146 {
147 CAN_FILTER_MODE_ID_MASK = 0x00, /*!< identifier mask mode */
148 CAN_FILTER_MODE_ID_LIST = 0x01 /*!< identifier list mode */
149 } can_filter_mode_type;
150
151 /**
152 * @brief can filter bit width select
153 */
154 typedef enum
155 {
156 CAN_FILTER_16BIT = 0x00, /*!< two 16-bit filters */
157 CAN_FILTER_32BIT = 0x01 /*!< one 32-bit filter */
158 } can_filter_bit_width_type;
159
160 /**
161 * @brief can mode
162 */
163 typedef enum
164 {
165 CAN_MODE_COMMUNICATE = 0x00, /*!< communication mode */
166 CAN_MODE_LOOPBACK = 0x01, /*!< loopback mode */
167 CAN_MODE_LISTENONLY = 0x02, /*!< listen-only mode */
168 CAN_MODE_LISTENONLY_LOOPBACK = 0x03 /*!< loopback combined with listen-only mode */
169 } can_mode_type;
170
171 /**
172 * @brief can operating mode
173 */
174 typedef enum
175 {
176 CAN_OPERATINGMODE_FREEZE = 0x00, /*!< freeze mode */
177 CAN_OPERATINGMODE_DOZE = 0x01, /*!< doze mode */
178 CAN_OPERATINGMODE_COMMUNICATE = 0x02 /*!< communication mode */
179 } can_operating_mode_type;
180
181 /**
182 * @brief can resynchronization adjust width
183 */
184 typedef enum
185 {
186 CAN_RSAW_1TQ = 0x00, /*!< 1 time quantum */
187 CAN_RSAW_2TQ = 0x01, /*!< 2 time quantum */
188 CAN_RSAW_3TQ = 0x02, /*!< 3 time quantum */
189 CAN_RSAW_4TQ = 0x03 /*!< 4 time quantum */
190 } can_rsaw_type;
191
192 /**
193 * @brief can bit time segment 1
194 */
195 typedef enum
196 {
197 CAN_BTS1_1TQ = 0x00, /*!< 1 time quantum */
198 CAN_BTS1_2TQ = 0x01, /*!< 2 time quantum */
199 CAN_BTS1_3TQ = 0x02, /*!< 3 time quantum */
200 CAN_BTS1_4TQ = 0x03, /*!< 4 time quantum */
201 CAN_BTS1_5TQ = 0x04, /*!< 5 time quantum */
202 CAN_BTS1_6TQ = 0x05, /*!< 6 time quantum */
203 CAN_BTS1_7TQ = 0x06, /*!< 7 time quantum */
204 CAN_BTS1_8TQ = 0x07, /*!< 8 time quantum */
205 CAN_BTS1_9TQ = 0x08, /*!< 9 time quantum */
206 CAN_BTS1_10TQ = 0x09, /*!< 10 time quantum */
207 CAN_BTS1_11TQ = 0x0A, /*!< 11 time quantum */
208 CAN_BTS1_12TQ = 0x0B, /*!< 12 time quantum */
209 CAN_BTS1_13TQ = 0x0C, /*!< 13 time quantum */
210 CAN_BTS1_14TQ = 0x0D, /*!< 14 time quantum */
211 CAN_BTS1_15TQ = 0x0E, /*!< 15 time quantum */
212 CAN_BTS1_16TQ = 0x0F /*!< 16 time quantum */
213 } can_bts1_type;
214
215 /**
216 * @brief can bit time segment 2
217 */
218 typedef enum
219 {
220 CAN_BTS2_1TQ = 0x00, /*!< 1 time quantum */
221 CAN_BTS2_2TQ = 0x01, /*!< 2 time quantum */
222 CAN_BTS2_3TQ = 0x02, /*!< 3 time quantum */
223 CAN_BTS2_4TQ = 0x03, /*!< 4 time quantum */
224 CAN_BTS2_5TQ = 0x04, /*!< 5 time quantum */
225 CAN_BTS2_6TQ = 0x05, /*!< 6 time quantum */
226 CAN_BTS2_7TQ = 0x06, /*!< 7 time quantum */
227 CAN_BTS2_8TQ = 0x07 /*!< 8 time quantum */
228 } can_bts2_type;
229
230 /**
231 * @brief can identifier type
232 */
233 typedef enum
234 {
235 CAN_ID_STANDARD = 0x00, /*!< standard Id */
236 CAN_ID_EXTENDED = 0x01 /*!< extended Id */
237 } can_identifier_type;
238
239 /**
240 * @brief can transmission frame type
241 */
242 typedef enum
243 {
244 CAN_TFT_DATA = 0x00, /*!< data frame */
245 CAN_TFT_REMOTE = 0x01 /*!< remote frame */
246 } can_trans_frame_type;
247
248 /**
249 * @brief can tx mailboxes
250 */
251 typedef enum
252 {
253 CAN_TX_MAILBOX0 = 0x00, /*!< can tx mailbox 0 */
254 CAN_TX_MAILBOX1 = 0x01, /*!< can tx mailbox 1 */
255 CAN_TX_MAILBOX2 = 0x02 /*!< can tx mailbox 2 */
256 } can_tx_mailbox_num_type;
257
258 /**
259 * @brief can receive fifo
260 */
261 typedef enum
262 {
263 CAN_RX_FIFO0 = 0x00, /*!< can fifo 0 used to receive */
264 CAN_RX_FIFO1 = 0x01 /*!< can fifo 1 used to receive */
265 } can_rx_fifo_num_type;
266
267 /**
268 * @brief can transmit status
269 */
270 typedef enum
271 {
272 CAN_TX_STATUS_FAILED = 0x00, /*!< can transmission failed */
273 CAN_TX_STATUS_SUCCESSFUL = 0x01, /*!< can transmission successful */
274 CAN_TX_STATUS_PENDING = 0x02, /*!< can transmission pending */
275 CAN_TX_STATUS_NO_EMPTY = 0x04 /*!< can transmission no empty mailbox */
276 } can_transmit_status_type;
277
278 /**
279 * @brief can enter doze mode status
280 */
281 typedef enum
282 {
283 CAN_ENTER_DOZE_FAILED = 0x00, /*!< can enter the doze mode failed */
284 CAN_ENTER_DOZE_SUCCESSFUL = 0x01 /*!< can enter the doze mode successful */
285 } can_enter_doze_status_type;
286
287 /**
288 * @brief can quit doze mode status
289 */
290 typedef enum
291 {
292 CAN_QUIT_DOZE_FAILED = 0x00, /*!< can quit doze mode failed */
293 CAN_QUIT_DOZE_SUCCESSFUL = 0x01 /*!< can quit doze mode successful */
294 } can_quit_doze_status_type;
295
296 /**
297 * @brief can message discarding rule select when overflow
298 */
299 typedef enum
300 {
301 CAN_DISCARDING_FIRST_RECEIVED = 0x00, /*!< can discarding the first received message */
302 CAN_DISCARDING_LAST_RECEIVED = 0x01 /*!< can discarding the last received message */
303 } can_msg_discarding_rule_type;
304
305 /**
306 * @brief can multiple message sending sequence rule
307 */
308 typedef enum
309 {
310 CAN_SENDING_BY_ID = 0x00, /*!< can sending the minimum id message first*/
311 CAN_SENDING_BY_REQUEST = 0x01 /*!< can sending the first request message first */
312 } can_msg_sending_rule_type;
313
314 /**
315 * @brief can error type record
316 */
317 typedef enum
318 {
319 CAN_ERRORRECORD_NOERR = 0x00, /*!< no error */
320 CAN_ERRORRECORD_STUFFERR = 0x01, /*!< stuff error */
321 CAN_ERRORRECORD_FORMERR = 0x02, /*!< form error */
322 CAN_ERRORRECORD_ACKERR = 0x03, /*!< acknowledgment error */
323 CAN_ERRORRECORD_BITRECESSIVEERR = 0x04, /*!< bit recessive error */
324 CAN_ERRORRECORD_BITDOMINANTERR = 0x05, /*!< bit dominant error */
325 CAN_ERRORRECORD_CRCERR = 0x06, /*!< crc error */
326 CAN_ERRORRECORD_SOFTWARESETERR = 0x07 /*!< software set error */
327 } can_error_record_type;
328
329 /**
330 * @brief can init structure definition
331 */
332 typedef struct
333 {
334 can_mode_type mode_selection; /*!< specifies the can mode.*/
335
336 confirm_state ttc_enable; /*!< time triggered communication mode enable */
337
338 confirm_state aebo_enable; /*!< automatic exit bus-off enable */
339
340 confirm_state aed_enable; /*!< automatic exit doze mode enable */
341
342 confirm_state prsf_enable; /*!< prohibit retransmission when sending fails enable */
343
344 can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
345
346 can_msg_sending_rule_type mmssr_selection; /*!< multiple message sending sequence rule */
347
348 } can_base_type;
349
350 /**
351 * @brief can baudrate structure definition
352 */
353 typedef struct
354 {
355 uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/
356
357 can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
358
359 can_bts1_type bts1_size; /*!< bit time segment 1 */
360
361 can_bts2_type bts2_size; /*!< bit time segment 2 */
362
363 } can_baudrate_type;
364
365 /**
366 * @brief can filter init structure definition
367 */
368 typedef struct
369 {
370 confirm_state filter_activate_enable; /*!< enable or disable the filter activate.*/
371
372 can_filter_mode_type filter_mode; /*!< config the filter mode mask or list.*/
373
374 can_filter_fifo_type filter_fifo; /*!< config the fifo which will be assigned to the filter. */
375
376 uint8_t filter_number; /*!< config the filter number, parameter ranges from 0 to 13. */
377
378 can_filter_bit_width_type filter_bit; /*!< config the filter bit width 16bit or 32bit.*/
379
380 uint16_t filter_id_high; /*!< config the filter identification, for 32-bit configuration
381 it's high 16 bits, for 16-bit configuration it's first. */
382
383 uint16_t filter_id_low; /*!< config the filter identification, for 32-bit configuration
384 it's low 16 bits, for 16-bit configuration it's second. */
385
386 uint16_t filter_mask_high; /*!< config the filter mask or identification, according to the filtering mode,
387 for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
388
389 uint16_t filter_mask_low; /*!< config the filter mask or identification, according to the filtering mode,
390 for 32-bit configuration it's low 16 bits, for 16-bit configuration it's second. */
391 } can_filter_init_type;
392
393 /**
394 * @brief can tx message structure definition
395 */
396 typedef struct
397 {
398 uint32_t standard_id; /*!< specifies the 11 bits standard identifier.
399 this parameter can be a value between 0 to 0x7FF. */
400
401 uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
402 this parameter can be a value between 0 to 0x1FFFFFFF. */
403
404 can_identifier_type id_type; /*!< specifies identifier type for the transmit message.*/
405
406 can_trans_frame_type frame_type; /*!< specifies frame type for the transmit message.*/
407
408 uint8_t dlc; /*!< specifies frame data length that will be transmitted.
409 this parameter can be a value between 0 to 8 */
410
411 uint8_t data[8]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
412
413 } can_tx_message_type;
414
415 /**
416 * @brief can rx message structure definition
417 */
418 typedef struct
419 {
420 uint32_t standard_id; /*!< specifies the 11 bits standard identifier
421 this parameter can be a value between 0 to 0x7FF. */
422
423 uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
424 this parameter can be a value between 0 to 0x1FFFFFFF. */
425
426 can_identifier_type id_type; /*!< specifies identifier type for the receive message.*/
427
428 can_trans_frame_type frame_type; /*!< specifies frame type for the receive message.*/
429
430 uint8_t dlc; /*!< specifies the frame data length that will be received.
431 this parameter can be a value between 0 to 8 */
432
433 uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF.*/
434
435 uint8_t filter_index; /*!< specifies the message stored in which filter
436 this parameter can be a value between 0 to 0xFF */
437 } can_rx_message_type;
438
439 /**
440 * @brief can controller area network tx mailbox
441 */
442 typedef struct
443 {
444 /**
445 * @brief can tmi register
446 */
447 union
448 {
449 __IO uint32_t tmi;
450 struct
451 {
452 __IO uint32_t tmsr : 1; /* [0] */
453 __IO uint32_t tmfrsel : 1; /* [1] */
454 __IO uint32_t tmidsel : 1; /* [2] */
455 __IO uint32_t tmeid : 18;/* [20:3] */
456 __IO uint32_t tmsid : 11;/* [31:21] */
457 } tmi_bit;
458 };
459
460 /**
461 * @brief can tmc register
462 */
463 union
464 {
465 __IO uint32_t tmc;
466 struct
467 {
468 __IO uint32_t tmdtbl : 4; /* [3:0] */
469 __IO uint32_t reserved1 : 4; /* [7:4] */
470 __IO uint32_t tmtsten : 1; /* [8] */
471 __IO uint32_t reserved2 : 7; /* [15:9] */
472 __IO uint32_t tmts : 16;/* [31:16] */
473 } tmc_bit;
474 };
475
476 /**
477 * @brief can tmdtl register
478 */
479 union
480 {
481 __IO uint32_t tmdtl;
482 struct
483 {
484 __IO uint32_t tmdt0 : 8; /* [7:0] */
485 __IO uint32_t tmdt1 : 8; /* [15:8] */
486 __IO uint32_t tmdt2 : 8; /* [23:16] */
487 __IO uint32_t tmdt3 : 8; /* [31:24] */
488 } tmdtl_bit;
489 };
490
491 /**
492 * @brief can tmdth register
493 */
494 union
495 {
496 __IO uint32_t tmdth;
497 struct
498 {
499 __IO uint32_t tmdt4 : 8; /* [7:0] */
500 __IO uint32_t tmdt5 : 8; /* [15:8] */
501 __IO uint32_t tmdt6 : 8; /* [23:16] */
502 __IO uint32_t tmdt7 : 8; /* [31:24] */
503 } tmdth_bit;
504 };
505 } can_tx_mailbox_type;
506
507 /**
508 * @brief can controller area network fifo mailbox
509 */
510 typedef struct
511 {
512 /**
513 * @brief can rfi register
514 */
515 union
516 {
517 __IO uint32_t rfi;
518 struct
519 {
520 __IO uint32_t reserved1 : 1; /* [0] */
521 __IO uint32_t rffri : 1; /* [1] */
522 __IO uint32_t rfidi : 1; /* [2] */
523 __IO uint32_t rfeid : 18;/* [20:3] */
524 __IO uint32_t rfsid : 11;/* [31:21] */
525 } rfi_bit;
526 };
527
528 /**
529 * @brief can rfc register
530 */
531 union
532 {
533 __IO uint32_t rfc;
534 struct
535 {
536 __IO uint32_t rfdtl : 4; /* [3:0] */
537 __IO uint32_t reserved1 : 4; /* [7:4] */
538 __IO uint32_t rffmn : 8; /* [15:8] */
539 __IO uint32_t rfts : 16;/* [31:16] */
540 } rfc_bit;
541 };
542
543 /**
544 * @brief can rfdtl register
545 */
546 union
547 {
548 __IO uint32_t rfdtl;
549 struct
550 {
551 __IO uint32_t rfdt0 : 8; /* [7:0] */
552 __IO uint32_t rfdt1 : 8; /* [15:8] */
553 __IO uint32_t rfdt2 : 8; /* [23:16] */
554 __IO uint32_t rfdt3 : 8; /* [31:24] */
555 } rfdtl_bit;
556 };
557
558 /**
559 * @brief can rfdth register
560 */
561 union
562 {
563 __IO uint32_t rfdth;
564 struct
565 {
566 __IO uint32_t rfdt4 : 8; /* [7:0] */
567 __IO uint32_t rfdt5 : 8; /* [15:8] */
568 __IO uint32_t rfdt6 : 8; /* [23:16] */
569 __IO uint32_t rfdt7 : 8; /* [31:24] */
570 } rfdth_bit;
571 };
572 } can_fifo_mailbox_type;
573
574 /**
575 * @brief can controller area network filter bit register
576 */
577 typedef struct
578 {
579 __IO uint32_t ffdb1;
580 __IO uint32_t ffdb2;
581 } can_filter_register_type;
582
583 /**
584 * @brief type define can register all
585 */
586 typedef struct
587 {
588
589 /**
590 * @brief can mctrl register, offset:0x00
591 */
592 union
593 {
594 __IO uint32_t mctrl;
595 struct
596 {
597 __IO uint32_t fzen : 1; /* [0] */
598 __IO uint32_t dzen : 1; /* [1] */
599 __IO uint32_t mmssr : 1; /* [2] */
600 __IO uint32_t mdrsel : 1; /* [3] */
601 __IO uint32_t prsfen : 1; /* [4] */
602 __IO uint32_t aeden : 1; /* [5] */
603 __IO uint32_t aeboen : 1; /* [6] */
604 __IO uint32_t ttcen : 1; /* [7] */
605 __IO uint32_t reserved1 : 7; /* [14:8] */
606 __IO uint32_t sprst : 1; /* [15] */
607 __IO uint32_t ptd : 1; /* [16] */
608 __IO uint32_t reserved2 : 15;/*[31:17] */
609 } mctrl_bit;
610 };
611
612 /**
613 * @brief can msts register, offset:0x04
614 */
615 union
616 {
617 __IO uint32_t msts;
618 struct
619 {
620 __IO uint32_t fzc : 1; /* [0] */
621 __IO uint32_t dzc : 1; /* [1] */
622 __IO uint32_t eoif : 1; /* [2] */
623 __IO uint32_t qdzif : 1; /* [3] */
624 __IO uint32_t edzif : 1; /* [4] */
625 __IO uint32_t reserved1 : 3; /* [7:5] */
626 __IO uint32_t cuss : 1; /* [8] */
627 __IO uint32_t curs : 1; /* [9] */
628 __IO uint32_t lsamprx : 1; /* [10] */
629 __IO uint32_t realrx : 1; /* [11] */
630 __IO uint32_t reserved2 : 20;/*[31:12] */
631 } msts_bit;
632 };
633
634 /**
635 * @brief can tsts register, offset:0x08
636 */
637 union
638 {
639 __IO uint32_t tsts;
640 struct
641 {
642 __IO uint32_t tm0tcf : 1; /* [0] */
643 __IO uint32_t tm0tsf : 1; /* [1] */
644 __IO uint32_t tm0alf : 1; /* [2] */
645 __IO uint32_t tm0tef : 1; /* [3] */
646 __IO uint32_t reserved1 : 3; /* [6:4] */
647 __IO uint32_t tm0ct : 1; /* [7] */
648 __IO uint32_t tm1tcf : 1; /* [8] */
649 __IO uint32_t tm1tsf : 1; /* [9] */
650 __IO uint32_t tm1alf : 1; /* [10] */
651 __IO uint32_t tm1tef : 1; /* [11] */
652 __IO uint32_t reserved2 : 3; /* [14:12] */
653 __IO uint32_t tm1ct : 1; /* [15] */
654 __IO uint32_t tm2tcf : 1; /* [16] */
655 __IO uint32_t tm2tsf : 1; /* [17] */
656 __IO uint32_t tm2alf : 1; /* [18] */
657 __IO uint32_t tm2tef : 1; /* [19] */
658 __IO uint32_t reserved3 : 3; /* [22:20] */
659 __IO uint32_t tm2ct : 1; /* [23] */
660 __IO uint32_t tmnr : 2; /* [25:24] */
661 __IO uint32_t tm0ef : 1; /* [26] */
662 __IO uint32_t tm1ef : 1; /* [27] */
663 __IO uint32_t tm2ef : 1; /* [28] */
664 __IO uint32_t tm0lpf : 1; /* [29] */
665 __IO uint32_t tm1lpf : 1; /* [30] */
666 __IO uint32_t tm2lpf : 1; /* [31] */
667 } tsts_bit;
668 };
669
670 /**
671 * @brief can rf0 register, offset:0x0C
672 */
673 union
674 {
675 __IO uint32_t rf0;
676 struct
677 {
678 __IO uint32_t rf0mn : 2; /* [1:0] */
679 __IO uint32_t reserved1 : 1; /* [2] */
680 __IO uint32_t rf0ff : 1; /* [3] */
681 __IO uint32_t rf0of : 1; /* [4] */
682 __IO uint32_t rf0r : 1; /* [5] */
683 __IO uint32_t reserved2 : 26;/* [31:6] */
684 } rf0_bit;
685 };
686
687 /**
688 * @brief can rf1 register, offset:0x10
689 */
690 union
691 {
692 __IO uint32_t rf1;
693 struct
694 {
695 __IO uint32_t rf1mn : 2; /* [1:0] */
696 __IO uint32_t reserved1 : 1; /* [2] */
697 __IO uint32_t rf1ff : 1; /* [3] */
698 __IO uint32_t rf1of : 1; /* [4] */
699 __IO uint32_t rf1r : 1; /* [5] */
700 __IO uint32_t reserved2 : 26;/* [31:6] */
701 } rf1_bit;
702 };
703
704 /**
705 * @brief can inten register, offset:0x14
706 */
707 union
708 {
709 __IO uint32_t inten;
710 struct
711 {
712 __IO uint32_t tcien : 1; /* [0] */
713 __IO uint32_t rf0mien : 1; /* [1] */
714 __IO uint32_t rf0fien : 1; /* [2] */
715 __IO uint32_t rf0oien : 1; /* [3] */
716 __IO uint32_t rf1mien : 1; /* [4] */
717 __IO uint32_t rf1fien : 1; /* [5] */
718 __IO uint32_t rf1oien : 1; /* [6] */
719 __IO uint32_t reserved1 : 1; /* [7] */
720 __IO uint32_t eaien : 1; /* [8] */
721 __IO uint32_t epien : 1; /* [9] */
722 __IO uint32_t boien : 1; /* [10] */
723 __IO uint32_t etrien : 1; /* [11] */
724 __IO uint32_t reserved2 : 3; /* [14:12] */
725 __IO uint32_t eoien : 1; /* [15] */
726 __IO uint32_t qdzien : 1; /* [16] */
727 __IO uint32_t edzien : 1; /* [17] */
728 __IO uint32_t reserved3 : 14;/* [31:18] */
729 } inten_bit;
730 };
731
732 /**
733 * @brief can ests register, offset:0x18
734 */
735 union
736 {
737 __IO uint32_t ests;
738 struct
739 {
740 __IO uint32_t eaf : 1; /* [0] */
741 __IO uint32_t epf : 1; /* [1] */
742 __IO uint32_t bof : 1; /* [2] */
743 __IO uint32_t reserved1 : 1; /* [3] */
744 __IO uint32_t etr : 3; /* [6:4] */
745 __IO uint32_t reserved2 : 9; /* [15:7] */
746 __IO uint32_t tec : 8; /* [23:16] */
747 __IO uint32_t rec : 8; /* [31:24] */
748 } ests_bit;
749 };
750
751 /**
752 * @brief can btmg register, offset:0x1C
753 */
754 union
755 {
756 __IO uint32_t btmg;
757 struct
758 {
759 __IO uint32_t brdiv : 12;/* [11:0] */
760 __IO uint32_t reserved1 : 4; /* [15:12] */
761 __IO uint32_t bts1 : 4; /* [19:16] */
762 __IO uint32_t bts2 : 3; /* [22:20] */
763 __IO uint32_t reserved2 : 1; /* [23] */
764 __IO uint32_t rsaw : 2; /* [25:24] */
765 __IO uint32_t reserved3 : 4; /* [29:26] */
766 __IO uint32_t lben : 1; /* [30] */
767 __IO uint32_t loen : 1; /* [31] */
768 } btmg_bit;
769 };
770
771 /**
772 * @brief can reserved register, offset:0x20~0x17C
773 */
774 __IO uint32_t reserved1[88];
775
776 /**
777 * @brief can controller area network tx mailbox register, offset:0x180~0x1AC
778 */
779 can_tx_mailbox_type tx_mailbox[3];
780
781 /**
782 * @brief can controller area network fifo mailbox register, offset:0x1B0~0x1CC
783 */
784 can_fifo_mailbox_type fifo_mailbox[2];
785
786 /**
787 * @brief can reserved register, offset:0x1D0~0x1FC
788 */
789 __IO uint32_t reserved2[12];
790
791 /**
792 * @brief can fctrl register, offset:0x200
793 */
794 union
795 {
796 __IO uint32_t fctrl;
797 struct
798 {
799 __IO uint32_t fcs : 1; /* [0] */
800 __IO uint32_t reserved1 : 31;/* [31:1] */
801 } fctrl_bit;
802 };
803
804 /**
805 * @brief can fmcfg register, offset:0x204
806 */
807 union
808 {
809 __IO uint32_t fmcfg;
810 struct
811 {
812 __IO uint32_t fmsel0 : 1; /* [0] */
813 __IO uint32_t fmsel1 : 1; /* [1] */
814 __IO uint32_t fmsel2 : 1; /* [2] */
815 __IO uint32_t fmsel3 : 1; /* [3] */
816 __IO uint32_t fmsel4 : 1; /* [4] */
817 __IO uint32_t fmsel5 : 1; /* [5] */
818 __IO uint32_t fmsel6 : 1; /* [6] */
819 __IO uint32_t fmsel7 : 1; /* [7] */
820 __IO uint32_t fmsel8 : 1; /* [8] */
821 __IO uint32_t fmsel9 : 1; /* [9] */
822 __IO uint32_t fmsel10 : 1; /* [10] */
823 __IO uint32_t fmsel11 : 1; /* [11] */
824 __IO uint32_t fmsel12 : 1; /* [12] */
825 __IO uint32_t fmsel13 : 1; /* [13] */
826 __IO uint32_t fmsel14 : 1; /* [14] */
827 __IO uint32_t fmsel15 : 1; /* [15] */
828 __IO uint32_t fmsel16 : 1; /* [16] */
829 __IO uint32_t fmsel17 : 1; /* [17] */
830 __IO uint32_t fmsel18 : 1; /* [18] */
831 __IO uint32_t fmsel19 : 1; /* [19] */
832 __IO uint32_t fmsel20 : 1; /* [20] */
833 __IO uint32_t fmsel21 : 1; /* [21] */
834 __IO uint32_t fmsel22 : 1; /* [22] */
835 __IO uint32_t fmsel23 : 1; /* [23] */
836 __IO uint32_t fmsel24 : 1; /* [24] */
837 __IO uint32_t fmsel25 : 1; /* [25] */
838 __IO uint32_t fmsel26 : 1; /* [26] */
839 __IO uint32_t fmsel27 : 1; /* [27] */
840 __IO uint32_t reserved1 : 4;/* [31:28] */
841 } fmcfg_bit;
842 };
843
844 /**
845 * @brief can reserved register, offset:0x208
846 */
847 __IO uint32_t reserved3;
848
849 /**
850 * @brief can fbwcfg register, offset:0x20C
851 */
852 union
853 {
854 __IO uint32_t fbwcfg;
855 struct
856 {
857 __IO uint32_t fbwsel0 : 1; /* [0] */
858 __IO uint32_t fbwsel1 : 1; /* [1] */
859 __IO uint32_t fbwsel2 : 1; /* [2] */
860 __IO uint32_t fbwsel3 : 1; /* [3] */
861 __IO uint32_t fbwsel4 : 1; /* [4] */
862 __IO uint32_t fbwsel5 : 1; /* [5] */
863 __IO uint32_t fbwsel6 : 1; /* [6] */
864 __IO uint32_t fbwsel7 : 1; /* [7] */
865 __IO uint32_t fbwsel8 : 1; /* [8] */
866 __IO uint32_t fbwsel9 : 1; /* [9] */
867 __IO uint32_t fbwsel10 : 1; /* [10] */
868 __IO uint32_t fbwsel11 : 1; /* [11] */
869 __IO uint32_t fbwsel12 : 1; /* [12] */
870 __IO uint32_t fbwsel13 : 1; /* [13] */
871 __IO uint32_t fbwsel14 : 1; /* [14] */
872 __IO uint32_t fbwsel15 : 1; /* [15] */
873 __IO uint32_t fbwsel16 : 1; /* [16] */
874 __IO uint32_t fbwsel17 : 1; /* [17] */
875 __IO uint32_t fbwsel18 : 1; /* [18] */
876 __IO uint32_t fbwsel19 : 1; /* [19] */
877 __IO uint32_t fbwsel20 : 1; /* [20] */
878 __IO uint32_t fbwsel21 : 1; /* [21] */
879 __IO uint32_t fbwsel22 : 1; /* [22] */
880 __IO uint32_t fbwsel23 : 1; /* [23] */
881 __IO uint32_t fbwsel24 : 1; /* [24] */
882 __IO uint32_t fbwsel25 : 1; /* [25] */
883 __IO uint32_t fbwsel26 : 1; /* [26] */
884 __IO uint32_t fbwsel27 : 1; /* [27] */
885 __IO uint32_t reserved1 : 4;/* [31:28] */
886 } fbwcfg_bit;
887 };
888
889 /**
890 * @brief can reserved register, offset:0x210
891 */
892 __IO uint32_t reserved4;
893
894 /**
895 * @brief can frf register, offset:0x214
896 */
897 union
898 {
899 __IO uint32_t frf;
900 struct
901 {
902 __IO uint32_t frfsel0 : 1; /* [0] */
903 __IO uint32_t frfsel1 : 1; /* [1] */
904 __IO uint32_t frfsel2 : 1; /* [2] */
905 __IO uint32_t frfsel3 : 1; /* [3] */
906 __IO uint32_t frfsel4 : 1; /* [4] */
907 __IO uint32_t frfsel5 : 1; /* [5] */
908 __IO uint32_t frfsel6 : 1; /* [6] */
909 __IO uint32_t frfsel7 : 1; /* [7] */
910 __IO uint32_t frfsel8 : 1; /* [8] */
911 __IO uint32_t frfsel9 : 1; /* [9] */
912 __IO uint32_t frfsel10 : 1; /* [10] */
913 __IO uint32_t frfsel11 : 1; /* [11] */
914 __IO uint32_t frfsel12 : 1; /* [12] */
915 __IO uint32_t frfsel13 : 1; /* [13] */
916 __IO uint32_t frfsel14 : 1; /* [14] */
917 __IO uint32_t frfsel15 : 1; /* [15] */
918 __IO uint32_t frfsel16 : 1; /* [16] */
919 __IO uint32_t frfsel17 : 1; /* [17] */
920 __IO uint32_t frfsel18 : 1; /* [18] */
921 __IO uint32_t frfsel19 : 1; /* [19] */
922 __IO uint32_t frfsel20 : 1; /* [20] */
923 __IO uint32_t frfsel21 : 1; /* [21] */
924 __IO uint32_t frfsel22 : 1; /* [22] */
925 __IO uint32_t frfsel23 : 1; /* [23] */
926 __IO uint32_t frfsel24 : 1; /* [24] */
927 __IO uint32_t frfsel25 : 1; /* [25] */
928 __IO uint32_t frfsel26 : 1; /* [26] */
929 __IO uint32_t frfsel27 : 1; /* [27] */
930 __IO uint32_t reserved1 : 4;/* [31:28] */
931 } frf_bit;
932 };
933
934 /**
935 * @brief can reserved register, offset:0x218
936 */
937 __IO uint32_t reserved5;
938
939 /**
940 * @brief can facfg register, offset:0x21C
941 */
942 union
943 {
944 __IO uint32_t facfg;
945 struct
946 {
947 __IO uint32_t faen0 : 1; /* [0] */
948 __IO uint32_t faen1 : 1; /* [1] */
949 __IO uint32_t faen2 : 1; /* [2] */
950 __IO uint32_t faen3 : 1; /* [3] */
951 __IO uint32_t faen4 : 1; /* [4] */
952 __IO uint32_t faen5 : 1; /* [5] */
953 __IO uint32_t faen6 : 1; /* [6] */
954 __IO uint32_t faen7 : 1; /* [7] */
955 __IO uint32_t faen8 : 1; /* [8] */
956 __IO uint32_t faen9 : 1; /* [9] */
957 __IO uint32_t faen10 : 1; /* [10] */
958 __IO uint32_t faen11 : 1; /* [11] */
959 __IO uint32_t faen12 : 1; /* [12] */
960 __IO uint32_t faen13 : 1; /* [13] */
961 __IO uint32_t faen14 : 1; /* [14] */
962 __IO uint32_t faen15 : 1; /* [15] */
963 __IO uint32_t faen16 : 1; /* [16] */
964 __IO uint32_t faen17 : 1; /* [17] */
965 __IO uint32_t faen18 : 1; /* [18] */
966 __IO uint32_t faen19 : 1; /* [19] */
967 __IO uint32_t faen20 : 1; /* [20] */
968 __IO uint32_t faen21 : 1; /* [21] */
969 __IO uint32_t faen22 : 1; /* [22] */
970 __IO uint32_t faen23 : 1; /* [23] */
971 __IO uint32_t faen24 : 1; /* [24] */
972 __IO uint32_t faen25 : 1; /* [25] */
973 __IO uint32_t faen26 : 1; /* [26] */
974 __IO uint32_t faen27 : 1; /* [27] */
975 __IO uint32_t reserved1 : 4;/* [31:28] */
976 } facfg_bit;
977 };
978
979 /**
980 * @brief can reserved register, offset:0x220~0x23C
981 */
982 __IO uint32_t reserved6[8];
983
984 /**
985 * @brief can ffb register, offset:0x240~0x2AC
986 */
987 can_filter_register_type ffb[28];
988 } can_type;
989
990 /**
991 * @}
992 */
993
994 #define CAN1 ((can_type *) CAN1_BASE)
995 #define CAN2 ((can_type *) CAN2_BASE)
996
997 /** @defgroup CAN_exported_functions
998 * @{
999 */
1000
1001 void can_reset(can_type* can_x);
1002 void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
1003 error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);
1004 void can_default_para_init(can_base_type* can_base_struct);
1005 error_status can_base_init(can_type* can_x, can_base_type* can_base_struct);
1006 void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct);
1007 void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct);
1008 void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state);
1009 void can_ttc_mode_enable(can_type* can_x, confirm_state new_state);
1010 uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct);
1011 can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
1012 void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
1013 void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct);
1014 void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number);
1015 uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number);
1016 error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode);
1017 can_enter_doze_status_type can_doze_mode_enter(can_type* can_x);
1018 can_quit_doze_status_type can_doze_mode_exit(can_type* can_x);
1019 can_error_record_type can_error_type_record_get(can_type* can_x);
1020 uint8_t can_receive_error_counter_get(can_type* can_x);
1021 uint8_t can_transmit_error_counter_get(can_type* can_x);
1022 void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
1023 flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
1024 void can_flag_clear(can_type* can_x, uint32_t can_flag);
1025
1026 /**
1027 * @}
1028 */
1029
1030 /**
1031 * @}
1032 */
1033
1034 /**
1035 * @}
1036 */
1037
1038 #ifdef __cplusplus
1039 }
1040 #endif
1041
1042 #endif
INAV: Navigation-enabled flight control software