lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_dac.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_dac.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 dac header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* Define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_DAC_H
  29 #define __AT32F435_437_DAC_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* Includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39 /** @addtogroup AT32F435_437_periph_driver
  40   * @{
  41   */
  42
  43 /** @addtogroup DAC
  44   * @{
  45   */
  46
  47 #define DAC1_D1DMAUDRF                   ((uint32_t)(0x00002000))
  48 #define DAC2_D2DMAUDRF                   ((uint32_t)(0x20000000))
  49
  50 /** @defgroup DAC_exported_types
  51   * @{
  52   */
  53
  54 /**
  55   * @brief dac select type
  56   */
  57 typedef enum
  58 {
  59   DAC1_SELECT                            = 0x01, /*!< dac1 select */
  60   DAC2_SELECT                            = 0x02  /*!< dac2 select */
  61 } dac_select_type;
  62
  63 /**
  64   * @brief dac trigger type
  65   */
  66 typedef enum
  67 {
  68   DAC_TMR6_TRGOUT_EVENT                  = 0x00, /*!< dac trigger selection:timer6 trgout event */
  69   DAC_TMR8_TRGOUT_EVENT                  = 0x01, /*!< dac trigger selection:timer8 trgout event */
  70   DAC_TMR7_TRGOUT_EVENT                  = 0x02, /*!< dac trigger selection:timer7 trgout event */
  71   DAC_TMR5_TRGOUT_EVENT                  = 0x03, /*!< dac trigger selection:timer5 trgout event */
  72   DAC_TMR2_TRGOUT_EVENT                  = 0x04, /*!< dac trigger selection:timer2 trgout event */
  73   DAC_TMR4_TRGOUT_EVENT                  = 0x05, /*!< dac trigger selection:timer4 trgout event */
  74   DAC_EXTERNAL_INTERRUPT_LINE_9          = 0x06, /*!< dac trigger selection:external line9 */
  75   DAC_SOFTWARE_TRIGGER                   = 0x07  /*!< dac trigger selection:software trigger */
  76 } dac_trigger_type;
  77
  78 /**
  79   * @brief dac wave type
  80   */
  81 typedef enum
  82 {
  83   DAC_WAVE_GENERATE_NONE                 = 0x00, /*!< dac wave generation disabled */
  84   DAC_WAVE_GENERATE_NOISE                = 0x01, /*!< dac noise wave generation enabled */
  85   DAC_WAVE_GENERATE_TRIANGLE             = 0x02  /*!< dac triangle wave generation enabled */
  86 } dac_wave_type;
  87
  88 /**
  89   * @brief dac mask amplitude type
  90   */
  91 typedef enum
  92 {
  93   DAC_LSFR_BIT0_AMPLITUDE_1              = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
  94   DAC_LSFR_BIT10_AMPLITUDE_3             = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
  95   DAC_LSFR_BIT20_AMPLITUDE_7             = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
  96   DAC_LSFR_BIT30_AMPLITUDE_15            = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
  97   DAC_LSFR_BIT40_AMPLITUDE_31            = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
  98   DAC_LSFR_BIT50_AMPLITUDE_63            = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
  99   DAC_LSFR_BIT60_AMPLITUDE_127           = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
 100   DAC_LSFR_BIT70_AMPLITUDE_255           = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
 101   DAC_LSFR_BIT80_AMPLITUDE_511           = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
 102   DAC_LSFR_BIT90_AMPLITUDE_1023          = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
 103   DAC_LSFR_BITA0_AMPLITUDE_2047          = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
 104   DAC_LSFR_BITB0_AMPLITUDE_4095          = 0x0B  /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
 105 } dac_mask_amplitude_type;
 106
 107 /**
 108   * @brief  dac1 aligned data type
 109   */
 110 typedef enum
 111 {
 112   DAC1_12BIT_RIGHT                       = 0x40007408, /*!< dac1 12-bit data right-aligned */
 113   DAC1_12BIT_LEFT                        = 0x4000740C, /*!< dac1 12-bit data left-aligned */
 114   DAC1_8BIT_RIGHT                        = 0x40007410  /*!< dac1 8-bit data right-aligned */
 115 } dac1_aligned_data_type;
 116
 117 /**
 118   * @brief  dac2 aligned data type
 119   */
 120 typedef enum
 121 {
 122   DAC2_12BIT_RIGHT                       = 0x40007414, /*!< dac2 12-bit data right-aligned */
 123   DAC2_12BIT_LEFT                        = 0x40007418, /*!< dac2 12-bit data left-aligned */
 124   DAC2_8BIT_RIGHT                        = 0x4000741C  /*!< dac2 8-bit data right-aligned */
 125 } dac2_aligned_data_type;
 126
 127 /**
 128   * @brief  dac dual data type
 129   */
 130 typedef enum
 131 {
 132   DAC_DUAL_12BIT_RIGHT                   = 0x40007420, /*!<double dac 12-bit data right-aligned */
 133   DAC_DUAL_12BIT_LEFT                    = 0x40007424, /*!<double dac 12-bit data left-aligned */
 134   DAC_DUAL_8BIT_RIGHT                    = 0x40007428  /*!<double dac 8-bit data right-aligned */
 135 } dac_dual_data_type;
 136
 137 /**
 138   * @brief type define dac register all
 139   */
 140 typedef struct
 141 {
 142   /**
 143     * @brief dac ctrl register, offset:0x00
 144     */
 145   union
 146   {
 147     __IO uint32_t ctrl;
 148     struct
 149     {
 150       __IO uint32_t d1en                 : 1; /* [0] */
 151       __IO uint32_t d1obdis              : 1; /* [1] */
 152       __IO uint32_t d1trgen              : 1; /* [2] */
 153       __IO uint32_t d1trgsel             : 3; /* [5:3] */
 154       __IO uint32_t d1nm                 : 2; /* [7:6] */
 155       __IO uint32_t d1nbsel              : 4; /* [11:8] */
 156       __IO uint32_t d1dmaen              : 1; /* [12] */
 157       __IO uint32_t d1dmaudrien          : 1; /* [13] */
 158       __IO uint32_t reserved1            : 2; /* [15:14] */
 159       __IO uint32_t d2en                 : 1; /* [16] */
 160       __IO uint32_t d2obdis              : 1; /* [17] */
 161       __IO uint32_t d2trgen              : 1; /* [18] */
 162       __IO uint32_t d2trgsel             : 3; /* [21:19] */
 163       __IO uint32_t d2nm                 : 2; /* [23:22] */
 164       __IO uint32_t d2nbsel              : 4; /* [27:24] */
 165       __IO uint32_t d2dmaen              : 1; /* [28] */
 166       __IO uint32_t d2dmaudrien          : 1; /* [29] */
 167       __IO uint32_t reserved2            : 2; /* [31:30] */
 168     } ctrl_bit;
 169   };
 170
 171  /**
 172     * @brief dac swtrg register, offset:0x04
 173     */
 174   union
 175   {
 176     __IO uint32_t swtrg;
 177     struct
 178     {
 179       __IO uint32_t d1swtrg              : 1; /* [0] */
 180       __IO uint32_t d2swtrg              : 1; /* [1] */
 181       __IO uint32_t reserved1            : 30;/* [31:2] */
 182     } swtrg_bit;
 183   };
 184
 185  /**
 186     * @brief dac d1dth12r register, offset:0x08
 187     */
 188   union
 189   {
 190     __IO uint32_t d1dth12r;
 191     struct
 192     {
 193       __IO uint32_t d1dt12r              : 12;/* [11:0] */
 194       __IO uint32_t reserved1            : 20;/* [31:2] */
 195     } d1dth12r_bit;
 196   };
 197
 198  /**
 199     * @brief dac d1dth12l register, offset:0x0C
 200     */
 201   union
 202   {
 203     __IO uint32_t d1dth12l;
 204     struct
 205     {
 206       __IO uint32_t d1dt12l              : 12;/* [11:0] */
 207       __IO uint32_t reserved1            : 20;/* [31:2] */
 208     } d1dth12l_bit;
 209   };
 210
 211  /**
 212     * @brief dac d1dth8r register, offset:0x10
 213     */
 214   union
 215   {
 216     __IO uint32_t d1dth8r;
 217     struct
 218     {
 219       __IO uint32_t d1dt8r               : 8; /* [7:0] */
 220       __IO uint32_t reserved1            : 24;/* [31:8] */
 221     } d1dth8r_bit;
 222   };
 223
 224  /**
 225     * @brief dac d2dth12r register, offset:0x14
 226     */
 227   union
 228   {
 229     __IO uint32_t d2dth12r;
 230     struct
 231     {
 232       __IO uint32_t d2dt12r              : 12;/* [11:0] */
 233       __IO uint32_t reserved1            : 20;/* [31:2] */
 234     } d2dth12r_bit;
 235   };
 236
 237  /**
 238     * @brief dac d2dth12l register, offset:0x18
 239     */
 240   union
 241   {
 242     __IO uint32_t d2dth12l;
 243     struct
 244     {
 245       __IO uint32_t d2dt12l              : 12;/* [11:0] */
 246       __IO uint32_t reserved1            : 20;/* [31:2] */
 247     } d2dth12l_bit;
 248   };
 249
 250  /**
 251     * @brief dac d2dth8r register, offset:0x1C
 252     */
 253   union
 254   {
 255     __IO uint32_t d2dth8r;
 256     struct
 257     {
 258       __IO uint32_t d2dt8r               : 8; /* [7:0] */
 259       __IO uint32_t reserved1            : 24;/* [31:8] */
 260     } d2dth8r_bit;
 261   };
 262
 263  /**
 264     * @brief dac ddth12r register, offset:0x20
 265     */
 266   union
 267   {
 268     __IO uint32_t ddth12r;
 269     struct
 270     {
 271       __IO uint32_t dd1dt12r             : 12;/* [11:0] */
 272       __IO uint32_t reserved1            : 4; /* [15:12] */
 273       __IO uint32_t dd2dt12r             : 12;/* [27:16] */
 274       __IO uint32_t reserved2            : 4; /* [31:28] */
 275     } ddth12r_bit;
 276   };
 277
 278  /**
 279     * @brief dac ddth12l register, offset:0x24
 280     */
 281   union
 282   {
 283     __IO uint32_t ddth12l;
 284     struct
 285     {
 286       __IO uint32_t reserved1            : 4; /* [3:0] */
 287       __IO uint32_t dd1dt12l             : 12;/* [15:4] */
 288       __IO uint32_t reserved2            : 4; /* [19:16] */
 289       __IO uint32_t dd2dt12l             : 12;/* [31:20] */
 290     } ddth12l_bit;
 291   };
 292
 293  /**
 294     * @brief dac ddth8r register, offset:0x28
 295     */
 296   union
 297   {
 298     __IO uint32_t ddth8r;
 299     struct
 300     {
 301       __IO uint32_t dd1dt8r              : 8; /* [7:0] */
 302       __IO uint32_t dd2dt8r              : 8; /* [15:8] */
 303       __IO uint32_t reserved1            : 16;/* [31:16] */
 304     } ddth8r_bit;
 305   };
 306
 307  /**
 308     * @brief dac d1odt register, offset:0x2c
 309     */
 310   union
 311   {
 312     __IO uint32_t d1odt;
 313     struct
 314     {
 315       __IO uint32_t d1odt                : 12;/* [11:0] */
 316       __IO uint32_t reserved1            : 20;/* [31:12] */
 317     } d1odt_bit;
 318   };
 319
 320  /**
 321     * @brief dac d2odt register, offset:0x30
 322     */
 323   union
 324   {
 325     __IO uint32_t d2odt;
 326     struct
 327     {
 328       __IO uint32_t d2odt                : 12;/* [11:0] */
 329       __IO uint32_t reserved1            : 20;/* [31:12] */
 330     } d2odt_bit;
 331   };
 332
 333  /**
 334     * @brief dac sr register, offset:0x34
 335     */
 336   union
 337   {
 338     __IO uint32_t sts;
 339     struct
 340     {
 341       __IO uint32_t reserved1            : 13;/* [12:0] */
 342       __IO uint32_t d1dmaudrf            : 1; /* [13] */
 343       __IO uint32_t reserved2            : 15;/* [28:14] */
 344       __IO uint32_t d2dmaudrf            : 1; /* [29] */
 345       __IO uint32_t reserved3            : 2;/* [31:30] */
 346     } sts_bit;
 347   };
 348 } dac_type;
 349
 350 /**
 351   * @}
 352   */
 353
 354 #define DAC                              ((dac_type *) DAC_BASE)
 355
 356 /** @defgroup DAC_exported_functions
 357   * @{
 358   */
 359
 360 void dac_reset(void);
 361 void dac_enable(dac_select_type dac_select, confirm_state new_state);
 362 void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
 363 void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
 364 void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source);
 365 void dac_software_trigger_generate(dac_select_type dac_select);
 366 void dac_dual_software_trigger_generate(void);
 367 void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);
 368 void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude);
 369 void dac_dma_enable(dac_select_type dac_select, confirm_state new_state);
 370 uint16_t dac_data_output_get(dac_select_type dac_select);
 371 void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data);
 372 void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data);
 373 void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2);
 374 void dac_udr_enable(dac_select_type dac_select, confirm_state new_state);
 375 flag_status dac_udr_flag_get(dac_select_type dac_select);
 376 void dac_udr_flag_clear(dac_select_type dac_select);
 377
 378 /**
 379   * @}
 380   */
 381
 382 /**
 383   * @}
 384   */
 385
 386 /**
 387   * @}
 388   */
 389
 390 #ifdef __cplusplus
 391 }
 392 #endif
 393
 394 #endif