lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_dvp.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_dvp.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 dvp header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* Define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_DVP_H
  29 #define __AT32F435_437_DVP_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* Includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39 /** @addtogroup AT32F435_437_periph_driver
  40   * @{
  41   */
  42
  43 /** @addtogroup DVP
  44   * @{
  45   */
  46
  47 /** @defgroup DVP_event_flags_definition
  48   * @brief dvp event flag
  49   * @{
  50   */
  51
  52 #define DVP_CFD_EVT_FLAG                 ((uint32_t)0x00000001) /*!< capture frame done event status flag */
  53 #define DVP_OVR_EVT_FLAG                 ((uint32_t)0x00000002) /*!< data fifo overrun event status flag */
  54 #define DVP_ESE_EVT_FLAG                 ((uint32_t)0x00000004) /*!< embedded synchronization error event status flag */
  55 #define DVP_VS_EVT_FLAG                  ((uint32_t)0x00000008) /*!< vertical synchonization event status flag */
  56 #define DVP_HS_EVT_FLAG                  ((uint32_t)0x00000010) /*!< horizontal synchonization event status flag */
  57
  58 /**
  59   * @}
  60   */
  61
  62 /** @defgroup DVP_interrupt_flags_definition
  63   * @brief dvp interrupt flag
  64   * @{
  65   */
  66
  67 #define DVP_CFD_INT_FLAG                 ((uint32_t)0x80000001) /*!< capture frame done interrupt status flag */
  68 #define DVP_OVR_INT_FLAG                 ((uint32_t)0x80000002) /*!< data fifo overrun interrupt status flag */
  69 #define DVP_ESE_INT_FLAG                 ((uint32_t)0x80000004) /*!< embedded synchronization error interrupt status flag */
  70 #define DVP_VS_INT_FLAG                  ((uint32_t)0x80000008) /*!< vertical synchonization interrupt status flag */
  71 #define DVP_HS_INT_FLAG                  ((uint32_t)0x80000010) /*!< horizontal synchonization interrupt status flag */
  72
  73 /**
  74   * @}
  75   */
  76
  77 /** @defgroup DVP_interrupts_definition
  78   * @brief dvp interrupt
  79   * @{
  80   */
  81
  82 #define DVP_CFD_INT                      ((uint32_t)0x00000001) /*!< capture frame done interrupt */
  83 #define DVP_OVR_INT                      ((uint32_t)0x00000002) /*!< data fifo overrun interrupt */
  84 #define DVP_ESE_INT                      ((uint32_t)0x00000004) /*!< embedded synchronization error interrupt */
  85 #define DVP_VS_INT                       ((uint32_t)0x00000008) /*!< vertical synchonization interrupt */
  86 #define DVP_HS_INT                       ((uint32_t)0x00000010) /*!< horizontal synchonization interrupt */
  87
  88 /**
  89   * @}
  90   */
  91
  92 /** @defgroup DVP_exported_types
  93   * @{
  94   */
  95
  96 /**
  97   * @brief dvp cfm type
  98   */
  99 typedef enum
 100 {
 101   DVP_CAP_FUNC_MODE_CONTINUOUS           = 0x00,
 102   DVP_CAP_FUNC_MODE_SINGLE               = 0x01
 103 } dvp_cfm_type;
 104
 105 /**
 106   * @brief dvp sm type
 107   */
 108 typedef enum
 109 {
 110   DVP_SYNC_MODE_HARDWARE                 = 0x00,
 111   DVP_SYNC_MODE_EMBEDDED                 = 0x01
 112 } dvp_sm_type;
 113
 114 /**
 115   * @brief dvp ckp type
 116   */
 117 typedef enum
 118 {
 119   DVP_CLK_POLARITY_RISING                = 0x00,
 120   DVP_CLK_POLARITY_FALLING               = 0x01
 121 } dvp_ckp_type;
 122
 123 /**
 124   * @brief dvp hsp type
 125   */
 126 typedef enum
 127 {
 128   DVP_HSYNC_POLARITY_HIGH                = 0x00,
 129   DVP_HSYNC_POLARITY_LOW                 = 0x01
 130 } dvp_hsp_type;
 131
 132 /**
 133   * @brief dvp vsp type
 134   */
 135 typedef enum
 136 {
 137   DVP_VSYNC_POLARITY_LOW                 = 0x00,
 138   DVP_VSYNC_POLARITY_HIGH                = 0x01
 139 } dvp_vsp_type;
 140
 141 /**
 142   * @brief dvp bfrc type
 143   */
 144 typedef enum
 145 {
 146   DVP_BFRC_ALL                           = 0x00,
 147   DVP_BFRC_HALF                          = 0x01,
 148   DVP_BFRC_QUARTER                       = 0x02
 149 } dvp_bfrc_type;
 150
 151 /**
 152   * @brief dvp pdl type
 153   */
 154 typedef enum
 155 {
 156   DVP_PIXEL_DATA_LENGTH_8                = 0x00,
 157   DVP_PIXEL_DATA_LENGTH_10               = 0x01,
 158   DVP_PIXEL_DATA_LENGTH_12               = 0x02,
 159   DVP_PIXEL_DATA_LENGTH_14               = 0x03
 160 } dvp_pdl_type;
 161
 162 /**
 163   * @brief dvp pcdc type
 164   */
 165 typedef enum
 166 {
 167   DVP_PCDC_ALL                           = 0x00,
 168   DVP_PCDC_ONE_IN_TWO                    = 0x01,
 169   DVP_PCDC_ONE_IN_FOUR                   = 0x02,
 170   DVP_PCDC_TWO_IN_FOUR                   = 0x03
 171 } dvp_pcdc_type;
 172
 173 /**
 174   * @brief dvp pcds type
 175   */
 176 typedef enum
 177 {
 178   DVP_PCDS_CAP_FIRST                     = 0x00,
 179   DVP_PCDS_DROP_FIRST                    = 0x01
 180 } dvp_pcds_type;
 181
 182 /**
 183   * @brief dvp lcdc type
 184   */
 185 typedef enum
 186 {
 187   DVP_LCDC_ALL                           = 0x00,
 188   DVP_LCDC_ONE_IN_TWO                    = 0x01
 189 } dvp_lcdc_type;
 190
 191 /**
 192   * @brief dvp lcds type
 193   */
 194 typedef enum
 195 {
 196   DVP_LCDS_CAP_FIRST                     = 0x00,
 197   DVP_LCDS_DROP_FIRST                    = 0x01
 198 } dvp_lcds_type;
 199
 200 /**
 201   * @brief dvp status basic type
 202   */
 203 typedef enum
 204 {
 205   DVP_STATUS_HSYN                        = 0x00,
 206   DVP_STATUS_VSYN                        = 0x01,
 207   DVP_STATUS_OFNE                        = 0x02
 208 } dvp_status_basic_type;
 209
 210 /**
 211   * @brief dvp pcdes type
 212   */
 213 typedef enum
 214 {
 215   DVP_PCDES_CAP_FIRST                    = 0x00,
 216   DVP_PCDES_DROP_FIRST                   = 0x01
 217 } dvp_pcdes_type;
 218
 219 /**
 220   * @brief dvp efdf type
 221   */
 222 typedef enum
 223 {
 224   DVP_EFDF_BYPASS                        = 0x00,
 225   DVP_EFDF_YUV422_UYVY                   = 0x04,
 226   DVP_EFDF_YUV422_YUYV                   = 0x05,
 227   DVP_EFDF_RGB565_555                    = 0x06,
 228   DVP_EFDF_Y8                            = 0x07
 229 } dvp_efdf_type;
 230
 231 /**
 232   * @brief dvp idus type
 233   */
 234 typedef enum
 235 {
 236   DVP_IDUS_MSB                           = 0x00,
 237   DVP_IDUS_LSB                           = 0x01
 238 } dvp_idus_type;
 239
 240 /**
 241   * @brief dvp dmabt type
 242   */
 243 typedef enum
 244 {
 245   DVP_DMABT_SINGLE                       = 0x00,
 246   DVP_DMABT_BURST                        = 0x01
 247 } dvp_dmabt_type;
 248
 249 /**
 250   * @brief dvp hseid type
 251   */
 252 typedef enum
 253 {
 254   DVP_HSEID_LINE_END                     = 0x00,
 255   DVP_HSEID_LINE_START                   = 0x01
 256 } dvp_hseid_type;
 257
 258 /**
 259   * @brief dvp vseid type
 260   */
 261 typedef enum
 262 {
 263   DVP_VSEID_FRAME_END                    = 0x00,
 264   DVP_VSEID_FRMAE_START                  = 0x01
 265 } dvp_vseid_type;
 266 /**
 267   * @brief dvp idun type
 268   */
 269 typedef enum
 270 {
 271   DVP_IDUN_0                             = 0x00,
 272   DVP_IDUN_2                             = 0x01,
 273   DVP_IDUN_4                             = 0x02,
 274   DVP_IDUN_6                             = 0x03
 275 } dvp_idun_type;
 276
 277 typedef struct
 278 {
 279   /**
 280     * @brief dvp ctrl register, offset:0x00
 281     */
 282   union
 283   {
 284     __IO uint32_t ctrl;
 285     struct
 286     {
 287       __IO uint32_t cap                  : 1; /* [0] */
 288       __IO uint32_t cfm                  : 1; /* [1] */
 289       __IO uint32_t crp                  : 1; /* [2] */
 290       __IO uint32_t jpeg                 : 1; /* [3] */
 291       __IO uint32_t sm                   : 1; /* [4] */
 292       __IO uint32_t ckp                  : 1; /* [5] */
 293       __IO uint32_t hsp                  : 1; /* [6] */
 294       __IO uint32_t vsp                  : 1; /* [7] */
 295       __IO uint32_t bfrc                 : 2; /* [9:8] */
 296       __IO uint32_t pdl                  : 2; /* [11:10] */
 297       __IO uint32_t reserved1            : 2; /* [13:12] */
 298       __IO uint32_t ena                  : 1; /* [14] */
 299       __IO uint32_t reserved2            : 1; /* [15] */
 300       __IO uint32_t pcdc                 : 2; /* [17:16] */
 301       __IO uint32_t pcds                 : 1; /* [18] */
 302       __IO uint32_t lcdc                 : 1; /* [19] */
 303       __IO uint32_t lcds                 : 1; /* [20] */
 304       __IO uint32_t                      : 11;/* [31:21] */
 305     } ctrl_bit;
 306   };
 307
 308   /**
 309     * @brief dvp sts register, offset:0x04
 310     */
 311   union
 312   {
 313     __IO uint32_t sts;
 314     struct
 315     {
 316       __IO uint32_t hsyn                 : 1; /* [0] */
 317       __IO uint32_t vsyn                 : 1; /* [1] */
 318       __IO uint32_t ofne                 : 1; /* [2] */
 319       __IO uint32_t reserved1            : 29;/* [31:3] */
 320     } sts_bit;
 321   };
 322
 323   /**
 324     * @brief dvp ests register, offset:0x08
 325     */
 326   union
 327   {
 328     __IO uint32_t ests;
 329     struct
 330     {
 331       __IO uint32_t cfdes                : 1; /* [0] */
 332       __IO uint32_t ovres                : 1; /* [1] */
 333       __IO uint32_t esees                : 1; /* [2] */
 334       __IO uint32_t vses                 : 1; /* [3] */
 335       __IO uint32_t hses                 : 1; /* [4] */
 336       __IO uint32_t reserved1            : 27;/* [31:5] */
 337     } ests_bit;
 338   };
 339
 340   /**
 341     * @brief dvp ier register, offset:0x0C
 342     */
 343   union
 344   {
 345     __IO uint32_t ier;
 346     struct
 347     {
 348       __IO uint32_t cfdie                : 1; /* [0] */
 349       __IO uint32_t ovrie                : 1; /* [1] */
 350       __IO uint32_t eseie                : 1; /* [2] */
 351       __IO uint32_t vsie                 : 1; /* [3] */
 352       __IO uint32_t hsie                 : 1; /* [4] */
 353       __IO uint32_t reserved1            : 27;/* [31:5] */
 354     } ier_bit;
 355   };
 356
 357   /**
 358     * @brief dvp ists register, offset:0x10
 359     */
 360   union
 361   {
 362     __IO uint32_t ists;
 363     struct
 364     {
 365       __IO uint32_t cfdis                : 1; /* [0] */
 366       __IO uint32_t ovris                : 1; /* [1] */
 367       __IO uint32_t eseis                : 1; /* [2] */
 368       __IO uint32_t vsis                 : 1; /* [3] */
 369       __IO uint32_t hsis                 : 1; /* [4] */
 370       __IO uint32_t reserved1            : 27;/* [31:5] */
 371     } ists_bit;
 372   };
 373
 374   /**
 375     * @brief dvp iclr register, offset:0x14
 376     */
 377   union
 378   {
 379     __IO uint32_t iclr;
 380     struct
 381     {
 382       __IO uint32_t cfdic                : 1; /* [0] */
 383       __IO uint32_t ovric                : 1; /* [1] */
 384       __IO uint32_t eseic                : 1; /* [2] */
 385       __IO uint32_t vsic                 : 1; /* [3] */
 386       __IO uint32_t hsic                 : 1; /* [4] */
 387       __IO uint32_t reserved1            : 27;/* [31:5] */
 388     } iclr_bit;
 389   };
 390
 391   /**
 392     * @brief dvp scr register, offset:0x18
 393     */
 394   union
 395   {
 396     __IO uint32_t scr;
 397     struct
 398     {
 399       __IO uint32_t fmsc                 : 8; /* [7:0] */
 400       __IO uint32_t lnsc                 : 8; /* [15:8] */
 401       __IO uint32_t lnec                 : 8; /* [23:16] */
 402       __IO uint32_t fmec                 : 8; /* [31:24] */
 403     } scr_bit;
 404   };
 405
 406   /**
 407     * @brief dvp sur register, offset:0x1C
 408     */
 409   union
 410   {
 411     __IO uint32_t sur;
 412     struct
 413     {
 414       __IO uint32_t fmsu                 : 8; /* [7:0] */
 415       __IO uint32_t lnsu                 : 8; /* [15:8] */
 416       __IO uint32_t lneu                 : 8; /* [23:16] */
 417       __IO uint32_t fmeu                 : 8; /* [31:24] */
 418     } sur_bit;
 419   };
 420
 421   /**
 422     * @brief dvp cwst register, offset:0x20
 423     */
 424   union
 425   {
 426     __IO uint32_t cwst;
 427     struct
 428     {
 429       __IO uint32_t chstr                : 14;/* [13:0] */
 430       __IO uint32_t reserved1            : 2; /* [15:14] */
 431       __IO uint32_t cvstr                : 13;/* [28:16] */
 432       __IO uint32_t reserved2            : 3; /* [31:29] */
 433     } cwst_bit;
 434   };
 435
 436   /**
 437     * @brief dvp cwsz register, offset:0x24
 438     */
 439   union
 440   {
 441     __IO uint32_t cwsz;
 442     struct
 443     {
 444       __IO uint32_t chnum                : 14;/* [13:0] */
 445       __IO uint32_t reserved1            : 2; /* [15:14] */
 446       __IO uint32_t cvnum                : 14;/* [29:16] */
 447       __IO uint32_t reserved2            : 2; /* [31:30] */
 448     } cwsz_bit;
 449   };
 450
 451   /**
 452     * @brief dvp dt register, offset:0x28
 453     */
 454   union
 455   {
 456     __IO uint32_t dt;
 457     struct
 458     {
 459       __IO uint32_t dr0                  : 8; /* [7:0] */
 460       __IO uint32_t dr1                  : 8; /* [15:8] */
 461       __IO uint32_t dr2                  : 8; /* [23:16] */
 462       __IO uint32_t dr3                  : 8; /* [31:24] */
 463     } dt_bit;
 464   };
 465
 466   /**
 467     * @brief dvp reserved1 register, offset:0x2C-0x3C
 468     */
 469   __IO uint32_t reserved1[5];
 470
 471   /**
 472     * @brief dvp actrl register, offset:0x40
 473     */
 474   union
 475   {
 476     __IO uint32_t actrl;
 477     struct
 478     {
 479       __IO uint32_t eisre                : 1; /* [0] */
 480       __IO uint32_t efrce                : 1; /* [1] */
 481       __IO uint32_t mibe                 : 1; /* [2] */
 482       __IO uint32_t pcdes                : 1; /* [3] */
 483       __IO uint32_t efdf                 : 3; /* [6:4] */
 484       __IO uint32_t reserved1            : 1; /* [7] */
 485       __IO uint32_t idun                 : 2; /* [9:8] */
 486       __IO uint32_t idus                 : 1; /* [10] */
 487       __IO uint32_t reserved2            : 1; /* [11] */
 488       __IO uint32_t dmabt                : 1; /* [12] */
 489       __IO uint32_t reserved3            : 1; /* [13] */
 490       __IO uint32_t reserved4            : 1; /* [14] */
 491       __IO uint32_t reserved5            : 1; /* [15] */
 492       __IO uint32_t hseid                : 1; /* [16] */
 493       __IO uint32_t vseid                : 1; /* [17] */
 494       __IO uint32_t reserved6            : 1; /* [18] */
 495       __IO uint32_t reserved7            : 2; /* [20:19] */
 496       __IO uint32_t reserved8            : 11;/* [31:21] */
 497     } actrl_bit;
 498   };
 499
 500   /**
 501     * @brief dvp reserved2 register, offset:0x44
 502     */
 503   __IO uint32_t reserved2;
 504
 505   /**
 506     * @brief dvp hscf register, offset:0x48
 507     */
 508   union
 509   {
 510     __IO uint32_t hscf;
 511     struct
 512     {
 513       __IO uint32_t hsrss                : 13;/* [12:0] */
 514       __IO uint32_t reserved1            : 3; /* [15:13] */
 515       __IO uint32_t hsrts                : 13;/* [28:16] */
 516       __IO uint32_t reserved2            : 3; /* [31:29] */
 517     } hscf_bit;
 518   };
 519
 520   /**
 521     * @brief dvp vscf register, offset:0x4C
 522     */
 523   union
 524   {
 525     __IO uint32_t vscf;
 526     struct
 527     {
 528       __IO uint32_t vsrss                : 13;/* [12:0] */
 529       __IO uint32_t reserved1            : 3; /* [15:13] */
 530       __IO uint32_t vsrts                : 13;/* [28:16] */
 531       __IO uint32_t reserved2            : 3; /* [31:29] */
 532     } vscf_bit;
 533   };
 534
 535   /**
 536     * @brief dvp frf register, offset:0x50
 537     */
 538   union
 539   {
 540     __IO uint32_t frf;
 541     struct
 542     {
 543       __IO uint32_t efrcsf               : 5; /* [4:0] */
 544       __IO uint32_t reserved1            : 3; /* [7:5] */
 545       __IO uint32_t efrctf               : 5; /* [12:8] */
 546       __IO uint32_t reserved2            : 19;/* [31:13] */
 547     } frf_bit;
 548   };
 549
 550   /**
 551     * @brief dvp bth register, offset:0x54
 552     */
 553   union
 554   {
 555     __IO uint32_t bth;
 556     struct
 557     {
 558       __IO uint32_t mibthd               : 8; /* [7:0] */
 559       __IO uint32_t reserved1            : 24;/* [31:8] */
 560     } bth_bit;
 561   };
 562
 563 } dvp_type;
 564
 565 /**
 566   * @}
 567   */
 568
 569 #define DVP                              ((dvp_type *) DVP_BASE)
 570
 571 /** @defgroup DVP_exported_functions
 572   * @{
 573   */
 574
 575 void dvp_reset(void);
 576 void dvp_capture_enable(confirm_state new_state);
 577 void dvp_capture_enable(confirm_state new_state);
 578 void dvp_capture_mode_set(dvp_cfm_type cap_mode);
 579 void dvp_window_crop_enable(confirm_state new_state);
 580 void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes);
 581 void dvp_jpeg_enable(confirm_state new_state);
 582 void dvp_sync_mode_set(dvp_sm_type sync_mode);
 583 void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec);
 584 void dvp_sync_unmask_set(uint8_t fmsu, uint8_t fmeu, uint8_t lnsu, uint8_t lneu);
 585 void dvp_pclk_polarity_set(dvp_ckp_type eage);
 586 void dvp_hsync_polarity_set(dvp_hsp_type hsync_pol);
 587 void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol);
 588 void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc);
 589 void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl);
 590 void dvp_enable(confirm_state new_state);
 591 void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes);
 592 void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds);
 593 flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic);
 594 void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state);
 595 flag_status dvp_flag_get(uint32_t flag);
 596 void dvp_flag_clear(uint32_t flag);
 597 void dvp_enhanced_scaling_resize_enable(confirm_state new_state);
 598 void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h);
 599 void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state);
 600 void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state);
 601 void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf);
 602 void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun);
 603 void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt);
 604 void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid);
 605
 606 /**
 607   * @}
 608   */
 609
 610 /**
 611   * @}
 612   */
 613
 614 /**
 615   * @}
 616   */
 617
 618 #ifdef __cplusplus
 619 }
 620 #endif
 621
 622 #endif