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[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_emac.h
blob04d5df5899607e6647f66d82ebdf5d23d5274943
1 /**
2 **************************************************************************
3 * @file at32f435_437_emac.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 eth header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* Define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_EMAC_H
29 #define __AT32F435_437_EMAC_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup EMAC
44 * @{
45 */
46
47 #define PHY_TIMEOUT (0x000FFFFF) /*!< timeout for phy response */
48
49 /** @defgroup EMAC_smi_clock_border_definition
50 * @brief emac smi clock border
51 * @{
52 */
53
54 #define EMAC_HCLK_BORDER_20MHZ (20000000) /*!< hclk boarder of 20 mhz */
55 #define EMAC_HCLK_BORDER_35MHZ (35000000) /*!< hclk boarder of 35 mhz */
56 #define EMAC_HCLK_BORDER_60MHZ (60000000) /*!< hclk boarder of 60 mhz */
57 #define EMAC_HCLK_BORDER_100MHZ (100000000) /*!< hclk boarder of 100 mhz */
58 #define EMAC_HCLK_BORDER_150MHZ (150000000) /*!< hclk boarder of 150 mhz */
59 #define EMAC_HCLK_BORDER_250MHZ (250000000) /*!< hclk boarder of 250 mhz */
60 #define EMAC_HCLK_BORDER_288MHZ (288000000) /*!< hclk boarder of 288 mhz */
61
62 /**
63 * @}
64 */
65
66 /** @defgroup EMAC_interrupts_definition
67 * @brief emac interrupts
68 * @{
69 */
70
71 #define EMAC_PMT_FLAG ((uint32_t)0x00000008) /*!< interrupt bit of pmt */
72 #define EMAC_MMC_FLAG ((uint32_t)0x00000010) /*!< interrupt bit of mmc */
73 #define EMAC_MMCR_FLAG ((uint32_t)0x00000020) /*!< interrupt bit of mmcr */
74 #define EMAC_MMCT_FLAG ((uint32_t)0x00000040) /*!< interrupt bit of mmct */
75 #define EMAC_TST_FLAG ((uint32_t)0x00000200) /*!< interrupt bit of tst */
76
77 /**
78 * @}
79 */
80
81 /** @defgroup EMAC_mmc_flags_definition
82 * @brief emac mmc flags
83 * @{
84 */
85
86 #define MMC_RX_CRC_ERROR ((uint32_t)0x00000020) /*!< mmc error flag of rx crc */
87 #define MMC_RX_ALIGN_ERROR ((uint32_t)0x00000040) /*!< mmc error flag of rx alignment */
88 #define MMC_RX_GOOD_UNICAST ((uint32_t)0x00020000) /*!< mmc error flag of rx unicast good frames */
89 #define MMC_TX_SINGLE_COL ((uint32_t)0x00004000) /*!< mmc error flag of tx single collision */
90 #define MMC_TX_MULTIPLE_COL ((uint32_t)0x00008000) /*!< mmc error flag of tx multiple collision */
91 #define MMC_TX_GOOD_FRAMES ((uint32_t)0x00200000) /*!< mmc error flag of tx good frames */
92
93 /**
94 * @}
95 */
96
97 /** @defgroup EMAC_packet_definition
98 * @brief emac packet
99 * @{
100 */
101
102 #define EMAC_MAX_PACKET_LENGTH 1520 /*!< emac_header + emac_extra + emac_max_payload + emac_crc */
103 #define EMAC_HEADER 14 /*!< 6 byte dest addr, 6 byte src addr, 2 byte length/ept_type */
104 #define EMAC_CRC 4 /*!< ethernet crc */
105 #define EMAC_EXTRA 2 /*!< extra bytes in some cases */
106 #define VLAN_TAG 4 /*!< optional 802.1q vlan tag */
107 #define EMAC_MIN_PAYLOAD 46 /*!< minimum ethernet payload size */
108 #define EMAC_MAX_PAYLOAD 1500 /*!< maximum ethernet payload size */
109 #define JUMBO_FRAME_PAYLOAD 9000 /*!< jumbo frame payload size */
110 #define EMAC_DMARXDESC_FRAME_LENGTHSHIFT 16
111
112 /**
113 * @}
114 */
115
116 /** @defgroup EMAC_dma_descriptor_tdes0_definition
117 * @brief tdes0 definition
118 * @{
119 */
120
121 #define EMAC_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< own bit: descriptor is owned by dma engine */
122 #define EMAC_DMATXDESC_IC ((uint32_t)0x40000000) /*!< interrupt on completion */
123 #define EMAC_DMATXDESC_LS ((uint32_t)0x20000000) /*!< last segment */
124 #define EMAC_DMATXDESC_FS ((uint32_t)0x10000000) /*!< first segment */
125 #define EMAC_DMATXDESC_DC ((uint32_t)0x08000000) /*!< disable crc */
126 #define EMAC_DMATXDESC_DP ((uint32_t)0x04000000) /*!< disable padding */
127 #define EMAC_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< transmit time stamp enable */
128 #define EMAC_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< checksum insertion control: 4 cases */
129 #define EMAC_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< do nothing: checksum engine is bypassed */
130 #define EMAC_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< ipv4 header checksum insertion */
131 #define EMAC_DMATXDESC_CIC_TUI_SEG ((uint32_t)0x00800000) /*!< tcp/udp/icmp checksum insertion calculated over segment only */
132 #define EMAC_DMATXDESC_CIC_TUI_FULL ((uint32_t)0x00C00000) /*!< tcp/udp/icmp checksum insertion fully calculated */
133 #define EMAC_DMATXDESC_TER ((uint32_t)0x00200000) /*!< transmit end of ring */
134 #define EMAC_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< second address chained */
135 #define EMAC_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< tx time stamp status */
136 #define EMAC_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< ip header error */
137 #define EMAC_DMATXDESC_ES ((uint32_t)0x00008000) /*!< error summary: or of the following bits: ue || ED || EC || LCO || NC || LCA || FF || JT */
138 #define EMAC_DMATXDESC_JT ((uint32_t)0x00004000) /*!< jabber timeout */
139 #define EMAC_DMATXDESC_FF ((uint32_t)0x00002000) /*!< frame flushed: dma/mtl flushed the frame due to SW flush */
140 #define EMAC_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< payload checksum error */
141 #define EMAC_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< loss of carrier: carrier lost during tramsmission */
142 #define EMAC_DMATXDESC_NC ((uint32_t)0x00000400) /*!< no carrier: no carrier signal from the tranceiver */
143 #define EMAC_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< late collision: transmission aborted due to collision */
144 #define EMAC_DMATXDESC_EC ((uint32_t)0x00000100) /*!< excessive collision: transmission aborted after 16 collisions */
145 #define EMAC_DMATXDESC_VF ((uint32_t)0x00000080) /*!< vlan frame */
146 #define EMAC_DMATXDESC_CC ((uint32_t)0x00000078) /*!< collision count */
147 #define EMAC_DMATXDESC_ED ((uint32_t)0x00000004) /*!< excessive deferral */
148 #define EMAC_DMATXDESC_UF ((uint32_t)0x00000002) /*!< underflow error: late data arrival from the memory */
149 #define EMAC_DMATXDESC_DB ((uint32_t)0x00000001) /*!< deferred bit */
150
151 /**
152 * @}
153 */
154
155 /** @defgroup EMAC_dma_descriptor_tdes1_definition
156 * @brief tdes1 descriptor
157 * @{
158 */
159
160 #define EMAC_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< transmit buffer2 size */
161 #define EMAC_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< transmit buffer1 size */
162
163 /**
164 * @}
165 */
166
167 /** @defgroup EMAC_dma_descriptor_tdes2_definition
168 * @brief tdes2 descriptor
169 * @{
170 */
171
172 #define EMAC_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< buffer1 address pointer */
173
174 /**
175 * @}
176 */
177
178 /** @defgroup EMAC_dma_descriptor_tdes3_definition
179 * @brief tdes3 descriptor
180 * @{
181 */
182
183 #define EMAC_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< buffer2 address pointer */
184
185 /**
186 * @}
187 */
188
189 /** @defgroup EMAC_dma_descriptor_rdes0_definition
190 * @brief rdes0 descriptor
191 * @{
192 */
193
194 #define EMAC_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< own bit: descriptor is owned by dma engine */
195 #define EMAC_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< da filter fail for the rx frame */
196 #define EMAC_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< receive descriptor frame length */
197 #define EMAC_DMARXDESC_ES ((uint32_t)0x00008000) /*!< error summary: or of the following bits: de || OE || IPC || LC || RWT || RE || CE */
198 #define EMAC_DMARXDESC_DE ((uint32_t)0x00004000) /*!< desciptor error: no more descriptors for receive frame */
199 #define EMAC_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< sa filter fail for the received frame */
200 #define EMAC_DMARXDESC_LE ((uint32_t)0x00001000) /*!< frame size not matching with length field */
201 #define EMAC_DMARXDESC_OE ((uint32_t)0x00000800) /*!< overflow error: frame was damaged due to buffer overflow */
202 #define EMAC_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< vlan tag: received frame is a vlan frame */
203 #define EMAC_DMARXDESC_FS ((uint32_t)0x00000200) /*!< first descriptor of the frame */
204 #define EMAC_DMARXDESC_LS ((uint32_t)0x00000100) /*!< last descriptor of the frame */
205 #define EMAC_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< ipc checksum error: rx ipv4 header checksum error */
206 #define EMAC_DMARXDESC_LC ((uint32_t)0x00000040) /*!< late collision occurred during reception */
207 #define EMAC_DMARXDESC_FT ((uint32_t)0x00000020) /*!< frame ept_type - ethernet, otherwise 802.3 */
208 #define EMAC_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< receive watchdog timeout: watchdog timer expired during reception */
209 #define EMAC_DMARXDESC_RE ((uint32_t)0x00000008) /*!< receive error: error reported by mii interface */
210 #define EMAC_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< dribble bit error: frame contains non int multiple of 8 bits */
211 #define EMAC_DMARXDESC_CE ((uint32_t)0x00000002) /*!< crc error */
212 #define EMAC_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< rx mac address/payload checksum error: rx mac address matched/ Rx Payload Checksum Error */
213
214 /**
215 * @}
216 */
217
218 /** @defgroup EMAC_dma_descriptor_rdes1_definition
219 * @brief rdes1 descriptor
220 * @{
221 */
222
223 #define EMAC_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< disable interrupt on completion */
224 #define EMAC_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< receive buffer2 size */
225 #define EMAC_DMARXDESC_RER ((uint32_t)0x00008000) /*!< receive end of ring */
226 #define EMAC_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< second address chained */
227 #define EMAC_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< receive buffer1 size */
228
229 /**
230 * @}
231 */
232
233 /** @defgroup EMAC_dma_descriptor_rdes2_definition
234 * @brief rdes2 descriptor
235 * @{
236 */
237
238 #define EMAC_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< buffer1 address pointer */
239
240 /**
241 * @}
242 */
243
244 /** @defgroup EMAC_dma_descriptor_rdes3_definition
245 * @brief rdes3 descriptor
246 * @{
247 */
248
249 #define EMAC_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< buffer2 address pointer */
250
251 /**
252 * @}
253 */
254
255 /**
256 * @brief emac dma flag
257 */
258 #define EMAC_DMA_TI_FLAG ((uint32_t)0x00000001) /*!< emac dma transmit interrupt */
259 #define EMAC_DMA_TPS_FLAG ((uint32_t)0x00000002) /*!< emac dma transmit process stopped */
260 #define EMAC_DMA_TBU_FLAG ((uint32_t)0x00000004) /*!< emac dma transmit buffer unavailable */
261 #define EMAC_DMA_TJT_FLAG ((uint32_t)0x00000008) /*!< emac dma transmit jabber timeout */
262 #define EMAC_DMA_OVF_FLAG ((uint32_t)0x00000010) /*!< emac dma receive overflow */
263 #define EMAC_DMA_UNF_FLAG ((uint32_t)0x00000020) /*!< emac dma transmit underflow */
264 #define EMAC_DMA_RI_FLAG ((uint32_t)0x00000040) /*!< emac dma receive interrupt */
265 #define EMAC_DMA_RBU_FLAG ((uint32_t)0x00000080) /*!< emac dma receive buffer unavailable */
266 #define EMAC_DMA_RPS_FLAG ((uint32_t)0x00000100) /*!< emac dma receive process stopped */
267 #define EMAC_DMA_RWT_FLAG ((uint32_t)0x00000200) /*!< emac dma receive watchdog timeout */
268 #define EMAC_DMA_ETI_FLAG ((uint32_t)0x00000400) /*!< emac dma early transmit interrupt */
269 #define EMAC_DMA_FBEI_FLAG ((uint32_t)0x00002000) /*!< emac dma fatal bus error interrupt */
270 #define EMAC_DMA_ERI_FLAG ((uint32_t)0x00004000) /*!< emac dma early receive interrupt */
271 #define EMAC_DMA_AIS_FLAG ((uint32_t)0x00008000) /*!< emac dma abnormal interrupt summary */
272 #define EMAC_DMA_NIS_FLAG ((uint32_t)0x00010000) /*!< emac dma normal interrupt summary */
273
274 /** @defgroup EMAC_exported_types
275 * @{
276 */
277
278 /**
279 * @brief emac auto negotiation type
280 */
281 typedef enum
282 {
283 EMAC_AUTO_NEGOTIATION_OFF = 0x00, /*!< disable auto negotiation */
284 EMAC_AUTO_NEGOTIATION_ON = 0x01 /*!< enable auto negotiation */
285 } emac_auto_negotiation_type;
286
287 /**
288 * @brief emac back_off limit type
289 */
290 typedef enum
291 {
292 EMAC_BACKOFF_LIMIT_0 = 0x00, /*!< retransmission clock gap numbers betwenn n and 10 */
293 EMAC_BACKOFF_LIMIT_1 = 0x01, /*!< retransmission clock gap numbers betwenn n and 8 */
294 EMAC_BACKOFF_LIMIT_2 = 0x02, /*!< retransmission clock gap numbers betwenn n and 4 */
295 EMAC_BACKOFF_LIMIT_3 = 0x03 /*!< retransmission clock gap numbers betwenn n and 1 */
296 } emac_bol_type;
297
298 /**
299 * @brief emac duplex type
300 */
301 typedef enum
302 {
303 EMAC_HALF_DUPLEX = 0x00, /*!< half duplex */
304 EMAC_FULL_DUPLEX = 0x01 /*!< full duplex */
305 } emac_duplex_type;
306
307 /**
308 * @brief emac speed type
309 */
310 typedef enum
311 {
312 EMAC_SPEED_10MBPS = 0x00, /*!< 10 mbps */
313 EMAC_SPEED_100MBPS = 0x01 /*!< 100 mbps */
314 } emac_speed_type;
315
316 /**
317 * @brief emac interframe gap type
318 */
319 typedef enum
320 {
321 EMAC_INTERFRAME_GAP_96BIT = 0x00, /*!< 96-bit numbers between two frames */
322 EMAC_INTERFRAME_GAP_88BIT = 0x01, /*!< 88-bit numbers between two frames */
323 EMAC_INTERFRAME_GAP_80BIT = 0x02, /*!< 80-bit numbers between two frames */
324 EMAC_INTERFRAME_GAP_72BIT = 0x03, /*!< 72-bit numbers between two frames */
325 EMAC_INTERFRAME_GAP_64BIT = 0x04, /*!< 64-bit numbers between two frames */
326 EMAC_INTERFRAME_GAP_56BIT = 0x05, /*!< 56-bit numbers between two frames */
327 EMAC_INTERFRAME_GAP_48BIT = 0x06, /*!< 48-bit numbers between two frames */
328 EMAC_INTERFRAME_GAP_40BIT = 0x07 /*!< 40-bit numbers between two frames */
329 } emac_intergrame_gap_type;
330
331 /**
332 * @brief mdc clock range type
333 */
334 typedef enum
335 {
336 EMAC_CLOCK_RANGE_60_TO_100 = 0x00, /*!< mdc is hclk/42 */
337 EMAC_CLOCK_RANGE_100_TO_150 = 0x01, /*!< mdc is hclk/62 */
338 EMAC_CLOCK_RANGE_20_TO_35 = 0x02, /*!< mdc is hclk/16 */
339 EMAC_CLOCK_RANGE_35_TO_60 = 0x03, /*!< mdc is hclk/26 */
340 EMAC_CLOCK_RANGE_150_TO_250 = 0x04, /*!< mdc is hclk/102 */
341 EMAC_CLOCK_RANGE_250_TO_288 = 0x05 /*!< mdc is hclk/102 */
342 } emac_clock_range_type;
343
344 /**
345 * @brief emac control frames filter type
346 */
347 typedef enum
348 {
349 EMAC_CONTROL_FRAME_PASSING_NO = 0x00, /*!< don't pass any control frame to application */
350 EMAC_CONTROL_FRAME_PASSING_ALL = 0x02, /*!< pass all control frames to application */
351 EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03 /*!< only pass filtered control frames to application */
352 } emac_control_frames_filter_type;
353
354 /**
355 * @brief pause threshold type
356 */
357 typedef enum
358 {
359 EMAC_PAUSE_4_SLOT_TIME = 0x00, /*!< pause time is 4 slot time */
360 EMAC_PAUSE_28_SLOT_TIME = 0x01, /*!< pause time is 28 slot time */
361 EMAC_PAUSE_144_SLOT_TIME = 0x02, /*!< pause time is 144 slot time */
362 EMAC_PAUSE_256_SLOT_TIME = 0x03 /*!< pause time is 256 slot time */
363 } emac_pause_slot_threshold_type;
364
365 /**
366 * @brief interrupt mask type
367 */
368 typedef enum
369 {
370 EMAC_INTERRUPT_PMT_MASK = 0x00, /*!< mask pmt interrupt */
371 EMAC_INTERRUPT_TST_MASK = 0x01 /*!< mask tst interrupt */
372 } emac_interrupt_mask_type;
373
374 /**
375 * @brief mac address type
376 */
377 typedef enum
378 {
379 EMAC_ADDRESS_FILTER_1 = 0x01, /*!< mac address 1 filter */
380 EMAC_ADDRESS_FILTER_2 = 0x02, /*!< mac address 2 filter */
381 EMAC_ADDRESS_FILTER_3 = 0x03 /*!< mac address 3 filter */
382 } emac_address_type;
383
384 /**
385 * @brief address filter type
386 */
387 typedef enum
388 {
389 EMAC_DESTINATION_FILTER = 0x00, /*!< destination mac address filter */
390 EMAC_SOURCE_FILTER = 0x01 /*!< source mac address filter */
391 } emac_address_filter_type;
392
393 /**
394 * @brief address mask type
395 */
396 typedef enum
397 {
398 EMAC_ADDRESS_MASK_8L0 = 0x01, /*!< byte 0 of mac address low register */
399 EMAC_ADDRESS_MASK_15L8 = 0x02, /*!< byte 1 of mac address low register */
400 EMAC_ADDRESS_MASK_23L16 = 0x04, /*!< byte 2 of mac address low register */
401 EMAC_ADDRESS_MASK_31L24 = 0x08, /*!< byte 3 of mac address low register */
402 EMAC_ADDRESS_MASK_7H0 = 0x10, /*!< byte 0 of mac address high register */
403 EMAC_ADDRESS_MASK_15H8 = 0x20 /*!< byte 1 of mac address high register */
404 } emac_address_mask_type;
405
406 /**
407 * @brief rx tx priority ratio type
408 */
409 typedef enum
410 {
411 EMAC_DMA_1_RX_1_TX = 0x00, /*!< rx/tx ratio is 1:1 */
412 EMAC_DMA_2_RX_1_TX = 0x01, /*!< rx/tx ratio is 2:1 */
413 EMAC_DMA_3_RX_1_TX = 0x02, /*!< rx/tx ratio is 3:1 */
414 EMAC_DMA_4_RX_1_TX = 0x03 /*!< rx/tx ratio is 4:1 */
415 } emac_dma_rx_tx_ratio_type;
416
417 /**
418 * @brief programmable burst length
419 */
420 typedef enum
421 {
422 EMAC_DMA_PBL_1 = 0x01, /*!< maximum 1 time of beats to be transferred in one dma transaction */
423 EMAC_DMA_PBL_2 = 0x02, /*!< maximum 2 times of beats to be transferred in one dma transaction */
424 EMAC_DMA_PBL_4 = 0x04, /*!< maximum 4 times of beats to be transferred in one dma transaction */
425 EMAC_DMA_PBL_8 = 0x08, /*!< maximum 8 times of beats to be transferred in one dma transaction */
426 EMAC_DMA_PBL_16 = 0x10, /*!< maximum 16 times of beats to be transferred in one dma transaction */
427 EMAC_DMA_PBL_32 = 0x20 /*!< maximum 32 times of beats to be transferred in one dma transaction */
428 } emac_dma_pbl_type;
429
430 /**
431 * @brief dma tx rx type
432 */
433 typedef enum
434 {
435 EMAC_DMA_TRANSMIT = 0x00, /*!< transmit dma */
436 EMAC_DMA_RECEIVE = 0x01 /*!< receive dma */
437 } emac_dma_tx_rx_type;
438
439 /**
440 * @brief dma receive process status type
441 */
442 typedef enum
443 {
444 EMAC_DMA_RX_RESET_STOP_COMMAND = 0x00, /*!< receive reset or stop command */
445 EMAC_DMA_RX_FETCH_DESCRIPTOR = 0x01, /*!< rx dma is fetching descriptor */
446 EMAC_DMA_RX_WAITING_PACKET = 0x03, /*!< rx dma is waiting for packets */
447 EMAC_DMA_RX_DESCRIPTOR_UNAVAILABLE = 0x04, /*!< rx dma descriptor is unavailable */
448 EMAC_DMA_RX_CLOSE_DESCRIPTOR = 0x05, /*!< rx dma is closing descriptor */
449 EMAC_DMA_RX_FIFO_TO_HOST = 0x07 /*!< rx dma is transferring data from fifo to host */
450 } emac_dma_receive_process_status_type;
451
452 /**
453 * @brief dma transmit process status type
454 */
455 typedef enum
456 {
457 EMAC_DMA_TX_RESET_STOP_COMMAND = 0x00, /*!< receive reset or stop command */
458 EMAC_DMA_TX_FETCH_DESCRIPTOR = 0x01, /*!< tx dma is fetching descriptor */
459 EMAC_DMA_TX_WAITING_FOR_STATUS = 0x02, /*!< tx dma is waiting for status message */
460 EMAC_DMA_TX_HOST_TO_FIFO = 0x03, /*!< tx dma is reading data from host and forward data to fifo */
461 EMAC_DMA_TX_DESCRIPTOR_UNAVAILABLE = 0x06, /*!< tx dma is unavailable or fifo underflow */
462 EMAC_DMA_TX_CLOSE_DESCRIPTOR = 0x07 /*!< tx dma is closing descriptor */
463 } emac_dma_transmit_process_status_type;
464
465 /**
466 * @brief dma operations type
467 */
468 typedef enum
469 {
470 EMAC_DMA_OPS_START_STOP_RECEIVE = 0x00, /*!< start/stop receive */
471 EMAC_DMA_OPS_SECOND_FRAME = 0x01, /*!< operate on second frame */
472 EMAC_DMA_OPS_FORWARD_UNDERSIZED = 0x02, /*!< forward undersized good frames*/
473 EMAC_DMA_OPS_FORWARD_ERROR = 0x03, /*!< forward error frames */
474 EMAC_DMA_OPS_START_STOP_TRANSMIT = 0x04, /*!< start/stop transmission */
475 EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO = 0x05, /*!< flush transmit fifo */
476 EMAC_DMA_OPS_TRANSMIT_STORE_FORWARD = 0x06, /*!< transmit store and forward */
477 EMAC_DMA_OPS_RECEIVE_FLUSH_DISABLE = 0x07, /*!< disable flushing of received frames */
478 EMAC_DMA_OPS_RECEIVE_STORE_FORWARD = 0x08, /*!< receive store and forward */
479 EMAC_DMA_OPS_DROP_ERROR_DISABLE = 0x09 /*!< disbale dropping of tcp/ip checksum error frames */
480 } emac_dma_operations_type;
481
482 /**
483 * @brief receive threshold control type
484 */
485 typedef enum
486 {
487 EMAC_DMA_RX_THRESHOLD_64_BYTES = 0x00, /*!< receive starts when the frame size within the receiv fifo is larger than 64 bytes */
488 EMAC_DMA_RX_THRESHOLD_32_BYTES = 0x01, /*!< receive starts when the frame size within the receiv fifo is larger than 32 bytes */
489 EMAC_DMA_RX_THRESHOLD_96_BYTES = 0x02, /*!< receive starts when the frame size within the receiv fifo is larger than 96 bytes */
490 EMAC_DMA_RX_THRESHOLD_128_BYTES = 0x03 /*!< receive starts when the frame size within the receiv fifo is larger than 128 bytes */
491 } emac_dma_receive_threshold_type;
492
493 /**
494 * @brief transmit threshold control type
495 */
496 typedef enum
497 {
498 EMAC_DMA_TX_THRESHOLD_64_BYTES = 0x00, /*!< transmission starts when the frame size within the transmit FIFO is larger than 64 bytes */
499 EMAC_DMA_TX_THRESHOLD_128_BYTES = 0x01, /*!< transmission starts when the frame size within the transmit FIFO is larger than 128 bytes */
500 EMAC_DMA_TX_THRESHOLD_192_BYTES = 0x02, /*!< transmission starts when the frame size within the transmit FIFO is larger than 192 bytes */
501 EMAC_DMA_TX_THRESHOLD_256_BYTES = 0x03, /*!< transmission starts when the frame size within the transmit FIFO is larger than 256 bytes */
502 EMAC_DMA_TX_THRESHOLD_40_BYTES = 0x04, /*!< transmission starts when the frame size within the transmit FIFO is larger than 40 bytes */
503 EMAC_DMA_TX_THRESHOLD_32_BYTES = 0x05, /*!< transmission starts when the frame size within the transmit FIFO is larger than 32 bytes */
504 EMAC_DMA_TX_THRESHOLD_24_BYTES = 0x06, /*!< transmission starts when the frame size within the transmit FIFO is larger than 24 bytes */
505 EMAC_DMA_TX_THRESHOLD_16_BYTES = 0x07 /*!< transmission starts when the frame size within the transmit FIFO is larger than 16 bytes */
506 } emac_dma_transmit_threshold_type;
507
508 /**
509 * @brief dma interrupt type
510 */
511 typedef enum
512 {
513 EMAC_DMA_INTERRUPT_TX = 0x00, /*!< transmit interrupt */
514 EMAC_DMA_INTERRUPT_TX_STOP = 0x01, /*!< transmit process stopped interrupt */
515 EMAC_DMA_INTERRUPT_TX_UNAVAILABLE = 0x02, /*!< transmit buffer unavailable interrupt */
516 EMAC_DMA_INTERRUPT_TX_JABBER = 0x03, /*!< transmit jabber timeout interrupt */
517 EMAC_DMA_INTERRUPT_RX_OVERFLOW = 0x04, /*!< receive overflow interrupt */
518 EMAC_DMA_INTERRUPT_TX_UNDERFLOW = 0x05, /*!< transmit underflow interrupt */
519 EMAC_DMA_INTERRUPT_RX = 0x06, /*!< receive interrupt */
520 EMAC_DMA_INTERRUPT_RX_UNAVAILABLE = 0x07, /*!< receive buffer unavailable interrupt */
521 EMAC_DMA_INTERRUPT_RX_STOP = 0x08, /*!< receive process stopped interrupt */
522 EMAC_DMA_INTERRUPT_RX_TIMEOUT = 0x09, /*!< receive watchdog timeout interrupt */
523 EMAC_DMA_INTERRUPT_TX_EARLY = 0x0A, /*!< early transmit interrupt */
524 EMAC_DMA_INTERRUPT_FATAL_BUS_ERROR = 0x0B, /*!< fatal bus error interrupt */
525 EMAC_DMA_INTERRUPT_RX_EARLY = 0x0C, /*!< early receive interrupt */
526 EMAC_DMA_INTERRUPT_ABNORMAL_SUMMARY = 0x0D, /*!< abnormal interrupt summary */
527 EMAC_DMA_INTERRUPT_NORMAL_SUMMARY = 0x0E /*!< normal interrupt summary */
528 } emac_dma_interrupt_type;
529
530 /**
531 * @brief dma tansfer address type
532 */
533 typedef enum
534 {
535 EMAC_DMA_TX_DESCRIPTOR = 0x00, /*!< transmit descriptor address */
536 EMAC_DMA_RX_DESCRIPTOR = 0x01, /*!< receive descriptor address */
537 EMAC_DMA_TX_BUFFER = 0x02, /*!< transmit buffer address */
538 EMAC_DMA_RX_BUFFER = 0x03 /*!< receive buffer address */
539 } emac_dma_transfer_address_type;
540
541 /**
542 * @brief clock node type
543 */
544 typedef enum
545 {
546 EMAC_PTP_NORMAL_CLOCK = 0x00, /*!< normal clock node */
547 EMAC_PTP_BOUNDARY_CLOCK = 0x01, /*!< boundary clock node */
548 EMAC_PTP_END_TO_END_CLOCK = 0x02, /*!< end to end transparent clock node */
549 EMAC_PTP_PEER_TO_PEER_CLOCK = 0x03 /*!< peer to peer transparent clock node */
550 } emac_ptp_clock_node_type;
551
552 /**
553 * @brief time stamp status type
554 */
555 typedef enum
556 {
557 EMAC_PTP_SECOND_OVERFLOW = 0x00, /*!< time stamp second overflow */
558 EMAC_PTP_TARGET_TIME_REACH = 0x01 /*!< time stamp target time reached */
559 } emac_ptp_timestamp_status_type;
560
561 /**
562 * @brief pps control type
563 */
564 typedef enum
565 {
566 EMAC_PTP_PPS_1HZ = 0x00, /*!< pps frequency is 1 hz */
567 EMAC_PTP_PPS_2HZ = 0x01, /*!< pps frequency is 2 hz */
568 EMAC_PTP_PPS_4HZ = 0x02, /*!< pps frequency is 4 hz */
569 EMAC_PTP_PPS_8HZ = 0x03, /*!< pps frequency is 8 hz */
570 EMAC_PTP_PPS_16HZ = 0x04, /*!< pps frequency is 16 hz */
571 EMAC_PTP_PPS_32HZ = 0x05, /*!< pps frequency is 32 hz */
572 EMAC_PTP_PPS_64HZ = 0x06, /*!< pps frequency is 64 hz */
573 EMAC_PTP_PPS_128HZ = 0x07, /*!< pps frequency is 128 hz */
574 EMAC_PTP_PPS_256HZ = 0x08, /*!< pps frequency is 256 hz */
575 EMAC_PTP_PPS_512HZ = 0x09, /*!< pps frequency is 512 hz */
576 EMAC_PTP_PPS_1024HZ = 0x0A, /*!< pps frequency is 1024 hz */
577 EMAC_PTP_PPS_2048HZ = 0x0B, /*!< pps frequency is 2048 hz */
578 EMAC_PTP_PPS_4096HZ = 0x0C, /*!< pps frequency is 4096 hz */
579 EMAC_PTP_PPS_8192HZ = 0x0D, /*!< pps frequency is 8192 hz */
580 EMAC_PTP_PPS_16384HZ = 0x0E, /*!< pps frequency is 16384 hz */
581 EMAC_PTP_PPS_32768HZ = 0x0F /*!< pps frequency is 32768 hz */
582 } emac_ptp_pps_control_type;
583
584 /**
585 * @brief ethernet mac control config type
586 */
587 typedef struct
588 {
589 emac_auto_negotiation_type auto_nego; /*!< auto negotiatin enable */
590 confirm_state deferral_check; /*!< deferral check enable */
591 emac_bol_type back_off_limit; /*!< back-off limit setting */
592 confirm_state auto_pad_crc_strip; /*!< automtic pad/crc stripping enable */
593 confirm_state retry_disable; /*!< retry disable*/
594 confirm_state ipv4_checksum_offload; /*!< ipv4 checksum offload enable */
595 emac_duplex_type duplex_mode; /*!< duplex mode enable */
596 confirm_state loopback_mode; /*!< loopback mode enable */
597 confirm_state receive_own_disable; /*!< receive own disbale */
598 emac_speed_type fast_ethernet_speed; /*!< fast ethernet speed enable */
599 confirm_state carrier_sense_disable; /*!< carrier sense disable*/
600 emac_intergrame_gap_type interframe_gap; /*!< set interframe gap */
601 confirm_state jabber_disable; /*!< jabber disbale */
602 confirm_state watchdog_disable; /*!< watchdog disable */
603 } emac_control_config_type;
604
605 /**
606 * @brief ethernet mac dma config type
607 */
608 typedef struct
609 {
610 confirm_state aab_enable; /*!< address-aligned beats enable */
611 confirm_state usp_enable; /*!< separate PBL enable */
612 emac_dma_pbl_type rx_dma_pal; /*!< rx dma pbl */
613 confirm_state fb_enable; /*!< separate PBL enable */
614 emac_dma_pbl_type tx_dma_pal; /*!< tx dma pbl */
615 uint8_t desc_skip_length; /*!< descriptor skip length */
616 confirm_state da_enable; /*!< dma arbitration enable */
617 emac_dma_rx_tx_ratio_type priority_ratio; /*!< priority ratio */
618 confirm_state dt_disable; /*!< disable dropping of tcp/ip checksum error frames */
619 confirm_state rsf_enable; /*!< enable receiving store or forward */
620 confirm_state flush_rx_disable; /*!< disable flushing of received frames */
621 confirm_state tsf_enable; /*!< enable transmitting store or forward */
622 emac_dma_transmit_threshold_type tx_threshold; /*!< transmit threshold control */
623 confirm_state fef_enable; /*!< enable forward error frames */
624 confirm_state fugf_enable; /*!< enable forward undersized good frames */
625 emac_dma_receive_threshold_type rx_threshold; /*!< receive threshold control */
626 confirm_state osf_enable; /*!< enable operating on second frames */
627 } emac_dma_config_type;
628
629 /**
630 * @brief dma desciptors data structure definition
631 */
632 typedef struct {
633 uint32_t status; /*!< status */
634 uint32_t controlsize; /*!< control and buffer1, buffer2 lengths */
635 uint32_t buf1addr; /*!< buffer1 address pointer */
636 uint32_t buf2nextdescaddr; /*!< buffer2 or next descriptor address pointer */
637 } emac_dma_desc_type;
638
639 /**
640 * @brief type define emac mac register all
641 */
642 typedef struct
643 {
644 /**
645 * @brief emac mac ctrl register, offset:0x00
646 */
647 union
648 {
649 __IO uint32_t ctrl;
650 struct
651 {
652 __IO uint32_t reserved1 : 2; /* [0:1] */
653 __IO uint32_t re : 1; /* [2] */
654 __IO uint32_t te : 1; /* [3] */
655 __IO uint32_t dc : 1; /* [4] */
656 __IO uint32_t bl : 2; /* [5:6] */
657 __IO uint32_t acs : 1; /* [7] */
658 __IO uint32_t reserved2 : 1; /* [8] */
659 __IO uint32_t dr : 1; /* [9] */
660 __IO uint32_t ipc : 1; /* [10] */
661 __IO uint32_t dm : 1; /* [11] */
662 __IO uint32_t lm : 1; /* [12] */
663 __IO uint32_t dro : 1; /* [13] */
664 __IO uint32_t fes : 1; /* [14] */
665 __IO uint32_t reserved3 : 1; /* [15] */
666 __IO uint32_t dcs : 1; /* [16] */
667 __IO uint32_t ifg : 3; /* [17:19] */
668 __IO uint32_t reserved4 : 2; /* [20:21] */
669 __IO uint32_t jd : 1; /* [22] */
670 __IO uint32_t wd : 1; /* [23] */
671 __IO uint32_t reserved5 : 8; /* [24:31] */
672 } ctrl_bit;
673 };
674
675 /**
676 * @brief emac mac frmf register, offset:0x04
677 */
678 union
679 {
680 __IO uint32_t frmf;
681 struct
682 {
683 __IO uint32_t pr : 1; /* [0] */
684 __IO uint32_t huc : 1; /* [1] */
685 __IO uint32_t hmc : 1; /* [2] */
686 __IO uint32_t daif : 1; /* [3] */
687 __IO uint32_t pmc : 1; /* [4] */
688 __IO uint32_t dbf : 1; /* [5] */
689 __IO uint32_t pcf : 2; /* [6:7] */
690 __IO uint32_t saif : 1; /* [8] */
691 __IO uint32_t saf : 1; /* [9] */
692 __IO uint32_t hpf : 1; /* [10] */
693 __IO uint32_t reserved1 : 20;/* [11:30] */
694 __IO uint32_t ra : 1; /* [31] */
695 } frmf_bit;
696 };
697
698 /**
699 * @brief emac mac hth register, offset:0x08
700 */
701 union
702 {
703 __IO uint32_t hth;
704 struct
705 {
706 __IO uint32_t hth : 32; /* [0:31] */
707 } hth_bit;
708 };
709
710 /**
711 * @brief emac mac htl register, offset:0x0c
712 */
713 union
714 {
715 __IO uint32_t htl;
716 struct
717 {
718 __IO uint32_t htl : 32; /* [0:31] */
719 } htl_bit;
720 };
721
722 /**
723 * @brief emac mac miiaddr register, offset:0x10
724 */
725 union
726 {
727 __IO uint32_t miiaddr;
728 struct
729 {
730 __IO uint32_t mb : 1; /* [0] */
731 __IO uint32_t mw : 1; /* [1] */
732 __IO uint32_t cr : 4; /* [2:5] */
733 __IO uint32_t mii : 5; /* [6:10] */
734 __IO uint32_t pa : 5; /* [11:15] */
735 __IO uint32_t reserved1 : 16;/* [16:31] */
736 } miiaddr_bit;
737 };
738
739 /**
740 * @brief emac mac miidt register, offset:0x14
741 */
742 union
743 {
744 __IO uint32_t miidt;
745 struct
746 {
747 __IO uint32_t md : 16;/* [0:15] */
748 __IO uint32_t reserved1 : 16;/* [16:31] */
749 } miidt_bit;
750 };
751
752 /**
753 * @brief emac mac fctrl register, offset:0x18
754 */
755 union
756 {
757 __IO uint32_t fctrl;
758 struct
759 {
760 __IO uint32_t fcbbpa : 1; /* [0] */
761 __IO uint32_t etf : 1; /* [1] */
762 __IO uint32_t erf : 1; /* [2] */
763 __IO uint32_t dup : 1; /* [3] */
764 __IO uint32_t plt : 2; /* [4:5] */
765 __IO uint32_t reserved1 : 1; /* [6] */
766 __IO uint32_t dzqp : 1; /* [7] */
767 __IO uint32_t reserved2 : 8; /* [8:15] */
768 __IO uint32_t pt : 16;/* [16:31] */
769 } fctrl_bit;
770 };
771
772 /**
773 * @brief emac mac vlt register, offset:0x1C
774 */
775 union
776 {
777 __IO uint32_t vlt;
778 struct
779 {
780 __IO uint32_t vti : 16;/* [0:15] */
781 __IO uint32_t etv : 1; /* [16] */
782 __IO uint32_t reserved1 : 15;/* [17:31] */
783 } vlt_bit;
784 };
785
786 /**
787 * @brief emac mac reserved1 register, offset:0x20~0x24
788 */
789 __IO uint32_t reserved1[2];
790
791 /**
792 * @brief emac mac rwff register, offset:0x28
793 */
794 __IO uint32_t rwff;
795
796 /**
797 * @brief emac mac pmtctrlsts register, offset:0x2C
798 */
799 union
800 {
801 __IO uint32_t pmtctrlsts;
802 struct
803 {
804 __IO uint32_t pd : 1; /* [0] */
805 __IO uint32_t emp : 1; /* [1] */
806 __IO uint32_t erwf : 1; /* [2] */
807 __IO uint32_t reserved1 : 2; /* [3:4] */
808 __IO uint32_t rmp : 1; /* [5] */
809 __IO uint32_t rrwf : 1; /* [6] */
810 __IO uint32_t reserved2 : 2; /* [7:8] */
811 __IO uint32_t guc : 1; /* [9] */
812 __IO uint32_t reserved3 : 21;/* [10:30] */
813 __IO uint32_t rwffpr : 1; /* [31] */
814 } pmtctrlsts_bit;
815 };
816
817 /**
818 * @brief emac mac reserved2 register, offset:0x30~0x34
819 */
820 __IO uint32_t reserved2[2];
821
822 /**
823 * @brief emac mac ists register, offset:0x38
824 */
825 union
826 {
827 __IO uint32_t ists;
828 struct
829 {
830 __IO uint32_t reserved1 : 3; /* [0:2] */
831 __IO uint32_t pis : 1; /* [3] */
832 __IO uint32_t mis : 1; /* [4] */
833 __IO uint32_t mris : 1; /* [5] */
834 __IO uint32_t mtis : 1; /* [6] */
835 __IO uint32_t reserved2 : 2; /* [7:8] */
836 __IO uint32_t tis : 1; /* [9] */
837 __IO uint32_t reserved3 : 22;/* [10:31] */
838 } ists_bit;
839 };
840
841 /**
842 * @brief emac mac imr register, offset:0x3C
843 */
844 union
845 {
846 __IO uint32_t imr;
847 struct
848 {
849 __IO uint32_t reserved1 : 3; /* [0:2] */
850 __IO uint32_t pim : 1; /* [3] */
851 __IO uint32_t reserved2 : 5; /* [4:8] */
852 __IO uint32_t tim : 1; /* [9] */
853 __IO uint32_t reserved3 : 22;/* [10:31] */
854 } imr_bit;
855 };
856
857 /**
858 * @brief emac mac a0h register, offset:0x40
859 */
860 union
861 {
862 __IO uint32_t a0h;
863 struct
864 {
865 __IO uint32_t ma0h : 16;/* [0:15] */
866 __IO uint32_t reserved1 : 15;/* [16:30] */
867 __IO uint32_t ae : 1; /* [31] */
868 } a0h_bit;
869 };
870
871 /**
872 * @brief emac mac a0l register, offset:0x44
873 */
874 union
875 {
876 __IO uint32_t a0l;
877 struct
878 {
879 __IO uint32_t ma0l : 32;/* [0:31] */
880 } a0l_bit;
881 };
882
883 /**
884 * @brief emac mac a1h register, offset:0x48
885 */
886 union
887 {
888 __IO uint32_t a1h;
889 struct
890 {
891 __IO uint32_t ma1h : 16;/* [0:15] */
892 __IO uint32_t reserved1 : 8; /* [16:23] */
893 __IO uint32_t mbc : 6; /* [24:29] */
894 __IO uint32_t sa : 1; /* [30] */
895 __IO uint32_t ae : 1; /* [31] */
896 } a1h_bit;
897 };
898
899 /**
900 * @brief emac mac a1l register, offset:0x4C
901 */
902 union
903 {
904 __IO uint32_t a1l;
905 struct
906 {
907 __IO uint32_t ma1l : 32;/* [0:31] */
908 } a1l_bit;
909 };
910
911 /**
912 * @brief emac mac a2h register, offset:0x50
913 */
914 union
915 {
916 __IO uint32_t a2h;
917 struct
918 {
919 __IO uint32_t ma2h : 16;/* [0:15] */
920 __IO uint32_t reserved1 : 8; /* [16:23] */
921 __IO uint32_t mbc : 6; /* [24:29] */
922 __IO uint32_t sa : 1; /* [30] */
923 __IO uint32_t ae : 1; /* [31] */
924 } a2h_bit;
925 };
926
927 /**
928 * @brief emac mac a2l register, offset:0x54
929 */
930 union
931 {
932 __IO uint32_t a2l;
933 struct
934 {
935 __IO uint32_t ma2l : 32;/* [0:31] */
936 } a2l_bit;
937 };
938
939 /**
940 * @brief emac mac a3h register, offset:0x58
941 */
942 union
943 {
944 __IO uint32_t a3h;
945 struct
946 {
947 __IO uint32_t ma3h : 16;/* [0:15] */
948 __IO uint32_t reserved1 : 8; /* [16:23] */
949 __IO uint32_t mbc : 6; /* [24:29] */
950 __IO uint32_t sa : 1; /* [30] */
951 __IO uint32_t ae : 1; /* [31] */
952 } a3h_bit;
953 };
954
955 /**
956 * @brief emac mac a3l register, offset:0x5C
957 */
958 union
959 {
960 __IO uint32_t a3l;
961 struct
962 {
963 __IO uint32_t ma3l : 32;/* [0:31] */
964 } a3l_bit;
965 };
966 } emac_type;
967
968 /**
969 * @brief type define emac mmc register all
970 */
971 typedef struct
972 {
973 /**
974 * @brief emac mmc ctrl register, offset:0x0100
975 */
976 union
977 {
978 __IO uint32_t ctrl;
979 struct
980 {
981 __IO uint32_t rc : 1; /* [0] */
982 __IO uint32_t scr : 1; /* [1] */
983 __IO uint32_t rr : 1; /* [2] */
984 __IO uint32_t fmc : 1; /* [3] */
985 __IO uint32_t reserved1 : 28;/* [4:31] */
986 } ctrl_bit;
987 };
988
989 /**
990 * @brief emac mmc ri register, offset:0x0104
991 */
992 union
993 {
994 __IO uint32_t ri;
995 struct
996 {
997 __IO uint32_t reserved1 : 5; /* [0:4] */
998 __IO uint32_t rfce : 1; /* [5] */
999 __IO uint32_t rfae : 1; /* [6] */
1000 __IO uint32_t reserved2 : 10;/* [7:16] */
1001 __IO uint32_t rguf : 1; /* [17] */
1002 __IO uint32_t reserved3 : 14;/* [18:31] */
1003 } ri_bit;
1004 };
1005
1006 /**
1007 * @brief emac mmc ti register, offset:0x0108
1008 */
1009 union
1010 {
1011 __IO uint32_t ti;
1012 struct
1013 {
1014 __IO uint32_t reserved1 : 14;/* [0:13] */
1015 __IO uint32_t tscgfci : 1; /* [14] */
1016 __IO uint32_t tgfmsc : 1; /* [15] */
1017 __IO uint32_t reserved2 : 5; /* [16:20] */
1018 __IO uint32_t tgf : 1; /* [21] */
1019 __IO uint32_t reserved3 : 10;/* [22:31] */
1020 } ti_bit;
1021 };
1022
1023 /**
1024 * @brief emac mmc rim register, offset:0x010C
1025 */
1026 union
1027 {
1028 __IO uint32_t rim;
1029 struct
1030 {
1031 __IO uint32_t reserved1 : 5; /* [0:4] */
1032 __IO uint32_t rcefcim : 1; /* [5] */
1033 __IO uint32_t raefacim : 1; /* [6] */
1034 __IO uint32_t reserved2 : 10;/* [7:16] */
1035 __IO uint32_t rugfcim : 1; /* [17] */
1036 __IO uint32_t reserved3 : 14;/* [18:31] */
1037 } rim_bit;
1038 };
1039
1040 /**
1041 * @brief emac mmc tim register, offset:0x0110
1042 */
1043 union
1044 {
1045 __IO uint32_t tim;
1046 struct
1047 {
1048 __IO uint32_t reserved1 : 14;/* [0:13] */
1049 __IO uint32_t tscgfcim : 1; /* [14] */
1050 __IO uint32_t tmcgfcim : 1; /* [15] */
1051 __IO uint32_t reserved2 : 5; /* [16:20] */
1052 __IO uint32_t tgfcim : 1; /* [21] */
1053 __IO uint32_t reserved3 : 10;/* [22:31] */
1054 } tim_bit;
1055 };
1056
1057 /**
1058 * @brief emac mmc reserved1 register, offset:0x0114~0x0148
1059 */
1060 __IO uint32_t reserved1[14];
1061
1062 /**
1063 * @brief emac mmc tfscc register, offset:0x014C
1064 */
1065 union
1066 {
1067 __IO uint32_t tfscc;
1068 struct
1069 {
1070 __IO uint32_t tgfscc : 32;/* [0:31] */
1071 } tfscc_bit;
1072 };
1073
1074 /**
1075 * @brief emac mmc tfmscc register, offset:0x0150
1076 */
1077 union
1078 {
1079 __IO uint32_t tfmscc;
1080 struct
1081 {
1082 __IO uint32_t tgfmscc : 32;/* [0:31] */
1083 } tfmscc_bit;
1084 };
1085
1086 /**
1087 * @brief emac mmc reserved2 register, offset:0x0154~0x0164
1088 */
1089 __IO uint32_t reserved2[5];
1090
1091 /**
1092 * @brief emac mmc tfcnt register, offset:0x0168
1093 */
1094 union
1095 {
1096 __IO uint32_t tfcnt;
1097 struct
1098 {
1099 __IO uint32_t tgfc : 32;/* [0:31] */
1100 } tfcnt_bit;
1101 };
1102
1103 /**
1104 * @brief emac mmc reserved3 register, offset:0x016C~0x0190
1105 */
1106 __IO uint32_t reserved3[10];
1107
1108 /**
1109 * @brief emac mmc rfcecnt register, offset:0x0194
1110 */
1111 union
1112 {
1113 __IO uint32_t rfcecnt;
1114 struct
1115 {
1116 __IO uint32_t rfcec : 32;/* [0:31] */
1117 } rfcecnt_bit;
1118 };
1119
1120 /**
1121 * @brief emac mmc rfaecnt register, offset:0x0198
1122 */
1123 union
1124 {
1125 __IO uint32_t rfaecnt;
1126 struct
1127 {
1128 __IO uint32_t rfaec : 32;/* [0:31] */
1129 } rfaecnt_bit;
1130 };
1131
1132 /**
1133 * @brief emac mmc reserved4 register, offset:0x019C~0x01C0
1134 */
1135 __IO uint32_t reserved4[10];
1136
1137 /**
1138 * @brief emac mmc rgufcnt register, offset:0x01C4
1139 */
1140 union
1141 {
1142 __IO uint32_t rgufcnt;
1143 struct
1144 {
1145 __IO uint32_t rgufc : 32;/* [0:31] */
1146 } rgufcnt_bit;
1147 };
1148 } emac_mmc_type;
1149
1150 /**
1151 * @brief type define emac ptp register all
1152 */
1153 typedef struct
1154 {
1155 /**
1156 * @brief emac ptp tsctrl register, offset:0x0700
1157 */
1158 union
1159 {
1160 __IO uint32_t tsctrl;
1161 struct
1162 {
1163 __IO uint32_t te : 1; /* [0] */
1164 __IO uint32_t tfcu : 1; /* [1] */
1165 __IO uint32_t ti : 1; /* [2] */
1166 __IO uint32_t tu : 1; /* [3] */
1167 __IO uint32_t tite : 1; /* [4] */
1168 __IO uint32_t aru : 1; /* [5] */
1169 __IO uint32_t reserved1 : 2; /* [6:7] */
1170 __IO uint32_t etaf : 1; /* [8] */
1171 __IO uint32_t tdbrc : 1; /* [9] */
1172 __IO uint32_t eppv2f : 1; /* [10] */
1173 __IO uint32_t eppef : 1; /* [11] */
1174 __IO uint32_t eppfsip6u : 1; /* [12] */
1175 __IO uint32_t eppfsip4u : 1; /* [13] */
1176 __IO uint32_t etsfem : 1; /* [14] */
1177 __IO uint32_t esfmrtm : 1; /* [15] */
1178 __IO uint32_t sppfts : 2; /* [16:17] */
1179 __IO uint32_t emafpff : 1; /* [18] */
1180 __IO uint32_t reserved2 : 13;/* [19:31] */
1181 } tsctrl_bit;
1182 };
1183
1184 /**
1185 * @brief emac ptp ssinc register, offset:0x0704
1186 */
1187 union
1188 {
1189 __IO uint32_t ssinc;
1190 struct
1191 {
1192 __IO uint32_t ssiv : 8; /* [0] */
1193 __IO uint32_t reserved1 : 24;/* [8:31] */
1194 } ssinc_bit;
1195 };
1196
1197 /**
1198 * @brief emac ptp tsh register, offset:0x0708
1199 */
1200 union
1201 {
1202 __IO uint32_t tsh;
1203 struct
1204 {
1205 __IO uint32_t ts : 32;/* [0:31] */
1206 } tsh_bit;
1207 };
1208
1209 /**
1210 * @brief emac ptp tsl register, offset:0x070C
1211 */
1212 union
1213 {
1214 __IO uint32_t tsl;
1215 struct
1216 {
1217 __IO uint32_t tss : 31;/* [0:30] */
1218 __IO uint32_t ast : 1; /* [31] */
1219 } tsl_bit;
1220 };
1221
1222 /**
1223 * @brief emac ptp tshud register, offset:0x0710
1224 */
1225 union
1226 {
1227 __IO uint32_t tshud;
1228 struct
1229 {
1230 __IO uint32_t ts : 32;/* [0:31] */
1231 } tshud_bit;
1232 };
1233
1234 /**
1235 * @brief emac ptp tslud register, offset:0x0714
1236 */
1237 union
1238 {
1239 __IO uint32_t tslud;
1240 struct
1241 {
1242 __IO uint32_t tss : 31;/* [0:30] */
1243 __IO uint32_t ast : 1; /* [31] */
1244 } tslud_bit;
1245 };
1246
1247 /**
1248 * @brief emac ptp tsad register, offset:0x0718
1249 */
1250 union
1251 {
1252 __IO uint32_t tsad;
1253 struct
1254 {
1255 __IO uint32_t tar : 32;/* [0:31] */
1256 } tsad_bit;
1257 };
1258
1259 /**
1260 * @brief emac ptp tth register, offset:0x071C
1261 */
1262 union
1263 {
1264 __IO uint32_t tth;
1265 struct
1266 {
1267 __IO uint32_t ttsr : 32;/* [0:31] */
1268 } tth_bit;
1269 };
1270
1271 /**
1272 * @brief emac ptp ttl register, offset:0x0720
1273 */
1274 union
1275 {
1276 __IO uint32_t ttl;
1277 struct
1278 {
1279 __IO uint32_t ttlr : 32;/* [0:31] */
1280 } ttl_bit;
1281 };
1282
1283 /**
1284 * @brief emac ptp reserved register, offset:0x0724
1285 */
1286 __IO uint32_t reserved1;
1287
1288 /**
1289 * @brief emac ptp tssr register, offset:0x0728
1290 */
1291 union
1292 {
1293 __IO uint32_t tssr;
1294 struct
1295 {
1296 __IO uint32_t tso : 1; /* [0] */
1297 __IO uint32_t tttr : 1; /* [1] */
1298 __IO uint32_t reserved1 : 30;/* [2:31] */
1299 } tssr_bit;
1300 };
1301
1302 /**
1303 * @brief emac ptp ppscr register, offset:0x072C
1304 */
1305 union
1306 {
1307 __IO uint32_t ppscr;
1308 struct
1309 {
1310 __IO uint32_t pofc : 4; /* [0:3] */
1311 __IO uint32_t reserved1 : 28;/* [4:31] */
1312 } ppscr_bit;
1313 };
1314 } emac_ptp_type;
1315
1316 /**
1317 * @brief type define emac ptp register all
1318 */
1319 typedef struct
1320 {
1321 /**
1322 * @brief emac dma bm register, offset:0x1000
1323 */
1324 union
1325 {
1326 __IO uint32_t bm;
1327 struct
1328 {
1329 __IO uint32_t swr : 1; /* [0] */
1330 __IO uint32_t da : 1; /* [1] */
1331 __IO uint32_t dsl : 5; /* [2:6] */
1332 __IO uint32_t reserved1 : 1; /* [7] */
1333 __IO uint32_t pbl : 6; /* [8:13] */
1334 __IO uint32_t pr : 2; /* [14:15] */
1335 __IO uint32_t fb : 1; /* [16] */
1336 __IO uint32_t rdp : 6; /* [17:22] */
1337 __IO uint32_t usp : 1; /* [23] */
1338 __IO uint32_t pblx8 : 1; /* [24] */
1339 __IO uint32_t aab : 1; /* [25] */
1340 __IO uint32_t reserved2 : 6; /* [26:31] */
1341 } bm_bit;
1342 };
1343
1344 /**
1345 * @brief emac dma tpd register, offset:0x1004
1346 */
1347 union
1348 {
1349 __IO uint32_t tpd;
1350 struct
1351 {
1352 __IO uint32_t tpd : 32; /* [0:31] */
1353 } tpd_bit;
1354 };
1355
1356 /**
1357 * @brief emac dma rpd register, offset:0x1008
1358 */
1359 union
1360 {
1361 __IO uint32_t rpd;
1362 struct
1363 {
1364 __IO uint32_t rpd : 32; /* [0:31] */
1365 } rpd_bit;
1366 };
1367
1368 /**
1369 * @brief emac dma rdladdr register, offset:0x100c
1370 */
1371 union
1372 {
1373 __IO uint32_t rdladdr;
1374 struct
1375 {
1376 __IO uint32_t srl : 32; /* [0:31] */
1377 } rdladdr_bit;
1378 };
1379
1380 /**
1381 * @brief emac dma tdladdr register, offset:0x1010
1382 */
1383 union
1384 {
1385 __IO uint32_t tdladdr;
1386 struct
1387 {
1388 __IO uint32_t stl : 32; /* [0:31] */
1389 } tdladdr_bit;
1390 };
1391
1392 /**
1393 * @brief emac dma sts register, offset:0x1014
1394 */
1395 union
1396 {
1397 __IO uint32_t sts;
1398 struct
1399 {
1400 __IO uint32_t ti : 1; /* [0] */
1401 __IO uint32_t tps : 1; /* [1] */
1402 __IO uint32_t tbu : 1; /* [2] */
1403 __IO uint32_t tjt : 1; /* [3] */
1404 __IO uint32_t ovf : 1; /* [4] */
1405 __IO uint32_t unf : 1; /* [5] */
1406 __IO uint32_t ri : 1; /* [6] */
1407 __IO uint32_t rbu : 1; /* [7] */
1408 __IO uint32_t rps : 1; /* [8] */
1409 __IO uint32_t rwt : 1; /* [9] */
1410 __IO uint32_t eti : 1; /* [10] */
1411 __IO uint32_t reserved1 : 2; /* [11:12] */
1412 __IO uint32_t fbei : 1; /* [13] */
1413 __IO uint32_t eri : 1; /* [14] */
1414 __IO uint32_t ais : 1; /* [15] */
1415 __IO uint32_t nis : 1; /* [16] */
1416 __IO uint32_t rs : 3; /* [17:19] */
1417 __IO uint32_t ts : 3; /* [20:22] */
1418 __IO uint32_t eb : 3; /* [23:25] */
1419 __IO uint32_t reserved2 : 1; /* [26] */
1420 __IO uint32_t mmi : 1; /* [27] */
1421 __IO uint32_t mpi : 1; /* [28] */
1422 __IO uint32_t tti : 1; /* [29] */
1423 __IO uint32_t reserved3 : 2; /* [30:31] */
1424 } sts_bit;
1425 };
1426
1427 /**
1428 * @brief emac dma opm register, offset:0x1018
1429 */
1430 union
1431 {
1432 __IO uint32_t opm;
1433 struct
1434 {
1435 __IO uint32_t reserved1 : 1; /* [0] */
1436 __IO uint32_t ssr : 1; /* [1] */
1437 __IO uint32_t osf : 1; /* [2] */
1438 __IO uint32_t rtc : 2; /* [3:4] */
1439 __IO uint32_t reserved2 : 1; /* [5] */
1440 __IO uint32_t fugf : 1; /* [6] */
1441 __IO uint32_t fef : 1; /* [7] */
1442 __IO uint32_t reserved3 : 5; /* [8:12] */
1443 __IO uint32_t sstc : 1; /* [13] */
1444 __IO uint32_t ttc : 3; /* [14:16] */
1445 __IO uint32_t reserved4 : 3; /* [17:19] */
1446 __IO uint32_t ftf : 1; /* [20] */
1447 __IO uint32_t tsf : 1; /* [21] */
1448 __IO uint32_t reserved5 : 2; /* [22:23] */
1449 __IO uint32_t dfrf : 1; /* [24] */
1450 __IO uint32_t rsf : 1; /* [25] */
1451 __IO uint32_t dt : 1; /* [26] */
1452 __IO uint32_t reserved6 : 5; /* [27:31] */
1453 } opm_bit;
1454 };
1455
1456 /**
1457 * @brief emac dma ie register, offset:0x101C
1458 */
1459 union
1460 {
1461 __IO uint32_t ie;
1462 struct
1463 {
1464 __IO uint32_t tie : 1; /* [0] */
1465 __IO uint32_t tse : 1; /* [1] */
1466 __IO uint32_t tue : 1; /* [2] */
1467 __IO uint32_t tje : 1; /* [3] */
1468 __IO uint32_t ove : 1; /* [4] */
1469 __IO uint32_t une : 1; /* [5] */
1470 __IO uint32_t rie : 1; /* [6] */
1471 __IO uint32_t rbue : 1; /* [7] */
1472 __IO uint32_t rse : 1; /* [8] */
1473 __IO uint32_t rwte : 1; /* [9] */
1474 __IO uint32_t eie : 1; /* [10] */
1475 __IO uint32_t reserved1 : 2; /* [11:12] */
1476 __IO uint32_t fbee : 1; /* [13] */
1477 __IO uint32_t ere : 1; /* [14] */
1478 __IO uint32_t aie : 1; /* [15] */
1479 __IO uint32_t nie : 1; /* [16] */
1480 __IO uint32_t reserved2 : 15;/* [17:31] */
1481 } ie_bit;
1482 };
1483
1484 /**
1485 * @brief emac dma mfbocnt register, offset:0x1020
1486 */
1487 union
1488 {
1489 __IO uint32_t mfbocnt;
1490 struct
1491 {
1492 __IO uint32_t mfc : 16;/* [0:15] */
1493 __IO uint32_t obmfc : 1; /* [16] */
1494 __IO uint32_t ofc : 11;/* [17:27] */
1495 __IO uint32_t obfoc : 1; /* [28] */
1496 __IO uint32_t reserved1 : 3; /* [29:31] */
1497 } mfbocnt_bit;
1498 };
1499
1500 /**
1501 * @brief emac dma reserved1 register, offset:0x1024~0x1044
1502 */
1503 __IO uint32_t reserved1[9];
1504
1505 /**
1506 * @brief emac ctd register, offset:0x1048
1507 */
1508 union
1509 {
1510 __IO uint32_t ctd;
1511 struct
1512 {
1513 __IO uint32_t htdap : 32;/* [0:31] */
1514 } ctd_bit;
1515 };
1516
1517 /**
1518 * @brief emac crd register, offset:0x104C
1519 */
1520 union
1521 {
1522 __IO uint32_t crd;
1523 struct
1524 {
1525 __IO uint32_t hrdap : 32;/* [0:31] */
1526 } crd_bit;
1527 };
1528
1529 /**
1530 * @brief emac ctbaddr register, offset:0x1050
1531 */
1532 union
1533 {
1534 __IO uint32_t ctbaddr;
1535 struct
1536 {
1537 __IO uint32_t htbap : 32;/* [0:31] */
1538 } ctbaddr_bit;
1539 };
1540
1541 /**
1542 * @brief emac crbaddr register, offset:0x1054
1543 */
1544 union
1545 {
1546 __IO uint32_t crbaddr;
1547 struct
1548 {
1549 __IO uint32_t hrbap : 32;/* [0:31] */
1550 } crbaddr_bit;
1551 };
1552 } emac_dma_type;
1553
1554 /**
1555 * @}
1556 */
1557
1558 #define EMAC ((emac_type *) EMAC_BASE)
1559 #define EMAC_MMC ((emac_mmc_type *) EMAC_MMC_BASE)
1560 #define EMAC_PTP ((emac_ptp_type *) EMAC_PTP_BASE)
1561 #define EMAC_DMA ((emac_dma_type *) EMAC_DMA_BASE)
1562
1563 /** @defgroup EMAC_exported_functions
1564 * @{
1565 */
1566
1567 void emac_reset(void);
1568 void emac_clock_range_set(void);
1569 void emac_dma_software_reset_set(void);
1570 flag_status emac_dma_software_reset_get(void);
1571 void emac_start(void);
1572 void emac_stop(void);
1573 error_status emac_phy_register_write(uint8_t address, uint8_t reg, uint16_t data);
1574 error_status emac_phy_register_read(uint8_t address, uint8_t reg, uint16_t *data);
1575 void emac_control_para_init(emac_control_config_type *control_para);
1576 void emac_control_config(emac_control_config_type *control_struct);
1577 void emac_receiver_enable(confirm_state new_state);
1578 void emac_trasmitter_enable(confirm_state new_state);
1579 void emac_deferral_check_set(confirm_state new_state);
1580 void emac_backoff_limit_set(emac_bol_type slot_time);
1581 void emac_auto_pad_crc_stripping_set(confirm_state new_state);
1582 void emac_retry_disable(confirm_state new_state);
1583 void emac_ipv4_checksum_offload_set(confirm_state new_state);
1584 void emac_loopback_mode_enable(confirm_state new_state);
1585 void emac_receive_own_disable(confirm_state new_state);
1586 void emac_carrier_sense_disable(confirm_state new_state);
1587 void emac_interframe_gap_set(emac_intergrame_gap_type number);
1588 void emac_jabber_disable(confirm_state new_state);
1589 void emac_watchdog_disable(confirm_state new_state);
1590 void emac_fast_speed_set(emac_speed_type speed);
1591 void emac_duplex_mode_set(emac_duplex_type duplex_mode);
1592 void emac_promiscuous_mode_set(confirm_state new_state);
1593 void emac_hash_unicast_set(confirm_state new_state);
1594 void emac_hash_multicast_set(confirm_state new_state);
1595 void emac_dstaddr_inverse_filter_set(confirm_state new_state);
1596 void emac_pass_all_multicasting_set(confirm_state new_state);
1597 void emac_broadcast_frames_disable(confirm_state new_state);
1598 void emac_pass_control_frames_set(emac_control_frames_filter_type condition);
1599 void emac_srcaddr_inverse_filter_set(confirm_state new_state);
1600 void emac_srcaddr_filter_set(confirm_state new_state);
1601 void emac_hash_perfect_filter_set(confirm_state new_state);
1602 void emac_receive_all_set(confirm_state new_state);
1603 void emac_hash_table_high32bits_set(uint32_t high32bits);
1604 void emac_hash_table_low32bits_set(uint32_t low32bits);
1605 flag_status emac_mii_busy_get(void);
1606 void emac_mii_write(confirm_state new_state);
1607 void emac_fcb_bpa_set(confirm_state new_state);
1608 void emac_transmit_flow_control_enable(confirm_state new_state);
1609 void emac_receive_flow_control_enable(confirm_state new_state);
1610 void emac_unicast_pause_frame_detect(confirm_state new_state);
1611 void emac_pause_low_threshold_set(emac_pause_slot_threshold_type pasue_threshold);
1612 void emac_zero_quanta_pause_disable(confirm_state new_state);
1613 void emac_pause_time_set(uint16_t pause_time);
1614 void emac_vlan_tag_identifier_set(uint16_t identifier);
1615 void emac_vlan_tag_comparison_set(confirm_state new_state);
1616 void emac_wakeup_frame_set(uint32_t value);
1617 uint32_t emac_wakeup_frame_get(void);
1618 void emac_power_down_set(confirm_state new_state);
1619 void emac_magic_packet_enable(confirm_state new_state);
1620 void emac_wakeup_frame_enable(confirm_state new_state);
1621 flag_status emac_received_magic_packet_get(void);
1622 flag_status emac_received_wakeup_frame_get(void);
1623 void emac_global_unicast_set(confirm_state new_state);
1624 void emac_wakeup_frame_filter_reset(confirm_state new_state);
1625 flag_status emac_interrupt_status_read(uint32_t flag);
1626 void emac_interrupt_mask_set(emac_interrupt_mask_type mask_type, confirm_state new_state);
1627 void emac_local_address_set(uint8_t *address);
1628 void emac_address_filter_set(emac_address_type mac, emac_address_filter_type filter, emac_address_mask_type mask_bit, confirm_state new_state);
1629 uint32_t emac_received_packet_size_get(void);
1630 uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc);
1631 void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count);
1632 uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type);
1633 void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state);
1634 void emac_dma_para_init(emac_dma_config_type *control_para);
1635 void emac_dma_config(emac_dma_config_type *control_para);
1636 void emac_dma_arbitation_set(emac_dma_rx_tx_ratio_type ratio, confirm_state new_state);
1637 void emac_dma_descriptor_skip_length_set(uint8_t length);
1638 void emac_dma_separate_pbl_set(emac_dma_pbl_type tx_length, emac_dma_pbl_type rx_length, confirm_state new_state);
1639 void emac_dma_eight_pbl_mode_set(confirm_state new_state);
1640 void emac_dma_address_aligned_beats_set(confirm_state new_state);
1641 void emac_dma_poll_demand_set(emac_dma_tx_rx_type transfer_type, uint32_t value);
1642 uint32_t emac_dma_poll_demand_get(emac_dma_tx_rx_type transfer_type);
1643 emac_dma_receive_process_status_type emac_dma_receive_status_get(void);
1644 emac_dma_transmit_process_status_type emac_dma_transmit_status_get(void);
1645 void emac_dma_operations_set(emac_dma_operations_type ops, confirm_state new_state);
1646 void emac_dma_receive_threshold_set(emac_dma_receive_threshold_type value);
1647 void emac_dma_transmit_threshold_set(emac_dma_transmit_threshold_type value);
1648 void emac_dma_interrupt_enable(emac_dma_interrupt_type it, confirm_state new_state);
1649 uint16_t emac_dma_controller_missing_frame_get(void);
1650 uint8_t emac_dma_missing_overflow_bit_get(void);
1651 uint16_t emac_dma_application_missing_frame_get(void);
1652 uint8_t emac_dma_fifo_overflow_bit_get(void);
1653 uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type);
1654 void emac_mmc_counter_reset(void);
1655 void emac_mmc_rollover_stop(confirm_state new_state);
1656 void emac_mmc_reset_on_read_enable(confirm_state new_state);
1657 void emac_mmc_counter_freeze(confirm_state new_state);
1658 flag_status emac_mmc_received_status_get(uint32_t flag);
1659 flag_status emac_mmc_transmit_status_get(uint32_t flag);
1660 void emac_mmc_received_interrupt_mask_set(uint32_t flag, confirm_state new_state);
1661 void emac_mmc_transmit_interrupt_mask_set(uint32_t flag, confirm_state new_state);
1662 uint32_t emac_mmc_transmit_good_frames_get(uint32_t flag);
1663 uint32_t emac_mmc_received_error_frames_get(uint32_t flag);
1664 void emac_ptp_timestamp_enable(confirm_state new_state);
1665 void emac_ptp_timestamp_fine_update_enable(confirm_state new_state);
1666 void emac_ptp_timestamp_system_time_init(confirm_state new_state);
1667 void emac_ptp_timestamp_system_time_update(confirm_state new_state);
1668 void emac_ptp_interrupt_trigger_enable(confirm_state new_state);
1669 void emac_ptp_addend_register_update(confirm_state new_state);
1670 void emac_ptp_snapshot_received_frames_enable(confirm_state new_state);
1671 void emac_ptp_subsecond_rollover_enable(confirm_state new_state);
1672 void emac_ptp_psv2_enable(confirm_state new_state);
1673 void emac_ptp_snapshot_emac_frames_enable(confirm_state new_state);
1674 void emac_ptp_snapshot_ipv6_frames_enable(confirm_state new_state);
1675 void emac_ptp_snapshot_ipv4_frames_enable(confirm_state new_state);
1676 void emac_ptp_snapshot_event_message_enable(confirm_state new_state);
1677 void emac_ptp_snapshot_master_event_enable(confirm_state new_state);
1678 void emac_ptp_clock_node_set(emac_ptp_clock_node_type node);
1679 void emac_ptp_mac_address_filter_enable(confirm_state new_state);
1680 void emac_ptp_subsecond_increment_set(uint8_t value);
1681 uint32_t emac_ptp_system_second_get(void);
1682 uint32_t emac_ptp_system_subsecond_get(void);
1683 confirm_state emac_ptp_system_time_sign_get(void);
1684 void emac_ptp_system_second_set(uint32_t second);
1685 void emac_ptp_system_subsecond_set(uint32_t subsecond);
1686 void emac_ptp_system_time_sign_set(confirm_state sign);
1687 void emac_ptp_timestamp_addend_set(uint32_t value);
1688 void emac_ptp_target_second_set(uint32_t value);
1689 void emac_ptp_target_nanosecond_set(uint32_t value);
1690 confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status);
1691 void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq);
1692 flag_status emac_dma_flag_get(uint32_t dma_flag);
1693 void emac_dma_flag_clear(uint32_t dma_flag);
1694
1695 /**
1696 * @}
1697 */
1698
1699 /**
1700 * @}
1701 */
1702
1703 /**
1704 * @}
1705 */
1706
1707 #ifdef __cplusplus
1708 }
1709 #endif
1710
1711 #endif
INAV: Navigation-enabled flight control software