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[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_qspi.h
blob6e3315eeaef128ab64755b994dfa8accc93b54c6
1 /**
2 **************************************************************************
3 * @file at32f435_437_qspi.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 qspi header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* Define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_QSPI_H
29 #define __AT32F435_437_QSPI_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup QSPI
44 * @{
45 */
46
47 /** @defgroup QSPI_flags_definition
48 * @brief qspi flag
49 * @{
50 */
51
52 #define QSPI_CMDSTS_FLAG ((uint32_t)0x00000001) /*!< qspi command complete status flag */
53 #define QSPI_RXFIFORDY_FLAG ((uint32_t)0x00000002) /*!< qspi rxfifo ready status flag */
54 #define QSPI_TXFIFORDY_FLAG ((uint32_t)0x00000004) /*!< qspi txfifo ready status flag */
55
56 /**
57 * @}
58 */
59
60 /** @defgroup QSPI_exported_types
61 * @{
62 */
63
64 /**
65 * @brief qspi xip read access mode type
66 */
67 typedef enum
68 {
69 QSPI_XIPR_SEL_MODED = 0x00, /*!< qspi xip read select mode d */
70 QSPI_XIPR_SEL_MODET = 0x01 /*!< qspi xip read select mode t */
71 } qspi_xip_read_sel_type;
72
73 /**
74 * @brief qspi xip write access mode type
75 */
76 typedef enum
77 {
78 QSPI_XIPW_SEL_MODED = 0x00, /*!< qspi xip write select mode d */
79 QSPI_XIPW_SEL_MODET = 0x01 /*!< qspi xip write select mode t */
80 } qspi_xip_write_sel_type;
81
82 /**
83 * @brief qspi busy bit offset position in status register type
84 */
85 typedef enum
86 {
87 QSPI_BUSY_OFFSET_0 = 0x00, /*!< qspi busy bit offset position 0 */
88 QSPI_BUSY_OFFSET_1 = 0x01, /*!< qspi busy bit offset position 1 */
89 QSPI_BUSY_OFFSET_2 = 0x02, /*!< qspi busy bit offset position 2 */
90 QSPI_BUSY_OFFSET_3 = 0x03, /*!< qspi busy bit offset position 3 */
91 QSPI_BUSY_OFFSET_4 = 0x04, /*!< qspi busy bit offset position 4 */
92 QSPI_BUSY_OFFSET_5 = 0x05, /*!< qspi busy bit offset position 5 */
93 QSPI_BUSY_OFFSET_6 = 0x06, /*!< qspi busy bit offset position 6 */
94 QSPI_BUSY_OFFSET_7 = 0x07 /*!< qspi busy bit offset position 7 */
95 } qspi_busy_pos_type;
96
97 /**
98 * @brief qspi read status configure type
99 */
100 typedef enum
101 {
102 QSPI_RSTSC_HW_AUTO = 0x00, /*!< qspi read status by hardware */
103 QSPI_RSTSC_SW_ONCE = 0x01 /*!< qspi read status by software */
104 } qspi_read_status_conf_type;
105
106 /**
107 * @brief qspi operate mode type
108 */
109 typedef enum
110 {
111 QSPI_OPERATE_MODE_111 = 0x00, /*!< qspi serial mode */
112 QSPI_OPERATE_MODE_112 = 0x01, /*!< qspi dual mode */
113 QSPI_OPERATE_MODE_114 = 0x02, /*!< qspi quad mode */
114 QSPI_OPERATE_MODE_122 = 0x03, /*!< qspi dual i/o mode */
115 QSPI_OPERATE_MODE_144 = 0x04, /*!< qspi quad i/o mode */
116 QSPI_OPERATE_MODE_222 = 0x05, /*!< qspi instruction 2-bit mode */
117 QSPI_OPERATE_MODE_444 = 0x06 /*!< qspi instruction 4-bit mode(qpi) */
118 } qspi_operate_mode_type;
119
120 /**
121 * @brief qspi clock division type
122 */
123 typedef enum
124 {
125 QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */
126 QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */
127 QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */
128 QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */
129 QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
130 QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
131 QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */
132 QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */
133 } qspi_clk_div_type;
134
135 /**
136 * @brief qspi command port address length type
137 */
138 typedef enum
139 {
140 QSPI_CMD_ADRLEN_0_BYTE = 0x00, /*!< qspi no address */
141 QSPI_CMD_ADRLEN_1_BYTE = 0x01, /*!< qspi address length 1 byte */
142 QSPI_CMD_ADRLEN_2_BYTE = 0x02, /*!< qspi address length 2 byte */
143 QSPI_CMD_ADRLEN_3_BYTE = 0x03, /*!< qspi address length 3 byte */
144 QSPI_CMD_ADRLEN_4_BYTE = 0x04 /*!< qspi address length 4 byte */
145 } qspi_cmd_adrlen_type;
146
147 /**
148 * @brief qspi command port instruction length type
149 */
150 typedef enum
151 {
152 QSPI_CMD_INSLEN_0_BYTE = 0x00, /*!< qspi no instruction code */
153 QSPI_CMD_INSLEN_1_BYTE = 0x01, /*!< qspi instruction code 1 byte */
154 QSPI_CMD_INSLEN_2_BYTE = 0x02 /*!< qspi instruction code 2 byte(repeat) */
155 } qspi_cmd_inslen_type;
156
157 /**
158 * @brief qspi xip r/w address length type
159 */
160 typedef enum
161 {
162 QSPI_XIP_ADDRLEN_3_BYTE = 0x00, /*!< qspi xip address length 3 byte */
163 QSPI_XIP_ADDRLEN_4_BYTE = 0x01 /*!< qspi xip address length 4 byte */
164 } qspi_xip_addrlen_type;
165
166 /**
167 * @brief qspi sckout mode type
168 */
169 typedef enum
170 {
171 QSPI_SCK_MODE_0 = 0x00, /*!< qspi sck mode 0 */
172 QSPI_SCK_MODE_3 = 0x01 /*!< qspi sck mode 3 */
173 } qspi_clk_mode_type;
174
175 /**
176 * @brief qspi dma tx/rx fifo threshold type
177 */
178 typedef enum
179 {
180 QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */
181 QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */
182 QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */
183 } qspi_dma_fifo_thod_type;
184
185 /**
186 * @brief qspi cmd type
187 */
188 typedef struct
189 {
190 confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */
191 uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */
192 uint8_t instruction_code; /*!< instruction code */
193 qspi_cmd_inslen_type instruction_length; /*!< instruction code length */
194 uint32_t address_code; /*!< address code */
195 qspi_cmd_adrlen_type address_length; /*!< address legnth */
196 uint32_t data_counter; /*!< read/write data counter */
197 uint8_t second_dummy_cycle_num; /*!< number of second dummy state cycle 0~32 */
198 qspi_operate_mode_type operation_mode; /*!< operation mode */
199 qspi_read_status_conf_type read_status_config; /*!< config to read status */
200 confirm_state read_status_enable; /*!< config to read status */
201 confirm_state write_data_enable; /*!< enable to write data */
202 } qspi_cmd_type;
203
204 /**
205 * @brief qspi xip type
206 */
207 typedef struct
208 {
209 uint8_t read_instruction_code; /*!< read instruction code */
210 qspi_xip_addrlen_type read_address_length; /*!< read address legnth */
211 qspi_operate_mode_type read_operation_mode; /*!< read operation mode */
212 uint8_t read_second_dummy_cycle_num; /*!< read number of second dummy state cycle 0~32 */
213 uint8_t write_instruction_code; /*!< write instruction code */
214 qspi_xip_addrlen_type write_address_length; /*!< write address legnth */
215 qspi_operate_mode_type write_operation_mode; /*!< write operation mode */
216 uint8_t write_second_dummy_cycle_num; /*!< write number of second dummy state cycle 0~32 */
217 qspi_xip_write_sel_type write_select_mode; /*!< write mode d or mode t selection */
218 uint8_t write_time_counter; /*!< write count for mode t */
219 uint8_t write_data_counter; /*!< write count for mode d */
220 qspi_xip_read_sel_type read_select_mode; /*!< read mode d or mode t selection */
221 uint8_t read_time_counter; /*!< read count for mode t */
222 uint8_t read_data_counter; /*!< read count for mode d */
223 } qspi_xip_type;
224
225 /**
226 * @brief type define qspi register all
227 */
228 typedef struct
229 {
230 /**
231 * @brief qspi cmd_w0 register, offset:0x00
232 */
233 union
234 {
235 __IO uint32_t cmd_w0;
236 struct
237 {
238
239 __IO uint32_t spiadr : 32;/* [31:0] */
240 } cmd_w0_bit;
241 };
242
243 /**
244 * @brief qspi cmd_w1 register, offset:0x04
245 */
246 union
247 {
248 __IO uint32_t cmd_w1;
249 struct
250 {
251 __IO uint32_t adrlen : 3; /* [2:0] */
252 __IO uint32_t reserved1 : 13;/* [15:3] */
253 __IO uint32_t dum2 : 8; /* [23:16] */
254 __IO uint32_t inslen : 2; /* [25:24] */
255 __IO uint32_t reserved2 : 2; /* [27:26] */
256 __IO uint32_t pemen : 1; /* [28] */
257 __IO uint32_t reserved3 : 3; /* [31:29] */
258 } cmd_w1_bit;
259 };
260
261 /**
262 * @brief qspi cmd_w2 register, offset:0x08
263 */
264 union
265 {
266 __IO uint32_t cmd_w2;
267 struct
268 {
269 __IO uint32_t dcnt : 32;/* [31:0] */
270 } cmd_w2_bit;
271 };
272
273 /**
274 * @brief qspi cmd_w3 register, offset:0x0C
275 */
276 union
277 {
278 __IO uint32_t cmd_w3;
279 struct
280 {
281 __IO uint32_t reserved1 : 1; /* [0] */
282 __IO uint32_t wen : 1; /* [1] */
283 __IO uint32_t rstsen : 1; /* [2] */
284 __IO uint32_t rstsc : 1; /* [3] */
285 __IO uint32_t reserved2 : 1; /* [4] */
286 __IO uint32_t opmode : 3; /* [7:5] */
287 __IO uint32_t reserved3 : 8; /* [15:8] */
288 __IO uint32_t pemopc : 8; /* [23:16] */
289 __IO uint32_t insc : 8; /* [31:24] */
290 } cmd_w3_bit;
291 };
292
293 /**
294 * @brief qspi ctrl register, offset:0x10
295 */
296 union
297 {
298 __IO uint32_t ctrl;
299 struct
300 {
301 __IO uint32_t clkdiv : 3; /* [2:0] */
302 __IO uint32_t reserved1 : 1; /* [3] */
303 __IO uint32_t sckmode : 1; /* [4] */
304 __IO uint32_t reserved2 : 2; /* [6:5] */
305 __IO uint32_t xipidle : 1; /* [7] */
306 __IO uint32_t abort : 1; /* [8] */
307 __IO uint32_t reserved3 : 7; /* [15:9] */
308 __IO uint32_t busy : 3; /* [18:16] */
309 __IO uint32_t xiprcmdf : 1; /* [19] */
310 __IO uint32_t xipsel : 1; /* [20] */
311 __IO uint32_t keyen : 1; /* [21] */
312 __IO uint32_t reserved4 : 10;/* [31:22] */
313 } ctrl_bit;
314 };
315
316 /**
317 * @brief qspi actr register, offset:0x14
318 */
319 union
320 {
321 __IO uint32_t actr;
322 struct
323 {
324 __IO uint32_t csdly : 4; /* [3:0] */
325 __IO uint32_t reserved1 : 28;/* [31:4] */
326 } actr_bit;
327 };
328
329 /**
330 * @brief qspi fifosts register, offset:0x18
331 */
332 union
333 {
334 __IO uint32_t fifosts;
335 struct
336 {
337 __IO uint32_t txfifordy : 1; /* [0] */
338 __IO uint32_t rxfifordy : 1; /* [1] */
339 __IO uint32_t reserved1 : 30;/* [31:2] */
340 } fifosts_bit;
341 };
342
343 /**
344 * @brief qspi reserved register, offset:0x1C
345 */
346 __IO uint32_t reserved1;
347
348 /**
349 * @brief qspi ctrl2 register, offset:0x20
350 */
351 union
352 {
353 __IO uint32_t ctrl2;
354 struct
355 {
356 __IO uint32_t dmaen : 1; /* [0] */
357 __IO uint32_t cmdie : 1; /* [1] */
358 __IO uint32_t reserved1 : 6; /* [7:2] */
359 __IO uint32_t txfifo_thod : 2; /* [9:8] */
360 __IO uint32_t reserved2 : 2; /* [11:10] */
361 __IO uint32_t rxfifo_thod : 2; /* [13:12] */
362 __IO uint32_t reserved3 : 18;/* [31:14] */
363 } ctrl2_bit;
364 };
365
366 /**
367 * @brief qspi cmdsts register, offset:0x24
368 */
369 union
370 {
371 __IO uint32_t cmdsts;
372 struct
373 {
374 __IO uint32_t cmdsts : 1; /* [0] */
375 __IO uint32_t reserved1 : 31;/* [31:1] */
376 } cmdsts_bit;
377 };
378
379 /**
380 * @brief qspi rsts register, offset:0x28
381 */
382 union
383 {
384 __IO uint32_t rsts;
385 struct
386 {
387 __IO uint32_t spists : 8; /* [7:0] */
388 __IO uint32_t reserved1 : 24;/* [31:8] */
389 } rsts_bit;
390 };
391
392 /**
393 * @brief qspi fsize register, offset:0x2C
394 */
395 union
396 {
397 __IO uint32_t fsize;
398 struct
399 {
400 __IO uint32_t spifsize : 32;/* [31:0] */
401 } fsize_bit;
402 };
403
404 /**
405 * @brief qspi xip_cmd_w0 register, offset:0x30
406 */
407 union
408 {
409 __IO uint32_t xip_cmd_w0;
410 struct
411 {
412 __IO uint32_t xipr_dum2 : 8; /* [7:0] */
413 __IO uint32_t xipr_opmode : 3; /* [10:8] */
414 __IO uint32_t xipr_adrlen : 1; /* [11] */
415 __IO uint32_t xipr_insc : 8; /* [19:12] */
416 __IO uint32_t reserved1 : 12;/* [31:20] */
417 } xip_cmd_w0_bit;
418 };
419
420 /**
421 * @brief qspi xip_cmd_w1 register, offset:0x34
422 */
423 union
424 {
425 __IO uint32_t xip_cmd_w1;
426 struct
427 {
428 __IO uint32_t xipr_dum2 : 8; /* [7:0] */
429 __IO uint32_t xipr_opmode : 3; /* [10:8] */
430 __IO uint32_t xipr_adrlen : 1; /* [11] */
431 __IO uint32_t xipr_insc : 8; /* [19:12] */
432 __IO uint32_t reserved1 : 12;/* [31:20] */
433 } xip_cmd_w1_bit;
434 };
435
436 /**
437 * @brief qspi xip_cmd_w2 register, offset:0x38
438 */
439 union
440 {
441 __IO uint32_t xip_cmd_w2;
442 struct
443 {
444 __IO uint32_t xipr_dcnt : 6; /* [5:0] */
445 __IO uint32_t reserved1 : 2; /* [7:6] */
446 __IO uint32_t xipr_tcnt : 7; /* [14:8] */
447 __IO uint32_t xipr_sel : 1; /* [15] */
448 __IO uint32_t xipw_dcnt : 6; /* [21:16] */
449 __IO uint32_t reserved2 : 2; /* [23:22] */
450 __IO uint32_t xipw_tcnt : 7; /* [30:24] */
451 __IO uint32_t xipw_sel : 1; /* [31] */
452 } xip_cmd_w2_bit;
453 };
454
455 /**
456 * @brief qspi xip_cmd_w3 register, offset:0x3C
457 */
458 union
459 {
460 __IO uint32_t xip_cmd_w3;
461 struct
462 {
463 __IO uint32_t bypassc : 1; /* [0] */
464 __IO uint32_t reserved1 : 2; /* [2:1] */
465 __IO uint32_t csts : 1; /* [3] */
466 __IO uint32_t reserved2 : 28;/* [31:4] */
467 } xip_cmd_w3_bit;
468 };
469
470 /**
471 * @brief qspi reserved register, offset:0x40~4C
472 */
473 __IO uint32_t reserved2[4];
474
475 /**
476 * @brief qspi rev register, offset:0x50
477 */
478 union
479 {
480 __IO uint32_t rev;
481 struct
482 {
483 __IO uint32_t rev : 32;/* [31:0] */
484 } rev_bit;
485 };
486
487 /**
488 * @brief qspi reserved register, offset:0x54~FC
489 */
490 __IO uint32_t reserved3[43];
491
492 /**
493 * @brief qspi dt register, offset:0x100
494 */
495 union
496 {
497 __IO uint8_t dt_u8;
498 __IO uint16_t dt_u16;
499 __IO uint32_t dt;
500 struct
501 {
502 __IO uint32_t dt : 32;/* [31:0] */
503 } dt_bit;
504 };
505
506 } qspi_type;
507
508 /**
509 * @}
510 */
511
512 #define QSPI1 ((qspi_type*)QSPI1_REG_BASE)
513 #define QSPI2 ((qspi_type*)QSPI2_REG_BASE)
514
515 /** @defgroup QSPI_exported_functions
516 * @{
517 */
518
519 void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
520 void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode);
521 void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
522 void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
523 void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
524 flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
525 void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag);
526 void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
527 void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
528 void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
529 void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos);
530 void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state);
531 void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct);
532 void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct);
533 uint8_t qspi_byte_read(qspi_type* qspi_x);
534 uint16_t qspi_half_word_read(qspi_type* qspi_x);
535 uint32_t qspi_word_read(qspi_type* qspi_x);
536 void qspi_word_write(qspi_type* qspi_x, uint32_t value);
537 void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
538 void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
539 /**
540 * @}
541 */
542
543 /**
544 * @}
545 */
546
547 /**
548 * @}
549 */
550
551 #ifdef __cplusplus
552 }
553 #endif
554
555 #endif
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