lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_usart.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_usart.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 usart header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_USART_H
  29 #define __AT32F435_437_USART_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39 /** @addtogroup AT32F435_437_periph_driver
  40   * @{
  41   */
  42
  43 /** @addtogroup USART
  44   * @{
  45   */
  46
  47 /** @defgroup USART_flags_definition
  48   * @brief usart flag
  49   * @{
  50   */
  51
  52 #define USART_PERR_FLAG                  ((uint32_t)0x00000001) /*!< usart parity error flag */
  53 #define USART_FERR_FLAG                  ((uint32_t)0x00000002) /*!< usart framing error flag */
  54 #define USART_NERR_FLAG                  ((uint32_t)0x00000004) /*!< usart noise error flag */
  55 #define USART_ROERR_FLAG                 ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
  56 #define USART_IDLEF_FLAG                 ((uint32_t)0x00000010) /*!< usart idle flag */
  57 #define USART_RDBF_FLAG                  ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
  58 #define USART_TDC_FLAG                   ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
  59 #define USART_TDBE_FLAG                  ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
  60 #define USART_BFF_FLAG                   ((uint32_t)0x00000100) /*!< usart break frame flag */
  61 #define USART_CTSCF_FLAG                 ((uint32_t)0x00000200) /*!< usart cts change flag */
  62
  63 /**
  64   * @}
  65   */
  66
  67 /** @defgroup USART_interrupts_definition
  68   * @brief usart interrupt
  69   * @{
  70   */
  71
  72 #define USART_IDLE_INT                   MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
  73 #define USART_RDBF_INT                   MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
  74 #define USART_TDC_INT                    MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
  75 #define USART_TDBE_INT                   MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
  76 #define USART_PERR_INT                   MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
  77 #define USART_BF_INT                     MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
  78 #define USART_ERR_INT                    MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
  79 #define USART_CTSCF_INT                  MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
  80
  81 /**
  82   * @}
  83   */
  84
  85 /** @defgroup USART_exported_types
  86   * @{
  87   */
  88
  89 /**
  90   * @brief  usart parity selection type
  91   */
  92 typedef enum
  93 {
  94   USART_PARITY_NONE                      = 0x00, /*!< usart no parity */
  95   USART_PARITY_EVEN                      = 0x01, /*!< usart even parity */
  96   USART_PARITY_ODD                       = 0x02  /*!< usart odd parity */
  97 } usart_parity_selection_type;
  98
  99 /**
 100   * @brief  usart wakeup mode type
 101   */
 102 typedef enum
 103 {
 104   USART_WAKEUP_BY_IDLE_FRAME             = 0x00, /*!< usart wakeup by idle frame */
 105   USART_WAKEUP_BY_MATCHING_ID            = 0x01  /*!< usart wakeup by matching id */
 106 } usart_wakeup_mode_type;
 107
 108 /**
 109   * @brief  usart data bit num type
 110   */
 111 typedef enum
 112 {
 113   USART_DATA_7BITS                       = 0x00, /*!< usart data size is 7 bits */
 114   USART_DATA_8BITS                       = 0x01, /*!< usart data size is 8 bits */
 115   USART_DATA_9BITS                       = 0x02  /*!< usart data size is 9 bits */
 116 } usart_data_bit_num_type;
 117
 118 /**
 119   * @brief  usart break frame bit num type
 120   */
 121 typedef enum
 122 {
 123   USART_BREAK_10BITS                     = 0x00, /*!< usart lin mode berak frame detection 10 bits */
 124   USART_BREAK_11BITS                     = 0x01  /*!< usart lin mode berak frame detection 11 bits */
 125 } usart_break_bit_num_type;
 126
 127 /**
 128   * @brief  usart phase of the clock type
 129   */
 130 typedef enum
 131 {
 132   USART_CLOCK_PHASE_1EDGE                = 0x00, /*!< usart data capture is done on the clock leading edge */
 133   USART_CLOCK_PHASE_2EDGE                = 0x01  /*!< usart data capture is done on the clock trailing edge */
 134 } usart_clock_phase_type;
 135
 136 /**
 137   * @brief  usart polarity of the clock type
 138   */
 139 typedef enum
 140 {
 141   USART_CLOCK_POLARITY_LOW               = 0x00, /*!< usart clock stay low level outside transmission window */
 142   USART_CLOCK_POLARITY_HIGH              = 0x01  /*!< usart clock stay high level outside transmission window */
 143 } usart_clock_polarity_type;
 144
 145 /**
 146   * @brief  usart last bit clock pulse type
 147   */
 148 typedef enum
 149 {
 150   USART_CLOCK_LAST_BIT_NONE              = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
 151   USART_CLOCK_LAST_BIT_OUTPUT            = 0x01  /*!< usart clock pulse of the last data bit is outputted */
 152 } usart_lbcp_type;
 153
 154 /**
 155   * @brief  usart stop bit num type
 156   */
 157 typedef enum
 158 {
 159   USART_STOP_1_BIT                       = 0x00, /*!< usart stop bits num is 1 */
 160   USART_STOP_0_5_BIT                     = 0x01, /*!< usart stop bits num is 0.5 */
 161   USART_STOP_2_BIT                       = 0x02, /*!< usart stop bits num is 2 */
 162   USART_STOP_1_5_BIT                     = 0x03  /*!< usart stop bits num is 1.5 */
 163 } usart_stop_bit_num_type;
 164
 165 /**
 166   * @brief  usart hardware flow control type
 167   */
 168 typedef enum
 169 {
 170   USART_HARDWARE_FLOW_NONE               = 0x00, /*!< usart without hardware flow */
 171   USART_HARDWARE_FLOW_RTS                = 0x01, /*!< usart hardware flow only rts */
 172   USART_HARDWARE_FLOW_CTS                = 0x02, /*!< usart hardware flow only cts */
 173   USART_HARDWARE_FLOW_RTS_CTS            = 0x03  /*!< usart hardware flow both rts and cts */
 174 } usart_hardware_flow_control_type;
 175
 176 /**
 177   * @brief  usart identification bit num type
 178   */
 179 typedef enum
 180 {
 181   USART_ID_FIXED_4_BIT                   = 0x00, /*!< usart id bit num fixed 4 bits */
 182   USART_ID_RELATED_DATA_BIT              = 0x01  /*!< usart id bit num related data bits */
 183 } usart_identification_bit_num_type;
 184
 185 /**
 186   * @brief  usart de polarity type
 187   */
 188 typedef enum
 189 {
 190   USART_DE_POLARITY_HIGH                 = 0x00, /*!< usart de polarity high */
 191   USART_DE_POLARITY_LOW                  = 0x01  /*!< usart de polarity low */
 192 } usart_de_polarity_type;
 193
 194 /**
 195   * @brief type define usart register all
 196   */
 197 typedef struct
 198 {
 199   /**
 200     * @brief usart sts register, offset:0x00
 201     */
 202   union
 203   {
 204     __IO uint32_t sts;
 205     struct
 206     {
 207       __IO uint32_t perr                 : 1; /* [0] */
 208       __IO uint32_t ferr                 : 1; /* [1] */
 209       __IO uint32_t nerr                 : 1; /* [2] */
 210       __IO uint32_t roerr                : 1; /* [3] */
 211       __IO uint32_t idlef                : 1; /* [4] */
 212       __IO uint32_t rdbf                 : 1; /* [5] */
 213       __IO uint32_t tdc                  : 1; /* [6] */
 214       __IO uint32_t tdbe                 : 1; /* [7] */
 215       __IO uint32_t bff                  : 1; /* [8] */
 216       __IO uint32_t ctscf                : 1; /* [9] */
 217       __IO uint32_t reserved1            : 22;/* [31:10] */
 218     } sts_bit;
 219   };
 220
 221   /**
 222     * @brief usart dt register, offset:0x04
 223     */
 224   union
 225   {
 226     __IO uint32_t dt;
 227     struct
 228     {
 229       __IO uint32_t dt                   : 9; /* [8:0] */
 230       __IO uint32_t reserved1            : 23;/* [31:9] */
 231     } dt_bit;
 232   };
 233
 234   /**
 235     * @brief usart baudr register, offset:0x08
 236     */
 237   union
 238   {
 239     __IO uint32_t baudr;
 240     struct
 241     {
 242       __IO uint32_t div                  : 16;/* [15:0] */
 243       __IO uint32_t reserved1            : 16;/* [31:16] */
 244     } baudr_bit;
 245   };
 246
 247   /**
 248     * @brief usart ctrl1 register, offset:0x0C
 249     */
 250   union
 251   {
 252     __IO uint32_t ctrl1;
 253     struct
 254     {
 255       __IO uint32_t sbf                  : 1; /* [0] */
 256       __IO uint32_t rm                   : 1; /* [1] */
 257       __IO uint32_t ren                  : 1; /* [2] */
 258       __IO uint32_t ten                  : 1; /* [3] */
 259       __IO uint32_t idleien              : 1; /* [4] */
 260       __IO uint32_t rdbfien              : 1; /* [5] */
 261       __IO uint32_t tdcien               : 1; /* [6] */
 262       __IO uint32_t tdbeien              : 1; /* [7] */
 263       __IO uint32_t perrien              : 1; /* [8] */
 264       __IO uint32_t psel                 : 1; /* [9] */
 265       __IO uint32_t pen                  : 1; /* [10] */
 266       __IO uint32_t wum                  : 1; /* [11] */
 267       __IO uint32_t dbn_l                : 1; /* [12] */
 268       __IO uint32_t uen                  : 1; /* [13] */
 269       __IO uint32_t reserved1            : 2; /* [15:14] */
 270       __IO uint32_t tcdt                 : 5; /* [20:16] */
 271       __IO uint32_t tsdt                 : 5; /* [25:21] */
 272       __IO uint32_t reserved2            : 2; /* [27:26] */
 273       __IO uint32_t dbn_h                : 1; /* [28] */
 274       __IO uint32_t reserved3            : 3; /* [31:29] */
 275     } ctrl1_bit;
 276   };
 277
 278   /**
 279     * @brief usart ctrl2 register, offset:0x10
 280     */
 281   union
 282   {
 283     __IO uint32_t ctrl2;
 284     struct
 285     {
 286       __IO uint32_t id_l                 : 4; /* [3:0] */
 287       __IO uint32_t idbn                 : 1; /* [4] */
 288       __IO uint32_t bfbn                 : 1; /* [5] */
 289       __IO uint32_t bfien                : 1; /* [6] */
 290       __IO uint32_t reserved1            : 1; /* [7] */
 291       __IO uint32_t lbcp                 : 1; /* [8] */
 292       __IO uint32_t clkpha               : 1; /* [9] */
 293       __IO uint32_t clkpol               : 1; /* [10] */
 294       __IO uint32_t clken                : 1; /* [11] */
 295       __IO uint32_t stopbn               : 2; /* [13:12] */
 296       __IO uint32_t linen                : 1; /* [14] */
 297       __IO uint32_t trpswap              : 1; /* [15] */
 298       __IO uint32_t reserved2            : 12;/* [27:16] */
 299       __IO uint32_t id_h                 : 4; /* [31:28] */
 300     } ctrl2_bit;
 301   };
 302
 303   /**
 304     * @brief usart ctrl3 register, offset:0x14
 305     */
 306   union
 307   {
 308     __IO uint32_t ctrl3;
 309     struct
 310     {
 311       __IO uint32_t errien               : 1; /* [0] */
 312       __IO uint32_t irdaen               : 1; /* [1] */
 313       __IO uint32_t irdalp               : 1; /* [2] */
 314       __IO uint32_t slben                : 1; /* [3] */
 315       __IO uint32_t scnacken             : 1; /* [4] */
 316       __IO uint32_t scmen                : 1; /* [5] */
 317       __IO uint32_t dmaren               : 1; /* [6] */
 318       __IO uint32_t dmaten               : 1; /* [7] */
 319       __IO uint32_t rtsen                : 1; /* [8] */
 320       __IO uint32_t ctsen                : 1; /* [9] */
 321       __IO uint32_t ctscfien             : 1; /* [10] */
 322       __IO uint32_t reserved1            : 3; /* [13:11] */
 323       __IO uint32_t rs485en              : 1; /* [14] */
 324       __IO uint32_t dep                  : 1; /* [15] */
 325       __IO uint32_t reserved2            : 16;/* [31:16] */
 326     } ctrl3_bit;
 327   };
 328
 329   /**
 330     * @brief usart gdiv register, offset:0x18
 331     */
 332   union
 333   {
 334     __IO uint32_t gdiv;
 335     struct
 336     {
 337       __IO uint32_t isdiv                : 8; /* [7:0] */
 338       __IO uint32_t scgt                 : 8; /* [15:8] */
 339       __IO uint32_t reserved1            : 16;/* [31:16] */
 340     } gdiv_bit;
 341   };
 342 } usart_type;
 343
 344 /**
 345   * @}
 346   */
 347
 348 #define USART1                           ((usart_type *) USART1_BASE)
 349 #define USART2                           ((usart_type *) USART2_BASE)
 350 #define USART3                           ((usart_type *) USART3_BASE)
 351 #define UART4                            ((usart_type *) UART4_BASE)
 352 #define UART5                            ((usart_type *) UART5_BASE)
 353 #define USART6                           ((usart_type *) USART6_BASE)
 354 #define UART7                            ((usart_type *) UART7_BASE)
 355 #define UART8                            ((usart_type *) UART8_BASE)
 356
 357 /** @defgroup USART_exported_functions
 358   * @{
 359   */
 360
 361 void usart_reset(usart_type* usart_x);
 362 void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
 363 void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
 364 void usart_enable(usart_type* usart_x, confirm_state new_state);
 365 void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
 366 void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
 367 void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
 368 void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
 369 void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
 370 void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
 371 void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
 372 void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
 373 void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
 374 void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
 375 void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
 376 void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
 377 void usart_data_transmit(usart_type* usart_x, uint16_t data);
 378 uint16_t usart_data_receive(usart_type* usart_x);
 379 void usart_break_send(usart_type* usart_x);
 380 void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
 381 void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
 382 void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
 383 void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
 384 void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
 385 void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
 386 void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
 387 void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
 388 flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
 389 void usart_flag_clear(usart_type* usart_x, uint32_t flag);
 390 void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
 391 void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
 392 void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
 393 void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
 394 void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
 395
 396 /**
 397   * @}
 398   */
 399
 400 /**
 401   * @}
 402   */
 403
 404 /**
 405   * @}
 406   */
 407
 408 #ifdef __cplusplus
 409 }
 410 #endif
 411
 412 #endif