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[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_usb.h
blobc6ab3b63991dfdf782759bb4a9fc09fd874e741e
1 /**
2 **************************************************************************
3 * @file at32f435_437_usb.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 usb header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* Define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_USB_H
29 #define __AT32F435_437_USB_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup USB
44 * @{
45 */
46
47 /** @defgroup USB_global_interrupts_definition
48 * @brief usb global interrupt mask
49 * @{
50 */
51
52 #define USB_OTG_MODEMIS_INT ((uint32_t)0x00000002) /*!< usb otg mode mismatch interrupt */
53 #define USB_OTG_OTGINT_INT ((uint32_t)0x00000004) /*!< usb otg interrupt */
54 #define USB_OTG_SOF_INT ((uint32_t)0x00000008) /*!< usb otg sof interrupt */
55 #define USB_OTG_RXFLVL_INT ((uint32_t)0x00000010) /*!< usb otg receive fifo non-empty interrupt */
56 #define USB_OTG_NPTXFEMP_INT ((uint32_t)0x00000020) /*!< usb otg non-periodic tx fifo empty interrupt */
57 #define USB_OTG_GINNAKEFF_INT ((uint32_t)0x00000040) /*!< usb otg global non-periodic in nak effective interrupt */
58 #define USB_OTG_GOUTNAKEFF_INT ((uint32_t)0x00000080) /*!< usb otg global out nak effective interrupt */
59 #define USB_OTG_ERLYSUSP_INT ((uint32_t)0x00000400) /*!< usb otg early suspend interrupt */
60 #define USB_OTG_USBSUSP_INT ((uint32_t)0x00000800) /*!< usb otg suspend interrupt */
61 #define USB_OTG_USBRST_INT ((uint32_t)0x00001000) /*!< usb otg reset interrupt */
62 #define USB_OTG_ENUMDONE_INT ((uint32_t)0x00002000) /*!< usb otg enumeration done interrupt */
63 #define USB_OTG_ISOOUTDROP_INT ((uint32_t)0x00004000) /*!< usb otg isochronous out packet dropped interrut */
64 #define USB_OTG_EOPF_INT ((uint32_t)0x00008000) /*!< usb otg eop interrupt */
65 #define USB_OTG_IEPT_INT ((uint32_t)0x00040000) /*!< usb otg in endpoint interrupt */
66 #define USB_OTG_OEPT_INT ((uint32_t)0x00080000) /*!< usb otg out endpoint interrupt */
67 #define USB_OTG_INCOMISOIN_INT ((uint32_t)0x00100000) /*!< usb otg incomplete isochronous in transfer interrupt */
68 #define USB_OTG_INCOMPIP_INCOMPISOOUT_INT ((uint32_t)0x00200000) /*!< usb otg incomplete periodic transfer/isochronous out interrupt */
69 #define USB_OTG_PRT_INT ((uint32_t)0x01000000) /*!< usb otg host port interrupt */
70 #define USB_OTG_HCH_INT ((uint32_t)0x02000000) /*!< usb otg host channel interrupt */
71 #define USB_OTG_PTXFEMP_INT ((uint32_t)0x04000000) /*!< usb otg periodic txfifo empty interrupt */
72 #define USB_OTG_CONIDSCHG_INT ((uint32_t)0x10000000) /*!< usb otg connector id status change interrupt */
73 #define USB_OTG_DISCON_INT ((uint32_t)0x20000000) /*!< usb otg disconnect detected interrupt */
74 #define USB_OTG_WKUP_INT ((uint32_t)0x80000000) /*!< usb otg wakeup interrupt */
75
76 /**
77 * @}
78 */
79
80 /** @defgroup USB_global_interrupt_flags_definition
81 * @brief usb global interrupt flag
82 * @{
83 */
84
85 #define USB_OTG_CURMODE ((uint32_t)0x00000001) /*!< usb otg current mode */
86 #define USB_OTG_MODEMIS_FLAG ((uint32_t)0x00000002) /*!< usb otg mode mismatch flag */
87 #define USB_OTG_OTGINT_FLAG ((uint32_t)0x00000004) /*!< usb otg flag */
88 #define USB_OTG_SOF_FLAG ((uint32_t)0x00000008) /*!< usb otg sof flag */
89 #define USB_OTG_RXFLVL_FLAG ((uint32_t)0x00000010) /*!< usb otg receive fifo non-empty flag */
90 #define USB_OTG_NPTXFEMP_FLAG ((uint32_t)0x00000020) /*!< usb otg non-periodic tx fifo empty flag */
91 #define USB_OTG_GINNAKEFF_FLAG ((uint32_t)0x00000040) /*!< usb otg global non-periodic in nak effective flag */
92 #define USB_OTG_GOUTNAKEFF_FLAG ((uint32_t)0x00000080) /*!< usb otg global out nak effective flag */
93 #define USB_OTG_ERLYSUSP_FLAG ((uint32_t)0x00000400) /*!< usb otg early suspend flag */
94 #define USB_OTG_USBSUSP_FLAG ((uint32_t)0x00000800) /*!< usb otg suspend flag */
95 #define USB_OTG_USBRST_FLAG ((uint32_t)0x00001000) /*!< usb otg reset flag */
96 #define USB_OTG_ENUMDONE_FLAG ((uint32_t)0x00002000) /*!< usb otg enumeration done flag */
97 #define USB_OTG_ISOOUTDROP_FLAG ((uint32_t)0x00004000) /*!< usb otg isochronous out packet dropped flag */
98 #define USB_OTG_EOPF_FLAG ((uint32_t)0x00008000) /*!< usb otg eop flag */
99 #define USB_OTG_IEPT_FLAG ((uint32_t)0x00040000) /*!< usb otg in endpoint flag */
100 #define USB_OTG_OEPT_FLAG ((uint32_t)0x00080000) /*!< usb otg out endpoint flag */
101 #define USB_OTG_INCOMISOIN_FLAG ((uint32_t)0x00100000) /*!< usb otg incomplete isochronous in transfer flag */
102 #define USB_OTG_INCOMPIP_INCOMPISOOUT_FLAG ((uint32_t)0x00200000) /*!< usb otg incomplete periodic transfer/isochronous out flag */
103 #define USB_OTG_PRT_FLAG ((uint32_t)0x01000000) /*!< usb otg host port flag */
104 #define USB_OTG_HCH_FLAG ((uint32_t)0x02000000) /*!< usb otg host channel flag */
105 #define USB_OTG_PTXFEMP_FLAG ((uint32_t)0x04000000) /*!< usb otg periodic txfifo empty flag */
106 #define USB_OTG_CONIDSCHG_FLAG ((uint32_t)0x10000000) /*!< usb otg connector id status change flag */
107 #define USB_OTG_DISCON_FLAG ((uint32_t)0x20000000) /*!< usb otg disconnect detected flag */
108 #define USB_OTG_WKUP_FLAG ((uint32_t)0x80000000) /*!< usb otg wakeup flag */
109
110 /**
111 * @}
112 */
113
114
115 /** @defgroup USB_global_setting_definition
116 * @brief usb global setting
117 * @{
118 */
119
120 /**
121 * @brief usb turnaround time
122 */
123 #define USB_TRDTIM_8 0x9 /*!< usb turn around time 8 */
124 #define USB_TRDTIM_16 0x5 /*!< usb turn around time 16 */
125
126 /**
127 * @brief usb receive status
128 */
129 #define USB_OTG_GRXSTSP_EPTNUM ((uint32_t)0x0000000F) /*!< usb device receive packet endpoint number*/
130 #define USB_OTG_GRXSTSP_CHNUM ((uint32_t)0x0000000F) /*!< usb host receive packet channel number*/
131 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< usb receive packet byte count */
132 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< usb receive packet pid */
133 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< usb receive packet status */
134
135 /**
136 * @brief usb host packet status
137 */
138 #define PKTSTS_IN_DATA_PACKET_RECV 0x2 /*!< usb host in data packet received */
139 #define PKTSTS_IN_TRANSFER_COMPLETE 0x3 /*!< usb host in transfer completed */
140 #define PKTSTS_DATA_BIT_ERROR 0x5 /*!< usb host data toggle error */
141 #define PKTSTS_CHANNEL_STOP 0x7 /*!< usb host channel halted */
142
143 /**
144 * @brief usb device packet status
145 */
146 #define USB_OUT_STS_NAK 0x1 /*!< usb device global out nak */
147 #define USB_OUT_STS_DATA 0x2 /*!< usb device out data packet received */
148 #define USB_OUT_STS_COMP 0x3 /*!< usb device out transfer completed */
149 #define USB_SETUP_STS_COMP 0x4 /*!< usb device setup transcation completed */
150 #define USB_SETUP_STS_DATA 0x6 /*!< usb device setup data packet received */
151
152 /**
153 * @}
154 */
155
156 /** @defgroup USB_host_config_definition
157 * @{
158 */
159
160 /**
161 * @brief usb host phy clock
162 */
163 #define USB_HCFG_CLK_60M 0 /*!< usb host phy clock 60mhz */
164 #define USB_HCFG_CLK_48M 1 /*!< usb host phy clock 48mhz */
165 #define USB_HCFG_CLK_6M 2 /*!< usb host phy clock 6mhz */
166
167 /**
168 * @brief usb host port status
169 */
170 #define USB_OTG_HPRT_PRTCONSTS ((uint32_t)0x00000001) /*!< usb host port connect status */
171 #define USB_OTG_HPRT_PRTCONDET ((uint32_t)0x00000002) /*!< usb host port connect detected */
172 #define USB_OTG_HPRT_PRTENA ((uint32_t)0x00000004) /*!< usb host port enable */
173 #define USB_OTG_HPRT_PRTENCHNG ((uint32_t)0x00000008) /*!< usb host port enable/disable change */
174 #define USB_OTG_HPRT_PRTOVRCACT ((uint32_t)0x00000010) /*!< usb host port overcurrent active */
175 #define USB_OTG_HPRT_PRTOVRCCHNG ((uint32_t)0x00000020) /*!< usb host port overcurrent change */
176 #define USB_OTG_HPRT_PRTRES ((uint32_t)0x00000040) /*!< usb host port resume */
177 #define USB_OTG_HPRT_PRTSUSP ((uint32_t)0x00000080) /*!< usb host port suspend */
178 #define USB_OTG_HPRT_PRTRST ((uint32_t)0x00000100) /*!< usb host port reset */
179 #define USB_OTG_HPRT_PRTLNSTS ((uint32_t)0x00000C00) /*!< usb host port line status */
180 #define USB_OTG_HPRT_PRTPWR ((uint32_t)0x00001000) /*!< usb host port power */
181 #define USB_OTG_HPRT_PRTSPD ((uint32_t)0x00060000) /*!< usb host port speed */
182
183 /**
184 * @brief usb port speed
185 */
186 #define USB_PRTSPD_HIGH_SPEED 0 /*!< usb host port high speed */
187 #define USB_PRTSPD_FULL_SPEED 1 /*!< usb host port full speed */
188 #define USB_PRTSPD_LOW_SPEED 2 /*!< usb host port low speed */
189
190 /**
191 * @brief usb host register hcchar bit define
192 */
193 #define USB_OTG_HCCHAR_MPS ((uint32_t)0x000007FF) /*!< channel maximum packet size */
194 #define USB_OTG_HCCHAR_EPTNUM ((uint32_t)0x00007800) /*!< endpoint number */
195 #define USB_OTG_HCCHAR_EPTDIR ((uint32_t)0x00008000) /*!< endpoint direction */
196 #define USB_OTG_HCCHAR_LSPDDEV ((uint32_t)0x00020000) /*!< low speed device */
197 #define USB_OTG_HCCHAR_EPTYPE ((uint32_t)0x000C0000) /*!< endpoint type */
198 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< multi count */
199 #define USB_OTG_HCCHAR_DEVADDR ((uint32_t)0x1FC00000) /*!< device address */
200 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< odd frame */
201 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< channel disable */
202 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< channel enable */
203
204 /**
205 * @brief usb host register hctsiz bit define
206 */
207 #define USB_OTG_HCTSIZ_XFERSIZE ((uint32_t)0x0007FFFF) /*!< channel transfer size */
208 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< channel packet count */
209 #define USB_OTG_HCTSIZ_PID ((uint32_t)0x60000000) /*!< channel pid */
210
211 /**
212 * @brief usb host channel interrupt mask
213 */
214 #define USB_OTG_HC_XFERCM_INT ((uint32_t)0x00000001) /*!< channel transfer complete interrupt */
215 #define USB_OTG_HC_CHHLTDM_INT ((uint32_t)0x00000002) /*!< channel halted interrupt */
216 #define USB_OTG_HC_STALLM_INT ((uint32_t)0x00000008) /*!< channel stall interrupt */
217 #define USB_OTG_HC_NAKM_INT ((uint32_t)0x00000010) /*!< channel nak interrupt */
218 #define USB_OTG_HC_ACKM_INT ((uint32_t)0x00000020) /*!< channel ack interrupt */
219 #define USB_OTG_HC_NYETM_INT ((uint32_t)0x00000040) /*!< channel nyet interrupt */
220 #define USB_OTG_HC_XACTERRM_INT ((uint32_t)0x00000080) /*!< channel transaction error interrupt */
221 #define USB_OTG_HC_BBLERRM_INT ((uint32_t)0x00000100) /*!< channel babble error interrupt */
222 #define USB_OTG_HC_FRMOVRRUN_INT ((uint32_t)0x00000200) /*!< channel frame overrun interrupt */
223 #define USB_OTG_HC_DTGLERRM_INT ((uint32_t)0x00000400) /*!< channel data toggle interrupt */
224
225 /**
226 * @brief usb host channel interrupt flag
227 */
228 #define USB_OTG_HC_XFERC_FLAG ((uint32_t)0x00000001) /*!< channel transfer complete flag */
229 #define USB_OTG_HC_CHHLTD_FLAG ((uint32_t)0x00000002) /*!< channel halted flag */
230 #define USB_OTG_HC_STALL_FLAG ((uint32_t)0x00000008) /*!< channel stall flag */
231 #define USB_OTG_HC_NAK_FLAG ((uint32_t)0x00000010) /*!< channel nak flag */
232 #define USB_OTG_HC_ACK_FLAG ((uint32_t)0x00000020) /*!< channel ack flag */
233 #define USB_OTG_HC_NYET_FLAG ((uint32_t)0x00000040) /*!< channel nyet flag */
234 #define USB_OTG_HC_XACTERR_FLAG ((uint32_t)0x00000080) /*!< channel transaction error flag */
235 #define USB_OTG_HC_BBLERR_FLAG ((uint32_t)0x00000100) /*!< channel babble error flag */
236 #define USB_OTG_HC_FRMOVRRUN_FLAG ((uint32_t)0x00000200) /*!< channel frame overrun flag */
237 #define USB_OTG_HC_DTGLERR_FLAG ((uint32_t)0x00000400) /*!< channel data toggle flag */
238
239 /**
240 * @}
241 */
242
243
244 /** @defgroup USB_device_config_definition
245 * @{
246 */
247 /**
248 * @brief usb device periodic frame interval
249 */
250 typedef enum
251 {
252 DCFG_PERFRINT_80 = 0x00, /*!< periodic frame interval 80% */
253 DCFG_PERFRINT_85 = 0x01, /*!< periodic frame interval 85% */
254 DCFG_PERFRINT_90 = 0x02, /*!< periodic frame interval 90% */
255 DCFG_PERFRINT_95 = 0x03 /*!< periodic frame interval 95% */
256 } dcfg_perfrint_type;
257
258
259 /**
260 * @brief usb device full speed
261 */
262 #define USB_DCFG_FULL_SPEED 3 /*!< device full speed */
263
264 /**
265 * @brief usb device ctrl define
266 */
267 #define USB_OTG_DCTL_RWKUPSIG ((uint32_t)0x00000001) /*!< usb device remote wakeup signaling */
268 #define USB_OTG_DCTL_SFTDISCON ((uint32_t)0x00000002) /*!< usb device soft disconnect */
269 #define USB_OTG_DCTL_GNPINNAKSTS ((uint32_t)0x00000004) /*!< usb device global non-periodic in nak status */
270 #define USB_OTG_DCTL_GOUTNAKSTS ((uint32_t)0x00000008) /*!< usb device global out nak status */
271 #define USB_OTG_DCTL_SGNPINNAK ((uint32_t)0x00000080) /*!< usb device set global non-periodic in nak */
272 #define USB_OTG_DCTL_CGNPINNAK ((uint32_t)0x00000100) /*!< usb device clear global non-periodic in nak */
273 #define USB_OTG_DCTL_SGOUTNAK ((uint32_t)0x00000200) /*!< usb device set global out nak status */
274 #define USB_OTG_DCTL_CGOUTNAK ((uint32_t)0x00000400) /*!< usb device clear global out nak status */
275 #define USB_OTG_DCTL_PWROPRGDNE ((uint32_t)0x00000800) /*!< usb device power on programming done */
276
277 /**
278 * @brief usb device in endpoint flag
279 */
280 #define USB_OTG_DIEPINT_XFERC_FLAG ((uint32_t)0x00000001) /*!< usb device in transfer completed flag */
281 #define USB_OTG_DIEPINT_EPTDISD_FLAG ((uint32_t)0x00000002) /*!< usb device endpoint disable flag */
282 #define USB_OTG_DIEPINT_TIMEOUT_FLAG ((uint32_t)0x00000008) /*!< usb device in timeout */
283 #define USB_OTG_DIEPINT_INTKNTXFEMP_FLAG ((uint32_t)0x00000010) /*!< usb device in token received when tx fifo is empty flag */
284 #define USB_OTG_DIEPINT_INEPTNAK_FLAG ((uint32_t)0x00000040) /*!< usb device in endpoint nak effective flag */
285 #define USB_OTG_DIEPINT_TXFEMP_FLAG ((uint32_t)0x00000080) /*!< usb device transmit fifo empty flag */
286
287 /**
288 * @brief usb device out endpoint flag
289 */
290 #define USB_OTG_DOEPINT_XFERC_FLAG ((uint32_t)0x00000001) /*!< usb device out transfer completed flag */
291 #define USB_OTG_DOEPINT_EPTDISD_FLAG ((uint32_t)0x00000002) /*!< usb device endpoint disable flag */
292 #define USB_OTG_DOEPINT_SETUP_FLAG ((uint32_t)0x00000008) /*!< usb device setup flag */
293 #define USB_OTG_DOEPINT_OUTTEPD_FLAG ((uint32_t)0x00000010) /*!< usb device out token recevied when endpoint disable flag */
294 #define USB_OTG_DOEPINT_B2BSTUP_FLAG ((uint32_t)0x00000040) /*!< back-to-back setup packets received */
295
296 /**
297 * @brief usb device in endpoint fifo space mask
298 */
299 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< usb device in endpoint tx fifo space avail */
300
301 /**
302 * @brief endpoint0 maximum packet size
303 */
304 #define USB_EPT0_MPS_64 0 /*!< usb device endpoint 0 maximum packet size 64byte */
305 #define USB_EPT0_MPS_32 1 /*!< usb device endpoint 0 maximum packet size 32byte */
306 #define USB_EPT0_MPS_16 2 /*!< usb device endpoint 0 maximum packet size 16byte */
307 #define USB_EPT0_MPS_8 3 /*!< usb device endpoint 0 maximum packet size 8byte */
308
309 /**
310 * @}
311 */
312
313 /**
314 * @brief otg fifo size (word)
315 */
316 #define OTG_FIFO_SIZE 320 /*!< otg usb total fifo size */
317
318 /**
319 * @brief otg host max buffer length (byte)
320 */
321 #define USB_MAX_DATA_LENGTH 0x200 /*!< usb host maximum buffer size */
322
323 #define OTGFS_USB_GLOBAL
324 #define OTGFS_USB_DEVICE
325 #define OTGFS_USB_HOST
326
327 /** @defgroup USB_exported_enum_types
328 * @{
329 */
330
331 /**
332 * @brief usb mode define(device, host, drd)
333 */
334 typedef enum
335 {
336 OTG_DEVICE_MODE, /*!< usb device mode */
337 OTG_HOST_MODE, /*!< usb host mode */
338 OTG_DRD_MODE /*!< usb drd mode */
339 } otg_mode_type;
340
341 /**
342 * @brief endpoint type define
343 */
344 typedef enum
345 {
346 EPT_CONTROL_TYPE = 0x00, /*!< usb endpoint type control */
347 EPT_ISO_TYPE = 0x01, /*!< usb endpoint type iso */
348 EPT_BULK_TYPE = 0x02, /*!< usb endpoint type bulk */
349 EPT_INT_TYPE = 0x03 /*!< usb endpoint type interrupt */
350 } endpoint_trans_type;
351
352 /**
353 * @brief usb endpoint number define type
354 */
355 typedef enum
356 {
357 USB_EPT0 = 0x00, /*!< usb endpoint 0 */
358 USB_EPT1 = 0x01, /*!< usb endpoint 1 */
359 USB_EPT2 = 0x02, /*!< usb endpoint 2 */
360 USB_EPT3 = 0x03, /*!< usb endpoint 3 */
361 USB_EPT4 = 0x04, /*!< usb endpoint 4 */
362 USB_EPT5 = 0x05, /*!< usb endpoint 5 */
363 USB_EPT6 = 0x06, /*!< usb endpoint 6 */
364 USB_EPT7 = 0x07 /*!< usb endpoint 7 */
365 } usb_endpoint_number_type;
366
367 /**
368 * @brief usb endpoint max num define
369 */
370 #ifndef USB_EPT_MAX_NUM
371 #define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */
372 #endif
373 /**
374 * @brief usb channel max num define
375 */
376 #ifndef USB_HOST_CHANNEL_NUM
377 #define USB_HOST_CHANNEL_NUM 16 /*!< usb host support channel number */
378 #endif
379
380 /**
381 * @brief endpoint trans dir type
382 */
383 typedef enum
384 {
385 EPT_DIR_IN = 0x00, /*!< usb transfer direction in */
386 EPT_DIR_OUT = 0x01 /*!< usb transfer direction out */
387 } endpoint_dir_type;
388
389 /**
390 * @brief otgfs1 and otgfs2 select type
391 */
392 typedef enum
393 {
394 USB_OTG1_ID, /*!< usb otg 1 id */
395 USB_OTG2_ID /*!< usb otg 2 id */
396 } otg_id_type;
397
398 /**
399 * @brief usb clock select
400 */
401 typedef enum
402 {
403 USB_CLK_HICK, /*!< usb clock use hick */
404 USB_CLK_HEXT /*!< usb clock use hext */
405 }usb_clk48_s;
406
407 /**
408 * @}
409 */
410
411
412
413 /** @defgroup USB_exported_types
414 * @{
415 */
416
417 /**
418 * @brief usb endpoint infomation structure definition
419 */
420 typedef struct
421 {
422 uint8_t eptn; /*!< endpoint register number (0~7) */
423 uint8_t ept_address; /*!< endpoint address */
424 uint8_t inout; /*!< endpoint dir EPT_DIR_IN or EPT_DIR_OUT */
425 uint8_t trans_type; /*!< endpoint type:
426 EPT_CONTROL_TYPE, EPT_BULK_TYPE, EPT_INT_TYPE, EPT_ISO_TYPE*/
427 uint16_t tx_addr; /*!< endpoint tx buffer offset address */
428 uint16_t rx_addr; /*!< endpoint rx buffer offset address */
429 uint32_t maxpacket; /*!< endpoint max packet*/
430 uint8_t is_double_buffer; /*!< endpoint double buffer flag */
431 uint8_t stall; /*!< endpoint is stall state */
432 uint32_t status;
433
434 /* transmission buffer and count */
435 uint8_t *trans_buf; /*!< endpoint transmission buffer */
436 uint32_t total_len; /*!< endpoint transmission lengtg */
437 uint32_t trans_len; /*!< endpoint transmission length*/
438
439 uint32_t last_len; /*!< last transfer length */
440 uint32_t rem0_len; /*!< rem transfer length */
441 uint32_t ept0_slen; /*!< endpoint 0 transfer sum length */
442 } usb_ept_info;
443
444
445 /**
446 * @brief usb host channel infomation structure definition
447 */
448 typedef struct
449 {
450 uint8_t ch_num; /*!< host channel number */
451 uint8_t address; /*!< device address */
452 uint8_t dir; /*!< transmission direction */
453 uint8_t ept_num; /*!< device endpoint number */
454 uint8_t ept_type; /*!< channel transmission type */
455 uint32_t maxpacket; /*!< support max packet size */
456 uint8_t data_pid; /*!< data pid */
457 uint8_t speed; /*!< usb speed */
458 uint8_t stall; /*!< channel stall flag */
459 uint32_t status; /*!< channel status */
460 uint32_t state; /*!< channel state */
461 uint32_t urb_sts; /*!< usb channel request block state */
462
463 uint8_t toggle_in; /*!< channel in transfer toggle */
464 uint8_t toggle_out; /*!< channel out transfer toggle */
465
466 /* transmission buffer and count */
467 uint8_t *trans_buf; /* host channel buffer */
468 uint32_t trans_len; /* host channel transmission len */
469 uint32_t trans_count; /* host channel transmission count*/
470 } usb_hch_type;
471
472
473 typedef struct
474 {
475 /**
476 * @brief otgfs control and status register, offset:0x00
477 */
478 union
479 {
480 __IO uint32_t gotgctrl;
481 struct
482 {
483 __IO uint32_t reserved1 : 16; /* [15:0] */
484 __IO uint32_t cidsts : 1; /* [16] */
485 __IO uint32_t reserved2 : 4; /* [20:17] */
486 __IO uint32_t curmod : 1; /* [21] */
487 __IO uint32_t reserved3 : 10; /* [31:22] */
488 } gotgctrl_bit;
489 };
490
491 /**
492 * @brief otgfs interrupt register, offset:0x04
493 */
494 union
495 {
496 __IO uint32_t gotgint;
497 struct
498 {
499 __IO uint32_t reserved1 : 2; /* [1:0] */
500 __IO uint32_t sesenddet : 1; /* [2] */
501 __IO uint32_t reserved2 : 29; /* [31:3] */
502
503 } gotgint_bit;
504 };
505
506 /**
507 * @brief otgfs gahbcfg configuration register, offset:0x08
508 */
509 union
510 {
511 __IO uint32_t gahbcfg;
512 struct
513 {
514 __IO uint32_t glbintmsk : 1; /* [0] */
515 __IO uint32_t reserved1 : 6; /* [6:1] */
516 __IO uint32_t nptxfemplvl : 1; /* [7] */
517 __IO uint32_t ptxfemplvl : 1; /* [8] */
518 __IO uint32_t reserved2 : 23; /* [31:9] */
519 } gahbcfg_bit;
520 };
521
522 /**
523 * @brief otgfs usb configuration register, offset:0x0C
524 */
525 union
526 {
527 __IO uint32_t gusbcfg;
528 struct
529 {
530 __IO uint32_t toutcal : 3; /* [2:0] */
531 __IO uint32_t reserved1 : 7; /* [9:3] */
532 __IO uint32_t usbtrdtim : 4; /* [13:10] */
533 __IO uint32_t reserved2 : 15; /* [28:14] */
534 __IO uint32_t fhstmode : 1; /* [29] */
535 __IO uint32_t fdevmode : 1; /* [30] */
536 __IO uint32_t cotxpkt : 1; /* [31] */
537 } gusbcfg_bit;
538 };
539
540 /**
541 * @brief otgfs reset register, offset:0x10
542 */
543 union
544 {
545 __IO uint32_t grstctl;
546 struct
547 {
548 __IO uint32_t csftrst : 1; /* [0] */
549 __IO uint32_t piusftrst : 1; /* [1] */
550 __IO uint32_t frmcntrst : 1; /* [2] */
551 __IO uint32_t reserved1 : 1; /* [3] */
552 __IO uint32_t rxfflsh : 1; /* [4] */
553 __IO uint32_t txfflsh : 1; /* [5] */
554 __IO uint32_t txfnum : 5; /* [10:6] */
555 __IO uint32_t reserved2 : 20; /* [30:11] */
556 __IO uint32_t ahbidle : 1; /* [31] */
557 } grstctl_bit;
558 };
559
560 /**
561 * @brief otgfs core interrupt register, offset:0x14
562 */
563 union
564 {
565 __IO uint32_t gintsts;
566 struct
567 {
568 __IO uint32_t curmode : 1; /* [0] */
569 __IO uint32_t modemis : 1; /* [1] */
570 __IO uint32_t otgint : 1; /* [2] */
571 __IO uint32_t sof : 1; /* [3] */
572 __IO uint32_t rxflvl : 1; /* [4] */
573 __IO uint32_t nptxfemp : 1; /* [5] */
574 __IO uint32_t ginnakeff : 1; /* [6] */
575 __IO uint32_t goutnakeff : 1; /* [7] */
576 __IO uint32_t reserved1 : 2; /* [9:8]] */
577 __IO uint32_t erlysusp : 1; /* [10] */
578 __IO uint32_t usbsusp : 1; /* [11] */
579 __IO uint32_t usbrst : 1; /* [12] */
580 __IO uint32_t enumdone : 1; /* [13] */
581 __IO uint32_t isooutdrop : 1; /* [14] */
582 __IO uint32_t eopf : 1; /* [15] */
583 __IO uint32_t reserved2 : 2; /* [17:16]] */
584 __IO uint32_t ieptint : 1; /* [18] */
585 __IO uint32_t oeptint : 1; /* [19] */
586 __IO uint32_t incompisoin : 1; /* [20] */
587 __IO uint32_t incompip_incompisoout : 1; /* [21] */
588 __IO uint32_t reserved3 : 2; /* [23:22] */
589 __IO uint32_t prtint : 1; /* [24] */
590 __IO uint32_t hchint : 1; /* [25] */
591 __IO uint32_t ptxfemp : 1; /* [26] */
592 __IO uint32_t reserved4 : 1; /* [27] */
593 __IO uint32_t conidschg : 1; /* [28] */
594 __IO uint32_t disconint : 1; /* [29] */
595 __IO uint32_t reserved5 : 1; /* [30] */
596 __IO uint32_t wkupint : 1; /* [31] */
597 } gintsts_bit;
598 };
599
600 /**
601 * @brief otgfs interrupt mask register, offset:0x18
602 */
603 union
604 {
605 __IO uint32_t gintmsk;
606 struct
607 {
608 __IO uint32_t reserved1 : 1; /* [0] */
609 __IO uint32_t modemismsk : 1; /* [1] */
610 __IO uint32_t otgintmsk : 1; /* [2] */
611 __IO uint32_t sofmsk : 1; /* [3] */
612 __IO uint32_t rxflvlmsk : 1; /* [4] */
613 __IO uint32_t nptxfempmsk : 1; /* [5] */
614 __IO uint32_t ginnakeffmsk : 1; /* [6] */
615 __IO uint32_t goutnakeffmsk : 1; /* [7] */
616 __IO uint32_t reserved2 : 2; /* [9:8]] */
617 __IO uint32_t erlysuspmsk : 1; /* [10] */
618 __IO uint32_t usbsuspmsk : 1; /* [11] */
619 __IO uint32_t usbrstmsk : 1; /* [12] */
620 __IO uint32_t enumdonemsk : 1; /* [13] */
621 __IO uint32_t isooutdropmsk : 1; /* [14] */
622 __IO uint32_t eopfmsk : 1; /* [15] */
623 __IO uint32_t reserved3 : 2; /* [17:16]] */
624 __IO uint32_t ieptintmsk : 1; /* [18] */
625 __IO uint32_t oeptintmsk : 1; /* [19] */
626 __IO uint32_t incompisoinmsk : 1; /* [20] */
627 __IO uint32_t incompip_incompisooutmsk : 1; /* [21] */
628 __IO uint32_t reserved4 : 2; /* [23:22] */
629 __IO uint32_t prtintmsk : 1; /* [24] */
630 __IO uint32_t hchintmsk : 1; /* [25] */
631 __IO uint32_t ptxfempmsk : 1; /* [26] */
632 __IO uint32_t reserved5 : 1; /* [27] */
633 __IO uint32_t conidschgmsk : 1; /* [28] */
634 __IO uint32_t disconintmsk : 1; /* [29] */
635 __IO uint32_t reserved6 : 1; /* [30] */
636 __IO uint32_t wkupintmsk : 1; /* [31] */
637 } gintmsk_bit;
638 };
639
640 /**
641 * @brief otgfs rx status debug read register, offset:0x1C
642 */
643 union
644 {
645 __IO uint32_t grxstsr;
646 struct
647 {
648 __IO uint32_t eptnum : 4; /* [3:0] */
649 __IO uint32_t bcnt : 11; /* [14:4] */
650 __IO uint32_t dpid : 2; /* [16:15] */
651 __IO uint32_t pktsts : 4; /* [20:17] */
652 __IO uint32_t fn : 4; /* [24:21] */
653 __IO uint32_t reserved1 : 7; /* [31:25] */
654 } grxstsr_bit;
655 };
656
657 /**
658 * @brief otgfs rx status read and pop register, offset:0x20
659 */
660 union
661 {
662 __IO uint32_t grxstsp;
663 struct
664 {
665 __IO uint32_t chnum : 4; /* [3:0] */
666 __IO uint32_t bcnt : 11; /* [14:4] */
667 __IO uint32_t dpid : 2; /* [16:15] */
668 __IO uint32_t pktsts : 4; /* [20:17] */
669 __IO uint32_t reserved1 : 11; /* [31:21] */
670 } grxstsp_bit;
671 };
672
673 /**
674 * @brief otgfs rx fifo size register, offset:0x24
675 */
676 union
677 {
678 __IO uint32_t grxfsiz;
679 struct
680 {
681 __IO uint32_t rxfdep : 16; /* [15:0] */
682 __IO uint32_t reserved1 : 16; /* [31:16] */
683 } grxfsiz_bit;
684 };
685
686 /**
687 * @brief otgfs non-periodic and ept0 tx fifo size register, offset:0x28
688 */
689 union
690 {
691 __IO uint32_t gnptxfsiz_ept0tx;
692 struct
693 {
694 __IO uint32_t nptxfstaddr : 16; /* [15:0] */
695 __IO uint32_t nptxfdep : 16; /* [31:16] */
696 } gnptxfsiz_ept0tx_bit;
697 };
698
699 /**
700 * @brief otgfs non-periodic tx fifo request queue status register, offset:0x2C
701 */
702 union
703 {
704 __IO uint32_t gnptxsts;
705 struct
706 {
707 __IO uint32_t nptxfspcavail : 16; /* [15:0] */
708 __IO uint32_t nptxqspcavail : 8; /* [23:16] */
709 __IO uint32_t nptxqtop : 7; /* [30:24] */
710 } gnptxsts_bit;
711 };
712
713 __IO uint32_t reserved2[2];
714
715 /**
716 * @brief otgfs general core configuration register, offset:0x38
717 */
718 union
719 {
720 __IO uint32_t gccfg;
721 struct
722 {
723 __IO uint32_t reserved1 : 16; /* [15:0] */
724 __IO uint32_t pwrdown : 1; /* [16] */
725 __IO uint32_t lp_mode : 1; /* [17] */
726 __IO uint32_t reserved2 : 2; /* [19:18] */
727 __IO uint32_t sofouten : 1; /* [20] */
728 __IO uint32_t vbusig : 1; /* [21] */
729 __IO uint32_t reserved3 : 10; /* [31:22] */
730 } gccfg_bit;
731 };
732
733 /**
734 * @brief otgfs core id register, offset:0x3C
735 */
736 union
737 {
738 __IO uint32_t guid;
739 struct
740 {
741 __IO uint32_t userid : 32; /* [31:0] */
742 } guid_bit;
743 };
744
745 __IO uint32_t reserved3[48];
746
747 /**
748 * @brief otgfs host periodic tx fifo size register, offset:0x100
749 */
750 union
751 {
752 __IO uint32_t hptxfsiz;
753 struct
754 {
755 __IO uint32_t ptxfstaddr : 16; /* [15:0] */
756 __IO uint32_t ptxfsize : 16; /* [31:16] */
757 } hptxfsiz_bit;
758 };
759
760 /**
761 * @brief otgfs host periodic tx fifo size register, offset:0x100
762 */
763 union
764 {
765 __IO uint32_t dieptxfn[7];
766 struct
767 {
768 __IO uint32_t ineptxfstaddr : 16; /* [15:0] */
769 __IO uint32_t ineptxfdep : 16; /* [31:16] */
770 } dieptxfn_bit[7];
771 };
772 } otg_global_type;
773
774
775 typedef struct
776 {
777 /**
778 * @brief otgfs host mode configuration register, offset:0x400
779 */
780 union
781 {
782 __IO uint32_t hcfg;
783 struct
784 {
785 __IO uint32_t fslspclksel : 2; /* [1:0] */
786 __IO uint32_t fslssupp : 1; /* [2] */
787 __IO uint32_t reserved1 : 29; /* [31:3] */
788 } hcfg_bit;
789 };
790
791 /**
792 * @brief otgfs host frame interval register, offset:0x404
793 */
794 union
795 {
796 __IO uint32_t hfir;
797 struct
798 {
799 __IO uint32_t frint : 16; /* [15:0] */
800 __IO uint32_t reserved1 : 16; /* [31:15] */
801 } hfir_bit;
802 };
803
804 /**
805 * @brief otgfs host frame number and time remaining register, offset:0x408
806 */
807 union
808 {
809 __IO uint32_t hfnum;
810 struct
811 {
812 __IO uint32_t frnum : 16; /* [15:0] */
813 __IO uint32_t ftrem : 16; /* [31:15] */
814 } hfnum_bit;
815 };
816
817 __IO uint32_t reserved1;
818
819 /**
820 * @brief otgfs host periodic tx fifo request queue register, offset:0x410
821 */
822 union
823 {
824 __IO uint32_t hptxsts;
825 struct
826 {
827 __IO uint32_t ptxfspcavil : 16; /* [15:0] */
828 __IO uint32_t ptxqspcavil : 8; /* [23:16] */
829 __IO uint32_t ptxqtop : 8; /* [31:24] */
830 } hptxsts_bit;
831 };
832
833 /**
834 * @brief otgfs host all channel interrupt register, offset:0x414
835 */
836 union
837 {
838 __IO uint32_t haint;
839 struct
840 {
841 __IO uint32_t haint : 16; /* [15:0] */
842 __IO uint32_t reserved1 : 16; /* [32:16] */
843 } haint_bit;
844 };
845
846 /**
847 * @brief otgfs host all channel interrupt mask register, offset:0x418
848 */
849 union
850 {
851 __IO uint32_t haintmsk;
852 struct
853 {
854 __IO uint32_t haintmsk : 16; /* [15:0] */
855 __IO uint32_t reserved1 : 16; /* [32:16] */
856 } haintmsk_bit;
857 };
858
859 __IO uint32_t reserved2[9];
860
861 /**
862 * @brief otgfs host port control and status register, offset:0x440
863 */
864 union
865 {
866 __IO uint32_t hprt;
867 struct
868 {
869 __IO uint32_t prtconsts : 1; /* [0] */
870 __IO uint32_t prtcondet : 1; /* [1] */
871 __IO uint32_t prtena : 1; /* [2] */
872 __IO uint32_t prtenchng : 1; /* [3] */
873 __IO uint32_t prtovrcact : 1; /* [4] */
874 __IO uint32_t prtovrcchng : 1; /* [5] */
875 __IO uint32_t prtres : 1; /* [6] */
876 __IO uint32_t prtsusp : 1; /* [7] */
877 __IO uint32_t prtrst : 1; /* [8] */
878 __IO uint32_t reserved1 : 1; /* [9] */
879 __IO uint32_t prtlnsts : 2; /* [11:10] */
880 __IO uint32_t prtpwr : 1; /* [12] */
881 __IO uint32_t prttsctl : 4; /* [16:13] */
882 __IO uint32_t prtspd : 2; /* [18:17] */
883 __IO uint32_t reserved2 : 13; /* [31:19] */
884
885 } hprt_bit;
886 };
887 } otg_host_type;
888
889 typedef struct
890 {
891 /**
892 * @brief otgfs host channel x characterisic register, offset:0x500
893 */
894 union
895 {
896 __IO uint32_t hcchar;
897 struct
898 {
899 __IO uint32_t mps : 11; /* [10:0] */
900 __IO uint32_t eptnum : 4; /* [14:11] */
901 __IO uint32_t eptdir : 1; /* [15] */
902 __IO uint32_t reserved1 : 1; /* [16] */
903 __IO uint32_t lspddev : 1; /* [17] */
904 __IO uint32_t eptype : 2; /* [19:18] */
905 __IO uint32_t mc : 2; /* [21:20] */
906 __IO uint32_t devaddr : 7; /* [28:22] */
907 __IO uint32_t oddfrm : 1; /* [29] */
908 __IO uint32_t chdis : 1; /* [30] */
909 __IO uint32_t chena : 1; /* [31] */
910 } hcchar_bit;
911 };
912
913 /**
914 * @brief otgfs host channel split control register, offset:0x504
915 */
916 union
917 {
918 __IO uint32_t hcsplt;
919 struct
920 {
921 __IO uint32_t prtaddr : 7; /* [6:0] */
922 __IO uint32_t hubaddr : 7; /* [13:7] */
923 __IO uint32_t xactpos : 2; /* [15:14] */
924 __IO uint32_t compsplt : 1; /* [16] */
925 __IO uint32_t reserved1 : 14; /* [30:17] */
926 __IO uint32_t spltena : 1; /* [31] */
927 } hcsplt_bit;
928 };
929
930 /**
931 * @brief otgfs host channel interrupt register, offset:0x508
932 */
933 union
934 {
935 __IO uint32_t hcint;
936 struct
937 {
938 __IO uint32_t xferc : 1; /* [0] */
939 __IO uint32_t chhltd : 1; /* [1] */
940 __IO uint32_t reserved1 : 1; /* [2] */
941 __IO uint32_t stall : 1; /* [3] */
942 __IO uint32_t nak : 1; /* [4] */
943 __IO uint32_t ack : 1; /* [5] */
944 __IO uint32_t reserved2 : 1; /* [6] */
945 __IO uint32_t xacterr : 1; /* [7] */
946 __IO uint32_t bblerr : 1; /* [8] */
947 __IO uint32_t frmovrun : 1; /* [9] */
948 __IO uint32_t dtglerr : 1; /* [10] */
949 __IO uint32_t reserved3 : 21; /* [31:11] */
950 } hcint_bit;
951 };
952
953 /**
954 * @brief otgfs host channel interrupt mask register, offset:0x50C
955 */
956 union
957 {
958 __IO uint32_t hcintmsk;
959 struct
960 {
961 __IO uint32_t xfercmsk : 1; /* [0] */
962 __IO uint32_t chhltdmsk : 1; /* [1] */
963 __IO uint32_t reserved1 : 1; /* [2] */
964 __IO uint32_t stallmsk : 1; /* [3] */
965 __IO uint32_t nakmsk : 1; /* [4] */
966 __IO uint32_t ackmsk : 1; /* [5] */
967 __IO uint32_t reserved2 : 1; /* [6] */
968 __IO uint32_t xacterrmsk : 1; /* [7] */
969 __IO uint32_t bblerrmsk : 1; /* [8] */
970 __IO uint32_t frmovrunmsk : 1; /* [9] */
971 __IO uint32_t dtglerrmsk : 1; /* [10] */
972 __IO uint32_t reserved3 : 21; /* [31:11] */
973 } hcintmsk_bit;
974 };
975
976 /**
977 * @brief otgfs host channel transfer size register, offset:0x510
978 */
979 union
980 {
981 __IO uint32_t hctsiz;
982 struct
983 {
984 __IO uint32_t xfersize : 19; /* [18:0] */
985 __IO uint32_t pktcnt : 10; /* [28:19] */
986 __IO uint32_t pid : 2; /* [30:29] */
987 __IO uint32_t reserved1 : 1; /* [31] */
988 } hctsiz_bit;
989 };
990 __IO uint32_t reserved3[3];
991
992 }otg_hchannel_type;
993
994
995 typedef struct
996 {
997 /**
998 * @brief otgfs device configuration register, offset:0x800
999 */
1000 union
1001 {
1002 __IO uint32_t dcfg;
1003 struct
1004 {
1005 __IO uint32_t devspd : 2; /* [1:0] */
1006 __IO uint32_t nzstsouthshk : 1; /* [2] */
1007 __IO uint32_t reserved1 : 1; /* [3] */
1008 __IO uint32_t devaddr : 7; /* [10:4] */
1009 __IO uint32_t perfrint : 2; /* [12:11] */
1010 __IO uint32_t reserved2 : 19; /* [31:13] */
1011 } dcfg_bit;
1012 };
1013
1014 /**
1015 * @brief otgfs device controls register, offset:0x804
1016 */
1017 union
1018 {
1019 __IO uint32_t dctl;
1020 struct
1021 {
1022 __IO uint32_t rwkupsig : 1; /* [0] */
1023 __IO uint32_t sftdiscon : 1; /* [1] */
1024 __IO uint32_t gnpinnaksts : 1; /* [2] */
1025 __IO uint32_t goutnaksts : 1; /* [3] */
1026 __IO uint32_t tstctl : 3; /* [6:4] */
1027 __IO uint32_t sgnpinak : 1; /* [7] */
1028 __IO uint32_t cgnpinak : 1; /* [8] */
1029 __IO uint32_t sgoutnak : 1; /* [9] */
1030 __IO uint32_t cgoutnak : 1; /* [10] */
1031 __IO uint32_t pwroprgdne : 1; /* [11] */
1032 __IO uint32_t reserved1 : 20; /* [31:12] */
1033 } dctl_bit;
1034 };
1035
1036 /**
1037 * @brief otgfs device status register, offset:0x80C
1038 */
1039 union
1040 {
1041 __IO uint32_t dsts;
1042 struct
1043 {
1044 __IO uint32_t suspsts : 1; /* [0] */
1045 __IO uint32_t enumspd : 2; /* [2:1] */
1046 __IO uint32_t eticerr : 1; /* [3] */
1047 __IO uint32_t reserved1 : 4; /* [7:4] */
1048 __IO uint32_t soffn : 14; /* [21:8] */
1049 __IO uint32_t reserved2 : 10; /* [31:22] */
1050 } dsts_bit;
1051 };
1052
1053 __IO uint32_t reserved1;
1054 /**
1055 * @brief otgfs device in endpoint general interrupt mask register, offset:0x810
1056 */
1057 union
1058 {
1059 __IO uint32_t diepmsk;
1060 struct
1061 {
1062 __IO uint32_t xfercmsk : 1; /* [0] */
1063 __IO uint32_t eptdismsk : 1; /* [1] */
1064 __IO uint32_t reserved1 : 1; /* [2] */
1065 __IO uint32_t timeoutmsk : 1; /* [3] */
1066 __IO uint32_t intkntxfempmsk : 1; /* [4] */
1067 __IO uint32_t intkneptmismsk : 1; /* [5] */
1068 __IO uint32_t ineptnakmsk : 1; /* [6] */
1069 __IO uint32_t reserved2 : 1; /* [7] */
1070 __IO uint32_t txfifoudrmsk : 1; /* [8] */
1071 __IO uint32_t bnainmsk : 1; /* [9] */
1072 __IO uint32_t reserved3 : 22; /* [31:10] */
1073 } diepmsk_bit;
1074 };
1075
1076 /**
1077 * @brief otgfs device out endpoint general interrupt mask register, offset:0x814
1078 */
1079 union
1080 {
1081 __IO uint32_t doepmsk;
1082 struct
1083 {
1084 __IO uint32_t xfercmsk : 1; /* [0] */
1085 __IO uint32_t eptdismsk : 1; /* [1] */
1086 __IO uint32_t reserved1 : 1; /* [2] */
1087 __IO uint32_t setupmsk : 1; /* [3] */
1088 __IO uint32_t outtepdmsk : 1; /* [4] */
1089 __IO uint32_t reserved2 : 1; /* [5] */
1090 __IO uint32_t b2bsetupmsk : 1; /* [6] */
1091 __IO uint32_t reserved3 : 1; /* [7] */
1092 __IO uint32_t outperrmsk : 1; /* [8] */
1093 __IO uint32_t bnaoutmsk : 1; /* [9] */
1094 __IO uint32_t reserved4 : 22; /* [31:10] */
1095 } doepmsk_bit;
1096 };
1097
1098 /**
1099 * @brief otgfs device all endpoint interrupt register, offset:0x818
1100 */
1101 union
1102 {
1103 __IO uint32_t daint;
1104 struct
1105 {
1106 __IO uint32_t ineptint : 16; /* [15:0] */
1107 __IO uint32_t outeptint : 16; /* [31:16] */
1108 } daint_bit;
1109 };
1110
1111 /**
1112 * @brief otgfs device all endpoint interrupt mask register, offset:0x81C
1113 */
1114 union
1115 {
1116 __IO uint32_t daintmsk;
1117 struct
1118 {
1119 __IO uint32_t ineptmsk : 16; /* [15:0] */
1120 __IO uint32_t outeptmsk : 16; /* [31:16] */
1121 } daintmsk_bit;
1122 };
1123
1124 __IO uint32_t reserved2[5];
1125
1126 /**
1127 * @brief otgfs device in endpoint fifo empty interrupt mask register, offset:0x834
1128 */
1129 union
1130 {
1131 __IO uint32_t diepempmsk;
1132 struct
1133 {
1134 __IO uint32_t ineptxfemsk : 16; /* [15:0] */
1135 __IO uint32_t reserved1 : 16; /* [31:16] */
1136 } diepempmsk_bit;
1137 };
1138
1139 } otg_device_type;
1140
1141 typedef struct
1142 {
1143 /**
1144 * @brief otgfs device out endpoint control register, offset:0x900
1145 */
1146 union
1147 {
1148 __IO uint32_t diepctl;
1149 struct
1150 {
1151 __IO uint32_t mps : 11; /* [10:0] */
1152 __IO uint32_t reserved1 : 4; /* [14:11] */
1153 __IO uint32_t usbacept : 1; /* [15] */
1154 __IO uint32_t dpid : 1; /* [16] */
1155 __IO uint32_t naksts : 1; /* [17] */
1156 __IO uint32_t eptype : 2; /* [19:18] */
1157 __IO uint32_t reserved2 : 1; /* [20] */
1158 __IO uint32_t stall : 1; /* [21] */
1159 __IO uint32_t txfnum : 4; /* [25:22] */
1160 __IO uint32_t cnak : 1; /* [26] */
1161 __IO uint32_t snak : 1; /* [27] */
1162 __IO uint32_t setd0pid : 1; /* [28] */
1163 __IO uint32_t setd1pid : 1; /* [29] */
1164 __IO uint32_t eptdis : 1; /* [30] */
1165 __IO uint32_t eptena : 1; /* [31] */
1166 } diepctl_bit;
1167 };
1168 __IO uint32_t reserved1;
1169
1170 /**
1171 * @brief otgfs device in endpoint interrupt register, offset:0x908
1172 */
1173 union
1174 {
1175 __IO uint32_t diepint;
1176 struct
1177 {
1178 __IO uint32_t xferc : 1; /* [0] */
1179 __IO uint32_t epdisd : 1; /* [1] */
1180 __IO uint32_t reserved1 : 1; /* [2] */
1181 __IO uint32_t timeout : 1; /* [3] */
1182 __IO uint32_t intkntxfemp : 1; /* [4] */
1183 __IO uint32_t reserved2 : 1; /* [5] */
1184 __IO uint32_t ineptnak : 1; /* [6] */
1185 __IO uint32_t txfemp : 1; /* [7] */
1186 __IO uint32_t reserved3 : 24; /* [31:8] */
1187 } diepint_bit;
1188 };
1189 __IO uint32_t reserved2;
1190
1191 /**
1192 * @brief otgfs device in endpoint transfer size register, offset:0x910 + endpoint number * 0x20
1193 */
1194 union
1195 {
1196 __IO uint32_t dieptsiz;
1197 struct
1198 {
1199 __IO uint32_t xfersize : 19; /* [18:0] */
1200 __IO uint32_t pktcnt : 10; /* [28:19] */
1201 __IO uint32_t mc : 2; /* [30:29] */
1202 __IO uint32_t reserved1 : 1; /* [31] */
1203 } dieptsiz_bit;
1204 };
1205
1206 __IO uint32_t reserved3;
1207
1208 /**
1209 * @brief otgfs device in endpoint tx fifo status register, offset:0x918 + endpoint number * 0x20
1210 */
1211 union
1212 {
1213 __IO uint32_t dtxfsts;
1214 struct
1215 {
1216 __IO uint32_t ineptxfsav : 16; /* [15:0] */
1217 __IO uint32_t reserved1 : 16; /* [31:16] */
1218 } dtxfsts_bit;
1219 };
1220
1221 } otg_eptin_type;
1222
1223 typedef struct
1224 {
1225 /**
1226 * @brief otgfs device out endpoint control register, offset:0xb00 + endpoint number * 0x20
1227 */
1228 union
1229 {
1230 __IO uint32_t doepctl;
1231 struct
1232 {
1233 __IO uint32_t mps : 11; /* [10:0] */
1234 __IO uint32_t reserved1 : 4; /* [14:11] */
1235 __IO uint32_t usbacept : 1; /* [15] */
1236 __IO uint32_t dpid : 1; /* [16] */
1237 __IO uint32_t naksts : 1; /* [17] */
1238 __IO uint32_t eptype : 2; /* [19:18] */
1239 __IO uint32_t snpm : 1; /* [20] */
1240 __IO uint32_t stall : 1; /* [21] */
1241 __IO uint32_t reserved2 : 4; /* [25:22] */
1242 __IO uint32_t cnak : 1; /* [26] */
1243 __IO uint32_t snak : 1; /* [27] */
1244 __IO uint32_t setd0pid : 1; /* [28] */
1245 __IO uint32_t setd1pid : 1; /* [29] */
1246 __IO uint32_t eptdis : 1; /* [30] */
1247 __IO uint32_t eptena : 1; /* [31] */
1248 } doepctl_bit;
1249 };
1250 __IO uint32_t reserved1;
1251
1252 /**
1253 * @brief otgfs device out endpoint interrupt register, offset:0xb08 + endpoint number * 0x20
1254 */
1255 union
1256 {
1257 __IO uint32_t doepint;
1258 struct
1259 {
1260 __IO uint32_t xferc : 1; /* [0] */
1261 __IO uint32_t epdisd : 1; /* [1] */
1262 __IO uint32_t reserved1 : 1; /* [2] */
1263 __IO uint32_t setup : 1; /* [3] */
1264 __IO uint32_t outtepd : 1; /* [4] */
1265 __IO uint32_t reserved2 : 1; /* [5] */
1266 __IO uint32_t b2pstup : 1; /* [6] */
1267 __IO uint32_t reserved3 : 25; /* [31:7] */
1268 } doepint_bit;
1269 };
1270 __IO uint32_t reserved2;
1271
1272 /**
1273 * @brief otgfs device out endpoint transfer size register, offset:0xb10 + endpoint number * 0x20
1274 */
1275 union
1276 {
1277 __IO uint32_t doeptsiz;
1278 struct
1279 {
1280 __IO uint32_t xfersize : 19; /* [18:0] */
1281 __IO uint32_t pktcnt : 10; /* [28:19] */
1282 __IO uint32_t rxdpid_setupcnt : 2; /* [30:29] */
1283 __IO uint32_t reserved1 : 1; /* [31] */
1284 } doeptsiz_bit;
1285 };
1286 } otg_eptout_type;
1287
1288 typedef struct
1289 {
1290 /**
1291 * @brief otgfs power and clock gating control registers, offset:0xe00
1292 */
1293 union
1294 {
1295 __IO uint32_t pcgcctl;
1296 struct
1297 {
1298 __IO uint32_t stoppclk : 1; /* [0] */
1299 __IO uint32_t reserved1 : 3; /* [3:1] */
1300 __IO uint32_t suspendm : 1; /* [4] */
1301 __IO uint32_t reserved2 : 27; /* [31:5] */
1302 } pcgcctl_bit;
1303 };
1304 } otg_pcgcctl_type;
1305
1306 /**
1307 * @}
1308 */
1309
1310 /** @defgroup USB_exported_functions
1311 * @{
1312 */
1313
1314 /**
1315 * @brief usb host and device offset address
1316 */
1317 #define OTG_HOST_ADDR_OFFSET 0x400 /*!< usb host register offset address */
1318 #define OTG_HOST_CHANNEL_ADDR_OFFSET 0x500 /*!< usb host channel register offset address */
1319 #define OTG_DEVICE_ADDR_OFFSET 0x800 /*!< usb device register offset address */
1320 #define OTG_DEVICE_EPTIN_ADDR_OFFSET 0x900 /*!< usb device endpoint in register offset address */
1321 #define OTG_DEVICE_EPTOUT_ADDR_OFFSET 0xB00 /*!< usb device endpoint out register offset address */
1322 #define OTG_PCGCCTL_ADDR_OFFSET 0xE00 /*!< usb power and clock control register offset address */
1323 #define OTG_FIFO_ADDR_OFFSET 0x1000 /*!< usb fifo offset address */
1324
1325 /**
1326 * @brief usb host and device register define
1327 */
1328 #define OTG1_GLOBAL ((otg_global_type *)(OTGFS1_BASE)) /*!< usb otg1 global register */
1329 #define OTG2_GLOBAL ((otg_global_type *)(OTGFS2_BASE)) /*!< usb otg2 global register */
1330 #define OTG_PCGCCTL(usbx) ((otg_pcgcctl_type *)((uint32_t)usbx + OTG_PCGCCTL_ADDR_OFFSET)) /*!< usb power and clock control register */
1331 #define OTG_DEVICE(usbx) ((otg_device_type *)((uint32_t)usbx + OTG_DEVICE_ADDR_OFFSET)) /*!< usb device register */
1332 #define OTG_HOST(usbx) ((otg_host_type *)((uint32_t)usbx + OTG_HOST_ADDR_OFFSET)) /*!< usb host register */
1333 #define USB_CHL(usbx, n) ((otg_hchannel_type *)((uint32_t)usbx + OTG_HOST_CHANNEL_ADDR_OFFSET + n * 0x20)) /*!< usb channel n register */
1334 #define USB_INEPT(usbx, eptn) ((otg_eptin_type *)((uint32_t)usbx + OTG_DEVICE_EPTIN_ADDR_OFFSET + eptn * 0x20)) /*!< usb device endpoint in register */
1335 #define USB_OUTEPT(usbx, eptn) ((otg_eptout_type *)((uint32_t)usbx + OTG_DEVICE_EPTOUT_ADDR_OFFSET + eptn * 0x20)) /*!< usb device endpoint out register */
1336 #define USB_FIFO(usbx, eptn) *(__IO uint32_t *)((uint32_t)usbx + OTG_FIFO_ADDR_OFFSET + eptn * 0x1000) /*!< usb fifo address */
1337
1338
1339
1340 typedef otg_global_type usb_reg_type;
1341
1342 /** @defgroup USB_exported_functions
1343 * @{
1344 */
1345
1346 #ifdef OTGFS_USB_GLOBAL
1347 error_status usb_global_reset(otg_global_type *usbx);
1348 void usb_global_init(otg_global_type *usbx);
1349 otg_global_type *usb_global_select_core(uint8_t usb_id);
1350 void usb_flush_tx_fifo(otg_global_type *usbx, uint32_t fifo_num);
1351 void usb_flush_rx_fifo(otg_global_type *usbx);
1352 void usb_global_interrupt_enable(otg_global_type *usbx, uint16_t interrupt, confirm_state new_state);
1353 uint32_t usb_global_get_all_interrupt(otg_global_type *usbx);
1354 void usb_global_clear_interrupt(otg_global_type *usbx, uint32_t flag);
1355 void usb_interrupt_enable(otg_global_type *usbx);
1356 void usb_interrupt_disable(otg_global_type *usbx);
1357 void usb_set_rx_fifo(otg_global_type *usbx, uint16_t size);
1358 void usb_set_tx_fifo(otg_global_type *usbx, uint8_t txfifo, uint16_t size);
1359 void usb_global_set_mode(otg_global_type *usbx, uint32_t mode);
1360 void usb_global_power_on(otg_global_type *usbx);
1361 void usb_write_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
1362 void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
1363 void usb_stop_phy_clk(otg_global_type *usbx);
1364 void usb_open_phy_clk(otg_global_type *usbx);
1365 #endif
1366
1367 #ifdef OTGFS_USB_DEVICE
1368 void usb_ept_open(otg_global_type *usbx, usb_ept_info *ept_info);
1369 void usb_ept_close(otg_global_type *usbx, usb_ept_info *ept_info);
1370 void usb_ept_stall(otg_global_type *usbx, usb_ept_info *ept_info);
1371 void usb_ept_clear_stall(otg_global_type *usbx, usb_ept_info *ept_info);
1372 uint32_t usb_get_all_out_interrupt(otg_global_type *usbx);
1373 uint32_t usb_get_all_in_interrupt(otg_global_type *usbx);
1374 uint32_t usb_ept_out_interrupt(otg_global_type *usbx, uint32_t eptn);
1375 uint32_t usb_ept_in_interrupt(otg_global_type *usbx, uint32_t eptn);
1376 void usb_ept_out_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
1377 void usb_ept_in_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
1378 void usb_set_address(otg_global_type *usbx, uint8_t address);
1379 void usb_ept0_start(otg_global_type *usbx);
1380 void usb_ept0_setup(otg_global_type *usbx);
1381 void usb_connect(otg_global_type *usbx);
1382 void usb_disconnect(otg_global_type *usbx);
1383 void usb_remote_wkup_set(otg_global_type *usbx);
1384 void usb_remote_wkup_clear(otg_global_type *usbx);
1385 uint8_t usb_suspend_status_get(otg_global_type *usbx);
1386 #endif
1387
1388 #ifdef OTGFS_USB_HOST
1389 void usb_port_power_on(otg_global_type *usbx, confirm_state state);
1390 uint32_t usbh_get_frame(otg_global_type *usbx);
1391 void usb_hc_enable(otg_global_type *usbx,
1392 uint8_t chn,
1393 uint8_t ept_num,
1394 uint8_t dev_address,
1395 uint8_t type,
1396 uint16_t maxpacket,
1397 uint8_t speed);
1398 uint32_t usb_hch_read_interrupt(otg_global_type *usbx);
1399 void usb_host_disable(otg_global_type *usbx);
1400 void usb_hch_halt(otg_global_type *usbx, uint8_t chn);
1401 void usbh_fsls_clksel(otg_global_type *usbx, uint8_t clk);
1402 #endif
1403 /**
1404 * @}
1405 */
1406
1407 /**
1408 * @}
1409 */
1410
1411 /**
1412 * @}
1413 */
1414
1415 /**
1416 * @}
1417 */
1418
1419 #ifdef __cplusplus
1420 }
1421 #endif
1422
1423 #endif
INAV: Navigation-enabled flight control software