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[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / src / at32f435_437_dma.c
bloba7d0313d8558b389ab03a4140f6c8e45e1e29beb
1 /**
2 **************************************************************************
3 * @file at32f435_437_dma.c
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief contains all the functions for the dma firmware library
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 #include "at32f435_437_conf.h"
28
29 /** @addtogroup AT32F435_437_periph_driver
30 * @{
31 */
32
33 /** @defgroup DMA
34 * @brief DMA driver modules
35 * @{
36 */
37
38 #ifdef DMA_MODULE_ENABLED
39
40 /** @defgroup DMA_private_functions
41 * @{
42 */
43
44 /**
45 * @brief reset dmax channely register.
46 * @param dmax_channely:
47 * this parameter can be one of the following values:
48 * - DMA1_CHANNEL1
49 * - DMA1_CHANNEL2
50 * - DMA1_CHANNEL3
51 * - DMA1_CHANNEL4
52 * - DMA1_CHANNEL5
53 * - DMA1_CHANNEL6
54 * - DMA1_CHANNEL7
55 * - DMA2_CHANNEL1
56 * - DMA2_CHANNEL2
57 * - DMA2_CHANNEL3
58 * - DMA2_CHANNEL4
59 * - DMA2_CHANNEL5
60 * - DMA2_CHANNEL6
61 * - DMA2_CHANNEL7
62 * @retval none.
63 */
64 void dma_reset(dma_channel_type *dmax_channely)
65 {
66 uint32_t temp = 0;
67 dmax_channely->ctrl_bit.chen = FALSE;
68 dmax_channely->ctrl = 0;
69 dmax_channely->dtcnt = 0;
70 dmax_channely->paddr = 0;
71 dmax_channely->maddr = 0;
72
73 temp = (uint32_t)dmax_channely;
74
75 if((temp & 0x6FF) < 0x608)
76 {
77 /* dma1 channel */
78 DMA1->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
79 }
80 else if((temp & 0x6FF) < 0x688)
81 {
82 /* dma2 channel */
83 DMA2->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
84 }
85 }
86
87 /**
88 * @brief set the number of data to be transferred.
89 * @param dmax_channely:
90 * this parameter can be one of the following values:
91 * - DMA1_CHANNEL1
92 * - DMA1_CHANNEL2
93 * - DMA1_CHANNEL3
94 * - DMA1_CHANNEL4
95 * - DMA1_CHANNEL5
96 * - DMA1_CHANNEL6
97 * - DMA1_CHANNEL7
98 * - DMA2_CHANNEL1
99 * - DMA2_CHANNEL2
100 * - DMA2_CHANNEL3
101 * - DMA2_CHANNEL4
102 * - DMA2_CHANNEL5
103 * - DMA2_CHANNEL6
104 * - DMA2_CHANNEL7
105 * @param data_number: the number of data to be transferred (0x0000~0xFFFF).
106 * @retval none.
107 */
108 void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number)
109 {
110 dmax_channely->dtcnt = data_number;
111 }
112
113 /**
114 * @brief get the number of data to be transferred.
115 * @param dmax_channely:
116 * this parameter can be one of the following values:
117 * - DMA1_CHANNEL1
118 * - DMA1_CHANNEL2
119 * - DMA1_CHANNEL3
120 * - DMA1_CHANNEL4
121 * - DMA1_CHANNEL5
122 * - DMA1_CHANNEL6
123 * - DMA1_CHANNEL7
124 * - DMA2_CHANNEL1
125 * - DMA2_CHANNEL2
126 * - DMA2_CHANNEL3
127 * - DMA2_CHANNEL4
128 * - DMA2_CHANNEL5
129 * - DMA2_CHANNEL6
130 * - DMA2_CHANNEL7
131 * @retval the number value.
132 */
133 uint16_t dma_data_number_get(dma_channel_type *dmax_channely)
134 {
135 return (uint16_t)dmax_channely->dtcnt;
136 }
137
138 /**
139 * @brief enable or disable dma interrupt.
140 * @param dmax_channely:
141 * this parameter can be one of the following values:
142 * - DMA1_CHANNEL1
143 * - DMA1_CHANNEL2
144 * - DMA1_CHANNEL3
145 * - DMA1_CHANNEL4
146 * - DMA1_CHANNEL5
147 * - DMA1_CHANNEL6
148 * - DMA1_CHANNEL7
149 * - DMA2_CHANNEL1
150 * - DMA2_CHANNEL2
151 * - DMA2_CHANNEL3
152 * - DMA2_CHANNEL4
153 * - DMA2_CHANNEL5
154 * - DMA2_CHANNEL6
155 * - DMA2_CHANNEL7
156 * @param dma_int:
157 * this parameter can be any combination of the following values:
158 * - DMA_FDT_INT
159 * - DMA_HDT_INT
160 * - DMA_DTERR_INT
161 * @param new_state (TRUE or FALSE)
162 * @retval none.
163 */
164 void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state)
165 {
166 if(new_state != FALSE)
167 {
168 dmax_channely->ctrl |= dma_int;
169 }
170 else
171 {
172 dmax_channely->ctrl &= ~dma_int;
173 }
174 }
175
176 /**
177 * @brief enable or disable dma channel.
178 * @param dmax_channely:
179 * this parameter can be one of the following values:
180 * - DMA1_CHANNEL1
181 * - DMA1_CHANNEL2
182 * - DMA1_CHANNEL3
183 * - DMA1_CHANNEL4
184 * - DMA1_CHANNEL5
185 * - DMA1_CHANNEL6
186 * - DMA1_CHANNEL7
187 * - DMA2_CHANNEL1
188 * - DMA2_CHANNEL2
189 * - DMA2_CHANNEL3
190 * - DMA2_CHANNEL4
191 * - DMA2_CHANNEL5
192 * - DMA2_CHANNEL6
193 * - DMA2_CHANNEL7
194 * @param new_state (TRUE or FALSE).
195 * @retval none.
196 */
197 void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state)
198 {
199 dmax_channely->ctrl_bit.chen = new_state;
200 }
201
202 /**
203 * @brief dma flag get.
204 * @param dma_flag
205 * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
206 * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
207 * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
208 * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
209 * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
210 * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
211 * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
212 * - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
213 * - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
214 * - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
215 * - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
216 * - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
217 * - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
218 * - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
219 * @retval state of dma flag.
220 */
221 flag_status dma_flag_get(uint32_t dmax_flag)
222 {
223 uint32_t temp = 0;
224
225 if(dmax_flag > 0x10000000)
226 {
227 temp = DMA2->sts;
228 }
229 else
230 {
231 temp = DMA1->sts;
232 }
233
234 if((temp & dmax_flag) != RESET)
235 {
236 return SET;
237 }
238 else
239 {
240 return RESET;
241 }
242 }
243
244 /**
245 * @brief dma flag clear.
246 * @param dma_flag
247 * this parameter can be one of the following values:
248 * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
249 * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
250 * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
251 * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
252 * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
253 * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
254 * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
255 * - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
256 * - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
257 * - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
258 * - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
259 * - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
260 * - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
261 * - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
262 * @retval none.
263 */
264 void dma_flag_clear(uint32_t dmax_flag)
265 {
266 if(dmax_flag > ((uint32_t)0x10000000))
267 {
268 DMA2->clr = (uint32_t)(dmax_flag & 0x0FFFFFFF);
269 }
270 else
271 {
272 DMA1->clr = dmax_flag;
273 }
274 }
275
276 /**
277 * @brief dma init config with its default value.
278 * @param dma_init_struct: pointer to a dma_init_type structure which will be initialized.
279 * @retval none.
280 */
281 void dma_default_para_init(dma_init_type *dma_init_struct)
282 {
283 dma_init_struct->peripheral_base_addr = 0;
284 dma_init_struct->memory_base_addr = 0;
285 dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
286 dma_init_struct->buffer_size = 0;
287 dma_init_struct->peripheral_inc_enable = FALSE;
288 dma_init_struct->memory_inc_enable = FALSE;
289 dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
290 dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
291 dma_init_struct->loop_mode_enable = FALSE;
292 dma_init_struct->priority = DMA_PRIORITY_LOW;
293 }
294
295 /**
296 * @brief dma init.
297 * @param dmax_channely:
298 * this parameter can be one of the following values:
299 * - DMA1_CHANNEL1
300 * - DMA1_CHANNEL2
301 * - DMA1_CHANNEL3
302 * - DMA1_CHANNEL4
303 * - DMA1_CHANNEL5
304 * - DMA1_CHANNEL6
305 * - DMA1_CHANNEL7
306 * - DMA2_CHANNEL1
307 * - DMA2_CHANNEL2
308 * - DMA2_CHANNEL3
309 * - DMA2_CHANNEL4
310 * - DMA2_CHANNEL5
311 * - DMA2_CHANNEL6
312 * - DMA2_CHANNEL7
313 * @param dma_init_struct: pointer to a dma_init_type structure.
314 * @retval none.
315 */
316 void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct)
317 {
318 /* clear ctrl register dtd bit and m2m bit */
319 dmax_channely->ctrl &= 0xbfef;
320 dmax_channely->ctrl |= dma_init_struct->direction;
321
322 dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
323 dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
324 dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
325 dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
326 dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
327 dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
328 dmax_channely->dtcnt_bit.cnt = dma_init_struct->buffer_size;
329 dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
330 dmax_channely->maddr = dma_init_struct->memory_base_addr;
331 }
332 /**
333 * @brief dmamux init.
334 * @param dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
335 * @param dmamux_channelx:
336 * this parameter can be one of the following values:
337 * - DMA1MUX_CHANNEL1
338 * - DMA1MUX_CHANNEL2
339 * - DMA1MUX_CHANNEL3
340 * - DMA1MUX_CHANNEL4
341 * - DMA1MUX_CHANNEL5
342 * - DMA1MUX_CHANNEL6
343 * - DMA1MUX_CHANNEL7
344 * - DMA2MUX_CHANNEL1
345 * - DMA2MUX_CHANNEL2
346 * - DMA2MUX_CHANNEL3
347 * - DMA2MUX_CHANNEL4
348 * - DMA2MUX_CHANNEL5
349 * - DMA2MUX_CHANNEL6
350 * - DMA2MUX_CHANNEL7
351 * @param dmamux_req_sel:
352 * this parameter can be one of the following values:
353 * - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
354 * - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_ADC2 - DMAMUX_DMAREQ_ID_ADC3 - DMAMUX_DMAREQ_ID_DAC1
355 * - DMAMUX_DMAREQ_ID_DAC2 - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW- DMAMUX_DMAREQ_ID_TMR7_OVERFLOW- DMAMUX_DMAREQ_ID_SPI1_RX
356 * - DMAMUX_DMAREQ_ID_SPI1_TX - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_SPI3_RX
357 * - DMAMUX_DMAREQ_ID_SPI3_TX - DMAMUX_DMAREQ_ID_SPI4_RX - DMAMUX_DMAREQ_ID_SPI4_TX - DMAMUX_DMAREQ_ID_I2S2_EXT_RX
358 * - DMAMUX_DMAREQ_ID_I2S2_EXT_TX - DMAMUX_DMAREQ_ID_I2S3_EXT_RX - DMAMUX_DMAREQ_ID_I2S3_EXT_TX - DMAMUX_DMAREQ_ID_I2C1_RX
359 * - DMAMUX_DMAREQ_ID_I2C1_TX - DMAMUX_DMAREQ_ID_I2C2_RX - DMAMUX_DMAREQ_ID_I2C2_TX - DMAMUX_DMAREQ_ID_I2C3_RX
360 * - DMAMUX_DMAREQ_ID_I2C3_TX - DMAMUX_DMAREQ_ID_USART1_RX - DMAMUX_DMAREQ_ID_USART1_TX - DMAMUX_DMAREQ_ID_USART2_RX
361 * - DMAMUX_DMAREQ_ID_USART2_TX - DMAMUX_DMAREQ_ID_USART3_RX - DMAMUX_DMAREQ_ID_USART3_TX - DMAMUX_DMAREQ_ID_UART4_RX
362 * - DMAMUX_DMAREQ_ID_UART4_TX - DMAMUX_DMAREQ_ID_UART5_RX - DMAMUX_DMAREQ_ID_UART5_TX - DMAMUX_DMAREQ_ID_USART6_RX
363 * - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX
364 * - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1
365 * - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3
366 * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM
367 * - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4
368 * - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1
369 * - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
370 * - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3
371 * - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1
372 * - DMAMUX_DMAREQ_ID_TMR4_CH2 - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
373 * - DMAMUX_DMAREQ_ID_TMR4_TRIG - DMAMUX_DMAREQ_ID_TMR5_CH1 - DMAMUX_DMAREQ_ID_TMR5_CH2 - DMAMUX_DMAREQ_ID_TMR5_CH3
374 * - DMAMUX_DMAREQ_ID_TMR5_CH4 - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW- DMAMUX_DMAREQ_ID_TMR5_TRIG - DMAMUX_DMAREQ_ID_TMR20_CH1
375 * - DMAMUX_DMAREQ_ID_TMR20_CH2 - DMAMUX_DMAREQ_ID_TMR20_CH3 - DMAMUX_DMAREQ_ID_TMR20_CH4 - DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
376 * - DMAMUX_DMAREQ_ID_TMR20_TRIG - DMAMUX_DMAREQ_ID_TMR20_HALL - DMAMUX_DMAREQ_ID_DVP
377 * @retval none.
378 */
379 void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
380 {
381 dma_x->muxsel_bit.tblsel = TRUE;
382 dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
383 }
384
385 /**
386 * @brief enable or disable the dmamux.
387 * @param dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
388 * @param new_state (TRUE or FALSE) .
389 * @retval none.
390 */
391 void dmamux_enable(dma_type *dma_x, confirm_state new_state)
392 {
393 dma_x->muxsel_bit.tblsel = new_state;
394 }
395
396 /**
397 * @brief dmamux init.
398 * @param dmamux_channelx:
399 * this parameter can be one of the following values:
400 * - DMA1MUX_CHANNEL1
401 * - DMA1MUX_CHANNEL2
402 * - DMA1MUX_CHANNEL3
403 * - DMA1MUX_CHANNEL4
404 * - DMA1MUX_CHANNEL5
405 * - DMA1MUX_CHANNEL6
406 * - DMA1MUX_CHANNEL7
407 * - DMA2MUX_CHANNEL1
408 * - DMA2MUX_CHANNEL2
409 * - DMA2MUX_CHANNEL3
410 * - DMA2MUX_CHANNEL4
411 * - DMA2MUX_CHANNEL5
412 * - DMA2MUX_CHANNEL6
413 * - DMA2MUX_CHANNEL7
414 * @param dmamux_req_sel:
415 * this parameter can be one of the following values:
416 * - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
417 * - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_ADC2 - DMAMUX_DMAREQ_ID_ADC3 - DMAMUX_DMAREQ_ID_DAC1
418 * - DMAMUX_DMAREQ_ID_DAC2 - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW- DMAMUX_DMAREQ_ID_TMR7_OVERFLOW- DMAMUX_DMAREQ_ID_SPI1_RX
419 * - DMAMUX_DMAREQ_ID_SPI1_TX - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_SPI3_RX
420 * - DMAMUX_DMAREQ_ID_SPI3_TX - DMAMUX_DMAREQ_ID_SPI4_RX - DMAMUX_DMAREQ_ID_SPI4_TX - DMAMUX_DMAREQ_ID_I2S2_EXT_RX
421 * - DMAMUX_DMAREQ_ID_I2S2_EXT_TX - DMAMUX_DMAREQ_ID_I2S3_EXT_RX - DMAMUX_DMAREQ_ID_I2S3_EXT_TX - DMAMUX_DMAREQ_ID_I2C1_RX
422 * - DMAMUX_DMAREQ_ID_I2C1_TX - DMAMUX_DMAREQ_ID_I2C2_RX - DMAMUX_DMAREQ_ID_I2C2_TX - DMAMUX_DMAREQ_ID_I2C3_RX
423 * - DMAMUX_DMAREQ_ID_I2C3_TX - DMAMUX_DMAREQ_ID_USART1_RX - DMAMUX_DMAREQ_ID_USART1_TX - DMAMUX_DMAREQ_ID_USART2_RX
424 * - DMAMUX_DMAREQ_ID_USART2_TX - DMAMUX_DMAREQ_ID_USART3_RX - DMAMUX_DMAREQ_ID_USART3_TX - DMAMUX_DMAREQ_ID_UART4_RX
425 * - DMAMUX_DMAREQ_ID_UART4_TX - DMAMUX_DMAREQ_ID_UART5_RX - DMAMUX_DMAREQ_ID_UART5_TX - DMAMUX_DMAREQ_ID_USART6_RX
426 * - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX
427 * - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1
428 * - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3
429 * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM
430 * - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4
431 * - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1
432 * - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
433 * - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3
434 * - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1
435 * - DMAMUX_DMAREQ_ID_TMR4_CH2 - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
436 * - DMAMUX_DMAREQ_ID_TMR4_TRIG - DMAMUX_DMAREQ_ID_TMR5_CH1 - DMAMUX_DMAREQ_ID_TMR5_CH2 - DMAMUX_DMAREQ_ID_TMR5_CH3
437 * - DMAMUX_DMAREQ_ID_TMR5_CH4 - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW- DMAMUX_DMAREQ_ID_TMR5_TRIG - DMAMUX_DMAREQ_ID_TMR20_CH1
438 * - DMAMUX_DMAREQ_ID_TMR20_CH2 - DMAMUX_DMAREQ_ID_TMR20_CH3 - DMAMUX_DMAREQ_ID_TMR20_CH4 - DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
439 * - DMAMUX_DMAREQ_ID_TMR20_TRIG - DMAMUX_DMAREQ_ID_TMR20_HALL - DMAMUX_DMAREQ_ID_DVP
440 * @retval none.
441 */
442 void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
443 {
444 dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
445 }
446
447 /**
448 * @brief dmamux sync init struct config with its default value.
449 * @param dmamux_sync_init_struct: pointer to a dmamux_sync_init_type structure which will be initialized.
450 * @retval none.
451 */
452 void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct)
453 {
454 dmamux_sync_init_struct->sync_enable = FALSE;
455 dmamux_sync_init_struct->sync_event_enable = FALSE;
456 dmamux_sync_init_struct->sync_polarity = DMAMUX_SYNC_POLARITY_DISABLE;
457 dmamux_sync_init_struct->sync_request_number = 0x0;
458 dmamux_sync_init_struct->sync_signal_sel = (dmamux_sync_id_sel_type)0;
459 }
460
461 /**
462 * @brief dmamux synchronization config.
463 * @param dmamux_channelx:
464 * this parameter can be one of the following values:
465 * - DMA1MUX_CHANNEL1
466 * - DMA1MUX_CHANNEL2
467 * - DMA1MUX_CHANNEL3
468 * - DMA1MUX_CHANNEL4
469 * - DMA1MUX_CHANNEL5
470 * - DMA1MUX_CHANNEL6
471 * - DMA1MUX_CHANNEL7
472 * - DMA2MUX_CHANNEL1
473 * - DMA2MUX_CHANNEL2
474 * - DMA2MUX_CHANNEL3
475 * - DMA2MUX_CHANNEL4
476 * - DMA2MUX_CHANNEL5
477 * - DMA2MUX_CHANNEL6
478 * - DMA2MUX_CHANNEL7
479 * @param dmamux_sync_init_struct: ointer to a dmamux_sync_init_type structure.
480 * @retval none.
481 */
482 void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct)
483 {
484 dmamux_channelx->muxctrl_bit.syncsel = dmamux_sync_init_struct->sync_signal_sel;
485 dmamux_channelx->muxctrl_bit.syncpol = dmamux_sync_init_struct->sync_polarity;
486 dmamux_channelx->muxctrl_bit.reqcnt = dmamux_sync_init_struct->sync_request_number;
487 dmamux_channelx->muxctrl_bit.evtgen = dmamux_sync_init_struct->sync_event_enable;
488 dmamux_channelx->muxctrl_bit.syncen = dmamux_sync_init_struct->sync_enable;
489 }
490
491 /**
492 * @brief dmamux request generator init struct config with its default value.
493 * @param dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
494 * @retval none.
495 */
496 void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct)
497 {
498 dmamux_gen_init_struct->gen_enable = FALSE;
499 dmamux_gen_init_struct->gen_polarity = DMAMUX_GEN_POLARITY_DISABLE;
500 dmamux_gen_init_struct->gen_request_number = 0x0;
501 dmamux_gen_init_struct->gen_signal_sel = (dmamux_gen_id_sel_type)0x0;
502 }
503
504 /**
505 * @brief dmamux request generator init.
506 * @param dmamux_gen_x :
507 * this parameter can be one of the following values:
508 * - DMA1MUX_GENERATOR1
509 * - DMA1MUX_GENERATOR2
510 * - DMA1MUX_GENERATOR3
511 * - DMA1MUX_GENERATOR4
512 * - DMA2MUX_GENERATOR1
513 * - DMA2MUX_GENERATOR2
514 * - DMA2MUX_GENERATOR3
515 * - DMA2MUX_GENERATOR4
516 * @param dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
517 * @retval none.
518 */
519 void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct)
520 {
521 dmamux_gen_x->gctrl_bit.sigsel = dmamux_gen_init_struct->gen_signal_sel;
522 dmamux_gen_x->gctrl_bit.gpol = dmamux_gen_init_struct->gen_polarity;
523 dmamux_gen_x->gctrl_bit.greqcnt = dmamux_gen_init_struct->gen_request_number;
524 dmamux_gen_x->gctrl_bit.gen = dmamux_gen_init_struct->gen_enable;
525 }
526
527 /**
528 * @brief enable or disable the dmamux sync interrupts.
529 * @param dmamux_channelx:
530 * this parameter can be one of the following values:
531 * - DMA1MUX_CHANNEL1
532 * - DMA1MUX_CHANNEL2
533 * - DMA1MUX_CHANNEL3
534 * - DMA1MUX_CHANNEL4
535 * - DMA1MUX_CHANNEL5
536 * - DMA1MUX_CHANNEL6
537 * - DMA1MUX_CHANNEL7
538 * - DMA2MUX_CHANNEL1
539 * - DMA2MUX_CHANNEL2
540 * - DMA2MUX_CHANNEL3
541 * - DMA2MUX_CHANNEL4
542 * - DMA2MUX_CHANNEL5
543 * - DMA2MUX_CHANNEL6
544 * - DMA2MUX_CHANNEL7
545 * @param new_state (TRUE or FALSE).
546 * @retval none.
547 */
548 void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state)
549 {
550 if(new_state != FALSE)
551 {
552 dmamux_channelx->muxctrl_bit.syncovien = TRUE;
553 }
554 else
555 {
556 dmamux_channelx->muxctrl_bit.syncovien = FALSE;
557 }
558 }
559
560 /**
561 * @brief enable or disable the dmamux request generator interrupts.
562 * @param dmamux_gen_x : pointer to a dmamux_generator_type structure.
563 * this parameter can be one of the following values:
564 * - DMA1MUX_GENERATOR1
565 * - DMA1MUX_GENERATOR2
566 * - DMA1MUX_GENERATOR3
567 * - DMA1MUX_GENERATOR4
568 * - DMA2MUX_GENERATOR1
569 * - DMA2MUX_GENERATOR2
570 * - DMA2MUX_GENERATOR3
571 * - DMA2MUX_GENERATOR4
572 * @param new_state (TRUE or FALSE).
573 * @retval none.
574 */
575 void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state)
576 {
577 if(new_state != FALSE)
578 {
579 dmamux_gen_x->gctrl_bit.trgovien = TRUE;
580 }
581 else
582 {
583 dmamux_gen_x->gctrl_bit.trgovien = FALSE;
584 }
585 }
586
587 /**
588 * @brief dmamux sync flag get.
589 * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
590 * @param flag
591 * this parameter can be any combination of the following values:
592 * - DMAMUX_SYNC_OV1_FLAG
593 * - DMAMUX_SYNC_OV2_FLAG
594 * - DMAMUX_SYNC_OV3_FLAG
595 * - DMAMUX_SYNC_OV4_FLAG
596 * - DMAMUX_SYNC_OV5_FLAG
597 * - DMAMUX_SYNC_OV6_FLAG
598 * - DMAMUX_SYNC_OV7_FLAG
599 * @retval state of dmamux sync flag.
600 */
601 flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag)
602 {
603 if((dma_x->muxsyncsts & flag) != RESET)
604 {
605 return SET;
606 }
607 else
608 {
609 return RESET;
610 }
611 }
612
613 /**
614 * @brief dmamux sync flag clear.
615 * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
616 * @param flag
617 * this parameter can be any combination of the following values:
618 * - DMAMUX_SYNC_OV1_FLAG
619 * - DMAMUX_SYNC_OV2_FLAG
620 * - DMAMUX_SYNC_OV3_FLAG
621 * - DMAMUX_SYNC_OV4_FLAG
622 * - DMAMUX_SYNC_OV5_FLAG
623 * - DMAMUX_SYNC_OV6_FLAG
624 * - DMAMUX_SYNC_OV7_FLAG
625 * @retval none.
626 */
627 void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag)
628 {
629 dma_x->muxsyncclr = flag;
630 }
631
632 /**
633 * @brief dmamux request generator flag get.
634 * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
635 * @param flag
636 * this parameter can be any combination of the following values:
637 * - DMAMUX_GEN_TRIG_OV1_FLAG
638 * - DMAMUX_GEN_TRIG_OV2_FLAG
639 * - DMAMUX_GEN_TRIG_OV3_FLAG
640 * - DMAMUX_GEN_TRIG_OV4_FLAG
641 * @retval state of dmamux sync flag.
642 */
643 flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag)
644 {
645 if((dma_x->muxgsts & flag) != RESET)
646 {
647 return SET;
648 }
649 else
650 {
651 return RESET;
652 }
653 }
654
655 /**
656 * @brief dmamux request generator flag clear.
657 * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
658 * @param flag
659 * this parameter can be any combination of the following values:
660 * - DMAMUX_GEN_TRIG_OV1_FLAG
661 * - DMAMUX_GEN_TRIG_OV2_FLAG
662 * - DMAMUX_GEN_TRIG_OV3_FLAG
663 * - DMAMUX_GEN_TRIG_OV4_FLAG
664 * @retval none.
665 */
666 void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag)
667 {
668 dma_x->muxgclr = flag;
669 }
670
671 /**
672 * @}
673 */
674
675 #endif
676
677 /**
678 * @}
679 */
680
681 /**
682 * @}
683 */
INAV: Navigation-enabled flight control software