lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_qspi.c

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_qspi.c
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    contain all the functions for qspi firmware library
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 #include "at32f435_437_conf.h"
  28
  29 /** @addtogroup AT32F435_437_periph_driver
  30   * @{
  31   */
  32
  33 /** @defgroup QSPI
  34   * @brief QSPI driver modules
  35   * @{
  36   */
  37
  38 #ifdef QSPI_MODULE_ENABLED
  39
  40 /** @defgroup QSPI_private_functions
  41   * @{
  42   */
  43
  44 /**
  45   * @brief  enable/disable encryption for qspi.
  46   * @note   the function must be configured only when qspi in command-port mode!!!
  47   * @param  qspi_x: select the qspi peripheral.
  48   *         this parameter can be one of the following values:
  49   *         QSPI1,QSPI2.
  50   * @param  new_state (TRUE or FALSE)
  51   * @retval none
  52   */
  53 void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state)
  54 {
  55   qspi_x->ctrl_bit.keyen = new_state;
  56 }
  57
  58 /**
  59   * @brief  set qspi sck mode.
  60   * @note   the function must be configured only when qspi in command-port mode!!!
  61   * @param  qspi_x: select the qspi peripheral.
  62   *         this parameter can be one of the following values:
  63   *         QSPI1,QSPI2.
  64   * @param  new_mode: new state to be set
  65   *         this parameter can be one of the following values:
  66   *         - QSPI_SCK_MODE_0
  67   *         - QSPI_SCK_MODE_3
  68   * @retval none
  69   */
  70 void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode)
  71 {
  72   qspi_x->ctrl_bit.sckmode = new_mode;
  73 }
  74
  75 /**
  76   * @brief  set qspi clock division
  77   * @note   the function must be configured only when qspi in command-port mode!!!
  78   * @param  qspi_x: select the qspi peripheral.
  79   *         this parameter can be one of the following values:
  80   *         QSPI1,QSPI2.
  81   * @param  new_clkdiv: new division value
  82   *         this parameter can be one of the following values:
  83   *         - QSPI_CLK_DIV_2
  84   *         - QSPI_CLK_DIV_4
  85   *         - QSPI_CLK_DIV_6
  86   *         - QSPI_CLK_DIV_8
  87   *         - QSPI_CLK_DIV_3
  88   *         - QSPI_CLK_DIV_5
  89   *         - QSPI_CLK_DIV_10
  90   *         - QSPI_CLK_DIV_12
  91   * @retval none
  92   */
  93 void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv)
  94 {
  95   qspi_x->ctrl_bit.clkdiv = new_clkdiv;
  96 }
  97
  98 /**
  99   * @brief  enable/disable cache in xip mode
 100   * @note   the function must be configured only when qspi in command-port mode!!!
 101   * @param  qspi_x: select the qspi peripheral.
 102   *         this parameter can be one of the following values:
 103   *         QSPI1,QSPI2.
 104   * @param  new_state (TRUE or FALSE)
 105   * @retval none
 106   */
 107 void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state)
 108 {
 109   qspi_x->xip_cmd_w3_bit.bypassc = new_state;
 110 }
 111
 112 /**
 113   * @brief  enable/disable interrupt when command is completed
 114   * @note   the function must be configured only when qspi in command-port mode!!!
 115   * @param  qspi_x: select the qspi peripheral.
 116   *         this parameter can be one of the following values:
 117   *         QSPI1,QSPI2.
 118   * @param  new_state (TRUE or FALSE)
 119   * @retval none
 120   */
 121 void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state)
 122 {
 123   qspi_x->ctrl2_bit.cmdie = new_state;
 124 }
 125
 126 /**
 127   * @brief  get status flags.
 128   * @param  qspi_x: select the qspi peripheral.
 129   *         this parameter can be one of the following values:
 130   *         QSPI1,QSPI2.
 131   * @param  flag: specifies the flag to check.
 132   *         this parameter can be one of the following values:
 133   *         - QSPI_RXFIFORDY_FLAG
 134   *         - QSPI_TXFIFORDY_FLAG
 135   *         - QSPI_CMDSTS_FLAG
 136   * @retval the new state of usart_flag (SET or RESET).
 137   */
 138 flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
 139 {
 140   flag_status bit_status = RESET;
 141   switch(flag)
 142   {
 143     case QSPI_RXFIFORDY_FLAG:
 144       bit_status = (flag_status)qspi_x->fifosts_bit.rxfifordy;
 145       break;
 146     case QSPI_TXFIFORDY_FLAG:
 147       bit_status = (flag_status)qspi_x->fifosts_bit.txfifordy;
 148       break;
 149     case QSPI_CMDSTS_FLAG:
 150       bit_status = (flag_status)qspi_x->cmdsts_bit.cmdsts;
 151       break;
 152     default:
 153       break;
 154   }
 155   return bit_status;
 156 }
 157
 158 /**
 159   * @brief  clear flags
 160   * @param  qspi_x: select the qspi peripheral.
 161   *         this parameter can be one of the following values:
 162   *         QSPI1,QSPI2.
 163   * @param  flag: flags to be clear
 164   *         this parameter can be one of the following values:
 165   *         - QSPI_CMDSTS_FLAG
 166   * @retval none
 167   */
 168 void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag)
 169 {
 170   UNUSED(flag);
 171   qspi_x->cmdsts = QSPI_CMDSTS_FLAG;
 172 }
 173
 174 /**
 175   * @brief  set dma threshold for dma rx
 176   * @note   the function must be configured only when qspi in command-port mode!!!
 177   * @param  qspi_x: select the qspi peripheral.
 178   *         this parameter can be one of the following values:
 179   *         QSPI1,QSPI2.
 180   * @param  new_threshold: value to set
 181   *         this parameter can be one of the following values:
 182   *         - QSPI_DMA_FIFO_THOD_WORD08
 183   *         - QSPI_DMA_FIFO_THOD_WORD16
 184   *         - QSPI_DMA_FIFO_THOD_WORD32
 185   * @retval none
 186   */
 187 void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
 188 {
 189   qspi_x->ctrl2_bit.rxfifo_thod = new_threshold;
 190 }
 191
 192 /**
 193   * @brief  set dma threshold for dma tx
 194   * @note   the function must be configured only when qspi in command-port mode!!!
 195   * @param  qspi_x: select the qspi peripheral.
 196   *         this parameter can be one of the following values:
 197   *         QSPI1,QSPI2.
 198   * @param  new_threshold: value to set
 199   *         this parameter can be one of the following values:
 200   *         - QSPI_DMA_FIFO_THOD_WORD08
 201   *         - QSPI_DMA_FIFO_THOD_WORD16
 202   *         - QSPI_DMA_FIFO_THOD_WORD32
 203   * @retval none
 204   */
 205 void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
 206 {
 207   qspi_x->ctrl2_bit.txfifo_thod = new_threshold;
 208 }
 209
 210 /**
 211   * @brief  enable/disable dma transfer
 212   * @note   the function must be configured only when qspi in command-port mode!!!
 213   * @param  qspi_x: select the qspi peripheral.
 214   *         this parameter can be one of the following values:
 215   *         QSPI1,QSPI2.
 216   * @param  new_state (TRUE or FALSE)
 217   * @retval none
 218   */
 219 void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state)
 220 {
 221   qspi_x->ctrl2_bit.dmaen = new_state;
 222 }
 223
 224 /**
 225   * @brief  set wip position in status register of flash
 226   * @note   the function must be configured only when qspi in command-port mode!!!
 227   * @param  qspi_x: select the qspi peripheral.
 228   *         this parameter can be one of the following values:
 229   *         QSPI1,QSPI2.
 230   * @param  busy_pos: value to set
 231   *         this parameter can be one of the following values:
 232   *         - QSPI_BUSY_OFFSET_0
 233   *         - QSPI_BUSY_OFFSET_1
 234   *         - QSPI_BUSY_OFFSET_2
 235   *         - QSPI_BUSY_OFFSET_3
 236   *         - QSPI_BUSY_OFFSET_4
 237   *         - QSPI_BUSY_OFFSET_5
 238   *         - QSPI_BUSY_OFFSET_6
 239   *         - QSPI_BUSY_OFFSET_7
 240   * @retval none
 241   */
 242 void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos)
 243 {
 244   qspi_x->ctrl_bit.busy = busy_pos;
 245 }
 246
 247 /**
 248   * @brief  enable xip mode or command-port mode.
 249   * @param  qspi_x: select the qspi peripheral.
 250   *         this parameter can be one of the following values:
 251   *         QSPI1,QSPI2.
 252   * @param  new_state (TRUE or FALSE)
 253   * @retval none
 254   */
 255 void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state)
 256 {
 257   /* skip if state is no change */
 258   if(new_state == (confirm_state)(qspi_x->ctrl_bit.xipsel))
 259   {
 260     return;
 261   }
 262
 263   /* wait until tx fifo emoty*/
 264   while(qspi_x->fifosts_bit.txfifordy == 0);
 265
 266   /* flush and reset qspi state */
 267   qspi_x->ctrl_bit.xiprcmdf = 1;
 268
 269   /* wait until action is finished */
 270   while(qspi_x->ctrl_bit.abort);
 271
 272   /* set xip mode to new state */
 273   qspi_x->ctrl_bit.xipsel = new_state;
 274
 275   /* wait until abort is not set */
 276   while(qspi_x->ctrl_bit.abort);
 277
 278   /* wait until cache status valid*/
 279   if(new_state == TRUE)
 280   {
 281     while( qspi_x->xip_cmd_w3_bit.csts );
 282   }
 283 }
 284
 285 /**
 286   * @brief  set command-port and qspi_x will start to work
 287   * @param  qspi_x: select the qspi peripheral.
 288   *         this parameter can be one of the following values:
 289   *         QSPI1,QSPI2.
 290   * @param  qspi_cmd_struct: pointer to qspi cmd structure
 291   * @retval none
 292   */
 293 void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct)
 294 {
 295   uint32_t w1_val = 0, w3_val = 0;
 296
 297   /* config analyse cmd_w0 register */
 298   qspi_x->cmd_w0 = (uint32_t)qspi_cmd_struct->address_code;
 299
 300   /* config analyse cmd_w1 register */
 301   w1_val = (uint32_t)qspi_cmd_struct->address_length;
 302   w1_val |= (uint32_t)(qspi_cmd_struct->second_dummy_cycle_num << 16);
 303   w1_val |= (uint32_t)(qspi_cmd_struct->instruction_length << 24);
 304   w1_val |= (uint32_t)(qspi_cmd_struct->pe_mode_enable << 28);
 305   qspi_x->cmd_w1 = w1_val;
 306
 307   /* config analyse cmd_w2 register */
 308   qspi_x->cmd_w2 = (uint32_t)qspi_cmd_struct->data_counter;
 309
 310   /* config analyse cmd_w3 register */
 311   w3_val = (uint32_t)(qspi_cmd_struct->write_data_enable << 1);
 312   w3_val |= (uint32_t)(qspi_cmd_struct->read_status_enable << 2);
 313   w3_val |= (uint32_t)(qspi_cmd_struct->read_status_config << 3);
 314   w3_val |= (uint32_t)(qspi_cmd_struct->operation_mode << 5);
 315   w3_val |= (uint32_t)(qspi_cmd_struct->pe_mode_operate_code << 16);
 316   w3_val |= (uint32_t)(qspi_cmd_struct->instruction_code << 24);
 317   qspi_x->cmd_w3 = w3_val;
 318 }
 319
 320 /**
 321   * @brief  initial xip mode for qspi_x
 322   * @param  qspi_x: select the qspi peripheral.
 323   *         this parameter can be one of the following values:
 324   *         QSPI1,QSPI2.
 325   * @param  xip_init_struct: pointer to xip init structure.
 326   * @retval none.
 327   */
 328 void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct)
 329 {
 330   uint32_t xc0_val = 0, xc1_val = 0, xc2_val = 0;
 331   /* config analyse xip_cmd_w0 register */
 332   xc0_val = (uint32_t)xip_init_struct->read_second_dummy_cycle_num;
 333   xc0_val |= (uint32_t)(xip_init_struct->read_operation_mode << 8);
 334   xc0_val |= (uint32_t)(xip_init_struct->read_address_length << 11);
 335   xc0_val |= (uint32_t)(xip_init_struct->read_instruction_code << 12);
 336   qspi_x->xip_cmd_w0 = xc0_val;
 337
 338   /* config analyse xip_cmd_w1 register */
 339   xc1_val = (uint32_t)xip_init_struct->write_second_dummy_cycle_num;
 340   xc1_val |= (uint32_t)(xip_init_struct->write_operation_mode << 8);
 341   xc1_val |= (uint32_t)(xip_init_struct->write_address_length << 11);
 342   xc1_val |= (uint32_t)(xip_init_struct->write_instruction_code << 12);
 343   qspi_x->xip_cmd_w1 = xc1_val;
 344
 345   /* config analyse xip_cmd_w2 register */
 346   xc2_val = (uint32_t)xip_init_struct->read_data_counter;
 347   xc2_val |= (uint32_t)(xip_init_struct->read_time_counter << 8);
 348   xc2_val |= (uint32_t)(xip_init_struct->read_select_mode << 15);
 349   xc2_val |= (uint32_t)(xip_init_struct->write_data_counter << 16);
 350   xc2_val |= (uint32_t)(xip_init_struct->write_time_counter << 24);
 351   xc2_val |= (uint32_t)(xip_init_struct->write_select_mode << 31);
 352   qspi_x->xip_cmd_w2 = xc2_val;
 353 }
 354
 355 /**
 356   * @brief  read one byte from qspi device in command mode
 357   * @param  qspi_x: select the qspi peripheral.
 358   * @retval 8-bit data.
 359   */
 360 uint8_t qspi_byte_read(qspi_type* qspi_x)
 361 {
 362   return qspi_x->dt_u8;
 363 }
 364
 365 /**
 366   * @brief  read one half-word from qspi device in command mode
 367   * @param  qspi_x: select the qspi peripheral.
 368   * @retval 16-bit data.
 369   */
 370 uint16_t qspi_half_word_read(qspi_type* qspi_x)
 371 {
 372   return qspi_x->dt_u16;
 373 }
 374
 375 /**
 376   * @brief  read one word from qspi device in command mode
 377   * @param  qspi_x: select the qspi peripheral.
 378   * @retval 32-bit data.
 379   */
 380 uint32_t qspi_word_read(qspi_type* qspi_x)
 381 {
 382   return qspi_x->dt;
 383 }
 384
 385 /**
 386   * @brief  write one byte to qspi device in command mode
 387   * @param  qspi_x: select the qspi peripheral.
 388   * @param  value:  8-bit data.
 389   * @retval none.
 390   */
 391 void qspi_byte_write(qspi_type* qspi_x, uint8_t value)
 392 {
 393   qspi_x->dt_u8 = value;
 394 }
 395
 396 /**
 397   * @brief  write one half-word to qspi device in command mode
 398   * @param  qspi_x: select the qspi peripheral.
 399   * @param  value:  16-bit data.
 400   * @retval none.
 401   */
 402 void qspi_half_word_write(qspi_type* qspi_x, uint16_t value)
 403 {
 404   qspi_x->dt_u16 = value;
 405 }
 406
 407 /**
 408   * @brief  write one word to qspi device in command mode
 409   * @param  qspi_x: select the qspi peripheral.
 410   * @param  value:  32-bit data.
 411   * @retval none.
 412   */
 413 void qspi_word_write(qspi_type* qspi_x, uint32_t value)
 414 {
 415   qspi_x->dt = value;
 416 }
 417
 418 /**
 419   * @}
 420   */
 421
 422 #endif
 423
 424 /**
 425   * @}
 426   */
 427
 428 /**
 429   * @}
 430   */