lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_scfg.c

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_scfg.c
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    contains all the functions for the system config firmware library
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 #include "at32f435_437_conf.h"
  28
  29 /** @addtogroup AT32F435_437_periph_driver
  30   * @{
  31   */
  32
  33 /** @defgroup SCFG
  34   * @brief SCFG driver modules
  35   * @{
  36   */
  37
  38 #ifdef SCFG_MODULE_ENABLED
  39
  40 /** @defgroup SCFG_private_functions
  41   * @{
  42   */
  43
  44 /**
  45   * @brief  scfg reset
  46   * @param  none
  47   * @retval none
  48   */
  49 void scfg_reset(void)
  50 {
  51   crm_periph_reset(CRM_SCFG_PERIPH_RESET, TRUE);
  52   crm_periph_reset(CRM_SCFG_PERIPH_RESET, FALSE);
  53 }
  54
  55 /**
  56   * @brief  scfg xmc address mapping swap set
  57   * @param  xmc_swap
  58   *         this parameter can be one of the following values:
  59   *         - SCFG_XMC_SWAP_NONE
  60   *         - SCFG_XMC_SWAP_MODE1
  61   *         - SCFG_XMC_SWAP_MODE2
  62   *         - SCFG_XMC_SWAP_MODE3
  63   * @retval none
  64   */
  65 void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap)
  66 {
  67   SCFG->cfg1_bit.swap_xmc = xmc_swap;
  68 }
  69
  70 /**
  71   * @brief  scfg infrared config
  72   * @param  source
  73   *         this parameter can be one of the following values:
  74   *         - SCFG_IR_SOURCE_TMR10
  75   *         - SCFG_IR_SOURCE_USART1
  76   *         - SCFG_IR_SOURCE_USART2
  77   * @param  polarity
  78   *         this parameter can be one of the following values:
  79   *         - SCFG_IR_POLARITY_NO_AFFECTE
  80   *         - SCFG_IR_POLARITY_REVERSE
  81   * @retval none
  82   */
  83 void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity)
  84 {
  85   SCFG->cfg1_bit.ir_src_sel = source;
  86   SCFG->cfg1_bit.ir_pol = polarity;
  87 }
  88
  89 /**
  90   * @brief  scfg memory address mapping set
  91   * @param  mem_map
  92   *         this parameter can be one of the following values:
  93   *         - SCFG_MEM_MAP_MAIN_MEMORY
  94   *         - SCFG_MEM_MAP_BOOT_MEMORY
  95   *         - SCFG_MEM_MAP_XMC_BANK1
  96   *         - SCFG_MEM_MAP_INTERNAL_SRAM
  97   *         - SCFG_MEM_MAP_XMC_SDRAM_BANK1
  98   * @retval none
  99   */
 100 void scfg_mem_map_set(scfg_mem_map_type mem_map)
 101 {
 102   SCFG->cfg1_bit.mem_map_sel = mem_map;
 103 }
 104
 105 /**
 106   * @brief  scfg emac interface set
 107   * @param  mode
 108   *         this parameter can be one of the following values:
 109   *         - SCFG_EMAC_SELECT_MII
 110   *         - SCFG_EMAC_SELECT_RMII
 111   * @retval none
 112   */
 113 void scfg_emac_interface_set(scfg_emac_interface_type mode)
 114 {
 115   SCFG->cfg2_bit.mii_rmii_sel = mode;
 116 }
 117
 118 /**
 119   * @brief  select the gpio pin used as exint line.
 120   * @param  port_source:
 121   *         select the gpio port to be used as source for exint lines.
 122   *         this parameter can be one of the following values:
 123   *         - SCFG_PORT_SOURCE_GPIOA
 124   *         - SCFG_PORT_SOURCE_GPIOB
 125   *         - SCFG_PORT_SOURCE_GPIOC
 126   *         - SCFG_PORT_SOURCE_GPIOD
 127   *         - SCFG_PORT_SOURCE_GPIOE
 128   *         - SCFG_PORT_SOURCE_GPIOF
 129   *         - SCFG_PORT_SOURCE_GPIOG
 130   *         - SCFG_PORT_SOURCE_GPIOH
 131   * @param  pin_source:
 132   *         specifies the exint line to be configured.
 133   *         this parameter can be one of the following values:
 134   *         - SCFG_PINS_SOURCE0
 135   *         - SCFG_PINS_SOURCE1
 136   *         - SCFG_PINS_SOURCE2
 137   *         - SCFG_PINS_SOURCE3
 138   *         - SCFG_PINS_SOURCE4
 139   *         - SCFG_PINS_SOURCE5
 140   *         - SCFG_PINS_SOURCE6
 141   *         - SCFG_PINS_SOURCE7
 142   *         - SCFG_PINS_SOURCE8
 143   *         - SCFG_PINS_SOURCE9
 144   *         - SCFG_PINS_SOURCE10
 145   *         - SCFG_PINS_SOURCE11
 146   *         - SCFG_PINS_SOURCE12
 147   *         - SCFG_PINS_SOURCE13
 148   *         - SCFG_PINS_SOURCE14
 149   *         - SCFG_PINS_SOURCE15
 150   * @retval none
 151   */
 152 void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source)
 153 {
 154   uint32_t tmp = 0x00;
 155   tmp = ((uint32_t)0x0F) << (0x04 * (pin_source & (uint8_t)0x03));
 156
 157   switch (pin_source >> 0x02)
 158   {
 159     case 0:
 160       SCFG->exintc1 &= ~tmp;
 161       SCFG->exintc1 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
 162       break;
 163     case 1:
 164       SCFG->exintc2 &= ~tmp;
 165       SCFG->exintc2 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
 166       break;
 167     case 2:
 168       SCFG->exintc3 &= ~tmp;
 169       SCFG->exintc3 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
 170       break;
 171     case 3:
 172       SCFG->exintc4 &= ~tmp;
 173       SCFG->exintc4 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
 174       break;
 175     default:
 176       break;
 177   }
 178 }
 179
 180 /**
 181   * @brief  enable or disable gpio pins ultra driven.
 182   * @param  value:
 183   *         this parameter can be one of the following values:
 184   *         - SCFG_ULTRA_DRIVEN_PB3
 185   *         - SCFG_ULTRA_DRIVEN_PB9
 186   *         - SCFG_ULTRA_DRIVEN_PB10
 187   *         - SCFG_ULTRA_DRIVEN_PD12
 188   *         - SCFG_ULTRA_DRIVEN_PD13
 189   *         - SCFG_ULTRA_DRIVEN_PD14
 190   *         - SCFG_ULTRA_DRIVEN_PD15
 191   *         - SCFG_ULTRA_DRIVEN_PF14
 192   *         - SCFG_ULTRA_DRIVEN_PF15
 193   * @param  new_state (TRUE or FALSE)
 194   * @retval none
 195   */
 196 void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state)
 197 {
 198   if(TRUE == new_state)
 199   {
 200     SCFG_REG(value) |= SCFG_REG_BIT(value);
 201   }
 202   else
 203   {
 204     SCFG_REG(value) &= ~(SCFG_REG_BIT(value));
 205   }
 206 }
 207
 208 /**
 209   * @}
 210   */
 211
 212 #endif
 213
 214 /**
 215   * @}
 216   */
 217
 218 /**
 219   * @}
 220   */