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[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / src / at32f435_437_xmc.c
blob7cb276832089c41067f39dc25903b17f31933b59
1 /**
2 **************************************************************************
3 * @file at32f435_437_xmc.c
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief contains all the functions for the xmc firmware library
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 #include "at32f435_437_conf.h"
28
29 /** @addtogroup AT32F435_437_periph_driver
30 * @{
31 */
32
33 /** @defgroup XMC
34 * @brief XMC driver modules
35 * @{
36 */
37
38 #ifdef XMC_MODULE_ENABLED
39
40 /** @defgroup XMC_private_functions
41 * @{
42 */
43
44 /**
45 * @brief xmc nor or sram registers reset
46 * @param xmc_subbank
47 * this parameter can be one of the following values:
48 * - XMC_BANK1_NOR_SRAM1
49 * - XMC_BANK1_NOR_SRAM2
50 * - XMC_BANK1_NOR_SRAM3
51 * - XMC_BANK1_NOR_SRAM4
52 * @retval none
53 */
54 void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
55 {
56 /* XMC_BANK1_NORSRAM1 */
57 if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
58 {
59 XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
60 }
61 /* XMC_BANK1_NORSRAM2, XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
62 else
63 {
64 XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
65 }
66 XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
67 XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
68 }
69
70 /**
71 * @brief initialize the xmc nor/sram banks according to the specified
72 * parameters in the xmc_norsraminitstruct.
73 * @param xmc_norsram_init_struct : pointer to a xmc_norsram_init_type
74 * structure that contains the configuration information for
75 * the xmc nor/sram specified banks.
76 * @retval none
77 */
78 void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
79 {
80 /* bank1 nor/sram control register configuration */
81 XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
82 (uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
83 xmc_norsram_init_struct->device |
84 xmc_norsram_init_struct->bus_type |
85 xmc_norsram_init_struct->burst_mode_enable |
86 xmc_norsram_init_struct->asynwait_enable |
87 xmc_norsram_init_struct->wait_signal_lv |
88 xmc_norsram_init_struct->wrapped_mode_enable |
89 xmc_norsram_init_struct->wait_signal_config |
90 xmc_norsram_init_struct->write_enable |
91 xmc_norsram_init_struct->wait_signal_enable |
92 xmc_norsram_init_struct->write_timing_enable |
93 xmc_norsram_init_struct->write_burst_syn;
94
95 /* if nor flash device */
96 if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
97 {
98 XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
99 }
100 }
101
102 /**
103 * @brief initialize the xmc nor/sram banks according to the specified
104 * parameters in the xmc_rw_timing_struct and xmc_w_timing_struct.
105 * @param xmc_rw_timing_struct : pointer to a xmc_norsram_timing_init_type
106 * structure that contains the configuration information for
107 * the xmc nor/sram specified banks.
108 * @param xmc_w_timing_struct : pointer to a xmc_norsram_timing_init_type
109 * structure that contains the configuration information for
110 * the xmc nor/sram specified banks.
111 * @retval none
112 */
113 void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
114 xmc_norsram_timing_init_type* xmc_w_timing_struct)
115 {
116 /* bank1 nor/sram timing register configuration */
117 XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
118 (uint32_t)xmc_rw_timing_struct->addr_setup_time |
119 (xmc_rw_timing_struct->addr_hold_time << 4) |
120 (xmc_rw_timing_struct->data_setup_time << 8) |
121 (xmc_rw_timing_struct->bus_latency_time <<16) |
122 (xmc_rw_timing_struct->clk_psc << 20) |
123 (xmc_rw_timing_struct->data_latency_time << 24) |
124 xmc_rw_timing_struct->mode;
125
126 /* bank1 nor/sram timing register for write configuration, if extended mode is used */
127 if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
128 {
129 XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
130 (uint32_t)xmc_w_timing_struct->addr_setup_time |
131 (xmc_w_timing_struct->addr_hold_time << 4) |
132 (xmc_w_timing_struct->data_setup_time << 8) |
133 (xmc_w_timing_struct->bus_latency_time << 16) |
134 (xmc_w_timing_struct->clk_psc << 20) |
135 (xmc_w_timing_struct->data_latency_time << 24) |
136 xmc_w_timing_struct->mode;
137 }
138 else
139 {
140 XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
141 }
142 }
143
144 /**
145 * @brief fill each xmc_nor_sram_init_struct member with its default value.
146 * @param xmc_nor_sram_init_struct: pointer to a xmc_norsram_init_type
147 * structure which will be initialized.
148 * @retval none
149 */
150 void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
151 {
152 /* reset nor/sram init structure parameters values */
153 xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
154 xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
155 xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
156 xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
157 xmc_nor_sram_init_struct->burst_mode_enable = XMC_BURST_MODE_DISABLE;
158 xmc_nor_sram_init_struct->asynwait_enable = XMC_ASYN_WAIT_DISABLE;
159 xmc_nor_sram_init_struct->wait_signal_lv = XMC_WAIT_SIGNAL_LEVEL_LOW;
160 xmc_nor_sram_init_struct->wrapped_mode_enable = XMC_WRAPPED_MODE_DISABLE;
161 xmc_nor_sram_init_struct->wait_signal_config = XMC_WAIT_SIGNAL_SYN_BEFORE;
162 xmc_nor_sram_init_struct->write_enable = XMC_WRITE_OPERATION_ENABLE;
163 xmc_nor_sram_init_struct->wait_signal_enable = XMC_WAIT_SIGNAL_ENABLE;
164 xmc_nor_sram_init_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
165 xmc_nor_sram_init_struct->write_burst_syn = XMC_WRITE_BURST_SYN_DISABLE;
166 }
167
168 /**
169 * @brief fill each xmc_rw_timing_struct and xmc_w_timing_struct member with its default value.
170 * @param xmc_rw_timing_struct: pointer to a xmc_norsram_timing_init_type
171 * structure which will be initialized.
172 * @param xmc_w_timing_struct: pointer to a xmc_norsram_timing_init_type
173 * structure which will be initialized.
174 * @retval none
175 */
176 void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
177 xmc_norsram_timing_init_type* xmc_w_timing_struct)
178 {
179 xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
180 xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
181 xmc_rw_timing_struct->addr_setup_time = 0xF;
182 xmc_rw_timing_struct->addr_hold_time = 0xF;
183 xmc_rw_timing_struct->data_setup_time = 0xFF;
184 xmc_rw_timing_struct->bus_latency_time = 0xF;
185 xmc_rw_timing_struct->clk_psc = 0xF;
186 xmc_rw_timing_struct->data_latency_time = 0xF;
187 xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
188 xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
189 xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
190 xmc_w_timing_struct->addr_setup_time = 0xF;
191 xmc_w_timing_struct->addr_hold_time = 0xF;
192 xmc_w_timing_struct->data_setup_time = 0xFF;
193 xmc_w_timing_struct->bus_latency_time = 0xF;
194 xmc_w_timing_struct->clk_psc = 0xF;
195 xmc_w_timing_struct->data_latency_time = 0xF;
196 xmc_w_timing_struct->mode = XMC_ACCESS_MODE_A;
197 }
198
199 /**
200 * @brief enable or disable the specified nor/sram memory bank.
201 * @param xmc_subbank
202 * this parameter can be one of the following values:
203 * - XMC_BANK1_NOR_SRAM1
204 * - XMC_BANK1_NOR_SRAM2
205 * - XMC_BANK1_NOR_SRAM3
206 * - XMC_BANK1_NOR_SRAM4
207 * @param new_state (TRUE or FALSE)
208 * @retval none
209 */
210 void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
211 {
212 XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
213 }
214
215 /**
216 * @brief config the bus turnaround phase.
217 * @param xmc_sub_bank
218 * this parameter can be one of the following values:
219 * - XMC_BANK1_NOR_SRAM1
220 * - XMC_BANK1_NOR_SRAM2
221 * - XMC_BANK1_NOR_SRAM3
222 * - XMC_BANK1_NOR_SRAM4
223 * @param w2w_timing :write timing
224 * @param r2r_timing :read timing
225 * @retval none
226 */
227 void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
228 {
229 XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
230 XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
231 }
232
233 /**
234 * @brief xmc nand flash registers reset
235 * @param xmc_bank
236 * this parameter can be one of the following values:
237 * - XMC_BANK2_NAND
238 * - XMC_BANK3_NAND
239 * @retval none
240 */
241 void xmc_nand_reset(xmc_class_bank_type xmc_bank)
242 {
243 /* set the xmc_bank2_nand registers to their reset values */
244 if(xmc_bank == XMC_BANK2_NAND)
245 {
246 XMC_BANK2->bk2ctrl = 0x00000018;
247 XMC_BANK2->bk2is = 0x00000040;
248 XMC_BANK2->bk2tmgatt = 0xFCFCFCFC;
249 XMC_BANK2->bk2tmgmem = 0xFCFCFCFC;
250 }
251 /* set the xmc_bank3_nand registers to their reset values */
252 else
253 {
254 XMC_BANK3->bk3ctrl = 0x00000018;
255 XMC_BANK3->bk3is = 0x00000040;
256 XMC_BANK3->bk3tmgatt = 0xFCFCFCFC;
257 XMC_BANK3->bk3tmgmem = 0xFCFCFCFC;
258 }
259 }
260
261 /**
262 * @brief initialize the xmc nand banks according to the specified
263 * parameters in the xmc_nandinitstruct.
264 * @param xmc_nand_init_struct : pointer to a xmc_nand_init_type
265 * structure that contains the configuration information for the xmc
266 * nand specified banks.
267 * @retval none
268 */
269 void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct)
270 {
271 uint32_t tempctrl = 0x0;
272
273 /* Set the tempctrl value according to xmc_nand_init_struct parameters */
274 tempctrl = (uint32_t)xmc_nand_init_struct->wait_enable |
275 xmc_nand_init_struct->bus_type |
276 xmc_nand_init_struct->ecc_enable |
277 xmc_nand_init_struct->ecc_pagesize |
278 (xmc_nand_init_struct->delay_time_cycle << 9) |
279 (xmc_nand_init_struct->delay_time_ar << 13) |
280 0x00000008;
281
282 /* xmc_bank2_nand registers configuration */
283 if(xmc_nand_init_struct->nand_bank == XMC_BANK2_NAND)
284 {
285 XMC_BANK2->bk2ctrl = tempctrl;
286 }
287 /* xmc_bank3_nand registers configuration */
288 else
289 {
290 XMC_BANK3->bk3ctrl = tempctrl;
291 }
292 }
293
294 /**
295 * @brief initialize the xmc nand banks according to the specified
296 * parameters in the xmc_nandinitstruct.
297 * @param xmc_regular_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
298 * structure that contains the configuration information for the xmc
299 * nand specified banks.
300 * @param xmc_special_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
301 * structure that contains the configuration information for the xmc
302 * nand specified banks.
303 * @retval none
304 */
305 void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
306 xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
307 {
308 uint32_t tempmem = 0x0, tempatt = 0x0;
309
310 /* set the tempmem value according to xmc_nand_init_struct parameters */
311 tempmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
312 (xmc_regular_spacetiming_struct->mem_waite_time << 8) |
313 (xmc_regular_spacetiming_struct->mem_hold_time << 16) |
314 (xmc_regular_spacetiming_struct->mem_hiz_time << 24);
315
316 /* set the tempatt value according to xmc_nand_init_struct parameters */
317 tempatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
318 (xmc_special_spacetiming_struct->mem_waite_time << 8) |
319 (xmc_special_spacetiming_struct->mem_hold_time << 16) |
320 (xmc_special_spacetiming_struct->mem_hiz_time << 24);
321 /* xmc_bank2_nand registers configuration */
322 if(xmc_regular_spacetiming_struct->class_bank == XMC_BANK2_NAND)
323 {
324 XMC_BANK2->bk2tmgatt = tempatt;
325 XMC_BANK2->bk2tmgmem = tempmem;
326 }
327 else
328 {
329 XMC_BANK3->bk3tmgatt = tempatt;
330 XMC_BANK3->bk3tmgmem = tempmem;
331 }
332 }
333
334 /**
335 * @brief fill each xmc_nand_init_struct member with its default value.
336 * @param xmc_nand_init_struct: pointer to a xmc_nand_init_type
337 * structure which will be initialized.
338 * @retval none
339 */
340 void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct)
341 {
342 /* reset nand init structure parameters values */
343 xmc_nand_init_struct->nand_bank = XMC_BANK2_NAND;
344 xmc_nand_init_struct->wait_enable = XMC_WAIT_OPERATION_DISABLE;
345 xmc_nand_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
346 xmc_nand_init_struct->ecc_enable = XMC_ECC_OPERATION_DISABLE;
347 xmc_nand_init_struct->ecc_pagesize = XMC_ECC_PAGESIZE_256_BYTES;
348 xmc_nand_init_struct->delay_time_cycle = 0x0;
349 xmc_nand_init_struct->delay_time_ar = 0x0;
350 }
351
352 /**
353 * @brief fill each xmc_common_spacetiming_struct and xmc_attribute_spacetiming_struct member with its default value.
354 * @param xmc_common_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
355 * structure which will be initialized.
356 * @param xmc_special_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
357 * structure which will be initialized.
358 * @retval none
359 */
360 void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
361 xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
362 {
363 xmc_regular_spacetiming_struct->class_bank = XMC_BANK2_NAND;
364 xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
365 xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
366 xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
367 xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
368 xmc_special_spacetiming_struct->class_bank = XMC_BANK2_NAND;
369 xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
370 xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
371 xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
372 xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
373 }
374
375 /**
376 * @brief enable or disable the specified nand memory bank.
377 * @param xmc_bank: specifies the xmc bank to be used
378 * this parameter can be one of the following values:
379 * - XMC_BANK2_NAND
380 * - XMC_BANK3_NAND
381 * @param new_state (TRUE or FALSE)
382 * @retval none
383 */
384 void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
385 {
386 /* enable or disable the nand bank2 by setting the en bit in the bk2ctrl register */
387 if(xmc_bank == XMC_BANK2_NAND)
388 {
389 XMC_BANK2->bk2ctrl_bit.en = new_state;
390 }
391 /* enable or disable the nand bank3 by setting the en bit in the bk3ctrl register */
392 else
393 {
394 XMC_BANK3->bk3ctrl_bit.en = new_state;
395 }
396 }
397
398 /**
399 * @brief enable or disable the xmc nand ecc feature.
400 * @param xmc_bank: specifies the xmc bank to be used
401 * this parameter can be one of the following values:
402 * - XMC_BANK2_NAND
403 * - XMC_BANK3_NAND
404 * @param new_state (TRUE or FALSE)
405 * @retval none
406 */
407 void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
408 {
409 /* enable the selected nand bank2 ecc function by setting the eccen bit in the bk2ctrl register */
410 if(xmc_bank == XMC_BANK2_NAND)
411 {
412 XMC_BANK2->bk2ctrl_bit.eccen = new_state;
413 }
414 /* enable the selected nand bank3 ecc function by setting the eccen bit in the bk3ctrl register */
415 else
416 {
417 XMC_BANK3->bk3ctrl_bit.eccen = new_state;
418 }
419 }
420
421 /**
422 * @brief return the error correction code register value.
423 * @param xmc_bank: specifies the xmc bank to be used
424 * this parameter can be one of the following values:
425 * - XMC_BANK2_NAND
426 * - XMC_BANK3_NAND
427 * @retval the error correction code (ecc) value.
428 */
429 uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank)
430 {
431 uint32_t eccvaule = 0x0;
432
433 /* get the bk2ecc register value */
434 if(xmc_bank == XMC_BANK2_NAND)
435 {
436 eccvaule = XMC_BANK2->bk2ecc;
437 }
438 /* get the bk3ecc register value */
439 else
440 {
441 eccvaule = XMC_BANK3->bk3ecc;
442 }
443 /* return the error correction code value */
444 return eccvaule;
445 }
446
447 /**
448 * @brief xmc sdram registers reset
449 * @param xmc_bank
450 * this parameter can be one of the following values:
451 * - XMC_SDRAM_BANK1
452 * - XMC_SDRAM_BANK2
453 * @retval none
454 */
455 void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank)
456 {
457 XMC_SDRAM->ctrl[xmc_bank] = 0x000002D0;
458 XMC_SDRAM->tm[xmc_bank] = 0x0FFFFFFF;
459 XMC_SDRAM->cmd = 0x00000000;
460 XMC_SDRAM->rcnt = 0x00000000;
461 XMC_SDRAM->sts = 0x00000000;
462 }
463
464 /**
465 * @brief initialize the xmc sdram banks according to the specified
466 * parameters in the xmc_sdram_init_struct and xmc_sdram_timing_struct.
467 * @param xmc_sdram_init_struct : pointer to a xmc_sdram_init_type
468 * structure that contains the configuration information for the xmc
469 * sdram specified banks.
470 * @param xmc_sdram_timing_struct : pointer to a xmc_sdram_timing_type
471 * structure that contains the configuration information for the xmc
472 * sdram specified banks.
473 * @retval none
474 */
475 void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
476 {
477 if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK1)
478 {
479 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ca = xmc_sdram_init_struct->column_address;
480 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ra = xmc_sdram_init_struct->row_address;
481 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].db = xmc_sdram_init_struct->width;
482 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].inbk = xmc_sdram_init_struct->internel_banks;
483 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].cas = xmc_sdram_init_struct->cas;
484 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].wrp = xmc_sdram_init_struct->write_protection;
485 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
486 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
487 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
488
489 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tmrd = xmc_sdram_timing_struct->tmrd;
490 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].txsr = xmc_sdram_timing_struct->txsr;
491 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tras = xmc_sdram_timing_struct->tras;
492 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
493 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].twr = xmc_sdram_timing_struct->twr;
494 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
495 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trcd = xmc_sdram_timing_struct->trcd;
496 }
497
498 if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK2)
499 {
500 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ca = xmc_sdram_init_struct->column_address;
501 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ra = xmc_sdram_init_struct->row_address;
502 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].db = xmc_sdram_init_struct->width;
503 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].inbk = xmc_sdram_init_struct->internel_banks;
504 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].cas = xmc_sdram_init_struct->cas;
505 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].wrp = xmc_sdram_init_struct->write_protection;
506 /* sdctrl2 bstr is not care */
507 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
508 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
509 /* sdctrl2 clkdiv is not care */
510 XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
511
512 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tmrd = xmc_sdram_timing_struct->tmrd;
513 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].txsr = xmc_sdram_timing_struct->txsr;
514 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tras = xmc_sdram_timing_struct->tras;
515 /* sdtm2 trc is not care */
516 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
517 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].twr = xmc_sdram_timing_struct->twr;
518 /* sdtm2 trp is not care */
519 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
520 XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].trcd = xmc_sdram_timing_struct->trcd;
521 }
522 }
523
524 /**
525 * @brief fill each xmc_sdram_init_struct member with its default value.
526 * @param xmc_sdram_init_struct: pointer to a xmc_sdram_init_type
527 * structure which will be initialized.
528 * @param xmc_sdram_timing_struct: pointer to a xmc_sdram_timing_type
529 * structure which will be initialized.
530 * @retval none
531 */
532 void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
533 {
534 /* reset sdram init structure parameters values */
535 xmc_sdram_init_struct->sdram_bank = XMC_SDRAM_BANK1;
536 xmc_sdram_init_struct->internel_banks = XMC_INBK_4;
537 xmc_sdram_init_struct->clkdiv = XMC_NO_CLK;
538 xmc_sdram_init_struct->write_protection = FALSE;
539 xmc_sdram_init_struct->burst_read = FALSE;
540 xmc_sdram_init_struct->column_address = XMC_COLUMN_8;
541 xmc_sdram_init_struct->row_address = XMC_ROW_11;
542 xmc_sdram_init_struct->cas = XMC_CAS_1;
543 xmc_sdram_init_struct->width = XMC_MEM_WIDTH_8;
544 xmc_sdram_init_struct->read_delay = XMC_READ_DELAY_1;
545
546 xmc_sdram_timing_struct->tmrd = XMC_DELAY_CYCLE_16;
547 xmc_sdram_timing_struct->txsr = XMC_DELAY_CYCLE_16;
548 xmc_sdram_timing_struct->tras = XMC_DELAY_CYCLE_16;
549 xmc_sdram_timing_struct->trc = XMC_DELAY_CYCLE_16;
550 xmc_sdram_timing_struct->twr = XMC_DELAY_CYCLE_16;
551 xmc_sdram_timing_struct->trp = XMC_DELAY_CYCLE_16;
552 xmc_sdram_timing_struct->trcd = XMC_DELAY_CYCLE_16;
553 }
554
555 /**
556 * @brief sdram command confg
557 * @param xmc_sdram_cmd_struct: pointer to a xmc_sdram_cmd_type
558 * structure which will be initialized.
559 * @retval none
560 */
561 void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct)
562 {
563 XMC_SDRAM->cmd = (xmc_sdram_cmd_struct->auto_refresh << 5) |
564 (xmc_sdram_cmd_struct->data << 9) |
565 xmc_sdram_cmd_struct->cmd |
566 xmc_sdram_cmd_struct->cmd_banks;
567 }
568
569
570 /**
571 * @brief get sdram bank status
572 * @param xmc_bank: specifies the xmc bank to be used
573 * this parameter can be one of the following values:
574 * - XMC_SDRAM_BANK1
575 * - XMC_SDRAM_BANK1
576 * @retval the bank status
577 */
578 uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank)
579 {
580 if(xmc_bank == XMC_SDRAM_BANK1)
581 {
582 return ((XMC_SDRAM->sts >> 1) & XMC_STATUS_MASK);
583 }
584 else
585 {
586 return ((XMC_SDRAM->sts >> 3) & XMC_STATUS_MASK);
587 }
588 }
589
590 /**
591 * @brief set sdram refresh counter
592 * @param counter: xmc sdram refresh counter
593 * @retval none
594 */
595 void xmc_sdram_refresh_counter_set(uint32_t counter)
596 {
597 XMC_SDRAM->rcnt_bit.rc = counter;
598 }
599
600 /**
601 * @brief set sdram auto refresh number
602 * @param number: xmc sdram auto refresh number
603 * @retval none
604 */
605 void xmc_sdram_auto_refresh_set(uint32_t number)
606 {
607 XMC_SDRAM->cmd_bit.art = number;
608 }
609
610 /**
611 * @brief enable or disable the specified xmc interrupts.
612 * @param xmc_bank: specifies the xmc bank to be used
613 * this parameter can be one of the following values:
614 * - XMC_BANK2_NAND
615 * - XMC_BANK3_NAND
616 * - XMC_BANK4_PCCARD
617 * - XMC_BANK5_6_SDRAM
618 * @param xmc_int: specifies the xmc interrupt sources to be enabled or disabled.
619 * this parameter can be any combination of the following values:
620 * - XMC_INT_RISING_EDGE
621 * - XMC_INT_LEVEL
622 * - XMC_INT_FALLING_EDGE
623 * - XMC_INT_ERR
624 * @param new_state (TRUE or FALSE)
625 * @retval none
626 */
627 void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
628 {
629 if(new_state != FALSE)
630 {
631 /* enable the selected xmc_bank2 interrupts */
632 if(xmc_bank == XMC_BANK2_NAND)
633 {
634 XMC_BANK2->bk2is |= xmc_int;
635 }
636 /* enable the selected xmc_bank3 interrupts */
637 else if(xmc_bank == XMC_BANK3_NAND)
638 {
639 XMC_BANK3->bk3is |= xmc_int;
640 }
641 /* enable the selected xmc_bank4 interrupts */
642 else if(xmc_bank == XMC_BANK4_PCCARD)
643 {
644 XMC_BANK4->bk4is |= xmc_int;
645 }
646 /* enable the selected xmc_sdram interrupts */
647 else
648 {
649 XMC_SDRAM->rcnt |= xmc_int;
650 }
651 }
652 else
653 {
654 /* disable the selected xmc_bank2 interrupts */
655 if(xmc_bank == XMC_BANK2_NAND)
656 {
657 XMC_BANK2->bk2is &= ~xmc_int;
658 }
659 /* disable the selected xmc_bank3 interrupts */
660 else if(xmc_bank == XMC_BANK3_NAND)
661 {
662 XMC_BANK3->bk3is &= ~xmc_int;
663 }
664 /* disable the selected xmc_bank4 interrupts */
665 else if(xmc_bank == XMC_BANK4_PCCARD)
666 {
667 XMC_BANK4->bk4is &= ~xmc_int;
668 }
669 /* disable the selected xmc_sdram interrupts */
670 else
671 {
672 XMC_SDRAM->rcnt &= ~xmc_int;
673 }
674 }
675 }
676
677 /**
678 * @brief check whether the specified xmc flag is set or not.
679 * @param xmc_bank: specifies the xmc bank to be used
680 * this parameter can be one of the following values:
681 * - XMC_BANK2_NAND
682 * - XMC_BANK3_NAND
683 * - XMC_BANK4_PCCARD
684 * - XMC_BANK5_6_SDRAM
685 * @param xmc_flag: specifies the flag to check.
686 * this parameter can be any combination of the following values:
687 * - XMC_RISINGEDGE_FLAG
688 * - XMC_LEVEL_FLAG
689 * - XMC_FALLINGEDGE_FLAG
690 * - XMC_FEMPT_FLAG
691 * - XMC_BUSY_FLAG
692 * - XMC_ERR_FLAG
693 * @retval none
694 */
695 flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
696 {
697 flag_status status = RESET;
698 uint32_t temp = 0;
699
700 if(xmc_bank == XMC_BANK2_NAND)
701 {
702 temp = XMC_BANK2->bk2is;
703 }
704 else if(xmc_bank == XMC_BANK3_NAND)
705 {
706 temp = XMC_BANK3->bk3is;
707 }
708 else if(xmc_bank == XMC_BANK4_PCCARD)
709 {
710 temp = XMC_BANK4->bk4is;
711 }
712 else
713 {
714 temp = XMC_SDRAM->sts;
715 }
716 /* get the flag status */
717 if((temp & xmc_flag) == RESET)
718 {
719 status = RESET;
720 }
721 else
722 {
723 status = SET;
724 }
725 /* return the flag status */
726 return status;
727 }
728
729 /**
730 * @brief clear the xmc's pending flags.
731 * @param xmc_bank: specifies the xmc bank to be used
732 * this parameter can be one of the following values:
733 * - XMC_BANK2_NAND
734 * - XMC_BANK3_NAND
735 * - XMC_BANK4_PCCARD
736 * - XMC_BANK5_6_SDRAM
737 * @param xmc_flag: specifies the flag to check.
738 * this parameter can be any combination of the following values:
739 * - XMC_RISINGEDGE_FLAG
740 * - XMC_LEVEL_FLAG
741 * - XMC_FALLINGEDGE_FLAG
742 * - XMC_ERR_FLAG
743 * @retval none
744 */
745 void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
746 {
747 __IO uint32_t int_state;
748 if(xmc_bank == XMC_BANK2_NAND)
749 {
750 int_state = XMC_BANK2->bk2is & 0x38; /* keep interrupt state */
751 XMC_BANK2->bk2is = (~(xmc_flag | 0x38) | int_state);
752 }
753 else if(xmc_bank == XMC_BANK3_NAND)
754 {
755 int_state = XMC_BANK3->bk3is & 0x38; /* keep interrupt state */
756 XMC_BANK3->bk3is = (~(xmc_flag | 0x38) | int_state);
757 }
758 else if(xmc_bank == XMC_BANK4_PCCARD)
759 {
760 int_state = XMC_BANK4->bk4is & 0x38; /* keep interrupt state */
761 XMC_BANK4->bk4is = (~(xmc_flag | 0x38) | int_state);
762 }
763 else
764 {
765 XMC_SDRAM->rcnt |= xmc_flag;
766 }
767 }
768
769 /**
770 * @brief xmc pc card registers reset
771 * @param none
772 * @retval none
773 */
774 void xmc_pccard_reset(void)
775 {
776 /* Set the XMC_Bank4 registers to their reset values */
777 XMC_BANK4->bk4ctrl = 0x00000018;
778 XMC_BANK4->bk4is = 0x00000000;
779 XMC_BANK4->bk4tmgatt = 0xFCFCFCFC;
780 XMC_BANK4->bk4tmgio = 0xFCFCFCFC;
781 XMC_BANK4->bk4tmgmem = 0xFCFCFCFC;
782 }
783
784 /**
785 * @brief initialize the xmc pccard bank according to the specified
786 * parameters in the xmc_pccard_init_struct.
787 * @param xmc_pccard_init_struct : pointer to a xmc_pccard_init_type
788 * structure that contains the configuration information for the xmc
789 * pccard bank.
790 * @retval none
791 */
792 void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct)
793 {
794 /* set the bk4ctrl register value according to xmc_pccard_init_struct parameters */
795 XMC_BANK4->bk4ctrl = (uint32_t)xmc_pccard_init_struct->enable_wait |
796 XMC_BUSTYPE_16_BITS |
797 (xmc_pccard_init_struct->delay_time_cr << 9) |
798 (xmc_pccard_init_struct->delay_time_ar << 13);
799 }
800
801 /**
802 * @brief initialize the xmc pccard bank according to the specified
803 * parameters in the xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
804 * and xmc_iospace_timing_struct.
805 * @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
806 * structure that contains the configuration information for the xmc
807 * pccard bank.
808 * @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
809 * structure that contains the configuration information for the xmc
810 * pccard bank.
811 * @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
812 * structure that contains the configuration information for the xmc
813 * pccard bank.
814 * @retval none
815 */
816 void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
817 xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
818 xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
819 {
820 /* set bk4tmgmem register value according to xmc_regular_spacetiming_struct parameters */
821 XMC_BANK4->bk4tmgmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
822 (xmc_regular_spacetiming_struct->mem_waite_time << 8) |
823 (xmc_regular_spacetiming_struct->mem_hold_time << 16) |
824 (xmc_regular_spacetiming_struct->mem_hiz_time << 24);
825
826 /* Set bk4tmgatt register value according to xmc_special_spacetiming_struct parameters */
827 XMC_BANK4->bk4tmgatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
828 (xmc_special_spacetiming_struct->mem_waite_time << 8) |
829 (xmc_special_spacetiming_struct->mem_hold_time << 16) |
830 (xmc_special_spacetiming_struct->mem_hiz_time << 24);
831
832 /* Set bk4tmgio register value according to xmc_iospace_timing_struct parameters */
833 XMC_BANK4->bk4tmgio = (uint32_t)xmc_iospace_timing_struct->mem_setup_time |
834 (xmc_iospace_timing_struct->mem_waite_time << 8) |
835 (xmc_iospace_timing_struct->mem_hold_time << 16) |
836 (xmc_iospace_timing_struct->mem_hiz_time << 24);
837 }
838 /**
839 * @brief fill each xmc_pccard_init_struct member with its default value.
840 * @param xmc_pccard_init_struct: pointer to a xmc_pccardinittype
841 * structure which will be initialized.
842 * @retval none
843 */
844 void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct)
845 {
846 /* reset pccard init structure parameters values */
847 xmc_pccard_init_struct->enable_wait = XMC_WAIT_OPERATION_DISABLE;
848 xmc_pccard_init_struct->delay_time_ar = 0x0;
849 xmc_pccard_init_struct->delay_time_cr = 0x0;
850
851 }
852 /**
853 * @brief fill each xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
854 * and xmc_iospace_timing_struct member with its default value.
855 * @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
856 * structure that contains the configuration information for the xmc
857 * pccard bank.
858 * @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
859 * structure that contains the configuration information for the xmc
860 * pccard bank.
861 * @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
862 * structure that contains the configuration information for the xmc
863 * pccard bank.
864 * @retval none
865 */
866 void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
867 xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
868 xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
869 {
870 xmc_regular_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
871 xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
872 xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
873 xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
874 xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
875 xmc_special_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
876 xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
877 xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
878 xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
879 xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
880 xmc_iospace_timing_struct->class_bank = XMC_BANK4_PCCARD;
881 xmc_iospace_timing_struct->mem_hold_time = 0xFC;
882 xmc_iospace_timing_struct->mem_waite_time = 0xFC;
883 xmc_iospace_timing_struct->mem_setup_time = 0xFC;
884 xmc_iospace_timing_struct->mem_hiz_time = 0xFC;
885 }
886 /**
887 * @brief enable or disable the pccard memory bank.
888 * @param new_state (TRUE or FALSE)
889 * @retval none
890 */
891 void xmc_pccard_enable(confirm_state new_state)
892 {
893 /* enable the pccard bank4 by setting the en bit in the bk4ctrl register */
894 XMC_BANK4->bk4ctrl_bit.en = new_state;
895 }
896
897 /**
898 * @}
899 */
900
901 #endif
902
903 /**
904 * @}
905 */
906
907 /**
908 * @}
909 */
INAV: Navigation-enabled flight control software