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[inav.git] / lib / main / CMSIS / Core / Include / core_armv8mbl.h
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1 /**************************************************************************//**
2 * @file core_armv8mbl.h
3 * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
4 * @version V5.0.4
5 * @date 10. January 2018
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_ARMV8MBL_H_GENERIC
32 #define __CORE_ARMV8MBL_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_ARMv8MBL
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS definitions */
66 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
69 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_M ( 2U) /*!< Cortex-M Core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75 */
76 #define __FPU_USED 0U
77
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_PCS_VFP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88 #elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93 #elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98 #elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103 #elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108 #elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113 #endif
114
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116
117
118 #ifdef __cplusplus
119 }
120 #endif
121
122 #endif /* __CORE_ARMV8MBL_H_GENERIC */
123
124 #ifndef __CMSIS_GENERIC
125
126 #ifndef __CORE_ARMV8MBL_H_DEPENDANT
127 #define __CORE_ARMV8MBL_H_DEPENDANT
128
129 #ifdef __cplusplus
130 extern "C" {
131 #endif
132
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135 #ifndef __ARMv8MBL_REV
136 #define __ARMv8MBL_REV 0x0000U
137 #warning "__ARMv8MBL_REV not defined in device header file; using default!"
138 #endif
139
140 #ifndef __FPU_PRESENT
141 #define __FPU_PRESENT 0U
142 #warning "__FPU_PRESENT not defined in device header file; using default!"
143 #endif
144
145 #ifndef __MPU_PRESENT
146 #define __MPU_PRESENT 0U
147 #warning "__MPU_PRESENT not defined in device header file; using default!"
148 #endif
149
150 #ifndef __SAUREGION_PRESENT
151 #define __SAUREGION_PRESENT 0U
152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
153 #endif
154
155 #ifndef __VTOR_PRESENT
156 #define __VTOR_PRESENT 0U
157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
158 #endif
159
160 #ifndef __NVIC_PRIO_BITS
161 #define __NVIC_PRIO_BITS 2U
162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
163 #endif
164
165 #ifndef __Vendor_SysTickConfig
166 #define __Vendor_SysTickConfig 0U
167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
168 #endif
169
170 #ifndef __ETM_PRESENT
171 #define __ETM_PRESENT 0U
172 #warning "__ETM_PRESENT not defined in device header file; using default!"
173 #endif
174
175 #ifndef __MTB_PRESENT
176 #define __MTB_PRESENT 0U
177 #warning "__MTB_PRESENT not defined in device header file; using default!"
178 #endif
179
180 #endif
181
182 /* IO definitions (access restrictions to peripheral registers) */
183 /**
184 \defgroup CMSIS_glob_defs CMSIS Global Defines
185
186 <strong>IO Type Qualifiers</strong> are used
187 \li to specify the access to peripheral variables.
188 \li for automatic generation of peripheral register debug information.
189 */
190 #ifdef __cplusplus
191 #define __I volatile /*!< Defines 'read only' permissions */
192 #else
193 #define __I volatile const /*!< Defines 'read only' permissions */
194 #endif
195 #define __O volatile /*!< Defines 'write only' permissions */
196 #define __IO volatile /*!< Defines 'read / write' permissions */
197
198 /* following defines should be used for structure members */
199 #define __IM volatile const /*! Defines 'read only' structure member permissions */
200 #define __OM volatile /*! Defines 'write only' structure member permissions */
201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
202
203 /*@} end of group ARMv8MBL */
204
205
206
207 /*******************************************************************************
208 * Register Abstraction
209 Core Register contain:
210 - Core Register
211 - Core NVIC Register
212 - Core SCB Register
213 - Core SysTick Register
214 - Core Debug Register
215 - Core MPU Register
216 - Core SAU Register
217 ******************************************************************************/
218 /**
219 \defgroup CMSIS_core_register Defines and Type Definitions
220 \brief Type definitions and defines for Cortex-M processor based devices.
221 */
222
223 /**
224 \ingroup CMSIS_core_register
225 \defgroup CMSIS_CORE Status and Control Registers
226 \brief Core Register type definitions.
227 @{
228 */
229
230 /**
231 \brief Union type to access the Application Program Status Register (APSR).
232 */
233 typedef union
234 {
235 struct
236 {
237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
242 } b; /*!< Structure used for bit access */
243 uint32_t w; /*!< Type used for word access */
244 } APSR_Type;
245
246 /* APSR Register Definitions */
247 #define APSR_N_Pos 31U /*!< APSR: N Position */
248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
249
250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
252
253 #define APSR_C_Pos 29U /*!< APSR: C Position */
254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
255
256 #define APSR_V_Pos 28U /*!< APSR: V Position */
257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
258
259
260 /**
261 \brief Union type to access the Interrupt Program Status Register (IPSR).
262 */
263 typedef union
264 {
265 struct
266 {
267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
269 } b; /*!< Structure used for bit access */
270 uint32_t w; /*!< Type used for word access */
271 } IPSR_Type;
272
273 /* IPSR Register Definitions */
274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
276
277
278 /**
279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
280 */
281 typedef union
282 {
283 struct
284 {
285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
293 } b; /*!< Structure used for bit access */
294 uint32_t w; /*!< Type used for word access */
295 } xPSR_Type;
296
297 /* xPSR Register Definitions */
298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
300
301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
303
304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
306
307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
309
310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
312
313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
315
316
317 /**
318 \brief Union type to access the Control Registers (CONTROL).
319 */
320 typedef union
321 {
322 struct
323 {
324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
327 } b; /*!< Structure used for bit access */
328 uint32_t w; /*!< Type used for word access */
329 } CONTROL_Type;
330
331 /* CONTROL Register Definitions */
332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
334
335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
337
338 /*@} end of group CMSIS_CORE */
339
340
341 /**
342 \ingroup CMSIS_core_register
343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
344 \brief Type definitions for the NVIC Registers
345 @{
346 */
347
348 /**
349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
350 */
351 typedef struct
352 {
353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
354 uint32_t RESERVED0[16U];
355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
356 uint32_t RSERVED1[16U];
357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
358 uint32_t RESERVED2[16U];
359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
360 uint32_t RESERVED3[16U];
361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
362 uint32_t RESERVED4[16U];
363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
364 uint32_t RESERVED5[16U];
365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
366 } NVIC_Type;
367
368 /*@} end of group CMSIS_NVIC */
369
370
371 /**
372 \ingroup CMSIS_core_register
373 \defgroup CMSIS_SCB System Control Block (SCB)
374 \brief Type definitions for the System Control Block Registers
375 @{
376 */
377
378 /**
379 \brief Structure type to access the System Control Block (SCB).
380 */
381 typedef struct
382 {
383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
387 #else
388 uint32_t RESERVED0;
389 #endif
390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
393 uint32_t RESERVED1;
394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
396 } SCB_Type;
397
398 /* SCB CPUID Register Definitions */
399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
401
402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
404
405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
407
408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
410
411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
413
414 /* SCB Interrupt Control State Register Definitions */
415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
417
418 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
419 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
420
421 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
423
424 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
426
427 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
429
430 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
432
433 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
434 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
435
436 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
437 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
438
439 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
440 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
441
442 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
443 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
444
445 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
446 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
447
448 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
449 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
450
451 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
452 /* SCB Vector Table Offset Register Definitions */
453 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
454 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
455 #endif
456
457 /* SCB Application Interrupt and Reset Control Register Definitions */
458 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
459 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
460
461 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
462 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
463
464 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
465 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
466
467 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
468 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
469
470 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
471 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
472
473 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
474 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
475
476 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
477 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
478
479 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
480 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
481
482 /* SCB System Control Register Definitions */
483 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
484 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
485
486 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
487 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
488
489 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
490 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
491
492 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
493 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
494
495 /* SCB Configuration Control Register Definitions */
496 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
497 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
498
499 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
500 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
501
502 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
503 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
504
505 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
506 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
507
508 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
509 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
510
511 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
512 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
513
514 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
515 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
516
517 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
518 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
519
520 /* SCB System Handler Control and State Register Definitions */
521 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
522 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
523
524 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
525 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
526
527 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
528 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
529
530 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
531 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
532
533 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
534 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
535
536 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
537 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
538
539 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
540 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
541
542 /*@} end of group CMSIS_SCB */
543
544
545 /**
546 \ingroup CMSIS_core_register
547 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
548 \brief Type definitions for the System Timer Registers.
549 @{
550 */
551
552 /**
553 \brief Structure type to access the System Timer (SysTick).
554 */
555 typedef struct
556 {
557 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
558 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
559 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
560 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
561 } SysTick_Type;
562
563 /* SysTick Control / Status Register Definitions */
564 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
565 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
566
567 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
568 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
569
570 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
571 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
572
573 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
574 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
575
576 /* SysTick Reload Register Definitions */
577 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
578 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
579
580 /* SysTick Current Register Definitions */
581 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
582 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
583
584 /* SysTick Calibration Register Definitions */
585 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
586 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
587
588 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
589 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
590
591 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
592 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
593
594 /*@} end of group CMSIS_SysTick */
595
596
597 /**
598 \ingroup CMSIS_core_register
599 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
600 \brief Type definitions for the Data Watchpoint and Trace (DWT)
601 @{
602 */
603
604 /**
605 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
606 */
607 typedef struct
608 {
609 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
610 uint32_t RESERVED0[6U];
611 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
612 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
613 uint32_t RESERVED1[1U];
614 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
615 uint32_t RESERVED2[1U];
616 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
617 uint32_t RESERVED3[1U];
618 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
619 uint32_t RESERVED4[1U];
620 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
621 uint32_t RESERVED5[1U];
622 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
623 uint32_t RESERVED6[1U];
624 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
625 uint32_t RESERVED7[1U];
626 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
627 uint32_t RESERVED8[1U];
628 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
629 uint32_t RESERVED9[1U];
630 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
631 uint32_t RESERVED10[1U];
632 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
633 uint32_t RESERVED11[1U];
634 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
635 uint32_t RESERVED12[1U];
636 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
637 uint32_t RESERVED13[1U];
638 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
639 uint32_t RESERVED14[1U];
640 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
641 uint32_t RESERVED15[1U];
642 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
643 uint32_t RESERVED16[1U];
644 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
645 uint32_t RESERVED17[1U];
646 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
647 uint32_t RESERVED18[1U];
648 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
649 uint32_t RESERVED19[1U];
650 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
651 uint32_t RESERVED20[1U];
652 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
653 uint32_t RESERVED21[1U];
654 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
655 uint32_t RESERVED22[1U];
656 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
657 uint32_t RESERVED23[1U];
658 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
659 uint32_t RESERVED24[1U];
660 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
661 uint32_t RESERVED25[1U];
662 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
663 uint32_t RESERVED26[1U];
664 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
665 uint32_t RESERVED27[1U];
666 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
667 uint32_t RESERVED28[1U];
668 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
669 uint32_t RESERVED29[1U];
670 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
671 uint32_t RESERVED30[1U];
672 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
673 uint32_t RESERVED31[1U];
674 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
675 } DWT_Type;
676
677 /* DWT Control Register Definitions */
678 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
679 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
680
681 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
682 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
683
684 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
685 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
686
687 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
688 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
689
690 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
691 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
692
693 /* DWT Comparator Function Register Definitions */
694 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
695 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
696
697 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
698 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
699
700 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
701 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
702
703 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
704 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
705
706 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
707 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
708
709 /*@}*/ /* end of group CMSIS_DWT */
710
711
712 /**
713 \ingroup CMSIS_core_register
714 \defgroup CMSIS_TPI Trace Port Interface (TPI)
715 \brief Type definitions for the Trace Port Interface (TPI)
716 @{
717 */
718
719 /**
720 \brief Structure type to access the Trace Port Interface Register (TPI).
721 */
722 typedef struct
723 {
724 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
725 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
726 uint32_t RESERVED0[2U];
727 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
728 uint32_t RESERVED1[55U];
729 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
730 uint32_t RESERVED2[131U];
731 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
732 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
733 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
734 uint32_t RESERVED3[759U];
735 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
736 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
737 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
738 uint32_t RESERVED4[1U];
739 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
740 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
741 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
742 uint32_t RESERVED5[39U];
743 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
744 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
745 uint32_t RESERVED7[8U];
746 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
747 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
748 } TPI_Type;
749
750 /* TPI Asynchronous Clock Prescaler Register Definitions */
751 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
752 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
753
754 /* TPI Selected Pin Protocol Register Definitions */
755 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
756 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
757
758 /* TPI Formatter and Flush Status Register Definitions */
759 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
760 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
761
762 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
763 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
764
765 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
766 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
767
768 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
769 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
770
771 /* TPI Formatter and Flush Control Register Definitions */
772 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
773 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
774
775 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
776 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
777
778 /* TPI TRIGGER Register Definitions */
779 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
780 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
781
782 /* TPI Integration ETM Data Register Definitions (FIFO0) */
783 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
784 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
785
786 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
787 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
788
789 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
790 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
791
792 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
793 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
794
795 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
796 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
797
798 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
799 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
800
801 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
802 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
803
804 /* TPI ITATBCTR2 Register Definitions */
805 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
806 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
807
808 /* TPI Integration ITM Data Register Definitions (FIFO1) */
809 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
810 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
811
812 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
813 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
814
815 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
816 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
817
818 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
819 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
820
821 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
822 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
823
824 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
825 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
826
827 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
828 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
829
830 /* TPI ITATBCTR0 Register Definitions */
831 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
832 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
833
834 /* TPI Integration Mode Control Register Definitions */
835 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
836 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
837
838 /* TPI DEVID Register Definitions */
839 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
840 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
841
842 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
843 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
844
845 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
846 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
847
848 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
849 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
850
851 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
852 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
853
854 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
855 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
856
857 /* TPI DEVTYPE Register Definitions */
858 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
859 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
860
861 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
862 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
863
864 /*@}*/ /* end of group CMSIS_TPI */
865
866
867 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
868 /**
869 \ingroup CMSIS_core_register
870 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
871 \brief Type definitions for the Memory Protection Unit (MPU)
872 @{
873 */
874
875 /**
876 \brief Structure type to access the Memory Protection Unit (MPU).
877 */
878 typedef struct
879 {
880 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
881 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
882 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
883 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
884 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
885 uint32_t RESERVED0[7U];
886 union {
887 __IOM uint32_t MAIR[2];
888 struct {
889 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
890 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
891 };
892 };
893 } MPU_Type;
894
895 #define MPU_TYPE_RALIASES 1U
896
897 /* MPU Type Register Definitions */
898 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
899 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
900
901 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
902 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
903
904 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
905 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
906
907 /* MPU Control Register Definitions */
908 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
909 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
910
911 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
912 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
913
914 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
915 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
916
917 /* MPU Region Number Register Definitions */
918 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
919 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
920
921 /* MPU Region Base Address Register Definitions */
922 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
923 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
924
925 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
926 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
927
928 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
929 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
930
931 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
932 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
933
934 /* MPU Region Limit Address Register Definitions */
935 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
936 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
937
938 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
939 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
940
941 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
942 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
943
944 /* MPU Memory Attribute Indirection Register 0 Definitions */
945 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
946 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
947
948 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
949 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
950
951 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
952 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
953
954 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
955 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
956
957 /* MPU Memory Attribute Indirection Register 1 Definitions */
958 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
959 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
960
961 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
962 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
963
964 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
965 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
966
967 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
968 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
969
970 /*@} end of group CMSIS_MPU */
971 #endif
972
973
974 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
975 /**
976 \ingroup CMSIS_core_register
977 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
978 \brief Type definitions for the Security Attribution Unit (SAU)
979 @{
980 */
981
982 /**
983 \brief Structure type to access the Security Attribution Unit (SAU).
984 */
985 typedef struct
986 {
987 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
988 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
989 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
990 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
991 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
992 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
993 #endif
994 } SAU_Type;
995
996 /* SAU Control Register Definitions */
997 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
998 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
999
1000 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1001 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1002
1003 /* SAU Type Register Definitions */
1004 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1005 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1006
1007 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1008 /* SAU Region Number Register Definitions */
1009 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1010 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1011
1012 /* SAU Region Base Address Register Definitions */
1013 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1014 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1015
1016 /* SAU Region Limit Address Register Definitions */
1017 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1018 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1019
1020 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1021 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1022
1023 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1024 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1025
1026 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1027
1028 /*@} end of group CMSIS_SAU */
1029 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1030
1031
1032 /**
1033 \ingroup CMSIS_core_register
1034 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1035 \brief Type definitions for the Core Debug Registers
1036 @{
1037 */
1038
1039 /**
1040 \brief Structure type to access the Core Debug Register (CoreDebug).
1041 */
1042 typedef struct
1043 {
1044 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1045 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1046 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1047 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1048 uint32_t RESERVED4[1U];
1049 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1050 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1051 } CoreDebug_Type;
1052
1053 /* Debug Halting Control and Status Register Definitions */
1054 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1055 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1056
1057 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
1058 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
1059
1060 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1061 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1062
1063 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1064 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1065
1066 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1067 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1068
1069 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1070 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1071
1072 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1073 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1074
1075 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1076 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1077
1078 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1079 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1080
1081 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1082 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1083
1084 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1085 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1086
1087 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1088 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1089
1090 /* Debug Core Register Selector Register Definitions */
1091 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1092 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1093
1094 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1095 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1096
1097 /* Debug Exception and Monitor Control Register */
1098 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
1099 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
1100
1101 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1102 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1103
1104 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1105 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1106
1107 /* Debug Authentication Control Register Definitions */
1108 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1109 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1110
1111 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1112 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1113
1114 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
1115 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1116
1117 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
1118 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1119
1120 /* Debug Security Control and Status Register Definitions */
1121 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
1122 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
1123
1124 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
1125 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
1126
1127 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
1128 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
1129
1130 /*@} end of group CMSIS_CoreDebug */
1131
1132
1133 /**
1134 \ingroup CMSIS_core_register
1135 \defgroup CMSIS_core_bitfield Core register bit field macros
1136 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1137 @{
1138 */
1139
1140 /**
1141 \brief Mask and shift a bit field value for use in a register bit range.
1142 \param[in] field Name of the register bit field.
1143 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1144 \return Masked and shifted value.
1145 */
1146 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1147
1148 /**
1149 \brief Mask and shift a register value to extract a bit filed value.
1150 \param[in] field Name of the register bit field.
1151 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1152 \return Masked and shifted bit field value.
1153 */
1154 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1155
1156 /*@} end of group CMSIS_core_bitfield */
1157
1158
1159 /**
1160 \ingroup CMSIS_core_register
1161 \defgroup CMSIS_core_base Core Definitions
1162 \brief Definitions for base addresses, unions, and structures.
1163 @{
1164 */
1165
1166 /* Memory mapping of Core Hardware */
1167 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1168 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1169 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1170 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1171 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1172 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1173 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1174
1175
1176 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1177 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1178 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1179 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1180 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1181 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
1182
1183 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1184 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1185 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1186 #endif
1187
1188 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1189 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
1190 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
1191 #endif
1192
1193 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1194 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
1195 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
1196 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
1197 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
1198 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
1199
1200 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
1201 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
1202 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
1203 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
1204
1205 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1206 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
1207 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
1208 #endif
1209
1210 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1211 /*@} */
1212
1213
1214
1215 /*******************************************************************************
1216 * Hardware Abstraction Layer
1217 Core Function Interface contains:
1218 - Core NVIC Functions
1219 - Core SysTick Functions
1220 - Core Register Access Functions
1221 ******************************************************************************/
1222 /**
1223 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1224 */
1225
1226
1227
1228 /* ########################## NVIC functions #################################### */
1229 /**
1230 \ingroup CMSIS_Core_FunctionInterface
1231 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1232 \brief Functions that manage interrupts and exceptions via the NVIC.
1233 @{
1234 */
1235
1236 #ifdef CMSIS_NVIC_VIRTUAL
1237 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1238 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1239 #endif
1240 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1241 #else
1242 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */
1243 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */
1244 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1245 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1246 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1247 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1248 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1249 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1250 #define NVIC_GetActive __NVIC_GetActive
1251 #define NVIC_SetPriority __NVIC_SetPriority
1252 #define NVIC_GetPriority __NVIC_GetPriority
1253 #define NVIC_SystemReset __NVIC_SystemReset
1254 #endif /* CMSIS_NVIC_VIRTUAL */
1255
1256 #ifdef CMSIS_VECTAB_VIRTUAL
1257 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1258 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1259 #endif
1260 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1261 #else
1262 #define NVIC_SetVector __NVIC_SetVector
1263 #define NVIC_GetVector __NVIC_GetVector
1264 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1265
1266 #define NVIC_USER_IRQ_OFFSET 16
1267
1268
1269 /* Interrupt Priorities are WORD accessible only under Armv6-M */
1270 /* The following MACROS handle generation of the register offset and byte masks */
1271 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1272 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1273 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1274
1275
1276 /**
1277 \brief Enable Interrupt
1278 \details Enables a device specific interrupt in the NVIC interrupt controller.
1279 \param [in] IRQn Device specific interrupt number.
1280 \note IRQn must not be negative.
1281 */
1282 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1283 {
1284 if ((int32_t)(IRQn) >= 0)
1285 {
1286 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1287 }
1288 }
1289
1290
1291 /**
1292 \brief Get Interrupt Enable status
1293 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1294 \param [in] IRQn Device specific interrupt number.
1295 \return 0 Interrupt is not enabled.
1296 \return 1 Interrupt is enabled.
1297 \note IRQn must not be negative.
1298 */
1299 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1300 {
1301 if ((int32_t)(IRQn) >= 0)
1302 {
1303 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1304 }
1305 else
1306 {
1307 return(0U);
1308 }
1309 }
1310
1311
1312 /**
1313 \brief Disable Interrupt
1314 \details Disables a device specific interrupt in the NVIC interrupt controller.
1315 \param [in] IRQn Device specific interrupt number.
1316 \note IRQn must not be negative.
1317 */
1318 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1319 {
1320 if ((int32_t)(IRQn) >= 0)
1321 {
1322 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1323 __DSB();
1324 __ISB();
1325 }
1326 }
1327
1328
1329 /**
1330 \brief Get Pending Interrupt
1331 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1332 \param [in] IRQn Device specific interrupt number.
1333 \return 0 Interrupt status is not pending.
1334 \return 1 Interrupt status is pending.
1335 \note IRQn must not be negative.
1336 */
1337 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1338 {
1339 if ((int32_t)(IRQn) >= 0)
1340 {
1341 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1342 }
1343 else
1344 {
1345 return(0U);
1346 }
1347 }
1348
1349
1350 /**
1351 \brief Set Pending Interrupt
1352 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1353 \param [in] IRQn Device specific interrupt number.
1354 \note IRQn must not be negative.
1355 */
1356 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1357 {
1358 if ((int32_t)(IRQn) >= 0)
1359 {
1360 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1361 }
1362 }
1363
1364
1365 /**
1366 \brief Clear Pending Interrupt
1367 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1368 \param [in] IRQn Device specific interrupt number.
1369 \note IRQn must not be negative.
1370 */
1371 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1372 {
1373 if ((int32_t)(IRQn) >= 0)
1374 {
1375 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1376 }
1377 }
1378
1379
1380 /**
1381 \brief Get Active Interrupt
1382 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1383 \param [in] IRQn Device specific interrupt number.
1384 \return 0 Interrupt status is not active.
1385 \return 1 Interrupt status is active.
1386 \note IRQn must not be negative.
1387 */
1388 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1389 {
1390 if ((int32_t)(IRQn) >= 0)
1391 {
1392 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1393 }
1394 else
1395 {
1396 return(0U);
1397 }
1398 }
1399
1400
1401 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1402 /**
1403 \brief Get Interrupt Target State
1404 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1405 \param [in] IRQn Device specific interrupt number.
1406 \return 0 if interrupt is assigned to Secure
1407 \return 1 if interrupt is assigned to Non Secure
1408 \note IRQn must not be negative.
1409 */
1410 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1411 {
1412 if ((int32_t)(IRQn) >= 0)
1413 {
1414 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1415 }
1416 else
1417 {
1418 return(0U);
1419 }
1420 }
1421
1422
1423 /**
1424 \brief Set Interrupt Target State
1425 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1426 \param [in] IRQn Device specific interrupt number.
1427 \return 0 if interrupt is assigned to Secure
1428 1 if interrupt is assigned to Non Secure
1429 \note IRQn must not be negative.
1430 */
1431 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1432 {
1433 if ((int32_t)(IRQn) >= 0)
1434 {
1435 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1436 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1437 }
1438 else
1439 {
1440 return(0U);
1441 }
1442 }
1443
1444
1445 /**
1446 \brief Clear Interrupt Target State
1447 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1448 \param [in] IRQn Device specific interrupt number.
1449 \return 0 if interrupt is assigned to Secure
1450 1 if interrupt is assigned to Non Secure
1451 \note IRQn must not be negative.
1452 */
1453 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1454 {
1455 if ((int32_t)(IRQn) >= 0)
1456 {
1457 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1458 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1459 }
1460 else
1461 {
1462 return(0U);
1463 }
1464 }
1465 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1466
1467
1468 /**
1469 \brief Set Interrupt Priority
1470 \details Sets the priority of a device specific interrupt or a processor exception.
1471 The interrupt number can be positive to specify a device specific interrupt,
1472 or negative to specify a processor exception.
1473 \param [in] IRQn Interrupt number.
1474 \param [in] priority Priority to set.
1475 \note The priority cannot be set for every processor exception.
1476 */
1477 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1478 {
1479 if ((int32_t)(IRQn) >= 0)
1480 {
1481 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1482 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1483 }
1484 else
1485 {
1486 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1487 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1488 }
1489 }
1490
1491
1492 /**
1493 \brief Get Interrupt Priority
1494 \details Reads the priority of a device specific interrupt or a processor exception.
1495 The interrupt number can be positive to specify a device specific interrupt,
1496 or negative to specify a processor exception.
1497 \param [in] IRQn Interrupt number.
1498 \return Interrupt Priority.
1499 Value is aligned automatically to the implemented priority bits of the microcontroller.
1500 */
1501 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1502 {
1503
1504 if ((int32_t)(IRQn) >= 0)
1505 {
1506 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1507 }
1508 else
1509 {
1510 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1511 }
1512 }
1513
1514
1515 /**
1516 \brief Set Interrupt Vector
1517 \details Sets an interrupt vector in SRAM based interrupt vector table.
1518 The interrupt number can be positive to specify a device specific interrupt,
1519 or negative to specify a processor exception.
1520 VTOR must been relocated to SRAM before.
1521 If VTOR is not present address 0 must be mapped to SRAM.
1522 \param [in] IRQn Interrupt number
1523 \param [in] vector Address of interrupt handler function
1524 */
1525 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1526 {
1527 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1528 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1529 #else
1530 uint32_t *vectors = (uint32_t *)0x0U;
1531 #endif
1532 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1533 }
1534
1535
1536 /**
1537 \brief Get Interrupt Vector
1538 \details Reads an interrupt vector from interrupt vector table.
1539 The interrupt number can be positive to specify a device specific interrupt,
1540 or negative to specify a processor exception.
1541 \param [in] IRQn Interrupt number.
1542 \return Address of interrupt handler function
1543 */
1544 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1545 {
1546 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1547 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1548 #else
1549 uint32_t *vectors = (uint32_t *)0x0U;
1550 #endif
1551 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1552 }
1553
1554
1555 /**
1556 \brief System Reset
1557 \details Initiates a system reset request to reset the MCU.
1558 */
1559 __STATIC_INLINE void __NVIC_SystemReset(void)
1560 {
1561 __DSB(); /* Ensure all outstanding memory accesses included
1562 buffered write are completed before reset */
1563 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1564 SCB_AIRCR_SYSRESETREQ_Msk);
1565 __DSB(); /* Ensure completion of memory access */
1566
1567 for(;;) /* wait until reset */
1568 {
1569 __NOP();
1570 }
1571 }
1572
1573 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1574 /**
1575 \brief Enable Interrupt (non-secure)
1576 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1577 \param [in] IRQn Device specific interrupt number.
1578 \note IRQn must not be negative.
1579 */
1580 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1581 {
1582 if ((int32_t)(IRQn) >= 0)
1583 {
1584 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1585 }
1586 }
1587
1588
1589 /**
1590 \brief Get Interrupt Enable status (non-secure)
1591 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
1592 \param [in] IRQn Device specific interrupt number.
1593 \return 0 Interrupt is not enabled.
1594 \return 1 Interrupt is enabled.
1595 \note IRQn must not be negative.
1596 */
1597 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1598 {
1599 if ((int32_t)(IRQn) >= 0)
1600 {
1601 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1602 }
1603 else
1604 {
1605 return(0U);
1606 }
1607 }
1608
1609
1610 /**
1611 \brief Disable Interrupt (non-secure)
1612 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1613 \param [in] IRQn Device specific interrupt number.
1614 \note IRQn must not be negative.
1615 */
1616 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1617 {
1618 if ((int32_t)(IRQn) >= 0)
1619 {
1620 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1621 }
1622 }
1623
1624
1625 /**
1626 \brief Get Pending Interrupt (non-secure)
1627 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
1628 \param [in] IRQn Device specific interrupt number.
1629 \return 0 Interrupt status is not pending.
1630 \return 1 Interrupt status is pending.
1631 \note IRQn must not be negative.
1632 */
1633 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1634 {
1635 if ((int32_t)(IRQn) >= 0)
1636 {
1637 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1638 }
1639 else
1640 {
1641 return(0U);
1642 }
1643 }
1644
1645
1646 /**
1647 \brief Set Pending Interrupt (non-secure)
1648 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1649 \param [in] IRQn Device specific interrupt number.
1650 \note IRQn must not be negative.
1651 */
1652 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1653 {
1654 if ((int32_t)(IRQn) >= 0)
1655 {
1656 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1657 }
1658 }
1659
1660
1661 /**
1662 \brief Clear Pending Interrupt (non-secure)
1663 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1664 \param [in] IRQn Device specific interrupt number.
1665 \note IRQn must not be negative.
1666 */
1667 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1668 {
1669 if ((int32_t)(IRQn) >= 0)
1670 {
1671 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1672 }
1673 }
1674
1675
1676 /**
1677 \brief Get Active Interrupt (non-secure)
1678 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
1679 \param [in] IRQn Device specific interrupt number.
1680 \return 0 Interrupt status is not active.
1681 \return 1 Interrupt status is active.
1682 \note IRQn must not be negative.
1683 */
1684 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1685 {
1686 if ((int32_t)(IRQn) >= 0)
1687 {
1688 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1689 }
1690 else
1691 {
1692 return(0U);
1693 }
1694 }
1695
1696
1697 /**
1698 \brief Set Interrupt Priority (non-secure)
1699 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
1700 The interrupt number can be positive to specify a device specific interrupt,
1701 or negative to specify a processor exception.
1702 \param [in] IRQn Interrupt number.
1703 \param [in] priority Priority to set.
1704 \note The priority cannot be set for every non-secure processor exception.
1705 */
1706 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
1707 {
1708 if ((int32_t)(IRQn) >= 0)
1709 {
1710 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1711 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1712 }
1713 else
1714 {
1715 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1716 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1717 }
1718 }
1719
1720
1721 /**
1722 \brief Get Interrupt Priority (non-secure)
1723 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
1724 The interrupt number can be positive to specify a device specific interrupt,
1725 or negative to specify a processor exception.
1726 \param [in] IRQn Interrupt number.
1727 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
1728 */
1729 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
1730 {
1731
1732 if ((int32_t)(IRQn) >= 0)
1733 {
1734 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1735 }
1736 else
1737 {
1738 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1739 }
1740 }
1741 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
1742
1743 /*@} end of CMSIS_Core_NVICFunctions */
1744
1745 /* ########################## MPU functions #################################### */
1746
1747 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1748
1749 #include "mpu_armv8.h"
1750
1751 #endif
1752
1753 /* ########################## FPU functions #################################### */
1754 /**
1755 \ingroup CMSIS_Core_FunctionInterface
1756 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1757 \brief Function that provides FPU type.
1758 @{
1759 */
1760
1761 /**
1762 \brief get FPU type
1763 \details returns the FPU type
1764 \returns
1765 - \b 0: No FPU
1766 - \b 1: Single precision FPU
1767 - \b 2: Double + Single precision FPU
1768 */
1769 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1770 {
1771 return 0U; /* No FPU */
1772 }
1773
1774
1775 /*@} end of CMSIS_Core_FpuFunctions */
1776
1777
1778
1779 /* ########################## SAU functions #################################### */
1780 /**
1781 \ingroup CMSIS_Core_FunctionInterface
1782 \defgroup CMSIS_Core_SAUFunctions SAU Functions
1783 \brief Functions that configure the SAU.
1784 @{
1785 */
1786
1787 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1788
1789 /**
1790 \brief Enable SAU
1791 \details Enables the Security Attribution Unit (SAU).
1792 */
1793 __STATIC_INLINE void TZ_SAU_Enable(void)
1794 {
1795 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
1796 }
1797
1798
1799
1800 /**
1801 \brief Disable SAU
1802 \details Disables the Security Attribution Unit (SAU).
1803 */
1804 __STATIC_INLINE void TZ_SAU_Disable(void)
1805 {
1806 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
1807 }
1808
1809 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1810
1811 /*@} end of CMSIS_Core_SAUFunctions */
1812
1813
1814
1815
1816 /* ################################## SysTick function ############################################ */
1817 /**
1818 \ingroup CMSIS_Core_FunctionInterface
1819 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1820 \brief Functions that configure the System.
1821 @{
1822 */
1823
1824 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1825
1826 /**
1827 \brief System Tick Configuration
1828 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1829 Counter is in free running mode to generate periodic interrupts.
1830 \param [in] ticks Number of ticks between two interrupts.
1831 \return 0 Function succeeded.
1832 \return 1 Function failed.
1833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1835 must contain a vendor-specific implementation of this function.
1836 */
1837 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1838 {
1839 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1840 {
1841 return (1UL); /* Reload value impossible */
1842 }
1843
1844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1848 SysTick_CTRL_TICKINT_Msk |
1849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1850 return (0UL); /* Function successful */
1851 }
1852
1853 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1854 /**
1855 \brief System Tick Configuration (non-secure)
1856 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
1857 Counter is in free running mode to generate periodic interrupts.
1858 \param [in] ticks Number of ticks between two interrupts.
1859 \return 0 Function succeeded.
1860 \return 1 Function failed.
1861 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1862 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
1863 must contain a vendor-specific implementation of this function.
1864
1865 */
1866 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
1867 {
1868 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1869 {
1870 return (1UL); /* Reload value impossible */
1871 }
1872
1873 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1874 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1875 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
1876 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1877 SysTick_CTRL_TICKINT_Msk |
1878 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1879 return (0UL); /* Function successful */
1880 }
1881 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1882
1883 #endif
1884
1885 /*@} end of CMSIS_Core_SysTickFunctions */
1886
1887
1888
1889
1890 #ifdef __cplusplus
1891 }
1892 #endif
1893
1894 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */
1895
1896 #endif /* __CMSIS_GENERIC */
INAV: Navigation-enabled flight control software