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[inav.git] / lib / main / CMSIS / Core / Include / core_cm4.h
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1 /**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V5.0.5
5 * @date 08. January 2018
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_CM4_H_GENERIC
32 #define __CORE_CM4_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M4
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM4 definitions */
66 #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
69 __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_M (4U) /*!< Cortex-M Core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
75 */
76 #if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89 #if defined __ARM_PCS_VFP
90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91 #define __FPU_USED 1U
92 #else
93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #define __FPU_USED 0U
95 #endif
96 #else
97 #define __FPU_USED 0U
98 #endif
99
100 #elif defined ( __GNUC__ )
101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
104 #else
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
107 #endif
108 #else
109 #define __FPU_USED 0U
110 #endif
111
112 #elif defined ( __ICCARM__ )
113 #if defined __ARMVFP__
114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115 #define __FPU_USED 1U
116 #else
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #define __FPU_USED 0U
119 #endif
120 #else
121 #define __FPU_USED 0U
122 #endif
123
124 #elif defined ( __TI_ARM__ )
125 #if defined __TI_VFP_SUPPORT__
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136 #elif defined ( __TASKING__ )
137 #if defined __FPU_VFP__
138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139 #define __FPU_USED 1U
140 #else
141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
143 #endif
144 #else
145 #define __FPU_USED 0U
146 #endif
147
148 #elif defined ( __CSMC__ )
149 #if ( __CSMC__ & 0x400U)
150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
152 #else
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
155 #endif
156 #else
157 #define __FPU_USED 0U
158 #endif
159
160 #endif
161
162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
163
164
165 #ifdef __cplusplus
166 }
167 #endif
168
169 #endif /* __CORE_CM4_H_GENERIC */
170
171 #ifndef __CMSIS_GENERIC
172
173 #ifndef __CORE_CM4_H_DEPENDANT
174 #define __CORE_CM4_H_DEPENDANT
175
176 #ifdef __cplusplus
177 extern "C" {
178 #endif
179
180 /* check device defines and use defaults */
181 #if defined __CHECK_DEVICE_DEFINES
182 #ifndef __CM4_REV
183 #define __CM4_REV 0x0000U
184 #warning "__CM4_REV not defined in device header file; using default!"
185 #endif
186
187 #ifndef __FPU_PRESENT
188 #define __FPU_PRESENT 0U
189 #warning "__FPU_PRESENT not defined in device header file; using default!"
190 #endif
191
192 #ifndef __MPU_PRESENT
193 #define __MPU_PRESENT 0U
194 #warning "__MPU_PRESENT not defined in device header file; using default!"
195 #endif
196
197 #ifndef __NVIC_PRIO_BITS
198 #define __NVIC_PRIO_BITS 3U
199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
200 #endif
201
202 #ifndef __Vendor_SysTickConfig
203 #define __Vendor_SysTickConfig 0U
204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
205 #endif
206 #endif
207
208 /* IO definitions (access restrictions to peripheral registers) */
209 /**
210 \defgroup CMSIS_glob_defs CMSIS Global Defines
211
212 <strong>IO Type Qualifiers</strong> are used
213 \li to specify the access to peripheral variables.
214 \li for automatic generation of peripheral register debug information.
215 */
216 #ifdef __cplusplus
217 #define __I volatile /*!< Defines 'read only' permissions */
218 #else
219 #define __I volatile const /*!< Defines 'read only' permissions */
220 #endif
221 #define __O volatile /*!< Defines 'write only' permissions */
222 #define __IO volatile /*!< Defines 'read / write' permissions */
223
224 /* following defines should be used for structure members */
225 #define __IM volatile const /*! Defines 'read only' structure member permissions */
226 #define __OM volatile /*! Defines 'write only' structure member permissions */
227 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
228
229 /*@} end of group Cortex_M4 */
230
231
232
233 /*******************************************************************************
234 * Register Abstraction
235 Core Register contain:
236 - Core Register
237 - Core NVIC Register
238 - Core SCB Register
239 - Core SysTick Register
240 - Core Debug Register
241 - Core MPU Register
242 - Core FPU Register
243 ******************************************************************************/
244 /**
245 \defgroup CMSIS_core_register Defines and Type Definitions
246 \brief Type definitions and defines for Cortex-M processor based devices.
247 */
248
249 /**
250 \ingroup CMSIS_core_register
251 \defgroup CMSIS_CORE Status and Control Registers
252 \brief Core Register type definitions.
253 @{
254 */
255
256 /**
257 \brief Union type to access the Application Program Status Register (APSR).
258 */
259 typedef union
260 {
261 struct
262 {
263 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
264 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
265 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
271 } b; /*!< Structure used for bit access */
272 uint32_t w; /*!< Type used for word access */
273 } APSR_Type;
274
275 /* APSR Register Definitions */
276 #define APSR_N_Pos 31U /*!< APSR: N Position */
277 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
278
279 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
280 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
281
282 #define APSR_C_Pos 29U /*!< APSR: C Position */
283 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
284
285 #define APSR_V_Pos 28U /*!< APSR: V Position */
286 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
287
288 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
289 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
290
291 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
292 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
293
294
295 /**
296 \brief Union type to access the Interrupt Program Status Register (IPSR).
297 */
298 typedef union
299 {
300 struct
301 {
302 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
303 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
304 } b; /*!< Structure used for bit access */
305 uint32_t w; /*!< Type used for word access */
306 } IPSR_Type;
307
308 /* IPSR Register Definitions */
309 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
310 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
311
312
313 /**
314 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
315 */
316 typedef union
317 {
318 struct
319 {
320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
321 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
322 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
323 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
324 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
325 uint32_t T:1; /*!< bit: 24 Thumb bit */
326 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
327 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
328 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
329 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
330 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
331 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
332 } b; /*!< Structure used for bit access */
333 uint32_t w; /*!< Type used for word access */
334 } xPSR_Type;
335
336 /* xPSR Register Definitions */
337 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
338 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
339
340 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
341 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
342
343 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
344 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
345
346 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
347 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
348
349 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
350 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
351
352 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
353 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
354
355 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
356 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
357
358 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
359 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
360
361 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
362 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
363
364 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
365 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
366
367
368 /**
369 \brief Union type to access the Control Registers (CONTROL).
370 */
371 typedef union
372 {
373 struct
374 {
375 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
376 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
377 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
378 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
379 } b; /*!< Structure used for bit access */
380 uint32_t w; /*!< Type used for word access */
381 } CONTROL_Type;
382
383 /* CONTROL Register Definitions */
384 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
385 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
386
387 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
388 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
389
390 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
391 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
392
393 /*@} end of group CMSIS_CORE */
394
395
396 /**
397 \ingroup CMSIS_core_register
398 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
399 \brief Type definitions for the NVIC Registers
400 @{
401 */
402
403 /**
404 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
405 */
406 typedef struct
407 {
408 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
409 uint32_t RESERVED0[24U];
410 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
411 uint32_t RSERVED1[24U];
412 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
413 uint32_t RESERVED2[24U];
414 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
415 uint32_t RESERVED3[24U];
416 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
417 uint32_t RESERVED4[56U];
418 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
419 uint32_t RESERVED5[644U];
420 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
421 } NVIC_Type;
422
423 /* Software Triggered Interrupt Register Definitions */
424 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
425 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
426
427 /*@} end of group CMSIS_NVIC */
428
429
430 /**
431 \ingroup CMSIS_core_register
432 \defgroup CMSIS_SCB System Control Block (SCB)
433 \brief Type definitions for the System Control Block Registers
434 @{
435 */
436
437 /**
438 \brief Structure type to access the System Control Block (SCB).
439 */
440 typedef struct
441 {
442 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
443 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
444 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
445 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
446 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
447 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
448 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
449 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
450 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
451 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
452 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
453 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
454 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
455 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
456 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
457 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
458 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
459 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
460 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
461 uint32_t RESERVED0[5U];
462 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
463 } SCB_Type;
464
465 /* SCB CPUID Register Definitions */
466 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
467 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
468
469 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
470 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
471
472 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
473 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
474
475 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
476 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
477
478 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
479 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
480
481 /* SCB Interrupt Control State Register Definitions */
482 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
483 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
484
485 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
486 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
487
488 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
489 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
490
491 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
492 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
493
494 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
495 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
496
497 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
498 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
499
500 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
501 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
502
503 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
504 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
505
506 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
507 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
508
509 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
510 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
511
512 /* SCB Vector Table Offset Register Definitions */
513 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
514 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
515
516 /* SCB Application Interrupt and Reset Control Register Definitions */
517 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
518 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
519
520 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
521 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
522
523 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
524 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
525
526 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
527 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
528
529 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
530 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
531
532 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
533 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
534
535 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
536 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
537
538 /* SCB System Control Register Definitions */
539 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
540 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
541
542 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
543 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
544
545 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
546 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
547
548 /* SCB Configuration Control Register Definitions */
549 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
550 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
551
552 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
553 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
554
555 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
556 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
557
558 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
559 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
560
561 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
562 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
563
564 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
565 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
566
567 /* SCB System Handler Control and State Register Definitions */
568 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
569 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
570
571 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
572 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
573
574 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
575 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
576
577 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
578 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
579
580 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
581 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
582
583 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
584 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
585
586 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
587 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
588
589 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
590 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
591
592 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
593 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
594
595 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
596 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
597
598 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
599 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
600
601 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
602 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
603
604 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
605 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
606
607 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
608 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
609
610 /* SCB Configurable Fault Status Register Definitions */
611 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
612 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
613
614 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
615 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
616
617 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
618 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
619
620 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
621 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
622 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
623
624 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
625 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
626
627 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
628 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
629
630 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
631 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
632
633 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
634 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
635
636 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
637 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
638
639 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
640 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
641 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
642
643 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
644 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
645
646 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
647 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
648
649 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
650 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
651
652 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
653 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
654
655 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
656 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
657
658 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
659 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
660
661 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
662 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
663 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
664
665 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
666 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
667
668 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
669 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
670
671 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
672 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
673
674 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
675 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
676
677 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
678 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
679
680 /* SCB Hard Fault Status Register Definitions */
681 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
682 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
683
684 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
685 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
686
687 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
688 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
689
690 /* SCB Debug Fault Status Register Definitions */
691 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
692 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
693
694 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
695 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
696
697 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
698 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
699
700 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
701 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
702
703 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
704 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
705
706 /*@} end of group CMSIS_SCB */
707
708
709 /**
710 \ingroup CMSIS_core_register
711 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
712 \brief Type definitions for the System Control and ID Register not in the SCB
713 @{
714 */
715
716 /**
717 \brief Structure type to access the System Control and ID Register not in the SCB.
718 */
719 typedef struct
720 {
721 uint32_t RESERVED0[1U];
722 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
723 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
724 } SCnSCB_Type;
725
726 /* Interrupt Controller Type Register Definitions */
727 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
728 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
729
730 /* Auxiliary Control Register Definitions */
731 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
732 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
733
734 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
735 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
736
737 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
738 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
739
740 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
741 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
742
743 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
744 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
745
746 /*@} end of group CMSIS_SCnotSCB */
747
748
749 /**
750 \ingroup CMSIS_core_register
751 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
752 \brief Type definitions for the System Timer Registers.
753 @{
754 */
755
756 /**
757 \brief Structure type to access the System Timer (SysTick).
758 */
759 typedef struct
760 {
761 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
762 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
763 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
764 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
765 } SysTick_Type;
766
767 /* SysTick Control / Status Register Definitions */
768 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
769 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
770
771 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
772 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
773
774 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
775 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
776
777 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
778 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
779
780 /* SysTick Reload Register Definitions */
781 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
782 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
783
784 /* SysTick Current Register Definitions */
785 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
786 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
787
788 /* SysTick Calibration Register Definitions */
789 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
790 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
791
792 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
793 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
794
795 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
796 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
797
798 /*@} end of group CMSIS_SysTick */
799
800
801 /**
802 \ingroup CMSIS_core_register
803 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
804 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
805 @{
806 */
807
808 /**
809 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
810 */
811 typedef struct
812 {
813 __OM union
814 {
815 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
816 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
817 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
818 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
819 uint32_t RESERVED0[864U];
820 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
821 uint32_t RESERVED1[15U];
822 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
823 uint32_t RESERVED2[15U];
824 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
825 uint32_t RESERVED3[29U];
826 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
827 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
828 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
829 uint32_t RESERVED4[43U];
830 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
831 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
832 uint32_t RESERVED5[6U];
833 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
834 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
835 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
836 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
837 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
838 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
839 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
840 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
841 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
842 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
843 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
844 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
845 } ITM_Type;
846
847 /* ITM Trace Privilege Register Definitions */
848 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
849 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
850
851 /* ITM Trace Control Register Definitions */
852 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
853 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
854
855 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
856 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
857
858 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
859 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
860
861 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
862 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
863
864 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
865 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
866
867 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
868 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
869
870 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
871 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
872
873 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
874 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
875
876 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
877 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
878
879 /* ITM Integration Write Register Definitions */
880 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
881 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
882
883 /* ITM Integration Read Register Definitions */
884 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
885 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
886
887 /* ITM Integration Mode Control Register Definitions */
888 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
889 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
890
891 /* ITM Lock Status Register Definitions */
892 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
893 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
894
895 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
896 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
897
898 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
899 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
900
901 /*@}*/ /* end of group CMSIS_ITM */
902
903
904 /**
905 \ingroup CMSIS_core_register
906 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
907 \brief Type definitions for the Data Watchpoint and Trace (DWT)
908 @{
909 */
910
911 /**
912 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
913 */
914 typedef struct
915 {
916 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
917 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
918 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
919 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
920 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
921 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
922 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
923 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
924 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
925 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
926 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
927 uint32_t RESERVED0[1U];
928 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
929 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
930 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
931 uint32_t RESERVED1[1U];
932 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
933 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
934 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
935 uint32_t RESERVED2[1U];
936 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
937 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
938 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
939 } DWT_Type;
940
941 /* DWT Control Register Definitions */
942 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
943 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
944
945 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
946 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
947
948 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
949 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
950
951 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
952 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
953
954 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
955 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
956
957 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
958 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
959
960 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
961 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
962
963 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
964 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
965
966 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
967 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
968
969 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
970 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
971
972 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
973 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
974
975 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
976 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
977
978 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
979 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
980
981 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
982 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
983
984 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
985 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
986
987 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
988 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
989
990 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
991 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
992
993 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
994 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
995
996 /* DWT CPI Count Register Definitions */
997 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
998 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
999
1000 /* DWT Exception Overhead Count Register Definitions */
1001 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1002 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1003
1004 /* DWT Sleep Count Register Definitions */
1005 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1006 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1007
1008 /* DWT LSU Count Register Definitions */
1009 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1010 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1011
1012 /* DWT Folded-instruction Count Register Definitions */
1013 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1014 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1015
1016 /* DWT Comparator Mask Register Definitions */
1017 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
1018 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1019
1020 /* DWT Comparator Function Register Definitions */
1021 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1022 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1023
1024 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
1025 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1026
1027 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
1028 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1029
1030 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1031 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1032
1033 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
1034 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1035
1036 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
1037 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1038
1039 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
1040 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1041
1042 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
1043 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1044
1045 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
1046 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1047
1048 /*@}*/ /* end of group CMSIS_DWT */
1049
1050
1051 /**
1052 \ingroup CMSIS_core_register
1053 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1054 \brief Type definitions for the Trace Port Interface (TPI)
1055 @{
1056 */
1057
1058 /**
1059 \brief Structure type to access the Trace Port Interface Register (TPI).
1060 */
1061 typedef struct
1062 {
1063 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1064 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1065 uint32_t RESERVED0[2U];
1066 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1067 uint32_t RESERVED1[55U];
1068 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1069 uint32_t RESERVED2[131U];
1070 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1071 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1072 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1073 uint32_t RESERVED3[759U];
1074 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1075 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1076 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1077 uint32_t RESERVED4[1U];
1078 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1079 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1080 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1081 uint32_t RESERVED5[39U];
1082 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1083 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1084 uint32_t RESERVED7[8U];
1085 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1086 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1087 } TPI_Type;
1088
1089 /* TPI Asynchronous Clock Prescaler Register Definitions */
1090 #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
1091 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
1092
1093 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
1094 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
1095
1096 /* TPI Selected Pin Protocol Register Definitions */
1097 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1098 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1099
1100 /* TPI Formatter and Flush Status Register Definitions */
1101 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1102 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1103
1104 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1105 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1106
1107 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1108 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1109
1110 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1111 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1112
1113 /* TPI Formatter and Flush Control Register Definitions */
1114 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1115 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1116
1117 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1118 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1119
1120 /* TPI TRIGGER Register Definitions */
1121 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1122 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1123
1124 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1125 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1126 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1127
1128 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1129 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1130
1131 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1132 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1133
1134 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1135 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1136
1137 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1138 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1139
1140 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1141 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1142
1143 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1144 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1145
1146 /* TPI ITATBCTR2 Register Definitions */
1147 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
1148 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1149
1150 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1151 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1152 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1153
1154 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1155 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1156
1157 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1158 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1159
1160 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1161 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1162
1163 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1164 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1165
1166 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1167 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1168
1169 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1170 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1171
1172 /* TPI ITATBCTR0 Register Definitions */
1173 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
1174 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1175
1176 /* TPI Integration Mode Control Register Definitions */
1177 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1178 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1179
1180 /* TPI DEVID Register Definitions */
1181 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1182 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1183
1184 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1185 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1186
1187 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1188 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1189
1190 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1191 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1192
1193 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1194 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1195
1196 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1197 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1198
1199 /* TPI DEVTYPE Register Definitions */
1200 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
1201 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1202
1203 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
1204 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1205
1206 /*@}*/ /* end of group CMSIS_TPI */
1207
1208
1209 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1210 /**
1211 \ingroup CMSIS_core_register
1212 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1213 \brief Type definitions for the Memory Protection Unit (MPU)
1214 @{
1215 */
1216
1217 /**
1218 \brief Structure type to access the Memory Protection Unit (MPU).
1219 */
1220 typedef struct
1221 {
1222 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1223 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1224 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1225 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1226 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1227 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1228 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1229 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1230 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1231 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1232 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1233 } MPU_Type;
1234
1235 #define MPU_TYPE_RALIASES 4U
1236
1237 /* MPU Type Register Definitions */
1238 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1239 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1240
1241 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1242 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1243
1244 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1245 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1246
1247 /* MPU Control Register Definitions */
1248 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1249 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1250
1251 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1252 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1253
1254 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1255 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1256
1257 /* MPU Region Number Register Definitions */
1258 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1259 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1260
1261 /* MPU Region Base Address Register Definitions */
1262 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1263 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1264
1265 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1266 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1267
1268 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1269 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1270
1271 /* MPU Region Attribute and Size Register Definitions */
1272 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1273 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1274
1275 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1276 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1277
1278 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1279 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1280
1281 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1282 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1283
1284 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1285 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1286
1287 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1288 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1289
1290 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1291 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1292
1293 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1294 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1295
1296 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1297 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1298
1299 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1300 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1301
1302 /*@} end of group CMSIS_MPU */
1303 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1304
1305
1306 /**
1307 \ingroup CMSIS_core_register
1308 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1309 \brief Type definitions for the Floating Point Unit (FPU)
1310 @{
1311 */
1312
1313 /**
1314 \brief Structure type to access the Floating Point Unit (FPU).
1315 */
1316 typedef struct
1317 {
1318 uint32_t RESERVED0[1U];
1319 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1320 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1321 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1322 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1323 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1324 } FPU_Type;
1325
1326 /* Floating-Point Context Control Register Definitions */
1327 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1328 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1329
1330 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1331 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1332
1333 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1334 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1335
1336 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1337 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1338
1339 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1340 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1341
1342 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1343 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1344
1345 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1346 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1347
1348 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1349 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1350
1351 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1352 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1353
1354 /* Floating-Point Context Address Register Definitions */
1355 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1356 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1357
1358 /* Floating-Point Default Status Control Register Definitions */
1359 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1360 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1361
1362 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1363 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1364
1365 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1366 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1367
1368 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1369 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1370
1371 /* Media and FP Feature Register 0 Definitions */
1372 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1373 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1374
1375 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1376 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1377
1378 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1379 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1380
1381 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1382 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1383
1384 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1385 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1386
1387 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1388 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1389
1390 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1391 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1392
1393 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1394 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1395
1396 /* Media and FP Feature Register 1 Definitions */
1397 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1398 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1399
1400 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1401 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1402
1403 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1404 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1405
1406 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1407 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1408
1409 /*@} end of group CMSIS_FPU */
1410
1411
1412 /**
1413 \ingroup CMSIS_core_register
1414 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1415 \brief Type definitions for the Core Debug Registers
1416 @{
1417 */
1418
1419 /**
1420 \brief Structure type to access the Core Debug Register (CoreDebug).
1421 */
1422 typedef struct
1423 {
1424 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1425 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1426 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1427 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1428 } CoreDebug_Type;
1429
1430 /* Debug Halting Control and Status Register Definitions */
1431 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1432 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1433
1434 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1435 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1436
1437 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1438 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1439
1440 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1441 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1442
1443 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1444 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1445
1446 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1447 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1448
1449 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1450 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1451
1452 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1453 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1454
1455 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1456 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1457
1458 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1459 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1460
1461 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1462 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1463
1464 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1465 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1466
1467 /* Debug Core Register Selector Register Definitions */
1468 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1469 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1470
1471 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1472 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1473
1474 /* Debug Exception and Monitor Control Register Definitions */
1475 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1476 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1477
1478 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1479 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1480
1481 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1482 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1483
1484 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1485 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1486
1487 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1488 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1489
1490 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1491 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1492
1493 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1494 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1495
1496 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1497 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1498
1499 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1500 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1501
1502 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1503 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1504
1505 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1506 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1507
1508 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1509 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1510
1511 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1512 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1513
1514 /*@} end of group CMSIS_CoreDebug */
1515
1516
1517 /**
1518 \ingroup CMSIS_core_register
1519 \defgroup CMSIS_core_bitfield Core register bit field macros
1520 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1521 @{
1522 */
1523
1524 /**
1525 \brief Mask and shift a bit field value for use in a register bit range.
1526 \param[in] field Name of the register bit field.
1527 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1528 \return Masked and shifted value.
1529 */
1530 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1531
1532 /**
1533 \brief Mask and shift a register value to extract a bit filed value.
1534 \param[in] field Name of the register bit field.
1535 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1536 \return Masked and shifted bit field value.
1537 */
1538 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1539
1540 /*@} end of group CMSIS_core_bitfield */
1541
1542
1543 /**
1544 \ingroup CMSIS_core_register
1545 \defgroup CMSIS_core_base Core Definitions
1546 \brief Definitions for base addresses, unions, and structures.
1547 @{
1548 */
1549
1550 /* Memory mapping of Core Hardware */
1551 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1552 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1553 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1554 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1555 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1556 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1557 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1558 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1559
1560 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1561 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1562 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1563 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1564 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1565 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1566 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1567 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1568
1569 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1570 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1571 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1572 #endif
1573
1574 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1575 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1576
1577 /*@} */
1578
1579
1580
1581 /*******************************************************************************
1582 * Hardware Abstraction Layer
1583 Core Function Interface contains:
1584 - Core NVIC Functions
1585 - Core SysTick Functions
1586 - Core Debug Functions
1587 - Core Register Access Functions
1588 ******************************************************************************/
1589 /**
1590 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1591 */
1592
1593
1594
1595 /* ########################## NVIC functions #################################### */
1596 /**
1597 \ingroup CMSIS_Core_FunctionInterface
1598 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1599 \brief Functions that manage interrupts and exceptions via the NVIC.
1600 @{
1601 */
1602
1603 #ifdef CMSIS_NVIC_VIRTUAL
1604 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1605 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1606 #endif
1607 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1608 #else
1609 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1610 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1611 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1612 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1613 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1614 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1615 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1616 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1617 #define NVIC_GetActive __NVIC_GetActive
1618 #define NVIC_SetPriority __NVIC_SetPriority
1619 #define NVIC_GetPriority __NVIC_GetPriority
1620 #define NVIC_SystemReset __NVIC_SystemReset
1621 #endif /* CMSIS_NVIC_VIRTUAL */
1622
1623 #ifdef CMSIS_VECTAB_VIRTUAL
1624 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1625 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1626 #endif
1627 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1628 #else
1629 #define NVIC_SetVector __NVIC_SetVector
1630 #define NVIC_GetVector __NVIC_GetVector
1631 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1632
1633 #define NVIC_USER_IRQ_OFFSET 16
1634
1635
1636
1637 /**
1638 \brief Set Priority Grouping
1639 \details Sets the priority grouping field using the required unlock sequence.
1640 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1641 Only values from 0..7 are used.
1642 In case of a conflict between priority grouping and available
1643 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1644 \param [in] PriorityGroup Priority grouping field.
1645 */
1646 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1647 {
1648 uint32_t reg_value;
1649 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1650
1651 reg_value = SCB->AIRCR; /* read old register configuration */
1652 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1653 reg_value = (reg_value |
1654 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1655 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1656 SCB->AIRCR = reg_value;
1657 }
1658
1659
1660 /**
1661 \brief Get Priority Grouping
1662 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1663 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1664 */
1665 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1666 {
1667 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1668 }
1669
1670
1671 /**
1672 \brief Enable Interrupt
1673 \details Enables a device specific interrupt in the NVIC interrupt controller.
1674 \param [in] IRQn Device specific interrupt number.
1675 \note IRQn must not be negative.
1676 */
1677 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1678 {
1679 if ((int32_t)(IRQn) >= 0)
1680 {
1681 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1682 }
1683 }
1684
1685
1686 /**
1687 \brief Get Interrupt Enable status
1688 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1689 \param [in] IRQn Device specific interrupt number.
1690 \return 0 Interrupt is not enabled.
1691 \return 1 Interrupt is enabled.
1692 \note IRQn must not be negative.
1693 */
1694 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1695 {
1696 if ((int32_t)(IRQn) >= 0)
1697 {
1698 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1699 }
1700 else
1701 {
1702 return(0U);
1703 }
1704 }
1705
1706
1707 /**
1708 \brief Disable Interrupt
1709 \details Disables a device specific interrupt in the NVIC interrupt controller.
1710 \param [in] IRQn Device specific interrupt number.
1711 \note IRQn must not be negative.
1712 */
1713 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1714 {
1715 if ((int32_t)(IRQn) >= 0)
1716 {
1717 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1718 __DSB();
1719 __ISB();
1720 }
1721 }
1722
1723
1724 /**
1725 \brief Get Pending Interrupt
1726 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1727 \param [in] IRQn Device specific interrupt number.
1728 \return 0 Interrupt status is not pending.
1729 \return 1 Interrupt status is pending.
1730 \note IRQn must not be negative.
1731 */
1732 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1733 {
1734 if ((int32_t)(IRQn) >= 0)
1735 {
1736 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1737 }
1738 else
1739 {
1740 return(0U);
1741 }
1742 }
1743
1744
1745 /**
1746 \brief Set Pending Interrupt
1747 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1748 \param [in] IRQn Device specific interrupt number.
1749 \note IRQn must not be negative.
1750 */
1751 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1752 {
1753 if ((int32_t)(IRQn) >= 0)
1754 {
1755 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1756 }
1757 }
1758
1759
1760 /**
1761 \brief Clear Pending Interrupt
1762 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1763 \param [in] IRQn Device specific interrupt number.
1764 \note IRQn must not be negative.
1765 */
1766 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1767 {
1768 if ((int32_t)(IRQn) >= 0)
1769 {
1770 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1771 }
1772 }
1773
1774
1775 /**
1776 \brief Get Active Interrupt
1777 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1778 \param [in] IRQn Device specific interrupt number.
1779 \return 0 Interrupt status is not active.
1780 \return 1 Interrupt status is active.
1781 \note IRQn must not be negative.
1782 */
1783 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1784 {
1785 if ((int32_t)(IRQn) >= 0)
1786 {
1787 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1788 }
1789 else
1790 {
1791 return(0U);
1792 }
1793 }
1794
1795
1796 /**
1797 \brief Set Interrupt Priority
1798 \details Sets the priority of a device specific interrupt or a processor exception.
1799 The interrupt number can be positive to specify a device specific interrupt,
1800 or negative to specify a processor exception.
1801 \param [in] IRQn Interrupt number.
1802 \param [in] priority Priority to set.
1803 \note The priority cannot be set for every processor exception.
1804 */
1805 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1806 {
1807 if ((int32_t)(IRQn) >= 0)
1808 {
1809 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1810 }
1811 else
1812 {
1813 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1814 }
1815 }
1816
1817
1818 /**
1819 \brief Get Interrupt Priority
1820 \details Reads the priority of a device specific interrupt or a processor exception.
1821 The interrupt number can be positive to specify a device specific interrupt,
1822 or negative to specify a processor exception.
1823 \param [in] IRQn Interrupt number.
1824 \return Interrupt Priority.
1825 Value is aligned automatically to the implemented priority bits of the microcontroller.
1826 */
1827 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1828 {
1829
1830 if ((int32_t)(IRQn) >= 0)
1831 {
1832 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1833 }
1834 else
1835 {
1836 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1837 }
1838 }
1839
1840
1841 /**
1842 \brief Encode Priority
1843 \details Encodes the priority for an interrupt with the given priority group,
1844 preemptive priority value, and subpriority value.
1845 In case of a conflict between priority grouping and available
1846 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1847 \param [in] PriorityGroup Used priority group.
1848 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1849 \param [in] SubPriority Subpriority value (starting from 0).
1850 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1851 */
1852 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1853 {
1854 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1855 uint32_t PreemptPriorityBits;
1856 uint32_t SubPriorityBits;
1857
1858 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1859 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1860
1861 return (
1862 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1863 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1864 );
1865 }
1866
1867
1868 /**
1869 \brief Decode Priority
1870 \details Decodes an interrupt priority value with a given priority group to
1871 preemptive priority value and subpriority value.
1872 In case of a conflict between priority grouping and available
1873 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1874 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1875 \param [in] PriorityGroup Used priority group.
1876 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1877 \param [out] pSubPriority Subpriority value (starting from 0).
1878 */
1879 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1880 {
1881 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1882 uint32_t PreemptPriorityBits;
1883 uint32_t SubPriorityBits;
1884
1885 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1886 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1887
1888 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1889 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1890 }
1891
1892
1893 /**
1894 \brief Set Interrupt Vector
1895 \details Sets an interrupt vector in SRAM based interrupt vector table.
1896 The interrupt number can be positive to specify a device specific interrupt,
1897 or negative to specify a processor exception.
1898 VTOR must been relocated to SRAM before.
1899 \param [in] IRQn Interrupt number
1900 \param [in] vector Address of interrupt handler function
1901 */
1902 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1903 {
1904 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1905 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1906 }
1907
1908
1909 /**
1910 \brief Get Interrupt Vector
1911 \details Reads an interrupt vector from interrupt vector table.
1912 The interrupt number can be positive to specify a device specific interrupt,
1913 or negative to specify a processor exception.
1914 \param [in] IRQn Interrupt number.
1915 \return Address of interrupt handler function
1916 */
1917 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1918 {
1919 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1920 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1921 }
1922
1923
1924 /**
1925 \brief System Reset
1926 \details Initiates a system reset request to reset the MCU.
1927 */
1928 __STATIC_INLINE void __NVIC_SystemReset(void)
1929 {
1930 __DSB(); /* Ensure all outstanding memory accesses included
1931 buffered write are completed before reset */
1932 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1933 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1934 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1935 __DSB(); /* Ensure completion of memory access */
1936
1937 for(;;) /* wait until reset */
1938 {
1939 __NOP();
1940 }
1941 }
1942
1943 /*@} end of CMSIS_Core_NVICFunctions */
1944
1945 /* ########################## MPU functions #################################### */
1946
1947 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1948
1949 #include "mpu_armv7.h"
1950
1951 #endif
1952
1953
1954 /* ########################## FPU functions #################################### */
1955 /**
1956 \ingroup CMSIS_Core_FunctionInterface
1957 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1958 \brief Function that provides FPU type.
1959 @{
1960 */
1961
1962 /**
1963 \brief get FPU type
1964 \details returns the FPU type
1965 \returns
1966 - \b 0: No FPU
1967 - \b 1: Single precision FPU
1968 - \b 2: Double + Single precision FPU
1969 */
1970 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1971 {
1972 uint32_t mvfr0;
1973
1974 mvfr0 = FPU->MVFR0;
1975 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
1976 {
1977 return 1U; /* Single precision FPU */
1978 }
1979 else
1980 {
1981 return 0U; /* No FPU */
1982 }
1983 }
1984
1985
1986 /*@} end of CMSIS_Core_FpuFunctions */
1987
1988
1989
1990 /* ################################## SysTick function ############################################ */
1991 /**
1992 \ingroup CMSIS_Core_FunctionInterface
1993 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1994 \brief Functions that configure the System.
1995 @{
1996 */
1997
1998 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1999
2000 /**
2001 \brief System Tick Configuration
2002 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2003 Counter is in free running mode to generate periodic interrupts.
2004 \param [in] ticks Number of ticks between two interrupts.
2005 \return 0 Function succeeded.
2006 \return 1 Function failed.
2007 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2008 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2009 must contain a vendor-specific implementation of this function.
2010 */
2011 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2012 {
2013 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2014 {
2015 return (1UL); /* Reload value impossible */
2016 }
2017
2018 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2019 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2020 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2021 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2022 SysTick_CTRL_TICKINT_Msk |
2023 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2024 return (0UL); /* Function successful */
2025 }
2026
2027 #endif
2028
2029 /*@} end of CMSIS_Core_SysTickFunctions */
2030
2031
2032
2033 /* ##################################### Debug In/Output function ########################################### */
2034 /**
2035 \ingroup CMSIS_Core_FunctionInterface
2036 \defgroup CMSIS_core_DebugFunctions ITM Functions
2037 \brief Functions that access the ITM debug interface.
2038 @{
2039 */
2040
2041 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2042 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2043
2044
2045 /**
2046 \brief ITM Send Character
2047 \details Transmits a character via the ITM channel 0, and
2048 \li Just returns when no debugger is connected that has booked the output.
2049 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2050 \param [in] ch Character to transmit.
2051 \returns Character to transmit.
2052 */
2053 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2054 {
2055 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2056 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2057 {
2058 while (ITM->PORT[0U].u32 == 0UL)
2059 {
2060 __NOP();
2061 }
2062 ITM->PORT[0U].u8 = (uint8_t)ch;
2063 }
2064 return (ch);
2065 }
2066
2067
2068 /**
2069 \brief ITM Receive Character
2070 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2071 \return Received character.
2072 \return -1 No character pending.
2073 */
2074 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2075 {
2076 int32_t ch = -1; /* no character available */
2077
2078 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2079 {
2080 ch = ITM_RxBuffer;
2081 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2082 }
2083
2084 return (ch);
2085 }
2086
2087
2088 /**
2089 \brief ITM Check Character
2090 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2091 \return 0 No character available.
2092 \return 1 Character available.
2093 */
2094 __STATIC_INLINE int32_t ITM_CheckChar (void)
2095 {
2096
2097 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2098 {
2099 return (0); /* no character available */
2100 }
2101 else
2102 {
2103 return (1); /* character available */
2104 }
2105 }
2106
2107 /*@} end of CMSIS_core_DebugFunctions */
2108
2109
2110
2111
2112 #ifdef __cplusplus
2113 }
2114 #endif
2115
2116 #endif /* __CORE_CM4_H_DEPENDANT */
2117
2118 #endif /* __CMSIS_GENERIC */
INAV: Navigation-enabled flight control software