2 ******************************************************************************
3 * @file stm32f7xx_hal_dfsdm.h
4 * @author MCD Application Team
7 * @brief Header file of DFSDM HAL module.
8 ******************************************************************************
11 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ******************************************************************************
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_DFSDM_H
40 #define __STM32F7xx_HAL_DFSDM_H
46 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f7xx_hal_def.h"
50 /** @addtogroup STM32F7xx_HAL_Driver
58 /* Exported types ------------------------------------------------------------*/
59 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types
64 * @brief HAL DFSDM Channel states definition
68 HAL_DFSDM_CHANNEL_STATE_RESET
= 0x00U
, /*!< DFSDM channel not initialized */
69 HAL_DFSDM_CHANNEL_STATE_READY
= 0x01U
, /*!< DFSDM channel initialized and ready for use */
70 HAL_DFSDM_CHANNEL_STATE_ERROR
= 0xFFU
/*!< DFSDM channel state error */
71 }HAL_DFSDM_Channel_StateTypeDef
;
74 * @brief DFSDM channel output clock structure definition
78 FunctionalState Activation
; /*!< Output clock enable/disable */
79 uint32_t Selection
; /*!< Output clock is system clock or audio clock.
80 This parameter can be a value of @ref DFSDM_Channel_OuputClock */
81 uint32_t Divider
; /*!< Output clock divider.
82 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
83 }DFSDM_Channel_OutputClockTypeDef
;
86 * @brief DFSDM channel input structure definition
90 uint32_t Multiplexer
; /*!< Input is external serial inputs or internal register.
91 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
92 uint32_t DataPacking
; /*!< Standard, interleaved or dual mode for internal register.
93 This parameter can be a value of @ref DFSDM_Channel_DataPacking */
94 uint32_t Pins
; /*!< Input pins are taken from same or following channel.
95 This parameter can be a value of @ref DFSDM_Channel_InputPins */
96 }DFSDM_Channel_InputTypeDef
;
99 * @brief DFSDM channel serial interface structure definition
103 uint32_t Type
; /*!< SPI or Manchester modes.
104 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
105 uint32_t SpiClock
; /*!< SPI clock select (external or internal with different sampling point).
106 This parameter can be a value of @ref DFSDM_Channel_SpiClock */
107 }DFSDM_Channel_SerialInterfaceTypeDef
;
110 * @brief DFSDM channel analog watchdog structure definition
114 uint32_t FilterOrder
; /*!< Analog watchdog Sinc filter order.
115 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
116 uint32_t Oversampling
; /*!< Analog watchdog filter oversampling ratio.
117 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
118 }DFSDM_Channel_AwdTypeDef
;
121 * @brief DFSDM channel init structure definition
125 DFSDM_Channel_OutputClockTypeDef OutputClock
; /*!< DFSDM channel output clock parameters */
126 DFSDM_Channel_InputTypeDef Input
; /*!< DFSDM channel input parameters */
127 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface
; /*!< DFSDM channel serial interface parameters */
128 DFSDM_Channel_AwdTypeDef Awd
; /*!< DFSDM channel analog watchdog parameters */
129 int32_t Offset
; /*!< DFSDM channel offset.
130 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
131 uint32_t RightBitShift
; /*!< DFSDM channel right bit shift.
132 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
133 }DFSDM_Channel_InitTypeDef
;
136 * @brief DFSDM channel handle structure definition
140 DFSDM_Channel_TypeDef
*Instance
; /*!< DFSDM channel instance */
141 DFSDM_Channel_InitTypeDef Init
; /*!< DFSDM channel init parameters */
142 HAL_DFSDM_Channel_StateTypeDef State
; /*!< DFSDM channel state */
143 }DFSDM_Channel_HandleTypeDef
;
146 * @brief HAL DFSDM Filter states definition
150 HAL_DFSDM_FILTER_STATE_RESET
= 0x00U
, /*!< DFSDM filter not initialized */
151 HAL_DFSDM_FILTER_STATE_READY
= 0x01U
, /*!< DFSDM filter initialized and ready for use */
152 HAL_DFSDM_FILTER_STATE_REG
= 0x02U
, /*!< DFSDM filter regular conversion in progress */
153 HAL_DFSDM_FILTER_STATE_INJ
= 0x03U
, /*!< DFSDM filter injected conversion in progress */
154 HAL_DFSDM_FILTER_STATE_REG_INJ
= 0x04U
, /*!< DFSDM filter regular and injected conversions in progress */
155 HAL_DFSDM_FILTER_STATE_ERROR
= 0xFFU
/*!< DFSDM filter state error */
156 }HAL_DFSDM_Filter_StateTypeDef
;
159 * @brief DFSDM filter regular conversion parameters structure definition
163 uint32_t Trigger
; /*!< Trigger used to start regular conversion: software or synchronous.
164 This parameter can be a value of @ref DFSDM_Filter_Trigger */
165 FunctionalState FastMode
; /*!< Enable/disable fast mode for regular conversion */
166 FunctionalState DmaMode
; /*!< Enable/disable DMA for regular conversion */
167 }DFSDM_Filter_RegularParamTypeDef
;
170 * @brief DFSDM filter injected conversion parameters structure definition
174 uint32_t Trigger
; /*!< Trigger used to start injected conversion: software, external or synchronous.
175 This parameter can be a value of @ref DFSDM_Filter_Trigger */
176 FunctionalState ScanMode
; /*!< Enable/disable scanning mode for injected conversion */
177 FunctionalState DmaMode
; /*!< Enable/disable DMA for injected conversion */
178 uint32_t ExtTrigger
; /*!< External trigger.
179 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
180 uint32_t ExtTriggerEdge
; /*!< External trigger edge: rising, falling or both.
181 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
182 }DFSDM_Filter_InjectedParamTypeDef
;
185 * @brief DFSDM filter parameters structure definition
189 uint32_t SincOrder
; /*!< Sinc filter order.
190 This parameter can be a value of @ref DFSDM_Filter_SincOrder */
191 uint32_t Oversampling
; /*!< Filter oversampling ratio.
192 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
193 uint32_t IntOversampling
; /*!< Integrator oversampling ratio.
194 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
195 }DFSDM_Filter_FilterParamTypeDef
;
198 * @brief DFSDM filter init structure definition
202 DFSDM_Filter_RegularParamTypeDef RegularParam
; /*!< DFSDM regular conversion parameters */
203 DFSDM_Filter_InjectedParamTypeDef InjectedParam
; /*!< DFSDM injected conversion parameters */
204 DFSDM_Filter_FilterParamTypeDef FilterParam
; /*!< DFSDM filter parameters */
205 }DFSDM_Filter_InitTypeDef
;
208 * @brief DFSDM filter handle structure definition
212 DFSDM_Filter_TypeDef
*Instance
; /*!< DFSDM filter instance */
213 DFSDM_Filter_InitTypeDef Init
; /*!< DFSDM filter init parameters */
214 DMA_HandleTypeDef
*hdmaReg
; /*!< Pointer on DMA handler for regular conversions */
215 DMA_HandleTypeDef
*hdmaInj
; /*!< Pointer on DMA handler for injected conversions */
216 uint32_t RegularContMode
; /*!< Regular conversion continuous mode */
217 uint32_t RegularTrigger
; /*!< Trigger used for regular conversion */
218 uint32_t InjectedTrigger
; /*!< Trigger used for injected conversion */
219 uint32_t ExtTriggerEdge
; /*!< Rising, falling or both edges selected */
220 FunctionalState InjectedScanMode
; /*!< Injected scanning mode */
221 uint32_t InjectedChannelsNbr
; /*!< Number of channels in injected sequence */
222 uint32_t InjConvRemaining
; /*!< Injected conversions remaining */
223 HAL_DFSDM_Filter_StateTypeDef State
; /*!< DFSDM filter state */
224 uint32_t ErrorCode
; /*!< DFSDM filter error code */
225 }DFSDM_Filter_HandleTypeDef
;
228 * @brief DFSDM filter analog watchdog parameters structure definition
232 uint32_t DataSource
; /*!< Values from digital filter or from channel watchdog filter.
233 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
234 uint32_t Channel
; /*!< Analog watchdog channel selection.
235 This parameter can be a values combination of @ref DFSDM_Channel_Selection */
236 int32_t HighThreshold
; /*!< High threshold for the analog watchdog.
237 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
238 int32_t LowThreshold
; /*!< Low threshold for the analog watchdog.
239 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
240 uint32_t HighBreakSignal
; /*!< Break signal assigned to analog watchdog high threshold event.
241 This parameter can be a values combination of @ref DFSDM_BreakSignals */
242 uint32_t LowBreakSignal
; /*!< Break signal assigned to analog watchdog low threshold event.
243 This parameter can be a values combination of @ref DFSDM_BreakSignals */
244 }DFSDM_Filter_AwdParamTypeDef
;
249 /* End of exported types -----------------------------------------------------*/
251 /* Exported constants --------------------------------------------------------*/
252 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
256 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
259 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
260 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
265 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
268 #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
269 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
274 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
277 #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */
278 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
279 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
284 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
287 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
288 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
293 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
296 #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */
297 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
298 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
299 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
304 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
307 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */
308 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
309 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
310 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
315 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
318 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
319 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
320 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
321 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
326 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
329 #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */
330 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
331 #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
336 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
339 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */
340 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
341 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
342 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1, 2 and 3 */
343 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1, 2 and 3 */
344 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
345 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
346 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \
347 DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
348 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM filter 0, 1, 2 and 3 */
349 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
350 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \
351 DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
352 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \
353 DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
358 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
361 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
362 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
363 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
368 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
371 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
372 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
373 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
374 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
375 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
376 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
381 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
384 #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */
385 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
390 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
393 #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
394 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
395 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
396 #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */
401 /** @defgroup DFSDM_BreakSignals DFSDM break signals
404 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
405 #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */
406 #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */
407 #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */
408 #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */
413 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
416 /* DFSDM Channels ------------------------------------------------------------*/
417 /* The DFSDM channels are defined as follows:
418 - in 16-bit LSB the channel mask is set
419 - in 16-bit MSB the channel number is set
420 e.g. for channel 5 definition:
421 - the channel mask is 0x00000020 (bit 5 is set)
422 - the channel number 5 is 0x00050000
423 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
424 #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
425 #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
426 #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
427 #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
428 #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
429 #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
430 #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
431 #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
436 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
439 #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
440 #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */
445 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
448 #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
449 #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
457 /* End of exported constants -------------------------------------------------*/
459 /* Exported macros -----------------------------------------------------------*/
460 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
464 /** @brief Reset DFSDM channel handle state.
465 * @param __HANDLE__: DFSDM channel handle.
468 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
470 /** @brief Reset DFSDM filter handle state.
471 * @param __HANDLE__: DFSDM filter handle.
474 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
479 /* End of exported macros ----------------------------------------------------*/
481 /* Exported functions --------------------------------------------------------*/
482 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
486 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
489 /* Channel initialization and de-initialization functions *********************/
490 HAL_StatusTypeDef
HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
491 HAL_StatusTypeDef
HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
492 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
493 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
498 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
501 /* Channel operation functions ************************************************/
502 HAL_StatusTypeDef
HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
503 HAL_StatusTypeDef
HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
504 HAL_StatusTypeDef
HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
505 HAL_StatusTypeDef
HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
507 HAL_StatusTypeDef
HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
, uint32_t Threshold
, uint32_t BreakSignal
);
508 HAL_StatusTypeDef
HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
, uint32_t Threshold
, uint32_t BreakSignal
);
509 HAL_StatusTypeDef
HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
510 HAL_StatusTypeDef
HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
512 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
513 HAL_StatusTypeDef
HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
, int32_t Offset
);
515 HAL_StatusTypeDef
HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
, uint32_t Timeout
);
516 HAL_StatusTypeDef
HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
, uint32_t Timeout
);
518 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
519 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
524 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
527 /* Channel state function *****************************************************/
528 HAL_DFSDM_Channel_StateTypeDef
HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef
*hdfsdm_channel
);
533 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
536 /* Filter initialization and de-initialization functions *********************/
537 HAL_StatusTypeDef
HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
538 HAL_StatusTypeDef
HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
539 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
540 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
545 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
548 /* Filter control functions *********************/
549 HAL_StatusTypeDef
HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
,
551 uint32_t ContinuousMode
);
552 HAL_StatusTypeDef
HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
,
558 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
561 /* Filter operation functions *********************/
562 HAL_StatusTypeDef
HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
563 HAL_StatusTypeDef
HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
564 HAL_StatusTypeDef
HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, int32_t *pData
, uint32_t Length
);
565 HAL_StatusTypeDef
HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, int16_t *pData
, uint32_t Length
);
566 HAL_StatusTypeDef
HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
567 HAL_StatusTypeDef
HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
568 HAL_StatusTypeDef
HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
569 HAL_StatusTypeDef
HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
570 HAL_StatusTypeDef
HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
571 HAL_StatusTypeDef
HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, int32_t *pData
, uint32_t Length
);
572 HAL_StatusTypeDef
HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, int16_t *pData
, uint32_t Length
);
573 HAL_StatusTypeDef
HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
574 HAL_StatusTypeDef
HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
575 HAL_StatusTypeDef
HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
576 HAL_StatusTypeDef
HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
,
577 DFSDM_Filter_AwdParamTypeDef
* awdParam
);
578 HAL_StatusTypeDef
HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
579 HAL_StatusTypeDef
HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, uint32_t Channel
);
580 HAL_StatusTypeDef
HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
582 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, uint32_t* Channel
);
583 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, uint32_t* Channel
);
584 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, uint32_t* Channel
);
585 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, uint32_t* Channel
);
586 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
588 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
590 HAL_StatusTypeDef
HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, uint32_t Timeout
);
591 HAL_StatusTypeDef
HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, uint32_t Timeout
);
593 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
594 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
595 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
596 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
597 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
, uint32_t Channel
, uint32_t Threshold
);
598 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
603 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
606 /* Filter state functions *****************************************************/
607 HAL_DFSDM_Filter_StateTypeDef
HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
608 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef
*hdfsdm_filter
);
616 /* End of exported functions -------------------------------------------------*/
618 /* Private macros ------------------------------------------------------------*/
619 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros
622 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
623 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
624 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
625 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
626 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
627 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
628 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
629 ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
630 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
631 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
632 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
633 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
634 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
635 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
636 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
637 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
638 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
639 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
640 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
641 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
642 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
643 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
644 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
645 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
646 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
647 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
648 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
649 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
650 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
651 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
652 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
653 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
654 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \
655 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
656 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \
657 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
658 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
659 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
660 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
661 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
662 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
663 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\
664 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))
665 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
666 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
667 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
668 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
669 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
670 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
671 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
672 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
673 ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
674 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
675 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
676 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
677 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
678 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
679 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
680 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
681 ((CHANNEL) == DFSDM_CHANNEL_1) || \
682 ((CHANNEL) == DFSDM_CHANNEL_2) || \
683 ((CHANNEL) == DFSDM_CHANNEL_3) || \
684 ((CHANNEL) == DFSDM_CHANNEL_4) || \
685 ((CHANNEL) == DFSDM_CHANNEL_5) || \
686 ((CHANNEL) == DFSDM_CHANNEL_6) || \
687 ((CHANNEL) == DFSDM_CHANNEL_7))
688 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
689 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
690 ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
694 /* End of private macros -----------------------------------------------------*/
703 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
708 #endif /* __STM32F7xx_HAL_DFSDM_H */
710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/