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[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_rcc.h
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1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_rcc.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of RCC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_RCC_H
40 #define __STM32F7xx_HAL_RCC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48
49 /* Include RCC HAL Extended module */
50 /* (include on top of file since RCC structures are defined in extended file) */
51 #include "stm32f7xx_hal_rcc_ex.h"
52
53 /** @addtogroup STM32F7xx_HAL_Driver
54 * @{
55 */
56
57 /** @addtogroup RCC
58 * @{
59 */
60
61 /* Exported types ------------------------------------------------------------*/
62
63 /** @defgroup RCC_Exported_Types RCC Exported Types
64 * @{
65 */
66
67 /**
68 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
69 */
70 typedef struct
71 {
72 uint32_t OscillatorType; /*!< The oscillators to be configured.
73 This parameter can be a value of @ref RCC_Oscillator_Type */
74
75 uint32_t HSEState; /*!< The new state of the HSE.
76 This parameter can be a value of @ref RCC_HSE_Config */
77
78 uint32_t LSEState; /*!< The new state of the LSE.
79 This parameter can be a value of @ref RCC_LSE_Config */
80
81 uint32_t HSIState; /*!< The new state of the HSI.
82 This parameter can be a value of @ref RCC_HSI_Config */
83
84 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
85 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
86
87 uint32_t LSIState; /*!< The new state of the LSI.
88 This parameter can be a value of @ref RCC_LSI_Config */
89
90 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
91
92 }RCC_OscInitTypeDef;
93
94 /**
95 * @brief RCC System, AHB and APB busses clock configuration structure definition
96 */
97 typedef struct
98 {
99 uint32_t ClockType; /*!< The clock to be configured.
100 This parameter can be a value of @ref RCC_System_Clock_Type */
101
102 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
103 This parameter can be a value of @ref RCC_System_Clock_Source */
104
105 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
106 This parameter can be a value of @ref RCC_AHB_Clock_Source */
107
108 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
109 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
110
111 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
112 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
113
114 }RCC_ClkInitTypeDef;
115
116 /**
117 * @}
118 */
119
120 /* Exported constants --------------------------------------------------------*/
121 /** @defgroup RCC_Exported_Constants RCC Exported Constants
122 * @{
123 */
124
125 /** @defgroup RCC_Oscillator_Type Oscillator Type
126 * @{
127 */
128 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
129 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
130 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
131 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
132 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
133 /**
134 * @}
135 */
136
137 /** @defgroup RCC_HSE_Config RCC HSE Config
138 * @{
139 */
140 #define RCC_HSE_OFF ((uint32_t)0x00000000U)
141 #define RCC_HSE_ON RCC_CR_HSEON
142 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
143 /**
144 * @}
145 */
146
147 /** @defgroup RCC_LSE_Config RCC LSE Config
148 * @{
149 */
150 #define RCC_LSE_OFF ((uint32_t)0x00000000U)
151 #define RCC_LSE_ON RCC_BDCR_LSEON
152 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
153 /**
154 * @}
155 */
156
157 /** @defgroup RCC_HSI_Config RCC HSI Config
158 * @{
159 */
160 #define RCC_HSI_OFF ((uint32_t)0x00000000U)
161 #define RCC_HSI_ON RCC_CR_HSION
162
163 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
164 /**
165 * @}
166 */
167
168 /** @defgroup RCC_LSI_Config RCC LSI Config
169 * @{
170 */
171 #define RCC_LSI_OFF ((uint32_t)0x00000000U)
172 #define RCC_LSI_ON RCC_CSR_LSION
173 /**
174 * @}
175 */
176
177 /** @defgroup RCC_PLL_Config RCC PLL Config
178 * @{
179 */
180 #define RCC_PLL_NONE ((uint32_t)0x00000000U)
181 #define RCC_PLL_OFF ((uint32_t)0x00000001U)
182 #define RCC_PLL_ON ((uint32_t)0x00000002U)
183 /**
184 * @}
185 */
186
187 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
188 * @{
189 */
190 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
191 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
192 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
193 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
194 /**
195 * @}
196 */
197
198 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
199 * @{
200 */
201 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
202 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
203 /**
204 * @}
205 */
206
207 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
208 * @{
209 */
210 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
211 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
212 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
213 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
214 /**
215 * @}
216 */
217
218 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
219 * @{
220 */
221 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
222 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
223 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
224 /**
225 * @}
226 */
227
228
229 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
230 * @{
231 */
232 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
233 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
234 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
235 /**
236 * @}
237 */
238
239 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
240 * @{
241 */
242 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
243 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
244 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
245 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
246 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
247 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
248 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
249 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
250 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
251 /**
252 * @}
253 */
254
255 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
256 * @{
257 */
258 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
259 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
260 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
261 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
262 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
263 /**
264 * @}
265 */
266
267 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
268 * @{
269 */
270 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
271 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
272 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
273 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
274 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
275 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
276 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
277 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
278 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
279 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
280 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
281 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
282 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
283 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
284 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
285 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
286 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
287 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
288 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
289 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
290 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
291 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
292 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
293 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
294 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
295 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
296 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
297 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
298 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
299 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
300 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
301 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
302 /**
303 * @}
304 */
305
306
307
308 /** @defgroup RCC_MCO_Index RCC MCO Index
309 * @{
310 */
311 #define RCC_MCO1 ((uint32_t)0x00000000U)
312 #define RCC_MCO2 ((uint32_t)0x00000001U)
313 /**
314 * @}
315 */
316
317 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
318 * @{
319 */
320 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
321 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
322 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
323 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
324 /**
325 * @}
326 */
327
328 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
329 * @{
330 */
331 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
332 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
333 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
334 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
335 /**
336 * @}
337 */
338
339 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
340 * @{
341 */
342 #define RCC_MCODIV_1 ((uint32_t)0x00000000U)
343 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
344 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
345 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
346 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
347 /**
348 * @}
349 */
350
351 /** @defgroup RCC_Interrupt RCC Interrupt
352 * @{
353 */
354 #define RCC_IT_LSIRDY ((uint8_t)0x01U)
355 #define RCC_IT_LSERDY ((uint8_t)0x02U)
356 #define RCC_IT_HSIRDY ((uint8_t)0x04U)
357 #define RCC_IT_HSERDY ((uint8_t)0x08U)
358 #define RCC_IT_PLLRDY ((uint8_t)0x10U)
359 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
360 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40U)
361 #define RCC_IT_CSS ((uint8_t)0x80U)
362 /**
363 * @}
364 */
365
366 /** @defgroup RCC_Flag RCC Flags
367 * Elements values convention: 0XXYYYYYb
368 * - YYYYY : Flag position in the register
369 * - 0XX : Register index
370 * - 01: CR register
371 * - 10: BDCR register
372 * - 11: CSR register
373 * @{
374 */
375 /* Flags in the CR register */
376 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
377 #define RCC_FLAG_HSERDY ((uint8_t)0x31U)
378 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
379 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
380 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU)
381
382 /* Flags in the BDCR register */
383 #define RCC_FLAG_LSERDY ((uint8_t)0x41U)
384
385 /* Flags in the CSR register */
386 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
387 #define RCC_FLAG_BORRST ((uint8_t)0x79U)
388 #define RCC_FLAG_PINRST ((uint8_t)0x7AU)
389 #define RCC_FLAG_PORRST ((uint8_t)0x7BU)
390 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
391 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
392 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
393 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
394 /**
395 * @}
396 */
397
398 /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
399 * @{
400 */
401 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
402 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
403 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
404 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
405 /**
406 * @}
407 */
408
409 /**
410 * @}
411 */
412
413 /* Exported macro ------------------------------------------------------------*/
414 /** @defgroup RCC_Exported_Macros RCC Exported Macros
415 * @{
416 */
417
418 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
419 * @brief Enable or disable the AHB1 peripheral clock.
420 * @note After reset, the peripheral clock (used for registers read/write access)
421 * is disabled and the application software has to enable this clock before
422 * using it.
423 * @{
424 */
425 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
426 __IO uint32_t tmpreg; \
427 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
428 /* Delay after an RCC peripheral clock enabling */ \
429 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
430 UNUSED(tmpreg); \
431 } while(0)
432
433 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
434 __IO uint32_t tmpreg; \
435 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
436 /* Delay after an RCC peripheral clock enabling */ \
437 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
438 UNUSED(tmpreg); \
439 } while(0)
440
441 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
442 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
443
444 /**
445 * @}
446 */
447
448 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
449 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
450 * @note After reset, the peripheral clock (used for registers read/write access)
451 * is disabled and the application software has to enable this clock before
452 * using it.
453 * @{
454 */
455 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
456 __IO uint32_t tmpreg; \
457 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
458 /* Delay after an RCC peripheral clock enabling */ \
459 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
460 UNUSED(tmpreg); \
461 } while(0)
462
463 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
464 __IO uint32_t tmpreg; \
465 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
466 /* Delay after an RCC peripheral clock enabling */ \
467 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
468 UNUSED(tmpreg); \
469 } while(0)
470
471 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
472 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
473 /**
474 * @}
475 */
476
477 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
478 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
479 * @note After reset, the peripheral clock (used for registers read/write access)
480 * is disabled and the application software has to enable this clock before
481 * using it.
482 * @{
483 */
484 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
485 __IO uint32_t tmpreg; \
486 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
487 /* Delay after an RCC peripheral clock enabling */ \
488 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
489 UNUSED(tmpreg); \
490 } while(0)
491
492 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
493
494 /**
495 * @}
496 */
497
498 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
499 * @brief Get the enable or disable status of the AHB1 peripheral clock.
500 * @note After reset, the peripheral clock (used for registers read/write access)
501 * is disabled and the application software has to enable this clock before
502 * using it.
503 * @{
504 */
505 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
506 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
507
508 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
509 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
510 /**
511 * @}
512 */
513
514 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
515 * @brief Get the enable or disable status of the APB1 peripheral clock.
516 * @note After reset, the peripheral clock (used for registers read/write access)
517 * is disabled and the application software has to enable this clock before
518 * using it.
519 * @{
520 */
521 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
522 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
523
524 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
525 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
526 /**
527 * @}
528 */
529
530 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
531 * @brief EGet the enable or disable status of the APB2 peripheral clock.
532 * @note After reset, the peripheral clock (used for registers read/write access)
533 * is disabled and the application software has to enable this clock before
534 * using it.
535 * @{
536 */
537 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
538 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
539 /**
540 * @}
541 */
542
543 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
544 * @brief Force or release AHB peripheral reset.
545 * @{
546 */
547 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
548 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
549 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
550
551 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
552 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
553 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
554 /**
555 * @}
556 */
557
558 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
559 * @brief Force or release APB1 peripheral reset.
560 * @{
561 */
562 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
563 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
564 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
565
566 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
567 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
568 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
569 /**
570 * @}
571 */
572
573 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
574 * @brief Force or release APB2 peripheral reset.
575 * @{
576 */
577 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
578 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
579
580 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
581 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
582
583 /**
584 * @}
585 */
586
587 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
588 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
589 * power consumption.
590 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
591 * @note By default, all peripheral clocks are enabled during SLEEP mode.
592 * @{
593 */
594 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
595 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
596
597 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
598 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
599
600 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
601 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
602 * power consumption.
603 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
604 * @note By default, all peripheral clocks are enabled during SLEEP mode.
605 */
606 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
607 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
608
609 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
610 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
611
612 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
613 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
614 * power consumption.
615 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
616 * @note By default, all peripheral clocks are enabled during SLEEP mode.
617 */
618 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
619 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
620
621 /**
622 * @}
623 */
624
625 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
626 * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
627 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
628 * power consumption.
629 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
630 * @note By default, all peripheral clocks are enabled during SLEEP mode.
631 * @{
632 */
633 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
634 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
635
636 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
637 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
638 /**
639 * @}
640 */
641
642 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
643 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
644 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
645 * power consumption.
646 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
647 * @note By default, all peripheral clocks are enabled during SLEEP mode.
648 * @{
649 */
650 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
651 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
652
653 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
654 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
655 /**
656 * @}
657 */
658
659 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
660 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
661 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
662 * power consumption.
663 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
664 * @note By default, all peripheral clocks are enabled during SLEEP mode.
665 * @{
666 */
667 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
668 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
669 /**
670 * @}
671 */
672
673 /** @defgroup RCC_HSI_Configuration HSI Configuration
674 * @{
675 */
676
677 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
678 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
679 * It is used (enabled by hardware) as system clock source after startup
680 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
681 * of the HSE used directly or indirectly as system clock (if the Clock
682 * Security System CSS is enabled).
683 * @note HSI can not be stopped if it is used as system clock source. In this case,
684 * you have to select another source of the system clock then stop the HSI.
685 * @note After enabling the HSI, the application software should wait on HSIRDY
686 * flag to be set indicating that HSI clock is stable and can be used as
687 * system clock source.
688 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
689 * clock cycles.
690 */
691 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
692 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
693
694 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
695 * @note The calibration is used to compensate for the variations in voltage
696 * and temperature that influence the frequency of the internal HSI RC.
697 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
698 * (default is RCC_HSICALIBRATION_DEFAULT).
699 */
700 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
701 RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
702 /**
703 * @}
704 */
705
706 /** @defgroup RCC_LSI_Configuration LSI Configuration
707 * @{
708 */
709
710 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
711 * @note After enabling the LSI, the application software should wait on
712 * LSIRDY flag to be set indicating that LSI clock is stable and can
713 * be used to clock the IWDG and/or the RTC.
714 * @note LSI can not be disabled if the IWDG is running.
715 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
716 * clock cycles.
717 */
718 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
719 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
720 /**
721 * @}
722 */
723
724 /** @defgroup RCC_HSE_Configuration HSE Configuration
725 * @{
726 */
727 /**
728 * @brief Macro to configure the External High Speed oscillator (HSE).
729 * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not
730 * supported by this macro. User should request a transition to HSE Off
731 * first and then HSE On or HSE Bypass.
732 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
733 * software should wait on HSERDY flag to be set indicating that HSE clock
734 * is stable and can be used to clock the PLL and/or system clock.
735 * @note HSE state can not be changed if it is used directly or through the
736 * PLL as system clock. In this case, you have to select another source
737 * of the system clock then change the HSE state (ex. disable it).
738 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
739 * @note This function reset the CSSON bit, so if the clock security system(CSS)
740 * was previously enabled you have to enable it again after calling this
741 * function.
742 * @param __STATE__: specifies the new state of the HSE.
743 * This parameter can be one of the following values:
744 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
745 * 6 HSE oscillator clock cycles.
746 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
747 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
748 */
749 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
750 do { \
751 if ((__STATE__) == RCC_HSE_ON) \
752 { \
753 SET_BIT(RCC->CR, RCC_CR_HSEON); \
754 } \
755 else if ((__STATE__) == RCC_HSE_OFF) \
756 { \
757 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
758 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
759 } \
760 else if ((__STATE__) == RCC_HSE_BYPASS) \
761 { \
762 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
763 SET_BIT(RCC->CR, RCC_CR_HSEON); \
764 } \
765 else \
766 { \
767 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
768 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
769 } \
770 } while(0)
771 /**
772 * @}
773 */
774
775 /** @defgroup RCC_LSE_Configuration LSE Configuration
776 * @{
777 */
778
779 /**
780 * @brief Macro to configure the External Low Speed oscillator (LSE).
781 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
782 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
783 * @note As the LSE is in the Backup domain and write access is denied to
784 * this domain after reset, you have to enable write access using
785 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
786 * (to be done once after reset).
787 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
788 * software should wait on LSERDY flag to be set indicating that LSE clock
789 * is stable and can be used to clock the RTC.
790 * @param __STATE__: specifies the new state of the LSE.
791 * This parameter can be one of the following values:
792 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
793 * 6 LSE oscillator clock cycles.
794 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
795 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
796 */
797 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
798 do { \
799 if((__STATE__) == RCC_LSE_ON) \
800 { \
801 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
802 } \
803 else if((__STATE__) == RCC_LSE_OFF) \
804 { \
805 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
806 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
807 } \
808 else if((__STATE__) == RCC_LSE_BYPASS) \
809 { \
810 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
811 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
812 } \
813 else \
814 { \
815 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
816 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
817 } \
818 } while(0)
819 /**
820 * @}
821 */
822
823 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
824 * @{
825 */
826
827 /** @brief Macros to enable or disable the RTC clock.
828 * @note These macros must be used only after the RTC clock source was selected.
829 */
830 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
831 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
832
833 /** @brief Macros to configure the RTC clock (RTCCLK).
834 * @note As the RTC clock configuration bits are in the Backup domain and write
835 * access is denied to this domain after reset, you have to enable write
836 * access using the Power Backup Access macro before to configure
837 * the RTC clock source (to be done once after reset).
838 * @note Once the RTC clock is configured it can't be changed unless the
839 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
840 * a Power On Reset (POR).
841 * @param __RTCCLKSource__: specifies the RTC clock source.
842 * This parameter can be one of the following values:
843 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
844 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
845 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
846 * as RTC clock, where x:[2,31]
847 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
848 * work in STOP and STANDBY modes, and can be used as wakeup source.
849 * However, when the HSE clock is used as RTC clock source, the RTC
850 * cannot be used in STOP and STANDBY modes.
851 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
852 * RTC clock source).
853 */
854 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
855 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
856
857 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
858 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
859 } while (0)
860
861 /** @brief Macros to force or release the Backup domain reset.
862 * @note This function resets the RTC peripheral (including the backup registers)
863 * and the RTC clock source selection in RCC_CSR register.
864 * @note The BKPSRAM is not affected by this reset.
865 */
866 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
867 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
868 /**
869 * @}
870 */
871
872 /** @defgroup RCC_PLL_Configuration PLL Configuration
873 * @{
874 */
875
876 /** @brief Macros to enable or disable the main PLL.
877 * @note After enabling the main PLL, the application software should wait on
878 * PLLRDY flag to be set indicating that PLL clock is stable and can
879 * be used as system clock source.
880 * @note The main PLL can not be disabled if it is used as system clock source
881 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
882 */
883 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
884 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
885
886 /** @brief Macro to configure the PLL clock source.
887 * @note This function must be used only when the main PLL is disabled.
888 * @param __PLLSOURCE__: specifies the PLL entry clock source.
889 * This parameter can be one of the following values:
890 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
891 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
892 *
893 */
894 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
895
896 /** @brief Macro to configure the PLL multiplication factor.
897 * @note This function must be used only when the main PLL is disabled.
898 * @param __PLLM__: specifies the division factor for PLL VCO input clock
899 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
900 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
901 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
902 * of 2 MHz to limit PLL jitter.
903 *
904 */
905 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
906 /**
907 * @}
908 */
909
910 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
911 * @{
912 */
913
914 /** @brief Macro to configure the I2S clock source (I2SCLK).
915 * @note This function must be called before enabling the I2S APB clock.
916 * @param __SOURCE__: specifies the I2S clock source.
917 * This parameter can be one of the following values:
918 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
919 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
920 * used as I2S clock source.
921 */
922 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
923 RCC->CFGR |= (__SOURCE__); \
924 }while(0)
925
926 /** @brief Macros to enable or disable the PLLI2S.
927 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
928 */
929 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
930 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
931 /**
932 * @}
933 */
934
935 /** @defgroup RCC_Get_Clock_source Get Clock source
936 * @{
937 */
938 /**
939 * @brief Macro to configure the system clock source.
940 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
941 * This parameter can be one of the following values:
942 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
943 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
944 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
945 */
946 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
947
948 /** @brief Macro to get the clock source used as system clock.
949 * @retval The clock source used as system clock. The returned value can be one
950 * of the following:
951 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
952 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
953 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
954 */
955 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
956
957 /**
958 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
959 * @note As the LSE is in the Backup domain and write access is denied to
960 * this domain after reset, you have to enable write access using
961 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
962 * (to be done once after reset).
963 * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
964 * This parameter can be one of the following values:
965 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
966 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
967 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
968 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
969 * @retval None
970 */
971 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
972 (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
973
974 /** @brief Macro to get the oscillator used as PLL clock source.
975 * @retval The oscillator used as PLL clock source. The returned value can be one
976 * of the following:
977 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
978 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
979 */
980 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
981 /**
982 * @}
983 */
984
985 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
986 * @{
987 */
988
989 /** @brief Macro to configure the MCO1 clock.
990 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
991 * This parameter can be one of the following values:
992 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
993 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
994 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
995 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
996 * @param __MCODIV__ specifies the MCO clock prescaler.
997 * This parameter can be one of the following values:
998 * @arg RCC_MCODIV_1: no division applied to MCOx clock
999 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
1000 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
1001 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
1002 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
1003 */
1004
1005 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1006 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1007
1008 /** @brief Macro to configure the MCO2 clock.
1009 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
1010 * This parameter can be one of the following values:
1011 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
1012 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
1013 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
1014 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
1015 * @param __MCODIV__ specifies the MCO clock prescaler.
1016 * This parameter can be one of the following values:
1017 * @arg RCC_MCODIV_1: no division applied to MCOx clock
1018 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
1019 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
1020 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
1021 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
1022 */
1023
1024 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1025 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
1026 /**
1027 * @}
1028 */
1029
1030 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1031 * @brief macros to manage the specified RCC Flags and interrupts.
1032 * @{
1033 */
1034
1035 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
1036 * the selected interrupts).
1037 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
1038 * This parameter can be any combination of the following values:
1039 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1040 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1041 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1042 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1043 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1044 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1045 */
1046 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1047
1048 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
1049 * the selected interrupts).
1050 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
1051 * This parameter can be any combination of the following values:
1052 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1053 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1054 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1055 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1056 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1057 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1058 */
1059 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1060
1061 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
1062 * bits to clear the selected interrupt pending bits.
1063 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
1064 * This parameter can be any combination of the following values:
1065 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1066 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1067 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1068 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1069 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1070 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1071 * @arg RCC_IT_CSS: Clock Security System interrupt
1072 */
1073 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1074
1075 /** @brief Check the RCC's interrupt has occurred or not.
1076 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
1077 * This parameter can be one of the following values:
1078 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
1079 * @arg RCC_IT_LSERDY: LSE ready interrupt.
1080 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
1081 * @arg RCC_IT_HSERDY: HSE ready interrupt.
1082 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
1083 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
1084 * @arg RCC_IT_CSS: Clock Security System interrupt
1085 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1086 */
1087 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1088
1089 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
1090 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
1091 */
1092 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1093
1094 /** @brief Check RCC flag is set or not.
1095 * @param __FLAG__: specifies the flag to check.
1096 * This parameter can be one of the following values:
1097 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
1098 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
1099 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
1100 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
1101 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
1102 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
1103 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
1104 * @arg RCC_FLAG_PINRST: Pin reset.
1105 * @arg RCC_FLAG_PORRST: POR/PDR reset.
1106 * @arg RCC_FLAG_SFTRST: Software reset.
1107 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
1108 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
1109 * @arg RCC_FLAG_LPWRRST: Low Power reset.
1110 * @retval The new state of __FLAG__ (TRUE or FALSE).
1111 */
1112 #define RCC_FLAG_MASK ((uint8_t)0x1F)
1113 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
1114
1115 /**
1116 * @}
1117 */
1118
1119 /**
1120 * @}
1121 */
1122
1123 /* Include RCC HAL Extension module */
1124 #include "stm32f7xx_hal_rcc_ex.h"
1125
1126 /* Exported functions --------------------------------------------------------*/
1127 /** @addtogroup RCC_Exported_Functions
1128 * @{
1129 */
1130
1131 /** @addtogroup RCC_Exported_Functions_Group1
1132 * @{
1133 */
1134 /* Initialization and de-initialization functions ******************************/
1135 void HAL_RCC_DeInit(void);
1136 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1137 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1138 /**
1139 * @}
1140 */
1141
1142 /** @addtogroup RCC_Exported_Functions_Group2
1143 * @{
1144 */
1145 /* Peripheral Control functions ************************************************/
1146 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1147 void HAL_RCC_EnableCSS(void);
1148 void HAL_RCC_DisableCSS(void);
1149 uint32_t HAL_RCC_GetSysClockFreq(void);
1150 uint32_t HAL_RCC_GetHCLKFreq(void);
1151 uint32_t HAL_RCC_GetPCLK1Freq(void);
1152 uint32_t HAL_RCC_GetPCLK2Freq(void);
1153 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1154 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1155
1156 /* CSS NMI IRQ handler */
1157 void HAL_RCC_NMI_IRQHandler(void);
1158
1159 /* User Callbacks in non blocking mode (IT mode) */
1160 void HAL_RCC_CSSCallback(void);
1161 /**
1162 * @}
1163 */
1164
1165 /**
1166 * @}
1167 */
1168
1169 /* Private types -------------------------------------------------------------*/
1170 /* Private variables ---------------------------------------------------------*/
1171 /* Private constants ---------------------------------------------------------*/
1172 /** @defgroup RCC_Private_Constants RCC Private Constants
1173 * @{
1174 */
1175 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1176 #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1177 #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1178 #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
1179 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
1180
1181 /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
1182 * @brief RCC registers bit address alias
1183 * @{
1184 */
1185 /* CIR register byte 2 (Bits[15:8]) base address */
1186 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
1187
1188 /* CIR register byte 3 (Bits[23:16]) base address */
1189 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
1190
1191 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
1192 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1193 /**
1194 * @}
1195 */
1196 /**
1197 * @}
1198 */
1199
1200 /* Private macros ------------------------------------------------------------*/
1201 /** @addtogroup RCC_Private_Macros RCC Private Macros
1202 * @{
1203 */
1204
1205 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
1206 * @{
1207 */
1208 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
1209
1210 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
1211 ((HSE) == RCC_HSE_BYPASS))
1212
1213 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
1214 ((LSE) == RCC_LSE_BYPASS))
1215
1216 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
1217
1218 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
1219
1220 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
1221
1222 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
1223 ((SOURCE) == RCC_PLLSOURCE_HSE))
1224
1225 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
1226 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
1227 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
1228 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
1229
1230 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
1231
1232 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
1233 ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
1234 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
1235
1236 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
1237 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
1238 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
1239 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
1240 ((HCLK) == RCC_SYSCLK_DIV512))
1241
1242 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
1243
1244 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
1245 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
1246 ((PCLK) == RCC_HCLK_DIV16))
1247
1248 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
1249
1250
1251 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
1252 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
1253
1254 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
1255 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
1256
1257 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
1258 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
1259 ((DIV) == RCC_MCODIV_5))
1260 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
1261
1262 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
1263 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
1264 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
1265 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
1266 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
1267 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
1268 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
1269 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
1270 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
1271 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
1272 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
1273 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
1274 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
1275 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
1276 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
1277 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
1278
1279
1280 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \
1281 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
1282 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
1283 ((DRIVE) == RCC_LSEDRIVE_HIGH))
1284 /**
1285 * @}
1286 */
1287
1288 /**
1289 * @}
1290 */
1291
1292 /**
1293 * @}
1294 */
1295
1296 /**
1297 * @}
1298 */
1299
1300 #ifdef __cplusplus
1301 }
1302 #endif
1303
1304 #endif /* __STM32F7xx_HAL_RCC_H */
1305
1306 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software