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[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_spi.h
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1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_spi.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of SPI LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_LL_SPI_H
40 #define __STM32F7xx_LL_SPI_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx.h"
48
49 /** @addtogroup STM32F7xx_LL_Driver
50 * @{
51 */
52
53 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
54
55 /** @defgroup SPI_LL SPI
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 #if defined(USE_FULL_LL_DRIVER)
65 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
66 * @{
67 */
68
69 /**
70 * @brief SPI Init structures definition
71 */
72 typedef struct
73 {
74 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
75 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
76
77 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
78
79 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
80 This parameter can be a value of @ref SPI_LL_EC_MODE.
81
82 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
83
84 uint32_t DataWidth; /*!< Specifies the SPI data width.
85 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
86
87 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
88
89 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
90 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
91
92 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
93
94 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
95 This parameter can be a value of @ref SPI_LL_EC_PHASE.
96
97 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
98
99 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
101
102 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
103
104 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
105 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
106 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
107
108 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
109
110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
112
113 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
114
115 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
116 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
117
118 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
119
120 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
121 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
122
123 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
124
125 } LL_SPI_InitTypeDef;
126
127 /**
128 * @}
129 */
130 #endif /* USE_FULL_LL_DRIVER */
131
132 /* Exported constants --------------------------------------------------------*/
133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
134 * @{
135 */
136
137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
138 * @brief Flags defines which can be used with LL_SPI_ReadReg function
139 * @{
140 */
141 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
142 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
143 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
144 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
145 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
146 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
147 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
148 /**
149 * @}
150 */
151
152 /** @defgroup SPI_LL_EC_IT IT Defines
153 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
154 * @{
155 */
156 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
157 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
158 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
159 /**
160 * @}
161 */
162
163 /** @defgroup SPI_LL_EC_MODE Operation Mode
164 * @{
165 */
166 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
167 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
168 /**
169 * @}
170 */
171
172 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
173 * @{
174 */
175 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
176 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
177 /**
178 * @}
179 */
180
181 /** @defgroup SPI_LL_EC_PHASE Clock Phase
182 * @{
183 */
184 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
185 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
186 /**
187 * @}
188 */
189
190 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
191 * @{
192 */
193 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
194 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
195 /**
196 * @}
197 */
198
199 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
200 * @{
201 */
202 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
203 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
204 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
205 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
206 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
207 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
208 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
209 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
210 /**
211 * @}
212 */
213
214 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
215 * @{
216 */
217 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
218 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
219 /**
220 * @}
221 */
222
223 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
224 * @{
225 */
226 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
227 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
228 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
229 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
230 /**
231 * @}
232 */
233
234 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
235 * @{
236 */
237 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
238 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
239 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
240 /**
241 * @}
242 */
243
244 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
245 * @{
246 */
247 #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
248 #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
249 #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
250 #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
251 #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
252 #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
253 #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
254 #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
255 #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
256 #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
257 #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
258 #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
259 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
260 /**
261 * @}
262 */
263 #if defined(USE_FULL_LL_DRIVER)
264
265 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
266 * @{
267 */
268 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
269 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
270 /**
271 * @}
272 */
273 #endif /* USE_FULL_LL_DRIVER */
274
275 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
276 * @{
277 */
278 #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
279 #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
280 /**
281 * @}
282 */
283
284 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
285 * @{
286 */
287 #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
288 #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
289 /**
290 * @}
291 */
292
293 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
294 * @{
295 */
296 #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
297 #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
298 #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
299 #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
300 /**
301 * @}
302 */
303
304 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
305 * @{
306 */
307 #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
308 #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
309 #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
310 #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
311 /**
312 * @}
313 */
314
315 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
316 * @{
317 */
318 #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
319 #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
320
321 /**
322 * @}
323 */
324
325 /**
326 * @}
327 */
328
329 /* Exported macro ------------------------------------------------------------*/
330 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
331 * @{
332 */
333
334 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
335 * @{
336 */
337
338 /**
339 * @brief Write a value in SPI register
340 * @param __INSTANCE__ SPI Instance
341 * @param __REG__ Register to be written
342 * @param __VALUE__ Value to be written in the register
343 * @retval None
344 */
345 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
346
347 /**
348 * @brief Read a value in SPI register
349 * @param __INSTANCE__ SPI Instance
350 * @param __REG__ Register to be read
351 * @retval Register value
352 */
353 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
354 /**
355 * @}
356 */
357
358 /**
359 * @}
360 */
361
362 /* Exported functions --------------------------------------------------------*/
363 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
364 * @{
365 */
366
367 /** @defgroup SPI_LL_EF_Configuration Configuration
368 * @{
369 */
370
371 /**
372 * @brief Enable SPI peripheral
373 * @rmtoll CR1 SPE LL_SPI_Enable
374 * @param SPIx SPI Instance
375 * @retval None
376 */
377 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
378 {
379 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
380 }
381
382 /**
383 * @brief Disable SPI peripheral
384 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
385 * @rmtoll CR1 SPE LL_SPI_Disable
386 * @param SPIx SPI Instance
387 * @retval None
388 */
389 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
390 {
391 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
392 }
393
394 /**
395 * @brief Check if SPI peripheral is enabled
396 * @rmtoll CR1 SPE LL_SPI_IsEnabled
397 * @param SPIx SPI Instance
398 * @retval State of bit (1 or 0).
399 */
400 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
401 {
402 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
403 }
404
405 /**
406 * @brief Set SPI operation mode to Master or Slave
407 * @note This bit should not be changed when communication is ongoing.
408 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
409 * CR1 SSI LL_SPI_SetMode
410 * @param SPIx SPI Instance
411 * @param Mode This parameter can be one of the following values:
412 * @arg @ref LL_SPI_MODE_MASTER
413 * @arg @ref LL_SPI_MODE_SLAVE
414 * @retval None
415 */
416 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
417 {
418 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
419 }
420
421 /**
422 * @brief Get SPI operation mode (Master or Slave)
423 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
424 * CR1 SSI LL_SPI_GetMode
425 * @param SPIx SPI Instance
426 * @retval Returned value can be one of the following values:
427 * @arg @ref LL_SPI_MODE_MASTER
428 * @arg @ref LL_SPI_MODE_SLAVE
429 */
430 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
431 {
432 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
433 }
434
435 /**
436 * @brief Set serial protocol used
437 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
438 * @rmtoll CR2 FRF LL_SPI_SetStandard
439 * @param SPIx SPI Instance
440 * @param Standard This parameter can be one of the following values:
441 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
442 * @arg @ref LL_SPI_PROTOCOL_TI
443 * @retval None
444 */
445 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
446 {
447 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
448 }
449
450 /**
451 * @brief Get serial protocol used
452 * @rmtoll CR2 FRF LL_SPI_GetStandard
453 * @param SPIx SPI Instance
454 * @retval Returned value can be one of the following values:
455 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
456 * @arg @ref LL_SPI_PROTOCOL_TI
457 */
458 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
459 {
460 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
461 }
462
463 /**
464 * @brief Set clock phase
465 * @note This bit should not be changed when communication is ongoing.
466 * This bit is not used in SPI TI mode.
467 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
468 * @param SPIx SPI Instance
469 * @param ClockPhase This parameter can be one of the following values:
470 * @arg @ref LL_SPI_PHASE_1EDGE
471 * @arg @ref LL_SPI_PHASE_2EDGE
472 * @retval None
473 */
474 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
475 {
476 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
477 }
478
479 /**
480 * @brief Get clock phase
481 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
482 * @param SPIx SPI Instance
483 * @retval Returned value can be one of the following values:
484 * @arg @ref LL_SPI_PHASE_1EDGE
485 * @arg @ref LL_SPI_PHASE_2EDGE
486 */
487 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
488 {
489 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
490 }
491
492 /**
493 * @brief Set clock polarity
494 * @note This bit should not be changed when communication is ongoing.
495 * This bit is not used in SPI TI mode.
496 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
497 * @param SPIx SPI Instance
498 * @param ClockPolarity This parameter can be one of the following values:
499 * @arg @ref LL_SPI_POLARITY_LOW
500 * @arg @ref LL_SPI_POLARITY_HIGH
501 * @retval None
502 */
503 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
504 {
505 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
506 }
507
508 /**
509 * @brief Get clock polarity
510 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
511 * @param SPIx SPI Instance
512 * @retval Returned value can be one of the following values:
513 * @arg @ref LL_SPI_POLARITY_LOW
514 * @arg @ref LL_SPI_POLARITY_HIGH
515 */
516 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
517 {
518 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
519 }
520
521 /**
522 * @brief Set baud rate prescaler
523 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
524 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
525 * @param SPIx SPI Instance
526 * @param BaudRate This parameter can be one of the following values:
527 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
528 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
529 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
530 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
531 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
532 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
533 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
534 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
535 * @retval None
536 */
537 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
538 {
539 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
540 }
541
542 /**
543 * @brief Get baud rate prescaler
544 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
545 * @param SPIx SPI Instance
546 * @retval Returned value can be one of the following values:
547 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
548 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
549 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
550 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
551 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
552 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
553 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
554 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
555 */
556 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
557 {
558 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
559 }
560
561 /**
562 * @brief Set transfer bit order
563 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
564 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
565 * @param SPIx SPI Instance
566 * @param BitOrder This parameter can be one of the following values:
567 * @arg @ref LL_SPI_LSB_FIRST
568 * @arg @ref LL_SPI_MSB_FIRST
569 * @retval None
570 */
571 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
572 {
573 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
574 }
575
576 /**
577 * @brief Get transfer bit order
578 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
579 * @param SPIx SPI Instance
580 * @retval Returned value can be one of the following values:
581 * @arg @ref LL_SPI_LSB_FIRST
582 * @arg @ref LL_SPI_MSB_FIRST
583 */
584 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
585 {
586 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
587 }
588
589 /**
590 * @brief Set transfer direction mode
591 * @note For Half-Duplex mode, Rx Direction is set by default.
592 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
593 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
594 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
595 * CR1 BIDIOE LL_SPI_SetTransferDirection
596 * @param SPIx SPI Instance
597 * @param TransferDirection This parameter can be one of the following values:
598 * @arg @ref LL_SPI_FULL_DUPLEX
599 * @arg @ref LL_SPI_SIMPLEX_RX
600 * @arg @ref LL_SPI_HALF_DUPLEX_RX
601 * @arg @ref LL_SPI_HALF_DUPLEX_TX
602 * @retval None
603 */
604 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
605 {
606 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
607 }
608
609 /**
610 * @brief Get transfer direction mode
611 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
612 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
613 * CR1 BIDIOE LL_SPI_GetTransferDirection
614 * @param SPIx SPI Instance
615 * @retval Returned value can be one of the following values:
616 * @arg @ref LL_SPI_FULL_DUPLEX
617 * @arg @ref LL_SPI_SIMPLEX_RX
618 * @arg @ref LL_SPI_HALF_DUPLEX_RX
619 * @arg @ref LL_SPI_HALF_DUPLEX_TX
620 */
621 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
622 {
623 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
624 }
625
626 /**
627 * @brief Set frame data width
628 * @rmtoll CR2 DS LL_SPI_SetDataWidth
629 * @param SPIx SPI Instance
630 * @param DataWidth This parameter can be one of the following values:
631 * @arg @ref LL_SPI_DATAWIDTH_4BIT
632 * @arg @ref LL_SPI_DATAWIDTH_5BIT
633 * @arg @ref LL_SPI_DATAWIDTH_6BIT
634 * @arg @ref LL_SPI_DATAWIDTH_7BIT
635 * @arg @ref LL_SPI_DATAWIDTH_8BIT
636 * @arg @ref LL_SPI_DATAWIDTH_9BIT
637 * @arg @ref LL_SPI_DATAWIDTH_10BIT
638 * @arg @ref LL_SPI_DATAWIDTH_11BIT
639 * @arg @ref LL_SPI_DATAWIDTH_12BIT
640 * @arg @ref LL_SPI_DATAWIDTH_13BIT
641 * @arg @ref LL_SPI_DATAWIDTH_14BIT
642 * @arg @ref LL_SPI_DATAWIDTH_15BIT
643 * @arg @ref LL_SPI_DATAWIDTH_16BIT
644 * @retval None
645 */
646 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
647 {
648 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
649 }
650
651 /**
652 * @brief Get frame data width
653 * @rmtoll CR2 DS LL_SPI_GetDataWidth
654 * @param SPIx SPI Instance
655 * @retval Returned value can be one of the following values:
656 * @arg @ref LL_SPI_DATAWIDTH_4BIT
657 * @arg @ref LL_SPI_DATAWIDTH_5BIT
658 * @arg @ref LL_SPI_DATAWIDTH_6BIT
659 * @arg @ref LL_SPI_DATAWIDTH_7BIT
660 * @arg @ref LL_SPI_DATAWIDTH_8BIT
661 * @arg @ref LL_SPI_DATAWIDTH_9BIT
662 * @arg @ref LL_SPI_DATAWIDTH_10BIT
663 * @arg @ref LL_SPI_DATAWIDTH_11BIT
664 * @arg @ref LL_SPI_DATAWIDTH_12BIT
665 * @arg @ref LL_SPI_DATAWIDTH_13BIT
666 * @arg @ref LL_SPI_DATAWIDTH_14BIT
667 * @arg @ref LL_SPI_DATAWIDTH_15BIT
668 * @arg @ref LL_SPI_DATAWIDTH_16BIT
669 */
670 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
671 {
672 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
673 }
674
675 /**
676 * @brief Set threshold of RXFIFO that triggers an RXNE event
677 * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
678 * @param SPIx SPI Instance
679 * @param Threshold This parameter can be one of the following values:
680 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
681 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
682 * @retval None
683 */
684 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
685 {
686 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
687 }
688
689 /**
690 * @brief Get threshold of RXFIFO that triggers an RXNE event
691 * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
692 * @param SPIx SPI Instance
693 * @retval Returned value can be one of the following values:
694 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
695 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
696 */
697 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
698 {
699 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
700 }
701
702 /**
703 * @}
704 */
705
706 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
707 * @{
708 */
709
710 /**
711 * @brief Enable CRC
712 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
713 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
714 * @param SPIx SPI Instance
715 * @retval None
716 */
717 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
718 {
719 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
720 }
721
722 /**
723 * @brief Disable CRC
724 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
725 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
726 * @param SPIx SPI Instance
727 * @retval None
728 */
729 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
730 {
731 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
732 }
733
734 /**
735 * @brief Check if CRC is enabled
736 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
737 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
738 * @param SPIx SPI Instance
739 * @retval State of bit (1 or 0).
740 */
741 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
742 {
743 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
744 }
745
746 /**
747 * @brief Set CRC Length
748 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
749 * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
750 * @param SPIx SPI Instance
751 * @param CRCLength This parameter can be one of the following values:
752 * @arg @ref LL_SPI_CRC_8BIT
753 * @arg @ref LL_SPI_CRC_16BIT
754 * @retval None
755 */
756 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
757 {
758 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
759 }
760
761 /**
762 * @brief Get CRC Length
763 * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
764 * @param SPIx SPI Instance
765 * @retval Returned value can be one of the following values:
766 * @arg @ref LL_SPI_CRC_8BIT
767 * @arg @ref LL_SPI_CRC_16BIT
768 */
769 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
770 {
771 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
772 }
773
774 /**
775 * @brief Set CRCNext to transfer CRC on the line
776 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
777 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
778 * @param SPIx SPI Instance
779 * @retval None
780 */
781 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
782 {
783 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
784 }
785
786 /**
787 * @brief Set polynomial for CRC calculation
788 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
789 * @param SPIx SPI Instance
790 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
791 * @retval None
792 */
793 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
794 {
795 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
796 }
797
798 /**
799 * @brief Get polynomial for CRC calculation
800 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
801 * @param SPIx SPI Instance
802 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
803 */
804 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
805 {
806 return (uint32_t)(READ_REG(SPIx->CRCPR));
807 }
808
809 /**
810 * @brief Get Rx CRC
811 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
812 * @param SPIx SPI Instance
813 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
814 */
815 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
816 {
817 return (uint32_t)(READ_REG(SPIx->RXCRCR));
818 }
819
820 /**
821 * @brief Get Tx CRC
822 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
823 * @param SPIx SPI Instance
824 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
825 */
826 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
827 {
828 return (uint32_t)(READ_REG(SPIx->TXCRCR));
829 }
830
831 /**
832 * @}
833 */
834
835 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
836 * @{
837 */
838
839 /**
840 * @brief Set NSS mode
841 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
842 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
843 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
844 * @param SPIx SPI Instance
845 * @param NSS This parameter can be one of the following values:
846 * @arg @ref LL_SPI_NSS_SOFT
847 * @arg @ref LL_SPI_NSS_HARD_INPUT
848 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
849 * @retval None
850 */
851 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
852 {
853 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
854 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
855 }
856
857 /**
858 * @brief Get NSS mode
859 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
860 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
861 * @param SPIx SPI Instance
862 * @retval Returned value can be one of the following values:
863 * @arg @ref LL_SPI_NSS_SOFT
864 * @arg @ref LL_SPI_NSS_HARD_INPUT
865 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
866 */
867 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
868 {
869 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
870 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
871 return (Ssm | Ssoe);
872 }
873
874 /**
875 * @brief Enable NSS pulse management
876 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
877 * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
878 * @param SPIx SPI Instance
879 * @retval None
880 */
881 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
882 {
883 SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
884 }
885
886 /**
887 * @brief Disable NSS pulse management
888 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
889 * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
890 * @param SPIx SPI Instance
891 * @retval None
892 */
893 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
894 {
895 CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
896 }
897
898 /**
899 * @brief Check if NSS pulse is enabled
900 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
901 * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
902 * @param SPIx SPI Instance
903 * @retval State of bit (1 or 0).
904 */
905 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
906 {
907 return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
908 }
909
910 /**
911 * @}
912 */
913
914 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
915 * @{
916 */
917
918 /**
919 * @brief Check if Rx buffer is not empty
920 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
921 * @param SPIx SPI Instance
922 * @retval State of bit (1 or 0).
923 */
924 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
925 {
926 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
927 }
928
929 /**
930 * @brief Check if Tx buffer is empty
931 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
932 * @param SPIx SPI Instance
933 * @retval State of bit (1 or 0).
934 */
935 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
936 {
937 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
938 }
939
940 /**
941 * @brief Get CRC error flag
942 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
943 * @param SPIx SPI Instance
944 * @retval State of bit (1 or 0).
945 */
946 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
947 {
948 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
949 }
950
951 /**
952 * @brief Get mode fault error flag
953 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
954 * @param SPIx SPI Instance
955 * @retval State of bit (1 or 0).
956 */
957 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
958 {
959 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
960 }
961
962 /**
963 * @brief Get overrun error flag
964 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
965 * @param SPIx SPI Instance
966 * @retval State of bit (1 or 0).
967 */
968 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
969 {
970 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
971 }
972
973 /**
974 * @brief Get busy flag
975 * @note The BSY flag is cleared under any one of the following conditions:
976 * -When the SPI is correctly disabled
977 * -When a fault is detected in Master mode (MODF bit set to 1)
978 * -In Master mode, when it finishes a data transmission and no new data is ready to be
979 * sent
980 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
981 * each data transfer.
982 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
983 * @param SPIx SPI Instance
984 * @retval State of bit (1 or 0).
985 */
986 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
987 {
988 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
989 }
990
991 /**
992 * @brief Get frame format error flag
993 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
994 * @param SPIx SPI Instance
995 * @retval State of bit (1 or 0).
996 */
997 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
998 {
999 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
1000 }
1001
1002 /**
1003 * @brief Get FIFO reception Level
1004 * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
1005 * @param SPIx SPI Instance
1006 * @retval Returned value can be one of the following values:
1007 * @arg @ref LL_SPI_RX_FIFO_EMPTY
1008 * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
1009 * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
1010 * @arg @ref LL_SPI_RX_FIFO_FULL
1011 */
1012 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
1013 {
1014 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
1015 }
1016
1017 /**
1018 * @brief Get FIFO Transmission Level
1019 * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
1020 * @param SPIx SPI Instance
1021 * @retval Returned value can be one of the following values:
1022 * @arg @ref LL_SPI_TX_FIFO_EMPTY
1023 * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
1024 * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
1025 * @arg @ref LL_SPI_TX_FIFO_FULL
1026 */
1027 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
1028 {
1029 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
1030 }
1031
1032 /**
1033 * @brief Clear CRC error flag
1034 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
1035 * @param SPIx SPI Instance
1036 * @retval None
1037 */
1038 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1039 {
1040 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
1041 }
1042
1043 /**
1044 * @brief Clear mode fault error flag
1045 * @note Clearing this flag is done by a read access to the SPIx_SR
1046 * register followed by a write access to the SPIx_CR1 register
1047 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
1048 * @param SPIx SPI Instance
1049 * @retval None
1050 */
1051 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1052 {
1053 __IO uint32_t tmpreg;
1054 tmpreg = SPIx->SR;
1055 (void) tmpreg;
1056 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
1057 (void) tmpreg;
1058 }
1059
1060 /**
1061 * @brief Clear overrun error flag
1062 * @note Clearing this flag is done by a read access to the SPIx_DR
1063 * register followed by a read access to the SPIx_SR register
1064 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
1065 * @param SPIx SPI Instance
1066 * @retval None
1067 */
1068 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1069 {
1070 __IO uint32_t tmpreg;
1071 tmpreg = SPIx->DR;
1072 (void) tmpreg;
1073 tmpreg = SPIx->SR;
1074 (void) tmpreg;
1075 }
1076
1077 /**
1078 * @brief Clear frame format error flag
1079 * @note Clearing this flag is done by reading SPIx_SR register
1080 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
1081 * @param SPIx SPI Instance
1082 * @retval None
1083 */
1084 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1085 {
1086 __IO uint32_t tmpreg;
1087 tmpreg = SPIx->SR;
1088 (void) tmpreg;
1089 }
1090
1091 /**
1092 * @}
1093 */
1094
1095 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
1096 * @{
1097 */
1098
1099 /**
1100 * @brief Enable error interrupt
1101 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
1102 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
1103 * @param SPIx SPI Instance
1104 * @retval None
1105 */
1106 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
1107 {
1108 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
1109 }
1110
1111 /**
1112 * @brief Enable Rx buffer not empty interrupt
1113 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
1114 * @param SPIx SPI Instance
1115 * @retval None
1116 */
1117 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
1118 {
1119 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
1120 }
1121
1122 /**
1123 * @brief Enable Tx buffer empty interrupt
1124 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
1125 * @param SPIx SPI Instance
1126 * @retval None
1127 */
1128 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
1129 {
1130 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
1131 }
1132
1133 /**
1134 * @brief Disable error interrupt
1135 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
1136 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
1137 * @param SPIx SPI Instance
1138 * @retval None
1139 */
1140 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
1141 {
1142 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
1143 }
1144
1145 /**
1146 * @brief Disable Rx buffer not empty interrupt
1147 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
1148 * @param SPIx SPI Instance
1149 * @retval None
1150 */
1151 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
1152 {
1153 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
1154 }
1155
1156 /**
1157 * @brief Disable Tx buffer empty interrupt
1158 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
1159 * @param SPIx SPI Instance
1160 * @retval None
1161 */
1162 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
1163 {
1164 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
1165 }
1166
1167 /**
1168 * @brief Check if error interrupt is enabled
1169 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
1170 * @param SPIx SPI Instance
1171 * @retval State of bit (1 or 0).
1172 */
1173 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
1174 {
1175 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
1176 }
1177
1178 /**
1179 * @brief Check if Rx buffer not empty interrupt is enabled
1180 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
1181 * @param SPIx SPI Instance
1182 * @retval State of bit (1 or 0).
1183 */
1184 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
1185 {
1186 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
1187 }
1188
1189 /**
1190 * @brief Check if Tx buffer empty interrupt
1191 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
1192 * @param SPIx SPI Instance
1193 * @retval State of bit (1 or 0).
1194 */
1195 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
1196 {
1197 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
1198 }
1199
1200 /**
1201 * @}
1202 */
1203
1204 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
1205 * @{
1206 */
1207
1208 /**
1209 * @brief Enable DMA Rx
1210 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
1211 * @param SPIx SPI Instance
1212 * @retval None
1213 */
1214 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1215 {
1216 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1217 }
1218
1219 /**
1220 * @brief Disable DMA Rx
1221 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
1222 * @param SPIx SPI Instance
1223 * @retval None
1224 */
1225 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1226 {
1227 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1228 }
1229
1230 /**
1231 * @brief Check if DMA Rx is enabled
1232 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
1233 * @param SPIx SPI Instance
1234 * @retval State of bit (1 or 0).
1235 */
1236 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1237 {
1238 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
1239 }
1240
1241 /**
1242 * @brief Enable DMA Tx
1243 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
1244 * @param SPIx SPI Instance
1245 * @retval None
1246 */
1247 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1248 {
1249 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1250 }
1251
1252 /**
1253 * @brief Disable DMA Tx
1254 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1255 * @param SPIx SPI Instance
1256 * @retval None
1257 */
1258 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1259 {
1260 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1261 }
1262
1263 /**
1264 * @brief Check if DMA Tx is enabled
1265 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1266 * @param SPIx SPI Instance
1267 * @retval State of bit (1 or 0).
1268 */
1269 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1270 {
1271 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
1272 }
1273
1274 /**
1275 * @brief Set parity of Last DMA reception
1276 * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
1277 * @param SPIx SPI Instance
1278 * @param Parity This parameter can be one of the following values:
1279 * @arg @ref LL_SPI_DMA_PARITY_ODD
1280 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1281 * @retval None
1282 */
1283 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
1284 {
1285 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
1286 }
1287
1288 /**
1289 * @brief Get parity configuration for Last DMA reception
1290 * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
1291 * @param SPIx SPI Instance
1292 * @retval Returned value can be one of the following values:
1293 * @arg @ref LL_SPI_DMA_PARITY_ODD
1294 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1295 */
1296 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
1297 {
1298 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
1299 }
1300
1301 /**
1302 * @brief Set parity of Last DMA transmission
1303 * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
1304 * @param SPIx SPI Instance
1305 * @param Parity This parameter can be one of the following values:
1306 * @arg @ref LL_SPI_DMA_PARITY_ODD
1307 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1308 * @retval None
1309 */
1310 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
1311 {
1312 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
1313 }
1314
1315 /**
1316 * @brief Get parity configuration for Last DMA transmission
1317 * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
1318 * @param SPIx SPI Instance
1319 * @retval Returned value can be one of the following values:
1320 * @arg @ref LL_SPI_DMA_PARITY_ODD
1321 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1322 */
1323 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
1324 {
1325 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
1326 }
1327
1328 /**
1329 * @brief Get the data register address used for DMA transfer
1330 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1331 * @param SPIx SPI Instance
1332 * @retval Address of data register
1333 */
1334 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
1335 {
1336 return (uint32_t) & (SPIx->DR);
1337 }
1338
1339 /**
1340 * @}
1341 */
1342
1343 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1344 * @{
1345 */
1346
1347 /**
1348 * @brief Read 8-Bits in the data register
1349 * @rmtoll DR DR LL_SPI_ReceiveData8
1350 * @param SPIx SPI Instance
1351 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1352 */
1353 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1354 {
1355 return (uint8_t)(READ_REG(SPIx->DR));
1356 }
1357
1358 /**
1359 * @brief Read 16-Bits in the data register
1360 * @rmtoll DR DR LL_SPI_ReceiveData16
1361 * @param SPIx SPI Instance
1362 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1363 */
1364 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1365 {
1366 return (uint16_t)(READ_REG(SPIx->DR));
1367 }
1368
1369
1370 #pragma GCC diagnostic push
1371 #pragma GCC diagnostic ignored "-Wstrict-aliasing"
1372 /**
1373 * @brief Write 8-Bits in the data register
1374 * @rmtoll DR DR LL_SPI_TransmitData8
1375 * @param SPIx SPI Instance
1376 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1377 * @retval None
1378 */
1379 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1380 {
1381 *((__IO uint8_t *)&SPIx->DR) = TxData;
1382 }
1383
1384 /**
1385 * @brief Write 16-Bits in the data register
1386 * @rmtoll DR DR LL_SPI_TransmitData16
1387 * @param SPIx SPI Instance
1388 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1389 * @retval None
1390 */
1391 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1392 {
1393 *((__IO uint16_t *)&SPIx->DR) = TxData;
1394 }
1395 #pragma GCC diagnostic pop
1396
1397 /**
1398 * @}
1399 */
1400 #if defined(USE_FULL_LL_DRIVER)
1401 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1402 * @{
1403 */
1404
1405 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
1406 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1407 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1408
1409 /**
1410 * @}
1411 */
1412 #endif /* USE_FULL_LL_DRIVER */
1413 /**
1414 * @}
1415 */
1416
1417 /**
1418 * @}
1419 */
1420
1421 /** @defgroup I2S_LL I2S
1422 * @{
1423 */
1424
1425 /* Private variables ---------------------------------------------------------*/
1426 /* Private constants ---------------------------------------------------------*/
1427 /* Private macros ------------------------------------------------------------*/
1428
1429 /* Exported types ------------------------------------------------------------*/
1430 #if defined(USE_FULL_LL_DRIVER)
1431 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1432 * @{
1433 */
1434
1435 /**
1436 * @brief I2S Init structure definition
1437 */
1438
1439 typedef struct
1440 {
1441 uint32_t Mode; /*!< Specifies the I2S operating mode.
1442 This parameter can be a value of @ref I2S_LL_EC_MODE
1443
1444 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1445
1446 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1447 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1448
1449 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1450
1451
1452 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1453 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1454
1455 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1456
1457
1458 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1459 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1460
1461 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1462
1463
1464 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1465 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1466
1467 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1468 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1469
1470
1471 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1472 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1473
1474 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1475
1476 } LL_I2S_InitTypeDef;
1477
1478 /**
1479 * @}
1480 */
1481 #endif /*USE_FULL_LL_DRIVER*/
1482
1483 /* Exported constants --------------------------------------------------------*/
1484 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1485 * @{
1486 */
1487
1488 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1489 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1490 * @{
1491 */
1492 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1493 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1494 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1495 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1496 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1497 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1498 /**
1499 * @}
1500 */
1501
1502 /** @defgroup SPI_LL_EC_IT IT Defines
1503 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1504 * @{
1505 */
1506 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1507 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1508 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1509 /**
1510 * @}
1511 */
1512
1513 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1514 * @{
1515 */
1516 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
1517 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
1518 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
1519 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
1520 /**
1521 * @}
1522 */
1523
1524 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1525 * @{
1526 */
1527 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1528 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1529 /**
1530 * @}
1531 */
1532
1533 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1534 * @{
1535 */
1536 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1537 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1538 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1539 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1540 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1541 /**
1542 * @}
1543 */
1544
1545 /** @defgroup I2S_LL_EC_MODE Operation Mode
1546 * @{
1547 */
1548 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1549 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1550 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1551 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1552 /**
1553 * @}
1554 */
1555
1556 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1557 * @{
1558 */
1559 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1560 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1561 /**
1562 * @}
1563 */
1564
1565 #if defined(USE_FULL_LL_DRIVER)
1566
1567 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1568 * @{
1569 */
1570 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1571 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1572 /**
1573 * @}
1574 */
1575
1576 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1577 * @{
1578 */
1579
1580 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1581 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1582 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1583 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1584 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1585 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1586 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1587 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1588 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1589 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1590 /**
1591 * @}
1592 */
1593 #endif /* USE_FULL_LL_DRIVER */
1594
1595 /**
1596 * @}
1597 */
1598
1599 /* Exported macro ------------------------------------------------------------*/
1600 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1601 * @{
1602 */
1603
1604 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1605 * @{
1606 */
1607
1608 /**
1609 * @brief Write a value in I2S register
1610 * @param __INSTANCE__ I2S Instance
1611 * @param __REG__ Register to be written
1612 * @param __VALUE__ Value to be written in the register
1613 * @retval None
1614 */
1615 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1616
1617 /**
1618 * @brief Read a value in I2S register
1619 * @param __INSTANCE__ I2S Instance
1620 * @param __REG__ Register to be read
1621 * @retval Register value
1622 */
1623 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1624 /**
1625 * @}
1626 */
1627
1628 /**
1629 * @}
1630 */
1631
1632
1633 /* Exported functions --------------------------------------------------------*/
1634
1635 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1636 * @{
1637 */
1638
1639 /** @defgroup I2S_LL_EF_Configuration Configuration
1640 * @{
1641 */
1642
1643 /**
1644 * @brief Select I2S mode and Enable I2S peripheral
1645 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1646 * I2SCFGR I2SE LL_I2S_Enable
1647 * @param SPIx SPI Instance
1648 * @retval None
1649 */
1650 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1651 {
1652 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1653 }
1654
1655 /**
1656 * @brief Disable I2S peripheral
1657 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1658 * @param SPIx SPI Instance
1659 * @retval None
1660 */
1661 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1662 {
1663 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1664 }
1665
1666 /**
1667 * @brief Check if I2S peripheral is enabled
1668 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1669 * @param SPIx SPI Instance
1670 * @retval State of bit (1 or 0).
1671 */
1672 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
1673 {
1674 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
1675 }
1676
1677 /**
1678 * @brief Set I2S data frame length
1679 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1680 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1681 * @param SPIx SPI Instance
1682 * @param DataFormat This parameter can be one of the following values:
1683 * @arg @ref LL_I2S_DATAFORMAT_16B
1684 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1685 * @arg @ref LL_I2S_DATAFORMAT_24B
1686 * @arg @ref LL_I2S_DATAFORMAT_32B
1687 * @retval None
1688 */
1689 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1690 {
1691 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1692 }
1693
1694 /**
1695 * @brief Get I2S data frame length
1696 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1697 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1698 * @param SPIx SPI Instance
1699 * @retval Returned value can be one of the following values:
1700 * @arg @ref LL_I2S_DATAFORMAT_16B
1701 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1702 * @arg @ref LL_I2S_DATAFORMAT_24B
1703 * @arg @ref LL_I2S_DATAFORMAT_32B
1704 */
1705 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
1706 {
1707 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1708 }
1709
1710 /**
1711 * @brief Set I2S clock polarity
1712 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1713 * @param SPIx SPI Instance
1714 * @param ClockPolarity This parameter can be one of the following values:
1715 * @arg @ref LL_I2S_POLARITY_LOW
1716 * @arg @ref LL_I2S_POLARITY_HIGH
1717 * @retval None
1718 */
1719 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1720 {
1721 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1722 }
1723
1724 /**
1725 * @brief Get I2S clock polarity
1726 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1727 * @param SPIx SPI Instance
1728 * @retval Returned value can be one of the following values:
1729 * @arg @ref LL_I2S_POLARITY_LOW
1730 * @arg @ref LL_I2S_POLARITY_HIGH
1731 */
1732 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
1733 {
1734 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1735 }
1736
1737 /**
1738 * @brief Set I2S standard protocol
1739 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1740 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1741 * @param SPIx SPI Instance
1742 * @param Standard This parameter can be one of the following values:
1743 * @arg @ref LL_I2S_STANDARD_PHILIPS
1744 * @arg @ref LL_I2S_STANDARD_MSB
1745 * @arg @ref LL_I2S_STANDARD_LSB
1746 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1747 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1748 * @retval None
1749 */
1750 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1751 {
1752 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1753 }
1754
1755 /**
1756 * @brief Get I2S standard protocol
1757 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1758 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1759 * @param SPIx SPI Instance
1760 * @retval Returned value can be one of the following values:
1761 * @arg @ref LL_I2S_STANDARD_PHILIPS
1762 * @arg @ref LL_I2S_STANDARD_MSB
1763 * @arg @ref LL_I2S_STANDARD_LSB
1764 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1765 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1766 */
1767 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
1768 {
1769 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1770 }
1771
1772 /**
1773 * @brief Set I2S transfer mode
1774 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1775 * @param SPIx SPI Instance
1776 * @param Mode This parameter can be one of the following values:
1777 * @arg @ref LL_I2S_MODE_SLAVE_TX
1778 * @arg @ref LL_I2S_MODE_SLAVE_RX
1779 * @arg @ref LL_I2S_MODE_MASTER_TX
1780 * @arg @ref LL_I2S_MODE_MASTER_RX
1781 * @retval None
1782 */
1783 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1784 {
1785 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1786 }
1787
1788 /**
1789 * @brief Get I2S transfer mode
1790 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1791 * @param SPIx SPI Instance
1792 * @retval Returned value can be one of the following values:
1793 * @arg @ref LL_I2S_MODE_SLAVE_TX
1794 * @arg @ref LL_I2S_MODE_SLAVE_RX
1795 * @arg @ref LL_I2S_MODE_MASTER_TX
1796 * @arg @ref LL_I2S_MODE_MASTER_RX
1797 */
1798 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
1799 {
1800 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1801 }
1802
1803 /**
1804 * @brief Set I2S linear prescaler
1805 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1806 * @param SPIx SPI Instance
1807 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1808 * @retval None
1809 */
1810 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1811 {
1812 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1813 }
1814
1815 /**
1816 * @brief Get I2S linear prescaler
1817 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1818 * @param SPIx SPI Instance
1819 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1820 */
1821 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
1822 {
1823 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1824 }
1825
1826 /**
1827 * @brief Set I2S parity prescaler
1828 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1829 * @param SPIx SPI Instance
1830 * @param PrescalerParity This parameter can be one of the following values:
1831 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1832 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1833 * @retval None
1834 */
1835 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1836 {
1837 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1838 }
1839
1840 /**
1841 * @brief Get I2S parity prescaler
1842 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1843 * @param SPIx SPI Instance
1844 * @retval Returned value can be one of the following values:
1845 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1846 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1847 */
1848 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
1849 {
1850 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1851 }
1852
1853 /**
1854 * @brief Enable the master clock ouput (Pin MCK)
1855 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1856 * @param SPIx SPI Instance
1857 * @retval None
1858 */
1859 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1860 {
1861 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1862 }
1863
1864 /**
1865 * @brief Disable the master clock ouput (Pin MCK)
1866 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1867 * @param SPIx SPI Instance
1868 * @retval None
1869 */
1870 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1871 {
1872 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1873 }
1874
1875 /**
1876 * @brief Check if the master clock ouput (Pin MCK) is enabled
1877 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1878 * @param SPIx SPI Instance
1879 * @retval State of bit (1 or 0).
1880 */
1881 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
1882 {
1883 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
1884 }
1885
1886 #if defined(SPI_I2SCFGR_ASTRTEN)
1887 /**
1888 * @brief Enable asynchronous start
1889 * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
1890 * @param SPIx SPI Instance
1891 * @retval None
1892 */
1893 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
1894 {
1895 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1896 }
1897
1898 /**
1899 * @brief Disable asynchronous start
1900 * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
1901 * @param SPIx SPI Instance
1902 * @retval None
1903 */
1904 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
1905 {
1906 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1907 }
1908
1909 /**
1910 * @brief Check if asynchronous start is enabled
1911 * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
1912 * @param SPIx SPI Instance
1913 * @retval State of bit (1 or 0).
1914 */
1915 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
1916 {
1917 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
1918 }
1919 #endif /* SPI_I2SCFGR_ASTRTEN */
1920
1921 /**
1922 * @}
1923 */
1924
1925 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1926 * @{
1927 */
1928
1929 /**
1930 * @brief Check if Rx buffer is not empty
1931 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1932 * @param SPIx SPI Instance
1933 * @retval State of bit (1 or 0).
1934 */
1935 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
1936 {
1937 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1938 }
1939
1940 /**
1941 * @brief Check if Tx buffer is empty
1942 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1943 * @param SPIx SPI Instance
1944 * @retval State of bit (1 or 0).
1945 */
1946 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
1947 {
1948 return LL_SPI_IsActiveFlag_TXE(SPIx);
1949 }
1950
1951 /**
1952 * @brief Get busy flag
1953 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1954 * @param SPIx SPI Instance
1955 * @retval State of bit (1 or 0).
1956 */
1957 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
1958 {
1959 return LL_SPI_IsActiveFlag_BSY(SPIx);
1960 }
1961
1962 /**
1963 * @brief Get overrun error flag
1964 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1965 * @param SPIx SPI Instance
1966 * @retval State of bit (1 or 0).
1967 */
1968 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1969 {
1970 return LL_SPI_IsActiveFlag_OVR(SPIx);
1971 }
1972
1973 /**
1974 * @brief Get underrun error flag
1975 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1976 * @param SPIx SPI Instance
1977 * @retval State of bit (1 or 0).
1978 */
1979 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1980 {
1981 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
1982 }
1983
1984 /**
1985 * @brief Get frame format error flag
1986 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
1987 * @param SPIx SPI Instance
1988 * @retval State of bit (1 or 0).
1989 */
1990 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1991 {
1992 return LL_SPI_IsActiveFlag_FRE(SPIx);
1993 }
1994
1995 /**
1996 * @brief Get channel side flag.
1997 * @note 0: Channel Left has to be transmitted or has been received\n
1998 * 1: Channel Right has to be transmitted or has been received\n
1999 * It has no significance in PCM mode.
2000 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
2001 * @param SPIx SPI Instance
2002 * @retval State of bit (1 or 0).
2003 */
2004 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
2005 {
2006 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
2007 }
2008
2009 /**
2010 * @brief Clear overrun error flag
2011 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
2012 * @param SPIx SPI Instance
2013 * @retval None
2014 */
2015 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
2016 {
2017 LL_SPI_ClearFlag_OVR(SPIx);
2018 }
2019
2020 /**
2021 * @brief Clear underrun error flag
2022 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
2023 * @param SPIx SPI Instance
2024 * @retval None
2025 */
2026 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
2027 {
2028 __IO uint32_t tmpreg;
2029 tmpreg = SPIx->SR;
2030 (void)tmpreg;
2031 }
2032
2033 /**
2034 * @brief Clear frame format error flag
2035 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
2036 * @param SPIx SPI Instance
2037 * @retval None
2038 */
2039 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
2040 {
2041 LL_SPI_ClearFlag_FRE(SPIx);
2042 }
2043
2044 /**
2045 * @}
2046 */
2047
2048 /** @defgroup I2S_LL_EF_IT Interrupt Management
2049 * @{
2050 */
2051
2052 /**
2053 * @brief Enable error IT
2054 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
2055 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
2056 * @param SPIx SPI Instance
2057 * @retval None
2058 */
2059 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
2060 {
2061 LL_SPI_EnableIT_ERR(SPIx);
2062 }
2063
2064 /**
2065 * @brief Enable Rx buffer not empty IT
2066 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
2067 * @param SPIx SPI Instance
2068 * @retval None
2069 */
2070 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
2071 {
2072 LL_SPI_EnableIT_RXNE(SPIx);
2073 }
2074
2075 /**
2076 * @brief Enable Tx buffer empty IT
2077 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
2078 * @param SPIx SPI Instance
2079 * @retval None
2080 */
2081 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
2082 {
2083 LL_SPI_EnableIT_TXE(SPIx);
2084 }
2085
2086 /**
2087 * @brief Disable error IT
2088 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
2089 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
2090 * @param SPIx SPI Instance
2091 * @retval None
2092 */
2093 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
2094 {
2095 LL_SPI_DisableIT_ERR(SPIx);
2096 }
2097
2098 /**
2099 * @brief Disable Rx buffer not empty IT
2100 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
2101 * @param SPIx SPI Instance
2102 * @retval None
2103 */
2104 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
2105 {
2106 LL_SPI_DisableIT_RXNE(SPIx);
2107 }
2108
2109 /**
2110 * @brief Disable Tx buffer empty IT
2111 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
2112 * @param SPIx SPI Instance
2113 * @retval None
2114 */
2115 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
2116 {
2117 LL_SPI_DisableIT_TXE(SPIx);
2118 }
2119
2120 /**
2121 * @brief Check if ERR IT is enabled
2122 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
2123 * @param SPIx SPI Instance
2124 * @retval State of bit (1 or 0).
2125 */
2126 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
2127 {
2128 return LL_SPI_IsEnabledIT_ERR(SPIx);
2129 }
2130
2131 /**
2132 * @brief Check if RXNE IT is enabled
2133 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
2134 * @param SPIx SPI Instance
2135 * @retval State of bit (1 or 0).
2136 */
2137 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
2138 {
2139 return LL_SPI_IsEnabledIT_RXNE(SPIx);
2140 }
2141
2142 /**
2143 * @brief Check if TXE IT is enabled
2144 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
2145 * @param SPIx SPI Instance
2146 * @retval State of bit (1 or 0).
2147 */
2148 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
2149 {
2150 return LL_SPI_IsEnabledIT_TXE(SPIx);
2151 }
2152
2153 /**
2154 * @}
2155 */
2156
2157 /** @defgroup I2S_LL_EF_DMA DMA Management
2158 * @{
2159 */
2160
2161 /**
2162 * @brief Enable DMA Rx
2163 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
2164 * @param SPIx SPI Instance
2165 * @retval None
2166 */
2167 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2168 {
2169 LL_SPI_EnableDMAReq_RX(SPIx);
2170 }
2171
2172 /**
2173 * @brief Disable DMA Rx
2174 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
2175 * @param SPIx SPI Instance
2176 * @retval None
2177 */
2178 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2179 {
2180 LL_SPI_DisableDMAReq_RX(SPIx);
2181 }
2182
2183 /**
2184 * @brief Check if DMA Rx is enabled
2185 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
2186 * @param SPIx SPI Instance
2187 * @retval State of bit (1 or 0).
2188 */
2189 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
2190 {
2191 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
2192 }
2193
2194 /**
2195 * @brief Enable DMA Tx
2196 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
2197 * @param SPIx SPI Instance
2198 * @retval None
2199 */
2200 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2201 {
2202 LL_SPI_EnableDMAReq_TX(SPIx);
2203 }
2204
2205 /**
2206 * @brief Disable DMA Tx
2207 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
2208 * @param SPIx SPI Instance
2209 * @retval None
2210 */
2211 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2212 {
2213 LL_SPI_DisableDMAReq_TX(SPIx);
2214 }
2215
2216 /**
2217 * @brief Check if DMA Tx is enabled
2218 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
2219 * @param SPIx SPI Instance
2220 * @retval State of bit (1 or 0).
2221 */
2222 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
2223 {
2224 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
2225 }
2226
2227 /**
2228 * @}
2229 */
2230
2231 /** @defgroup I2S_LL_EF_DATA DATA Management
2232 * @{
2233 */
2234
2235 /**
2236 * @brief Read 16-Bits in data register
2237 * @rmtoll DR DR LL_I2S_ReceiveData16
2238 * @param SPIx SPI Instance
2239 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
2240 */
2241 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
2242 {
2243 return LL_SPI_ReceiveData16(SPIx);
2244 }
2245
2246 /**
2247 * @brief Write 16-Bits in data register
2248 * @rmtoll DR DR LL_I2S_TransmitData16
2249 * @param SPIx SPI Instance
2250 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
2251 * @retval None
2252 */
2253 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2254 {
2255 LL_SPI_TransmitData16(SPIx, TxData);
2256 }
2257
2258 /**
2259 * @}
2260 */
2261
2262 #if defined(USE_FULL_LL_DRIVER)
2263 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
2264 * @{
2265 */
2266
2267 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
2268 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
2269 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
2270 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
2271
2272 /**
2273 * @}
2274 */
2275 #endif /* USE_FULL_LL_DRIVER */
2276
2277 /**
2278 * @}
2279 */
2280
2281 /**
2282 * @}
2283 */
2284
2285 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
2286
2287 /**
2288 * @}
2289 */
2290
2291 #ifdef __cplusplus
2292 }
2293 #endif
2294
2295 #endif /* __STM32F7xx_LL_SPI_H */
2296
2297 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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