?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
before merging master
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_spi.c
blobc1f386dc35cc10253d8cf27ece2e5cdc7ddfc448
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_spi.c
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief SPI LL module driver.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37 #if defined(USE_FULL_LL_DRIVER)
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32f7xx_ll_spi.h"
41 #include "stm32f7xx_ll_bus.h"
42 #include "stm32f7xx_ll_rcc.h"
43
44 #ifdef USE_FULL_ASSERT
45 #include "stm32_assert.h"
46 #else
47 #define assert_param(expr) ((void)0U)
48 #endif
49
50 /** @addtogroup STM32F7xx_LL_Driver
51 * @{
52 */
53
54 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
55
56 /** @addtogroup SPI_LL
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62
63 /* Private constants ---------------------------------------------------------*/
64 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
65 * @{
66 */
67 /* SPI registers Masks */
68 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
69 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
70 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
71 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
72 SPI_CR1_BIDIMODE)
73 /**
74 * @}
75 */
76
77 /* Private macros ------------------------------------------------------------*/
78 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
79 * @{
80 */
81 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
82 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
83 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
84 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
85
86 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
87 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
88
89 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
90 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
91 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
92 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
93 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
94 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
95 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
96 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
97 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
98 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
99 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
100 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
101 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
102
103 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
104 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
105
106 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
107 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
108
109 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
110 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
111 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
112
113 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
114 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
115 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
116 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
117 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
118 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
119 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
120 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
121
122 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
123 || ((__VALUE__) == LL_SPI_MSB_FIRST))
124
125 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
126 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
127
128 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
129
130 /**
131 * @}
132 */
133
134 /* Private function prototypes -----------------------------------------------*/
135
136 /* Exported functions --------------------------------------------------------*/
137 /** @addtogroup SPI_LL_Exported_Functions
138 * @{
139 */
140
141 /** @addtogroup SPI_LL_EF_Init
142 * @{
143 */
144
145 /**
146 * @brief De-initialize the SPI registers to their default reset values.
147 * @param SPIx SPI Instance
148 * @retval An ErrorStatus enumeration value:
149 * - SUCCESS: SPI registers are de-initialized
150 * - ERROR: SPI registers are not de-initialized
151 */
152 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
153 {
154 ErrorStatus status = ERROR;
155
156 /* Check the parameters */
157 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
158
159 #if defined(SPI1)
160 if (SPIx == SPI1)
161 {
162 /* Force reset of SPI clock */
163 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
164
165 /* Release reset of SPI clock */
166 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
167
168 status = SUCCESS;
169 }
170 #endif /* SPI1 */
171 #if defined(SPI2)
172 if (SPIx == SPI2)
173 {
174 /* Force reset of SPI clock */
175 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
176
177 /* Release reset of SPI clock */
178 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
179
180 status = SUCCESS;
181 }
182 #endif /* SPI2 */
183 #if defined(SPI3)
184 if (SPIx == SPI3)
185 {
186 /* Force reset of SPI clock */
187 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
188
189 /* Release reset of SPI clock */
190 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
191
192 status = SUCCESS;
193 }
194 #endif /* SPI3 */
195 #if defined(SPI4)
196 if (SPIx == SPI4)
197 {
198 /* Force reset of SPI clock */
199 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
200
201 /* Release reset of SPI clock */
202 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
203
204 status = SUCCESS;
205 }
206 #endif /* SPI4 */
207 #if defined(SPI5)
208 if (SPIx == SPI5)
209 {
210 /* Force reset of SPI clock */
211 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
212
213 /* Release reset of SPI clock */
214 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
215
216 status = SUCCESS;
217 }
218 #endif /* SPI5 */
219 #if defined(SPI6)
220 if (SPIx == SPI6)
221 {
222 /* Force reset of SPI clock */
223 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
224
225 /* Release reset of SPI clock */
226 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
227
228 status = SUCCESS;
229 }
230 #endif /* SPI6 */
231
232 return status;
233 }
234
235 /**
236 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
237 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
238 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
239 * @param SPIx SPI Instance
240 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
241 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
242 */
243 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
244 {
245 ErrorStatus status = ERROR;
246
247 /* Check the SPI Instance SPIx*/
248 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
249
250 /* Check the SPI parameters from SPI_InitStruct*/
251 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
252 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
253 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
254 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
255 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
256 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
257 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
258 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
259 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
260
261 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
262 {
263 /*---------------------------- SPIx CR1 Configuration ------------------------
264 * Configure SPIx CR1 with parameters:
265 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
266 * - Master/Slave Mode: SPI_CR1_MSTR bit
267 * - ClockPolarity: SPI_CR1_CPOL bit
268 * - ClockPhase: SPI_CR1_CPHA bit
269 * - NSS management: SPI_CR1_SSM bit
270 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
271 * - BitOrder: SPI_CR1_LSBFIRST bit
272 * - CRCCalculation: SPI_CR1_CRCEN bit
273 */
274 MODIFY_REG(SPIx->CR1,
275 SPI_CR1_CLEAR_MASK,
276 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
277 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
278 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
279 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
280
281 /*---------------------------- SPIx CR2 Configuration ------------------------
282 * Configure SPIx CR2 with parameters:
283 * - DataWidth: DS[3:0] bits
284 * - NSS management: SSOE bit
285 */
286 MODIFY_REG(SPIx->CR2,
287 SPI_CR2_DS | SPI_CR2_SSOE,
288 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
289
290 /*---------------------------- SPIx CRCPR Configuration ----------------------
291 * Configure SPIx CRCPR with parameters:
292 * - CRCPoly: CRCPOLY[15:0] bits
293 */
294 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
295 {
296 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
297 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
298 }
299 status = SUCCESS;
300 }
301
302 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
303 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
304 return status;
305 }
306
307 /**
308 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
309 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
310 * whose fields will be set to default values.
311 * @retval None
312 */
313 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
314 {
315 /* Set SPI_InitStruct fields to default values */
316 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
317 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
318 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
319 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
320 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
321 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
322 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
323 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
324 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
325 SPI_InitStruct->CRCPoly = 7U;
326 }
327
328 /**
329 * @}
330 */
331
332 /**
333 * @}
334 */
335
336 /**
337 * @}
338 */
339
340 /** @addtogroup I2S_LL
341 * @{
342 */
343
344 /* Private types -------------------------------------------------------------*/
345 /* Private variables ---------------------------------------------------------*/
346 /* Private constants ---------------------------------------------------------*/
347 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
348 * @{
349 */
350 /* I2S registers Masks */
351 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
352 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
353 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
354
355 #define I2S_I2SPR_CLEAR_MASK 0x0002U
356 /**
357 * @}
358 */
359 /* Private macros ------------------------------------------------------------*/
360 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
361 * @{
362 */
363
364 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
365 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
366 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
367 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
368
369 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
370 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
371
372 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
373 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
374 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
375 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
376 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
377
378 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
379 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
380 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
381 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
382
383 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
384 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
385
386 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
387 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
388 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
389
390 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
391
392 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
393 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
394 /**
395 * @}
396 */
397
398 /* Private function prototypes -----------------------------------------------*/
399
400 /* Exported functions --------------------------------------------------------*/
401 /** @addtogroup I2S_LL_Exported_Functions
402 * @{
403 */
404
405 /** @addtogroup I2S_LL_EF_Init
406 * @{
407 */
408
409 /**
410 * @brief De-initialize the SPI/I2S registers to their default reset values.
411 * @param SPIx SPI Instance
412 * @retval An ErrorStatus enumeration value:
413 * - SUCCESS: SPI registers are de-initialized
414 * - ERROR: SPI registers are not de-initialized
415 */
416 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
417 {
418 return LL_SPI_DeInit(SPIx);
419 }
420
421 /**
422 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
423 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
424 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
425 * @param SPIx SPI Instance
426 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
427 * @retval An ErrorStatus enumeration value:
428 * - SUCCESS: SPI registers are Initialized
429 * - ERROR: SPI registers are not Initialized
430 */
431 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
432 {
433 uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
434 uint32_t tmp = 0U;
435 uint32_t sourceclock = 0U;
436 ErrorStatus status = ERROR;
437
438 /* Check the I2S parameters */
439 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
440 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
441 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
442 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
443 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
444 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
445 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
446
447 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
448 {
449 /*---------------------------- SPIx I2SCFGR Configuration --------------------
450 * Configure SPIx I2SCFGR with parameters:
451 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
452 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
453 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
454 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
455 */
456
457 /* Write to SPIx I2SCFGR */
458 MODIFY_REG(SPIx->I2SCFGR,
459 I2S_I2SCFGR_CLEAR_MASK,
460 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
461 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
462 SPI_I2SCFGR_I2SMOD);
463
464 /*---------------------------- SPIx I2SPR Configuration ----------------------
465 * Configure SPIx I2SPR with parameters:
466 * - MCLKOutput: SPI_I2SPR_MCKOE bit
467 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
468 */
469
470 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
471 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
472 */
473 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
474 {
475 /* Check the frame length (For the Prescaler computing)
476 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
477 */
478 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
479 {
480 /* Packet length is 32 bits */
481 packetlength = 2U;
482 }
483
484 /* If an external I2S clock has to be used, the specific define should be set
485 in the project configuration or in the stm32f7xx_ll_rcc.h file */
486 /* Get the I2S source clock value */
487 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
488
489 /* Compute the Real divider depending on the MCLK output state with a floating point */
490 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
491 {
492 /* MCLK output is enabled */
493 tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
494 }
495 else
496 {
497 /* MCLK output is disabled */
498 tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
499 }
500
501 /* Remove the floating point */
502 tmp = tmp / 10U;
503
504 /* Check the parity of the divider */
505 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
506
507 /* Compute the i2sdiv prescaler */
508 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
509
510 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
511 i2sodd = (uint16_t)(i2sodd << 8U);
512 }
513
514 /* Test if the divider is 1 or 0 or greater than 0xFF */
515 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
516 {
517 /* Set the default values */
518 i2sdiv = 2U;
519 i2sodd = 0U;
520 }
521
522 /* Write to SPIx I2SPR register the computed value */
523 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
524
525 status = SUCCESS;
526 }
527 return status;
528 }
529
530 /**
531 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
532 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
533 * whose fields will be set to default values.
534 * @retval None
535 */
536 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
537 {
538 /*--------------- Reset I2S init structure parameters values -----------------*/
539 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
540 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
541 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
542 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
543 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
544 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
545 }
546
547 /**
548 * @brief Set linear and parity prescaler.
549 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
550 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
551 * @param SPIx SPI Instance
552 * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
553 * @param PrescalerParity This parameter can be one of the following values:
554 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
555 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
556 * @retval None
557 */
558 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
559 {
560 /* Check the I2S parameters */
561 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
562 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
563 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
564
565 /* Write to SPIx I2SPR */
566 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
567 }
568
569 /**
570 * @}
571 */
572
573 /**
574 * @}
575 */
576
577 /**
578 * @}
579 */
580
581 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
582
583 /**
584 * @}
585 */
586
587 #endif /* USE_FULL_LL_DRIVER */
588
589 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software