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[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_utils.c
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1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_utils.c
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief UTILS LL module driver.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f7xx_ll_utils.h"
39 #include "stm32f7xx_ll_rcc.h"
40 #include "stm32f7xx_ll_system.h"
41 #include "stm32f7xx_ll_pwr.h"
42 #ifdef USE_FULL_ASSERT
43 #include "stm32_assert.h"
44 #else
45 #define assert_param(expr) ((void)0U)
46 #endif /* USE_FULL_ASSERT */
47
48 /** @addtogroup STM32F7xx_LL_Driver
49 * @{
50 */
51
52 /** @addtogroup UTILS_LL
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58 /* Private constants ---------------------------------------------------------*/
59 /** @addtogroup UTILS_LL_Private_Constants
60 * @{
61 */
62 #define UTILS_MAX_FREQUENCY_SCALE1 216000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
63 #define UTILS_MAX_FREQUENCY_SCALE2 180000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
64 #define UTILS_MAX_FREQUENCY_SCALE3 144000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
65
66 /* Defines used for PLL range */
67 #define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
68 #define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
69 #define UTILS_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
70 #define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
71
72 /* Defines used for HSE range */
73 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
74 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
75
76 /* Defines used for FLASH latency according to HCLK Frequency */
77 #define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
78 #define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
79 #define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
80 #define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
81 #define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
82 #define UTILS_SCALE1_LATENCY6_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 with over-drive mode */
83 #define UTILS_SCALE1_LATENCY7_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 with over-drive mode */
84 #define UTILS_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
85 #define UTILS_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
86 #define UTILS_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
87 #define UTILS_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
88 #define UTILS_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
89 #define UTILS_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
90 #define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
91 #define UTILS_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
92 #define UTILS_SCALE3_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
93 /**
94 * @}
95 */
96
97 /* Private macros ------------------------------------------------------------*/
98 /** @addtogroup UTILS_LL_Private_Macros
99 * @{
100 */
101 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
102 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
103 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
104 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
105 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
106 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
107 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
108 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
109 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
110
111 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
112 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
113 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
114 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
115 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
116
117 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
118 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
119 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
120 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
121 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
122
123 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
124 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
125 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
126 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
127 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
128 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
129 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
130 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
131 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
132 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
133 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
134 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
135 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
136 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
137 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
138 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
139 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
140 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
141 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
142 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
143 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
144 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
145 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
146 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
147 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
148 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
149 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
150 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
151 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
152 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
153 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
154 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
155 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
156 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
157 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
158 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
159 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
160 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
161 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
162 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
163 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
164 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
165 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
166 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
167 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
168 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
169 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
170 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
171 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
172 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
173 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
174 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
175 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
176 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
177 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
178 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
179 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
180 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
181 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
182 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
183 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
184 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
185
186 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432))
187
188 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
189 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
190 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
191 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
192
193 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
194
195 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
196
197 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
198 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
199 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
200
201 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
202 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
203
204 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
205 /**
206 * @}
207 */
208 /* Private function prototypes -----------------------------------------------*/
209 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
210 * @{
211 */
212 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
213 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
214 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
215 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
216 static ErrorStatus UTILS_PLL_IsBusy(void);
217 /**
218 * @}
219 */
220
221 /* Exported functions --------------------------------------------------------*/
222 /** @addtogroup UTILS_LL_Exported_Functions
223 * @{
224 */
225
226 /** @addtogroup UTILS_LL_EF_DELAY
227 * @{
228 */
229
230 /**
231 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
232 * @note When a RTOS is used, it is recommended to avoid changing the Systick
233 * configuration by calling this function, for a delay use rather osDelay RTOS service.
234 * @param HCLKFrequency HCLK frequency in Hz
235 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
236 * @retval None
237 */
238 void LL_Init1msTick(uint32_t HCLKFrequency)
239 {
240 /* Use frequency provided in argument */
241 LL_InitTick(HCLKFrequency, 1000U);
242 }
243
244 /**
245 * @brief This function provides accurate delay (in milliseconds) based
246 * on SysTick counter flag
247 * @note When a RTOS is used, it is recommended to avoid using blocking delay
248 * and use rather osDelay service.
249 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
250 * will configure Systick to 1ms
251 * @param Delay specifies the delay time length, in milliseconds.
252 * @retval None
253 */
254 void LL_mDelay(uint32_t Delay)
255 {
256 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
257 /* Add this code to indicate that local variable is not used */
258 ((void)tmp);
259
260 /* Add a period to guaranty minimum wait */
261 if(Delay < LL_MAX_DELAY)
262 {
263 Delay++;
264 }
265
266 while (Delay)
267 {
268 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
269 {
270 Delay--;
271 }
272 }
273 }
274
275 /**
276 * @}
277 */
278
279 /** @addtogroup UTILS_EF_SYSTEM
280 * @brief System Configuration functions
281 *
282 @verbatim
283 ===============================================================================
284 ##### System Configuration functions #####
285 ===============================================================================
286 [..]
287 System, AHB and APB buses clocks configuration
288
289 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz.
290 @endverbatim
291 @internal
292 Depending on the device voltage range, the maximum frequency should be
293 adapted accordingly:
294 (++) +------------------------------------------------------------------------------------------------+
295 (++) | Wait states | HCLK clock frequency (MHz) |
296 (++) | |-------------------------------------------------------------------------------|
297 (++) | (Latency) | voltage range | voltage range | voltage range | voltage range |
298 (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.7V | 1.8V - 2.1V |
299 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
300 (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 22 | 0 < HCLK <= 20 |
301 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
302 (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 22 < HCLK <= 44 | 20 < HCLK <= 44 |
303 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
304 (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 44 < HCLK <= 66 | 40 < HCLK <= 60 |
305 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
306 (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 66 < HCLK <= 88 | 60 < HCLK <= 80 |
307 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
308 (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 | 96 < HCLK <= 120 | 88 < HCLK <= 110 | 80 < HCLK <= 100 |
309 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
310 (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 100 < HCLK <= 120 |
311 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
312 (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 120 < HCLK <= 140 |
313 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
314 (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 140 < HCLK <= 160 |
315 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
316 (++) |8WS(9CPU cycle) | -- | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 160 < HCLK <= 180 |
317 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
318 (++) |9WS(10CPU cycle)| -- | -- | 198 < HCLK <= 216 | -- |
319 (++) +------------------------------------------------------------------------------------------------+
320
321 @endinternal
322 * @{
323 */
324
325 /**
326 * @brief This function sets directly SystemCoreClock CMSIS variable.
327 * @note Variable can be calculated also through SystemCoreClockUpdate function.
328 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
329 * @retval None
330 */
331 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
332 {
333 /* HCLK clock frequency */
334 SystemCoreClock = HCLKFrequency;
335 }
336
337 /**
338 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
339 * @note The application need to ensure that PLL is disabled.
340 * @note Function is based on the following formula:
341 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
342 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = HSI frequency / PLLM)
343 * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
344 * - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP)
345 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
346 * the configuration information for the PLL.
347 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
348 * the configuration information for the BUS prescalers.
349 * @retval An ErrorStatus enumeration value:
350 * - SUCCESS: Max frequency configuration done
351 * - ERROR: Max frequency configuration not done
352 */
353 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
354 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
355 {
356 ErrorStatus status = SUCCESS;
357 uint32_t pllfreq = 0U;
358
359 /* Check if one of the PLL is enabled */
360 if(UTILS_PLL_IsBusy() == SUCCESS)
361 {
362 /* Calculate the new PLL output frequency */
363 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
364
365 /* Enable HSI if not enabled */
366 if(LL_RCC_HSI_IsReady() != 1U)
367 {
368 LL_RCC_HSI_Enable();
369 while (LL_RCC_HSI_IsReady() != 1U)
370 {
371 /* Wait for HSI ready */
372 }
373 }
374
375 /* Configure PLL */
376 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
377 UTILS_PLLInitStruct->PLLP);
378
379 /* Enable PLL and switch system clock to PLL */
380 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
381 }
382 else
383 {
384 /* Current PLL configuration cannot be modified */
385 status = ERROR;
386 }
387
388 return status;
389 }
390
391 /**
392 * @brief This function configures system clock with HSE as clock source of the PLL
393 * @note The application need to ensure that PLL is disabled.
394 * @note Function is based on the following formula:
395 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
396 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
397 * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
398 * - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP)
399 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
400 * @param HSEBypass This parameter can be one of the following values:
401 * @arg @ref LL_UTILS_HSEBYPASS_ON
402 * @arg @ref LL_UTILS_HSEBYPASS_OFF
403 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
404 * the configuration information for the PLL.
405 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
406 * the configuration information for the BUS prescalers.
407 * @retval An ErrorStatus enumeration value:
408 * - SUCCESS: Max frequency configuration done
409 * - ERROR: Max frequency configuration not done
410 */
411 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
412 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
413 {
414 ErrorStatus status = SUCCESS;
415 uint32_t pllfreq = 0U;
416
417 /* Check the parameters */
418 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
419 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
420
421 /* Check if one of the PLL is enabled */
422 if(UTILS_PLL_IsBusy() == SUCCESS)
423 {
424 /* Calculate the new PLL output frequency */
425 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
426
427 /* Enable HSE if not enabled */
428 if(LL_RCC_HSE_IsReady() != 1U)
429 {
430 /* Check if need to enable HSE bypass feature or not */
431 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
432 {
433 LL_RCC_HSE_EnableBypass();
434 }
435 else
436 {
437 LL_RCC_HSE_DisableBypass();
438 }
439
440 /* Enable HSE */
441 LL_RCC_HSE_Enable();
442 while (LL_RCC_HSE_IsReady() != 1U)
443 {
444 /* Wait for HSE ready */
445 }
446 }
447
448 /* Configure PLL */
449 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
450 UTILS_PLLInitStruct->PLLP);
451
452 /* Enable PLL and switch system clock to PLL */
453 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
454 }
455 else
456 {
457 /* Current PLL configuration cannot be modified */
458 status = ERROR;
459 }
460
461 return status;
462 }
463
464 /**
465 * @}
466 */
467
468 /**
469 * @}
470 */
471
472 /** @addtogroup UTILS_LL_Private_Functions
473 * @{
474 */
475 /**
476 * @brief Update number of Flash wait states in line with new frequency and current
477 voltage range.
478 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
479 * @param HCLK_Frequency HCLK frequency
480 * @retval An ErrorStatus enumeration value:
481 * - SUCCESS: Latency has been modified
482 * - ERROR: Latency cannot be modified
483 */
484 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
485 {
486 ErrorStatus status = SUCCESS;
487
488 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
489
490 /* Frequency cannot be equal to 0 */
491 if(HCLK_Frequency == 0U)
492 {
493 status = ERROR;
494 }
495 else
496 {
497 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
498 {
499 if(LL_PWR_IsEnabledOverDriveMode() != 0U)
500 {
501 if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
502 {
503 /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */
504 latency = LL_FLASH_LATENCY_7;
505 }
506 else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */
507 {
508 /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */
509 latency = LL_FLASH_LATENCY_6;
510 }
511 }
512 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0))
513 {
514 /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */
515 latency = LL_FLASH_LATENCY_5;
516 }
517 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0))
518 {
519 /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
520 latency = LL_FLASH_LATENCY_4;
521 }
522 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0))
523 {
524 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
525 latency = LL_FLASH_LATENCY_3;
526 }
527 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0))
528 {
529 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
530 latency = LL_FLASH_LATENCY_2;
531 }
532 else
533 {
534 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0))
535 {
536 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
537 latency = LL_FLASH_LATENCY_1;
538 }
539 /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
540 }
541 }
542 else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
543 {
544 if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)
545 {
546 /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */
547 latency = LL_FLASH_LATENCY_5;
548 }
549 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)
550 {
551 /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
552 latency = LL_FLASH_LATENCY_4;
553 }
554 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
555 {
556 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
557 latency = LL_FLASH_LATENCY_3;
558 }
559 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
560 {
561 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
562 latency = LL_FLASH_LATENCY_2;
563 }
564 else
565 {
566 if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
567 {
568 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
569 latency = LL_FLASH_LATENCY_1;
570 }
571 /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
572 }
573 }
574 else /* Scale 3 */
575 {
576 if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ)
577 {
578 /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */
579 latency = LL_FLASH_LATENCY_4;
580 }
581 else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)
582 {
583 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
584 latency = LL_FLASH_LATENCY_3;
585 }
586 else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)
587 {
588 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
589 latency = LL_FLASH_LATENCY_2;
590 }
591 else
592 {
593 if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)
594 {
595 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
596 latency = LL_FLASH_LATENCY_1;
597 }
598 /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */
599 }
600 }
601
602 LL_FLASH_SetLatency(latency);
603
604 /* Check that the new number of wait states is taken into account to access the Flash
605 memory by reading the FLASH_ACR register */
606 if(LL_FLASH_GetLatency() != latency)
607 {
608 status = ERROR;
609 }
610 }
611 return status;
612 }
613
614 /**
615 * @brief Function to check that PLL can be modified
616 * @param PLL_InputFrequency PLL input frequency (in Hz)
617 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
618 * the configuration information for the PLL.
619 * @retval PLL output frequency (in Hz)
620 */
621 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
622 {
623 uint32_t pllfreq = 0U;
624
625 /* Check the parameters */
626 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
627 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
628 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
629
630 /* Check different PLL parameters according to RM */
631 /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */
632 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
633 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
634
635 /* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/
636 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
637 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
638
639 /* - PLLP: ensure that max frequency at 216000000 Hz is reached */
640 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
641 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
642
643 return pllfreq;
644 }
645
646 /**
647 * @brief Function to check that PLL can be modified
648 * @retval An ErrorStatus enumeration value:
649 * - SUCCESS: PLL modification can be done
650 * - ERROR: PLL is busy
651 */
652 static ErrorStatus UTILS_PLL_IsBusy(void)
653 {
654 ErrorStatus status = SUCCESS;
655
656 /* Check if PLL is busy*/
657 if(LL_RCC_PLL_IsReady() != 0U)
658 {
659 /* PLL configuration cannot be modified */
660 status = ERROR;
661 }
662
663 /* Check if PLLSAI is busy*/
664 if(LL_RCC_PLLSAI_IsReady() != 0U)
665 {
666 /* PLLSAI1 configuration cannot be modified */
667 status = ERROR;
668 }
669 /* Check if PLLI2S is busy*/
670 if(LL_RCC_PLLI2S_IsReady() != 0U)
671 {
672 /* PLLI2S configuration cannot be modified */
673 status = ERROR;
674 }
675 return status;
676 }
677
678 /**
679 * @brief Function to enable PLL and switch system clock to PLL
680 * @param SYSCLK_Frequency SYSCLK frequency
681 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
682 * the configuration information for the BUS prescalers.
683 * @retval An ErrorStatus enumeration value:
684 * - SUCCESS: No problem to switch system to PLL
685 * - ERROR: Problem to switch system to PLL
686 */
687 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
688 {
689 ErrorStatus status = SUCCESS;
690 uint32_t hclk_frequency = 0U;
691
692 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
693 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
694 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
695
696 /* Calculate HCLK frequency */
697 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
698
699 /* Increasing the number of wait states because of higher CPU frequency */
700 if(SystemCoreClock < hclk_frequency)
701 {
702 /* Set FLASH latency to highest latency */
703 status = UTILS_SetFlashLatency(hclk_frequency);
704 }
705
706 /* Update system clock configuration */
707 if(status == SUCCESS)
708 {
709 /* Enable PLL */
710 LL_RCC_PLL_Enable();
711 while (LL_RCC_PLL_IsReady() != 1U)
712 {
713 /* Wait for PLL ready */
714 }
715
716 /* Sysclk activation on the main PLL */
717 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
718 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
719 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
720 {
721 /* Wait for system clock switch to PLL */
722 }
723
724 /* Set APB1 & APB2 prescaler*/
725 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
726 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
727 }
728
729 /* Decreasing the number of wait states because of lower CPU frequency */
730 if(SystemCoreClock > hclk_frequency)
731 {
732 /* Set FLASH latency to lowest latency */
733 status = UTILS_SetFlashLatency(hclk_frequency);
734 }
735
736 /* Update SystemCoreClock variable */
737 if(status == SUCCESS)
738 {
739 LL_SetSystemCoreClock(hclk_frequency);
740 }
741
742 return status;
743 }
744
745 /**
746 * @}
747 */
748
749 /**
750 * @}
751 */
752
753 /**
754 * @}
755 */
756
757 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software