src/main/startup/startup_stm32f427xx.s

   1 /**
   2   ******************************************************************************
   3   * @file      startup_stm32f427xx.s
   4   * @author    MCD Application Team
   5   * @version   V2.6.1
   6   * @date      14-February-2017
   7   * @brief     STM32F427xx Devices vector table for GCC based toolchains.
   8   *            This module performs:
   9   *                - Set the initial SP
  10   *                - Set the initial PC == Reset_Handler,
  11   *                - Set the vector table entries with the exceptions ISR address
  12   *                - Branches to main in the C library (which eventually
  13   *                  calls main()).
  14   *            After Reset the Cortex-M4 processor is in Thread mode,
  15   *            priority is Privileged, and the Stack is set to Main.
  16   ******************************************************************************
  17   * @attention
  18   *
  19   * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
  20   *
  21   * Redistribution and use in source and binary forms, with or without modification,
  22   * are permitted provided that the following conditions are met:
  23   *   1. Redistributions of source code must retain the above copyright notice,
  24   *      this list of conditions and the following disclaimer.
  25   *   2. Redistributions in binary form must reproduce the above copyright notice,
  26   *      this list of conditions and the following disclaimer in the documentation
  27   *      and/or other materials provided with the distribution.
  28   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  29   *      may be used to endorse or promote products derived from this software
  30   *      without specific prior written permission.
  31   *
  32   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  33   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  34   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  36   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  37   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  38   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  39   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  40   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42   *
  43   ******************************************************************************
  44   */
  45
  46   .syntax unified
  47   .cpu cortex-m4
  48   .fpu softvfp
  49   .thumb
  50
  51 .global  g_pfnVectors
  52 .global  Default_Handler
  53
  54 /* start address for the initialization values of the .data section.
  55 defined in linker script */
  56 .word  _sidata
  57 /* start address for the .data section. defined in linker script */
  58 .word  _sdata
  59 /* end address for the .data section. defined in linker script */
  60 .word  _edata
  61 /* start address for the .bss section. defined in linker script */
  62 .word  _sbss
  63 /* end address for the .bss section. defined in linker script */
  64 .word  _ebss
  65 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
  66
  67 /**
  68  * @brief  This is the code that gets called when the processor first
  69  *          starts execution following a reset event. Only the absolutely
  70  *          necessary set is performed, after which the application
  71  *          supplied main() routine is called.
  72  * @param  None
  73  * @retval : None
  74 */
  75
  76     .section  .text.Reset_Handler
  77   .weak  Reset_Handler
  78   .type  Reset_Handler, %function
  79 Reset_Handler:
  80   ldr   sp, =_estack      /* set stack pointer */
  81
  82   // Enable CCM
  83   // RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN;
  84   ldr     r0, =0x40023800       // RCC_BASE
  85   ldr     r1, [r0, #0x30]       // AHB1ENR
  86   orr     r1, r1, 0x00100000    // RCC_AHB1ENR_CCMDATARAMEN
  87   str     r1, [r0, #0x30]
  88   dsb
  89
  90   // Defined in C code
  91   bl persistentObjectInit
  92   bl checkForBootLoaderRequest
  93
  94 /* Copy the data segment initializers from flash to SRAM */
  95   movs  r1, #0
  96   b  LoopCopyDataInit
  97
  98 CopyDataInit:
  99   ldr  r3, =_sidata
 100   ldr  r3, [r3, r1]
 101   str  r3, [r0, r1]
 102   adds  r1, r1, #4
 103
 104 LoopCopyDataInit:
 105   ldr  r0, =_sdata
 106   ldr  r3, =_edata
 107   adds  r2, r0, r1
 108   cmp  r2, r3
 109   bcc  CopyDataInit
 110   ldr  r2, =_sbss
 111   b  LoopFillZerobss
 112 /* Zero fill the bss segment. */
 113 FillZerobss:
 114   movs  r3, #0
 115   str  r3, [r2], #4
 116
 117 LoopFillZerobss:
 118   ldr  r3, = _ebss
 119   cmp  r2, r3
 120   bcc  FillZerobss
 121
 122 /* Zero fill FASTRAM */
 123   ldr  r2, =__fastram_bss_start__
 124   b  LoopFillZeroFASTRAM
 125
 126 FillZeroFASTRAM:
 127   movs  r3, #0
 128   str  r3, [r2], #4
 129
 130 LoopFillZeroFASTRAM:
 131   ldr  r3, = __fastram_bss_end__
 132   cmp  r2, r3
 133   bcc  FillZeroFASTRAM
 134
 135 /* Mark the heap and stack */
 136     ldr r2, =_heap_stack_begin
 137     b   LoopMarkHeapStack
 138
 139 MarkHeapStack:
 140         movs    r3, 0xa5a5a5a5
 141         str     r3, [r2], #4
 142
 143 LoopMarkHeapStack:
 144         ldr     r3, = _heap_stack_end
 145         cmp     r2, r3
 146         bcc     MarkHeapStack
 147
 148 /*FPU settings*/
 149  ldr     r0, =0xE000ED88           /* Enable CP10,CP11 */
 150  ldr     r1,[r0]
 151  orr     r1,r1,#(0xF << 20)
 152  str     r1,[r0]
 153
 154 /* Call the clock system intitialization function.*/
 155     bl  SystemInit
 156
 157 /* Call the application's entry point.*/
 158   bl  main
 159   bx  lr
 160
 161 LoopForever:
 162   b LoopForever
 163
 164 .size  Reset_Handler, .-Reset_Handler
 165
 166 /**
 167  * @brief  This is the code that gets called when the processor receives an
 168  *         unexpected interrupt.  This simply enters an infinite loop, preserving
 169  *         the system state for examination by a debugger.
 170  * @param  None
 171  * @retval None
 172 */
 173     .section  .text.Default_Handler,"ax",%progbits
 174 Default_Handler:
 175 Infinite_Loop:
 176   b  Infinite_Loop
 177   .size  Default_Handler, .-Default_Handler
 178 /******************************************************************************
 179 *
 180 * The minimal vector table for a Cortex M3. Note that the proper constructs
 181 * must be placed on this to ensure that it ends up at physical address
 182 * 0x0000.0000.
 183 *
 184 *******************************************************************************/
 185    .section  .isr_vector,"a",%progbits
 186   .type  g_pfnVectors, %object
 187   .size  g_pfnVectors, .-g_pfnVectors
 188
 189
 190 g_pfnVectors:
 191   .word  _estack
 192   .word  Reset_Handler
 193
 194   .word  NMI_Handler
 195   .word  HardFault_Handler
 196   .word  MemManage_Handler
 197   .word  BusFault_Handler
 198   .word  UsageFault_Handler
 199   .word  0
 200   .word  0
 201   .word  0
 202   .word  0
 203   .word  SVC_Handler
 204   .word  DebugMon_Handler
 205   .word  0
 206   .word  PendSV_Handler
 207   .word  SysTick_Handler
 208
 209   /* External Interrupts */
 210   .word     WWDG_IRQHandler                   /* Window WatchDog              */
 211   .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
 212   .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
 213   .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
 214   .word     FLASH_IRQHandler                  /* FLASH                        */
 215   .word     RCC_IRQHandler                    /* RCC                          */
 216   .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
 217   .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
 218   .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
 219   .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
 220   .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
 221   .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
 222   .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
 223   .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
 224   .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
 225   .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
 226   .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
 227   .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
 228   .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
 229   .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */
 230   .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */
 231   .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */
 232   .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */
 233   .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
 234   .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */
 235   .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */
 236   .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
 237   .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
 238   .word     TIM2_IRQHandler                   /* TIM2                         */
 239   .word     TIM3_IRQHandler                   /* TIM3                         */
 240   .word     TIM4_IRQHandler                   /* TIM4                         */
 241   .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
 242   .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
 243   .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
 244   .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
 245   .word     SPI1_IRQHandler                   /* SPI1                         */
 246   .word     SPI2_IRQHandler                   /* SPI2                         */
 247   .word     USART1_IRQHandler                 /* USART1                       */
 248   .word     USART2_IRQHandler                 /* USART2                       */
 249   .word     USART3_IRQHandler                 /* USART3                       */
 250   .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
 251   .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
 252   .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */
 253   .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
 254   .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
 255   .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
 256   .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
 257   .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
 258   .word     FMC_IRQHandler                    /* FMC                          */
 259   .word     SDIO_IRQHandler                   /* SDIO                         */
 260   .word     TIM5_IRQHandler                   /* TIM5                         */
 261   .word     SPI3_IRQHandler                   /* SPI3                         */
 262   .word     UART4_IRQHandler                  /* UART4                        */
 263   .word     UART5_IRQHandler                  /* UART5                        */
 264   .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
 265   .word     TIM7_IRQHandler                   /* TIM7                         */
 266   .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
 267   .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
 268   .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
 269   .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
 270   .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
 271   .word     ETH_IRQHandler                    /* Ethernet                     */
 272   .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
 273   .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */
 274   .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */
 275   .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */
 276   .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */
 277   .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
 278   .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
 279   .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
 280   .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
 281   .word     USART6_IRQHandler                 /* USART6                       */
 282   .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
 283   .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
 284   .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
 285   .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
 286   .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
 287   .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
 288   .word     DCMI_IRQHandler                   /* DCMI                         */
 289   .word     0                                 /* Reserved                     */
 290   .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
 291   .word     FPU_IRQHandler                    /* FPU                          */
 292   .word     UART7_IRQHandler                  /* UART7                        */
 293   .word     UART8_IRQHandler                  /* UART8                         */
 294   .word     SPI4_IRQHandler                   /* SPI4                          */
 295   .word     SPI5_IRQHandler                   /* SPI5                                             */
 296   .word     SPI6_IRQHandler                   /* SPI6                                             */
 297   .word     SAI1_IRQHandler                   /* SAI1                                             */
 298   .word     0                                 /* Reserved                                         */
 299   .word     0                                 /* Reserved                                         */
 300   .word     DMA2D_IRQHandler                  /* DMA2D                                            */
 301 /*******************************************************************************
 302 *
 303 * Provide weak aliases for each Exception handler to the Default_Handler.
 304 * As they are weak aliases, any function with the same name will override
 305 * this definition.
 306 *
 307 *******************************************************************************/
 308    .weak      NMI_Handler
 309    .thumb_set NMI_Handler,Default_Handler
 310
 311    .weak      HardFault_Handler
 312    .thumb_set HardFault_Handler,Default_Handler
 313
 314    .weak      MemManage_Handler
 315    .thumb_set MemManage_Handler,Default_Handler
 316
 317    .weak      BusFault_Handler
 318    .thumb_set BusFault_Handler,Default_Handler
 319
 320    .weak      UsageFault_Handler
 321    .thumb_set UsageFault_Handler,Default_Handler
 322
 323    .weak      SVC_Handler
 324    .thumb_set SVC_Handler,Default_Handler
 325
 326    .weak      DebugMon_Handler
 327    .thumb_set DebugMon_Handler,Default_Handler
 328
 329    .weak      PendSV_Handler
 330    .thumb_set PendSV_Handler,Default_Handler
 331
 332    .weak      SysTick_Handler
 333    .thumb_set SysTick_Handler,Default_Handler
 334
 335    .weak      WWDG_IRQHandler
 336    .thumb_set WWDG_IRQHandler,Default_Handler
 337
 338    .weak      PVD_IRQHandler
 339    .thumb_set PVD_IRQHandler,Default_Handler
 340
 341    .weak      TAMP_STAMP_IRQHandler
 342    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
 343
 344    .weak      RTC_WKUP_IRQHandler
 345    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
 346
 347    .weak      FLASH_IRQHandler
 348    .thumb_set FLASH_IRQHandler,Default_Handler
 349
 350    .weak      RCC_IRQHandler
 351    .thumb_set RCC_IRQHandler,Default_Handler
 352
 353    .weak      EXTI0_IRQHandler
 354    .thumb_set EXTI0_IRQHandler,Default_Handler
 355
 356    .weak      EXTI1_IRQHandler
 357    .thumb_set EXTI1_IRQHandler,Default_Handler
 358
 359    .weak      EXTI2_IRQHandler
 360    .thumb_set EXTI2_IRQHandler,Default_Handler
 361
 362    .weak      EXTI3_IRQHandler
 363    .thumb_set EXTI3_IRQHandler,Default_Handler
 364
 365    .weak      EXTI4_IRQHandler
 366    .thumb_set EXTI4_IRQHandler,Default_Handler
 367
 368    .weak      DMA1_Stream0_IRQHandler
 369    .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
 370
 371    .weak      DMA1_Stream1_IRQHandler
 372    .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
 373
 374    .weak      DMA1_Stream2_IRQHandler
 375    .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
 376
 377    .weak      DMA1_Stream3_IRQHandler
 378    .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
 379
 380    .weak      DMA1_Stream4_IRQHandler
 381    .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
 382
 383    .weak      DMA1_Stream5_IRQHandler
 384    .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
 385
 386    .weak      DMA1_Stream6_IRQHandler
 387    .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
 388
 389    .weak      ADC_IRQHandler
 390    .thumb_set ADC_IRQHandler,Default_Handler
 391
 392    .weak      CAN1_TX_IRQHandler
 393    .thumb_set CAN1_TX_IRQHandler,Default_Handler
 394
 395    .weak      CAN1_RX0_IRQHandler
 396    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
 397
 398    .weak      CAN1_RX1_IRQHandler
 399    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
 400
 401    .weak      CAN1_SCE_IRQHandler
 402    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
 403
 404    .weak      EXTI9_5_IRQHandler
 405    .thumb_set EXTI9_5_IRQHandler,Default_Handler
 406
 407    .weak      TIM1_BRK_TIM9_IRQHandler
 408    .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
 409
 410    .weak      TIM1_UP_TIM10_IRQHandler
 411    .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
 412
 413    .weak      TIM1_TRG_COM_TIM11_IRQHandler
 414    .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
 415
 416    .weak      TIM1_CC_IRQHandler
 417    .thumb_set TIM1_CC_IRQHandler,Default_Handler
 418
 419    .weak      TIM2_IRQHandler
 420    .thumb_set TIM2_IRQHandler,Default_Handler
 421
 422    .weak      TIM3_IRQHandler
 423    .thumb_set TIM3_IRQHandler,Default_Handler
 424
 425    .weak      TIM4_IRQHandler
 426    .thumb_set TIM4_IRQHandler,Default_Handler
 427
 428    .weak      I2C1_EV_IRQHandler
 429    .thumb_set I2C1_EV_IRQHandler,Default_Handler
 430
 431    .weak      I2C1_ER_IRQHandler
 432    .thumb_set I2C1_ER_IRQHandler,Default_Handler
 433
 434    .weak      I2C2_EV_IRQHandler
 435    .thumb_set I2C2_EV_IRQHandler,Default_Handler
 436
 437    .weak      I2C2_ER_IRQHandler
 438    .thumb_set I2C2_ER_IRQHandler,Default_Handler
 439
 440    .weak      SPI1_IRQHandler
 441    .thumb_set SPI1_IRQHandler,Default_Handler
 442
 443    .weak      SPI2_IRQHandler
 444    .thumb_set SPI2_IRQHandler,Default_Handler
 445
 446    .weak      USART1_IRQHandler
 447    .thumb_set USART1_IRQHandler,Default_Handler
 448
 449    .weak      USART2_IRQHandler
 450    .thumb_set USART2_IRQHandler,Default_Handler
 451
 452    .weak      USART3_IRQHandler
 453    .thumb_set USART3_IRQHandler,Default_Handler
 454
 455    .weak      EXTI15_10_IRQHandler
 456    .thumb_set EXTI15_10_IRQHandler,Default_Handler
 457
 458    .weak      RTC_Alarm_IRQHandler
 459    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
 460
 461    .weak      OTG_FS_WKUP_IRQHandler
 462    .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
 463
 464    .weak      TIM8_BRK_TIM12_IRQHandler
 465    .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
 466
 467    .weak      TIM8_UP_TIM13_IRQHandler
 468    .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
 469
 470    .weak      TIM8_TRG_COM_TIM14_IRQHandler
 471    .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
 472
 473    .weak      TIM8_CC_IRQHandler
 474    .thumb_set TIM8_CC_IRQHandler,Default_Handler
 475
 476    .weak      DMA1_Stream7_IRQHandler
 477    .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
 478
 479    .weak      FMC_IRQHandler
 480    .thumb_set FMC_IRQHandler,Default_Handler
 481
 482    .weak      SDIO_IRQHandler
 483    .thumb_set SDIO_IRQHandler,Default_Handler
 484
 485    .weak      TIM5_IRQHandler
 486    .thumb_set TIM5_IRQHandler,Default_Handler
 487
 488    .weak      SPI3_IRQHandler
 489    .thumb_set SPI3_IRQHandler,Default_Handler
 490
 491    .weak      UART4_IRQHandler
 492    .thumb_set UART4_IRQHandler,Default_Handler
 493
 494    .weak      UART5_IRQHandler
 495    .thumb_set UART5_IRQHandler,Default_Handler
 496
 497    .weak      TIM6_DAC_IRQHandler
 498    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
 499
 500    .weak      TIM7_IRQHandler
 501    .thumb_set TIM7_IRQHandler,Default_Handler
 502
 503    .weak      DMA2_Stream0_IRQHandler
 504    .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
 505
 506    .weak      DMA2_Stream1_IRQHandler
 507    .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
 508
 509    .weak      DMA2_Stream2_IRQHandler
 510    .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
 511
 512    .weak      DMA2_Stream3_IRQHandler
 513    .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
 514
 515    .weak      DMA2_Stream4_IRQHandler
 516    .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
 517
 518    .weak      ETH_IRQHandler
 519    .thumb_set ETH_IRQHandler,Default_Handler
 520
 521    .weak      ETH_WKUP_IRQHandler
 522    .thumb_set ETH_WKUP_IRQHandler,Default_Handler
 523
 524    .weak      CAN2_TX_IRQHandler
 525    .thumb_set CAN2_TX_IRQHandler,Default_Handler
 526
 527    .weak      CAN2_RX0_IRQHandler
 528    .thumb_set CAN2_RX0_IRQHandler,Default_Handler
 529
 530    .weak      CAN2_RX1_IRQHandler
 531    .thumb_set CAN2_RX1_IRQHandler,Default_Handler
 532
 533    .weak      CAN2_SCE_IRQHandler
 534    .thumb_set CAN2_SCE_IRQHandler,Default_Handler
 535
 536    .weak      OTG_FS_IRQHandler
 537    .thumb_set OTG_FS_IRQHandler,Default_Handler
 538
 539    .weak      DMA2_Stream5_IRQHandler
 540    .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
 541
 542    .weak      DMA2_Stream6_IRQHandler
 543    .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
 544
 545    .weak      DMA2_Stream7_IRQHandler
 546    .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
 547
 548    .weak      USART6_IRQHandler
 549    .thumb_set USART6_IRQHandler,Default_Handler
 550
 551    .weak      I2C3_EV_IRQHandler
 552    .thumb_set I2C3_EV_IRQHandler,Default_Handler
 553
 554    .weak      I2C3_ER_IRQHandler
 555    .thumb_set I2C3_ER_IRQHandler,Default_Handler
 556
 557    .weak      OTG_HS_EP1_OUT_IRQHandler
 558    .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
 559
 560    .weak      OTG_HS_EP1_IN_IRQHandler
 561    .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
 562
 563    .weak      OTG_HS_WKUP_IRQHandler
 564    .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
 565
 566    .weak      OTG_HS_IRQHandler
 567    .thumb_set OTG_HS_IRQHandler,Default_Handler
 568
 569    .weak      DCMI_IRQHandler
 570    .thumb_set DCMI_IRQHandler,Default_Handler
 571
 572    .weak      HASH_RNG_IRQHandler
 573    .thumb_set HASH_RNG_IRQHandler,Default_Handler
 574
 575    .weak      FPU_IRQHandler
 576    .thumb_set FPU_IRQHandler,Default_Handler
 577
 578    .weak      UART7_IRQHandler
 579    .thumb_set UART7_IRQHandler,Default_Handler
 580
 581    .weak      UART8_IRQHandler
 582    .thumb_set UART8_IRQHandler,Default_Handler
 583
 584    .weak      SPI4_IRQHandler
 585    .thumb_set SPI4_IRQHandler,Default_Handler
 586
 587    .weak      SPI5_IRQHandler
 588    .thumb_set SPI5_IRQHandler,Default_Handler
 589
 590    .weak      SPI6_IRQHandler
 591    .thumb_set SPI6_IRQHandler,Default_Handler
 592
 593    .weak      SAI1_IRQHandler
 594    .thumb_set SAI1_IRQHandler,Default_Handler
 595
 596    .weak      DMA2D_IRQHandler
 597    .thumb_set DMA2D_IRQHandler,Default_Handler
 598
 599 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 600