src/main/target/system_stm32f7xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f7xx.c
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    22-April-2016
   7   * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
   8   *
   9   *   This file provides two functions and one global variable to be called from
  10   *   user application:
  11   *      - SystemInit(): This function is called at startup just after reset and
  12   *                      before branch to main program. This call is made inside
  13   *                      the "startup_stm32f7xx.s" file.
  14   *
  15   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16   *                                  by the user application to setup the SysTick
  17   *                                  timer or configure other parameters.
  18   *
  19   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20   *                                 be called whenever the core clock is changed
  21   *                                 during program execution.
  22   *
  23   *
  24   ******************************************************************************
  25   * @attention
  26   *
  27   * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
  28   *
  29   * Redistribution and use in source and binary forms, with or without modification,
  30   * are permitted provided that the following conditions are met:
  31   *   1. Redistributions of source code must retain the above copyright notice,
  32   *      this list of conditions and the following disclaimer.
  33   *   2. Redistributions in binary form must reproduce the above copyright notice,
  34   *      this list of conditions and the following disclaimer in the documentation
  35   *      and/or other materials provided with the distribution.
  36   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  37   *      may be used to endorse or promote products derived from this software
  38   *      without specific prior written permission.
  39   *
  40   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  41   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  42   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  43   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  44   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  45   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  46   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  47   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  48   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  49   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  50   *
  51   ******************************************************************************
  52   */
  53
  54 /** @addtogroup CMSIS
  55   * @{
  56   */
  57
  58 /** @addtogroup stm32f7xx_system
  59   * @{
  60   */
  61
  62 /** @addtogroup STM32F7xx_System_Private_Includes
  63   * @{
  64   */
  65
  66 #include <string.h>
  67 #include "stm32f7xx.h"
  68 #include "drivers/system.h"
  69
  70 #if !defined  (HSE_VALUE)
  71   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
  72 #endif /* HSE_VALUE */
  73
  74 #if !defined  (HSI_VALUE)
  75   #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
  76 #endif /* HSI_VALUE */
  77
  78 #if !defined(MHZ_VALUE)
  79   #define MHZ_VALUE     216
  80 #endif
  81
  82 #if MHZ_VALUE == 216
  83   #define PLL_N     432
  84   #define PLL_Q     9
  85 #elif MHZ_VALUE == 168
  86   #define PLL_N     336
  87   #define PLL_Q     7
  88 #else
  89   #error "Unsupported MHZ_VALUE!"
  90 #endif
  91
  92 #define PLL_M     8
  93 #define PLL_P     RCC_PLLP_DIV2 /* 2 */
  94
  95 #define PLL_SAIN  384
  96 #define PLL_SAIQ  7
  97 #define PLL_SAIP  RCC_PLLSAIP_DIV8
  98
  99 /**
 100   * @}
 101   */
 102
 103 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
 104   * @{
 105   */
 106
 107 /**
 108   * @}
 109   */
 110
 111 /** @addtogroup STM32F7xx_System_Private_Defines
 112   * @{
 113   */
 114
 115 /************************* Miscellaneous Configuration ************************/
 116
 117 /*!< Uncomment the following line if you need to relocate your vector Table in
 118      Internal SRAM. */
 119 /* #define VECT_TAB_SRAM */
 120 #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
 121                                    This value must be a multiple of 0x200. */
 122 /******************************************************************************/
 123
 124 /**
 125   * @}
 126   */
 127
 128 /** @addtogroup STM32F7xx_System_Private_Macros
 129   * @{
 130   */
 131
 132 /**
 133   * @}
 134   */
 135
 136 /** @addtogroup STM32F7xx_System_Private_Variables
 137   * @{
 138   */
 139
 140   /* This variable is updated in three ways:
 141       1) by calling CMSIS function SystemCoreClockUpdate()
 142       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 143       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 144          Note: If you use this function to configure the system clock; then there
 145                is no need to call the 2 first functions listed above, since SystemCoreClock
 146                variable is updated automatically.
 147   */
 148   uint32_t SystemCoreClock = (PLL_N / PLL_P) * 1000000;
 149   const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 150   const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
 151
 152 /**
 153   * @}
 154   */
 155
 156 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
 157   * @{
 158   */
 159
 160   /// TODO: F7 check if this is the best configuration for the clocks.
 161   // current settings are just a copy from one of the example projects
 162   void SystemClock_Config(void)
 163   {
 164       RCC_ClkInitTypeDef RCC_ClkInitStruct;
 165       RCC_OscInitTypeDef RCC_OscInitStruct;
 166       RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
 167       HAL_StatusTypeDef ret;
 168
 169       __HAL_RCC_PWR_CLK_ENABLE();
 170
 171       __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 172
 173       /* Enable HSE Oscillator and activate PLL with HSE as source */
 174       RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 175       RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 176       RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 177       RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 178       RCC_OscInitStruct.PLL.PLLM = PLL_M;
 179       RCC_OscInitStruct.PLL.PLLN = PLL_N;
 180       RCC_OscInitStruct.PLL.PLLP = PLL_P;
 181       RCC_OscInitStruct.PLL.PLLQ = PLL_Q;
 182
 183       ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
 184       if (ret != HAL_OK)
 185       {
 186         while (1) { ; }
 187       }
 188
 189       /* Activate the OverDrive to reach the 216 MHz Frequency */
 190       ret = HAL_PWREx_EnableOverDrive();
 191       if (ret != HAL_OK)
 192       {
 193         while (1) { ; }
 194       }
 195       /* Select PLLSAI output as USB clock source */
 196       PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
 197       PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
 198       PeriphClkInitStruct.PLLSAI.PLLSAIN = PLL_SAIN;
 199       PeriphClkInitStruct.PLLSAI.PLLSAIQ = PLL_SAIQ;
 200       PeriphClkInitStruct.PLLSAI.PLLSAIP = PLL_SAIP;
 201       if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct)  != HAL_OK)
 202       {
 203         while (1) {};
 204       }
 205
 206       /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 207       RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 208       RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 209       RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 210       RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
 211       RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
 212
 213       ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
 214       if (ret != HAL_OK)
 215       {
 216         while (1) { ; }
 217       }
 218
 219       PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2
 220                                   |RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_USART6
 221                                   |RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_UART5
 222                                   |RCC_PERIPHCLK_UART7|RCC_PERIPHCLK_UART8
 223                                   |RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C3
 224                                   |RCC_PERIPHCLK_I2C2|RCC_PERIPHCLK_I2C4;
 225       PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
 226       PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
 227       PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
 228       PeriphClkInitStruct.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1;
 229       PeriphClkInitStruct.Uart5ClockSelection = RCC_UART5CLKSOURCE_PCLK1;
 230       PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
 231       PeriphClkInitStruct.Uart7ClockSelection = RCC_UART7CLKSOURCE_PCLK1;
 232       PeriphClkInitStruct.Uart8ClockSelection = RCC_UART8CLKSOURCE_PCLK1;
 233       PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
 234       PeriphClkInitStruct.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
 235       PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
 236       PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PCLK1;
 237       ret = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 238       if (ret != HAL_OK)
 239       {
 240           while (1) { ; }
 241       }
 242
 243     // Activating the timerprescalers while the APBx prescalers are 1/2/4 will connect the TIMxCLK to HCLK which has been configured to 216MHz
 244     __HAL_RCC_TIMCLKPRESCALER(RCC_TIMPRES_ACTIVATED);
 245
 246     SystemCoreClockUpdate();
 247   }
 248
 249 /**
 250   * @}
 251   */
 252
 253 /** @addtogroup STM32F7xx_System_Private_Functions
 254   * @{
 255   */
 256
 257 /**
 258   * @brief  Setup the microcontroller system
 259   *         Initialize the Embedded Flash Interface, the PLL and update the
 260   *         SystemFrequency variable.
 261   * @param  None
 262   * @retval None
 263   */
 264 void SystemInit(void)
 265 {
 266   initialiseMemorySections();
 267
 268   /* FPU settings ------------------------------------------------------------*/
 269   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 270     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 271   #endif
 272   /* Reset the RCC clock configuration to the default reset state ------------*/
 273   /* Set HSION bit */
 274   RCC->CR |= (uint32_t)0x00000001;
 275
 276   /* Reset CFGR register */
 277   RCC->CFGR = 0x00000000;
 278
 279   /* Reset HSEON, CSSON and PLLON bits */
 280   RCC->CR &= (uint32_t)0xFEF6FFFF;
 281
 282   /* Reset PLLCFGR register */
 283   RCC->PLLCFGR = 0x24003010;
 284
 285   /* Reset HSEBYP bit */
 286   RCC->CR &= (uint32_t)0xFFFBFFFF;
 287
 288   /* Disable all interrupts */
 289   RCC->CIR = 0x00000000;
 290
 291   /* Configure the Vector Table location add offset address ------------------*/
 292 #ifdef VECT_TAB_SRAM
 293   SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 294 #else
 295   extern uint8_t isr_vector_table_base; /* Vector Table Relocation in Internal FLASH */
 296   SCB->VTOR = (uint32_t) &isr_vector_table_base;
 297 #endif
 298
 299   /* Enable I-Cache */
 300   SCB_EnableICache();
 301
 302   /* Enable D-Cache */
 303   //SCB_EnableDCache();
 304
 305   /* Configure the system clock to 216 MHz */
 306   SystemClock_Config();
 307
 308   if (SystemCoreClock != MHZ_VALUE * 1000000)
 309   {
 310       while (1)
 311       {
 312           // There is a mismatch between the configured clock and the expected clock in portable.h
 313       }
 314   }
 315
 316
 317 }
 318
 319 /**
 320    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 321   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 322   *         be used by the user application to setup the SysTick timer or configure
 323   *         other parameters.
 324   *
 325   * @note   Each time the core clock (HCLK) changes, this function must be called
 326   *         to update SystemCoreClock variable value. Otherwise, any configuration
 327   *         based on this variable will be incorrect.
 328   *
 329   * @note   - The system frequency computed by this function is not the real
 330   *           frequency in the chip. It is calculated based on the predefined
 331   *           constant and the selected clock source:
 332   *
 333   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 334   *
 335   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 336   *
 337   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 338   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 339   *
 340   *         (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
 341   *             16 MHz) but the real value may vary depending on the variations
 342   *             in voltage and temperature.
 343   *
 344   *         (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
 345   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
 346   *              frequency of the crystal used. Otherwise, this function may
 347   *              have wrong result.
 348   *
 349   *         - The result of this function could be not correct when using fractional
 350   *           value for HSE crystal.
 351   *
 352   * @param  None
 353   * @retval None
 354   */
 355 void SystemCoreClockUpdate(void)
 356 {
 357   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
 358
 359   /* Get SYSCLK source -------------------------------------------------------*/
 360   tmp = RCC->CFGR & RCC_CFGR_SWS;
 361
 362   switch (tmp)
 363   {
 364     case 0x00:  /* HSI used as system clock source */
 365       SystemCoreClock = HSI_VALUE;
 366       break;
 367     case 0x04:  /* HSE used as system clock source */
 368       SystemCoreClock = HSE_VALUE;
 369       break;
 370     case 0x08:  /* PLL used as system clock source */
 371
 372       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 373          SYSCLK = PLL_VCO / PLL_P
 374          */
 375       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 376       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 377
 378       if (pllsource != 0)
 379       {
 380         /* HSE used as PLL clock source */
 381         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 382       }
 383       else
 384       {
 385         /* HSI used as PLL clock source */
 386         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 387       }
 388
 389       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
 390       SystemCoreClock = pllvco/pllp;
 391       break;
 392     default:
 393       SystemCoreClock = HSI_VALUE;
 394       break;
 395   }
 396   /* Compute HCLK frequency --------------------------------------------------*/
 397   /* Get HCLK prescaler */
 398   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 399   /* HCLK frequency */
 400   SystemCoreClock >>= tmp;
 401 }
 402
 403 /**
 404   * @}
 405   */
 406
 407 /**
 408   * @}
 409   */
 410
 411 /**
 412   * @}
 413   */
 414 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/