Acc g scaling with DSP
[inav.git] / src / main / drivers / rcc.c
blob3ca5b153e14c3c34445f3ecb2068b8e8233e45bc
1 #include "build/debug.h"
2 #include "platform.h"
3 #include "rcc.h"
5 #define RCC_BIT_CMD(ptr, mask, state) do { if (state != DISABLE) { ptr |= mask; } else { ptr &= ~mask; } } while(0)
8 void RCC_ClockCmd(rccPeriphTag_t periphTag, FunctionalState NewState)
10 int tag = periphTag >> 5;
11 uint32_t mask = 1 << (periphTag & 0x1f);
12 switch (tag)
15 #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
16 case RCC_AHB1:
17 RCC_BIT_CMD(RCC->AHB1ENR, mask, NewState);
18 break;
20 case RCC_AHB2:
21 RCC_BIT_CMD(RCC->AHB2ENR, mask, NewState);
22 break;
23 #endif
25 #if defined(STM32H7)
26 case RCC_AHB3:
27 RCC_BIT_CMD(RCC->AHB3ENR, mask, NewState);
28 break;
30 case RCC_AHB4:
31 RCC_BIT_CMD(RCC->AHB4ENR, mask, NewState);
32 break;
34 case RCC_APB1L:
35 RCC_BIT_CMD(RCC->APB1LENR, mask, NewState);
36 break;
38 case RCC_APB1H:
39 RCC_BIT_CMD(RCC->APB1HENR, mask, NewState);
40 break;
42 case RCC_APB3:
43 RCC_BIT_CMD(RCC->APB3ENR, mask, NewState);
44 break;
46 case RCC_APB4:
47 RCC_BIT_CMD(RCC->APB4ENR, mask, NewState);
48 break;
49 #endif
51 #if defined(AT32F43x)
52 case RCC_AHB1:
53 RCC_BIT_CMD(CRM->ahben1, mask, NewState);
54 break;
56 case RCC_AHB2:
57 RCC_BIT_CMD(CRM->ahben2, mask, NewState);
58 break;
60 case RCC_APB1:
61 RCC_BIT_CMD(CRM->apb1en, mask, NewState);
62 break;
64 case RCC_APB2:
65 RCC_BIT_CMD(CRM->apb2en, mask, NewState);
66 break;
67 #else
68 #if !(defined(STM32H7) || defined(STM32G4))
69 case RCC_APB1:
70 RCC_BIT_CMD(RCC->APB1ENR, mask, NewState);
71 break;
72 #endif
74 case RCC_APB2:
75 RCC_BIT_CMD(RCC->APB2ENR, mask, NewState);
76 break;
78 #endif
82 void RCC_ResetCmd(rccPeriphTag_t periphTag, FunctionalState NewState)
84 int tag = periphTag >> 5;
85 uint32_t mask = 1 << (periphTag & 0x1f);
87 switch (tag)
90 #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
91 case RCC_AHB1:
92 RCC_BIT_CMD(RCC->AHB1RSTR, mask, NewState);
93 break;
95 case RCC_AHB2:
96 RCC_BIT_CMD(RCC->AHB2RSTR, mask, NewState);
97 break;
98 #endif
100 #if defined(STM32H7)
101 case RCC_AHB3:
102 RCC_BIT_CMD(RCC->AHB3RSTR, mask, NewState);
103 break;
105 case RCC_AHB4:
106 RCC_BIT_CMD(RCC->AHB4RSTR, mask, NewState);
107 break;
109 case RCC_APB1L:
110 RCC_BIT_CMD(RCC->APB1LRSTR, mask, NewState);
111 break;
113 case RCC_APB1H:
114 RCC_BIT_CMD(RCC->APB1HRSTR, mask, NewState);
115 break;
117 case RCC_APB3:
118 RCC_BIT_CMD(RCC->APB3RSTR, mask, NewState);
119 break;
121 case RCC_APB4:
122 RCC_BIT_CMD(RCC->APB4RSTR, mask, NewState);
123 break;
124 #endif
126 #if defined(AT32F43x)
127 case RCC_AHB1:
128 RCC_BIT_CMD(CRM->ahbrst1, mask, NewState);
129 break;
130 case RCC_AHB2:
131 RCC_BIT_CMD(CRM->ahbrst2, mask, NewState);
132 break;
133 case RCC_APB1:
134 RCC_BIT_CMD(CRM->apb1rst, mask, NewState);
135 break;
136 case RCC_APB2:
137 RCC_BIT_CMD(CRM->apb2rst, mask, NewState);
138 break;
140 #else
141 #if !(defined(STM32H7) || defined(STM32G4))
142 case RCC_APB1:
143 RCC_BIT_CMD(RCC->APB1RSTR, mask, NewState);
144 break;
145 #endif
148 case RCC_APB2:
149 RCC_BIT_CMD(RCC->APB2RSTR, mask, NewState);
150 break;
151 #endif