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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32F7 / Drivers / CMSIS / Device / ST / STM32F7xx / Include / stm32f779xx.h
blob96542edb30b3ae4aeb5cbbaf0809748974cd351c
1 /**
2 ******************************************************************************
3 * @file stm32f779xx.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 30-December-2016
7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral’s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 /** @addtogroup CMSIS_Device
45 * @{
46 */
47
48 /** @addtogroup stm32f779xx
49 * @{
50 */
51
52 #ifndef __STM32F779xx_H
53 #define __STM32F779xx_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif /* __cplusplus */
58
59 /** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63 /**
64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
65 * in @ref Library_configuration_section
66 */
67 typedef enum
68 {
69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
78 /****** STM32 specific Interrupt Numbers **********************************************************************/
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
84 RCC_IRQn = 5, /*!< RCC global Interrupt */
85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
127 FMC_IRQn = 48, /*!< FMC global Interrupt */
128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
150 USART6_IRQn = 71, /*!< USART6 global interrupt */
151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
158 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
159 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
160 FPU_IRQn = 81, /*!< FPU global interrupt */
161 UART7_IRQn = 82, /*!< UART7 global interrupt */
162 UART8_IRQn = 83, /*!< UART8 global interrupt */
163 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
164 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
165 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
166 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
167 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
168 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
169 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
170 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
171 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
172 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
173 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
174 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
175 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
176 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
177 DSI_IRQn = 98, /*!< DSI global Interrupt */
178 DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
179 DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
180 DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
181 DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
182 SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
183 CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
184 CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
185 CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
186 CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
187 JPEG_IRQn = 108, /*!< JPEG global Interrupt */
188 MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
189 } IRQn_Type;
190
191 /**
192 * @}
193 */
194
195 /**
196 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
197 */
198 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
199 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
200 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
201 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
202 #define __FPU_PRESENT 1 /*!< FPU present */
203 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
204 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
205 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
206
207
208 #include "system_stm32f7xx.h"
209 #include <stdint.h>
210
211 /** @addtogroup Peripheral_registers_structures
212 * @{
213 */
214
215 /**
216 * @brief Analog to Digital Converter
217 */
218
219 typedef struct
220 {
221 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
222 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
223 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
224 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
225 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
226 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
227 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
228 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
229 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
230 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
231 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
232 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
233 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
234 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
235 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
236 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
237 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
238 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
239 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
240 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
241 } ADC_TypeDef;
242
243 typedef struct
244 {
245 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
246 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
247 __IO uint32_t CDR; /*!< ADC common regular data register for dual
248 AND triple modes, Address offset: ADC1 base address + 0x308 */
249 } ADC_Common_TypeDef;
250
251
252 /**
253 * @brief Controller Area Network TxMailBox
254 */
255
256 typedef struct
257 {
258 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
259 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
260 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
261 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
262 } CAN_TxMailBox_TypeDef;
263
264 /**
265 * @brief Controller Area Network FIFOMailBox
266 */
267
268 typedef struct
269 {
270 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
271 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
272 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
273 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
274 } CAN_FIFOMailBox_TypeDef;
275
276 /**
277 * @brief Controller Area Network FilterRegister
278 */
279
280 typedef struct
281 {
282 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
283 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
284 } CAN_FilterRegister_TypeDef;
285
286 /**
287 * @brief Controller Area Network
288 */
289
290 typedef struct
291 {
292 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
293 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
294 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
295 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
296 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
297 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
298 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
299 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
300 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
301 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
302 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
303 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
304 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
305 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
306 uint32_t RESERVED2; /*!< Reserved, 0x208 */
307 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
308 uint32_t RESERVED3; /*!< Reserved, 0x210 */
309 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
310 uint32_t RESERVED4; /*!< Reserved, 0x218 */
311 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
312 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
313 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
314 } CAN_TypeDef;
315
316 /**
317 * @brief HDMI-CEC
318 */
319
320 typedef struct
321 {
322 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
323 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
324 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
325 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
326 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
327 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
328 }CEC_TypeDef;
329
330 /**
331 * @brief CRC calculation unit
332 */
333
334 typedef struct
335 {
336 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
337 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
338 uint8_t RESERVED0; /*!< Reserved, 0x05 */
339 uint16_t RESERVED1; /*!< Reserved, 0x06 */
340 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
341 uint32_t RESERVED2; /*!< Reserved, 0x0C */
342 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
343 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
344 } CRC_TypeDef;
345
346 /**
347 * @brief Digital to Analog Converter
348 */
349
350 typedef struct
351 {
352 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
353 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
354 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
355 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
356 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
357 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
358 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
359 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
360 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
361 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
362 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
363 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
364 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
365 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
366 } DAC_TypeDef;
367
368 /**
369 * @brief DFSDM module registers
370 */
371 typedef struct
372 {
373 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
374 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
375 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
376 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
377 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
378 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
379 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
380 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
381 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
382 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
383 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
384 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
385 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
386 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
387 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
388 } DFSDM_Filter_TypeDef;
389
390 /**
391 * @brief DFSDM channel configuration registers
392 */
393 typedef struct
394 {
395 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
396 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
397 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
398 short circuit detector register, Address offset: 0x08 */
399 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
400 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
401 } DFSDM_Channel_TypeDef;
402
403 /**
404 * @brief Debug MCU
405 */
406
407 typedef struct
408 {
409 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
410 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
411 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
412 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
413 }DBGMCU_TypeDef;
414
415 /**
416 * @brief DCMI
417 */
418
419 typedef struct
420 {
421 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
422 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
423 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
424 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
425 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
426 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
427 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
428 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
429 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
430 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
431 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
432 } DCMI_TypeDef;
433
434 /**
435 * @brief DMA Controller
436 */
437
438 typedef struct
439 {
440 __IO uint32_t CR; /*!< DMA stream x configuration register */
441 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
442 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
443 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
444 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
445 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
446 } DMA_Stream_TypeDef;
447
448 typedef struct
449 {
450 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
451 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
452 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
453 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
454 } DMA_TypeDef;
455
456 /**
457 * @brief DMA2D Controller
458 */
459
460 typedef struct
461 {
462 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
463 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
464 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
465 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
466 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
467 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
468 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
469 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
470 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
471 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
472 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
473 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
474 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
475 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
476 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
477 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
478 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
479 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
480 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
481 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
482 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
483 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
484 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
485 } DMA2D_TypeDef;
486
487
488 /**
489 * @brief Ethernet MAC
490 */
491
492 typedef struct
493 {
494 __IO uint32_t MACCR;
495 __IO uint32_t MACFFR;
496 __IO uint32_t MACHTHR;
497 __IO uint32_t MACHTLR;
498 __IO uint32_t MACMIIAR;
499 __IO uint32_t MACMIIDR;
500 __IO uint32_t MACFCR;
501 __IO uint32_t MACVLANTR; /* 8 */
502 uint32_t RESERVED0[2];
503 __IO uint32_t MACRWUFFR; /* 11 */
504 __IO uint32_t MACPMTCSR;
505 uint32_t RESERVED1;
506 __IO uint32_t MACDBGR;
507 __IO uint32_t MACSR; /* 15 */
508 __IO uint32_t MACIMR;
509 __IO uint32_t MACA0HR;
510 __IO uint32_t MACA0LR;
511 __IO uint32_t MACA1HR;
512 __IO uint32_t MACA1LR;
513 __IO uint32_t MACA2HR;
514 __IO uint32_t MACA2LR;
515 __IO uint32_t MACA3HR;
516 __IO uint32_t MACA3LR; /* 24 */
517 uint32_t RESERVED2[40];
518 __IO uint32_t MMCCR; /* 65 */
519 __IO uint32_t MMCRIR;
520 __IO uint32_t MMCTIR;
521 __IO uint32_t MMCRIMR;
522 __IO uint32_t MMCTIMR; /* 69 */
523 uint32_t RESERVED3[14];
524 __IO uint32_t MMCTGFSCCR; /* 84 */
525 __IO uint32_t MMCTGFMSCCR;
526 uint32_t RESERVED4[5];
527 __IO uint32_t MMCTGFCR;
528 uint32_t RESERVED5[10];
529 __IO uint32_t MMCRFCECR;
530 __IO uint32_t MMCRFAECR;
531 uint32_t RESERVED6[10];
532 __IO uint32_t MMCRGUFCR;
533 uint32_t RESERVED7[334];
534 __IO uint32_t PTPTSCR;
535 __IO uint32_t PTPSSIR;
536 __IO uint32_t PTPTSHR;
537 __IO uint32_t PTPTSLR;
538 __IO uint32_t PTPTSHUR;
539 __IO uint32_t PTPTSLUR;
540 __IO uint32_t PTPTSAR;
541 __IO uint32_t PTPTTHR;
542 __IO uint32_t PTPTTLR;
543 __IO uint32_t RESERVED8;
544 __IO uint32_t PTPTSSR;
545 uint32_t RESERVED9[565];
546 __IO uint32_t DMABMR;
547 __IO uint32_t DMATPDR;
548 __IO uint32_t DMARPDR;
549 __IO uint32_t DMARDLAR;
550 __IO uint32_t DMATDLAR;
551 __IO uint32_t DMASR;
552 __IO uint32_t DMAOMR;
553 __IO uint32_t DMAIER;
554 __IO uint32_t DMAMFBOCR;
555 __IO uint32_t DMARSWTR;
556 uint32_t RESERVED10[8];
557 __IO uint32_t DMACHTDR;
558 __IO uint32_t DMACHRDR;
559 __IO uint32_t DMACHTBAR;
560 __IO uint32_t DMACHRBAR;
561 } ETH_TypeDef;
562
563 /**
564 * @brief External Interrupt/Event Controller
565 */
566
567 typedef struct
568 {
569 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
570 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
571 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
572 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
573 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
574 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
575 } EXTI_TypeDef;
576
577 /**
578 * @brief FLASH Registers
579 */
580
581 typedef struct
582 {
583 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
584 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
585 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
586 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
587 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
588 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
589 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
590 } FLASH_TypeDef;
591
592
593
594 /**
595 * @brief Flexible Memory Controller
596 */
597
598 typedef struct
599 {
600 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
601 } FMC_Bank1_TypeDef;
602
603 /**
604 * @brief Flexible Memory Controller Bank1E
605 */
606
607 typedef struct
608 {
609 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
610 } FMC_Bank1E_TypeDef;
611
612 /**
613 * @brief Flexible Memory Controller Bank3
614 */
615
616 typedef struct
617 {
618 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
619 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
620 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
621 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
622 uint32_t RESERVED0; /*!< Reserved, 0x90 */
623 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
624 } FMC_Bank3_TypeDef;
625
626 /**
627 * @brief Flexible Memory Controller Bank5_6
628 */
629
630 typedef struct
631 {
632 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
633 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
634 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
635 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
636 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
637 } FMC_Bank5_6_TypeDef;
638
639
640 /**
641 * @brief General Purpose I/O
642 */
643
644 typedef struct
645 {
646 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
647 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
648 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
649 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
650 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
651 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
652 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
653 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
654 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
655 } GPIO_TypeDef;
656
657 /**
658 * @brief System configuration controller
659 */
660
661 typedef struct
662 {
663 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
664 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
665 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
666 uint32_t RESERVED; /*!< Reserved, 0x18 */
667 __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
668 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
669 } SYSCFG_TypeDef;
670
671 /**
672 * @brief Inter-integrated Circuit Interface
673 */
674
675 typedef struct
676 {
677 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
678 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
679 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
680 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
681 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
682 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
683 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
684 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
685 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
686 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
687 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
688 } I2C_TypeDef;
689
690 /**
691 * @brief Independent WATCHDOG
692 */
693
694 typedef struct
695 {
696 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
697 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
698 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
699 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
700 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
701 } IWDG_TypeDef;
702
703
704 /**
705 * @brief LCD-TFT Display Controller
706 */
707
708 typedef struct
709 {
710 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
711 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
712 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
713 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
714 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
715 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
716 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
717 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
718 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
719 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
720 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
721 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
722 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
723 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
724 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
725 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
726 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
727 } LTDC_TypeDef;
728
729 /**
730 * @brief LCD-TFT Display layer x Controller
731 */
732
733 typedef struct
734 {
735 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
736 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
737 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
738 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
739 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
740 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
741 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
742 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
743 uint32_t RESERVED0[2]; /*!< Reserved */
744 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
745 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
746 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
747 uint32_t RESERVED1[3]; /*!< Reserved */
748 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
749
750 } LTDC_Layer_TypeDef;
751
752 /**
753 * @brief Power Control
754 */
755
756 typedef struct
757 {
758 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
759 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
760 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
761 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
762 } PWR_TypeDef;
763
764
765 /**
766 * @brief Reset and Clock Control
767 */
768
769 typedef struct
770 {
771 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
772 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
773 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
774 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
775 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
776 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
777 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
778 uint32_t RESERVED0; /*!< Reserved, 0x1C */
779 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
780 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
781 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
782 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
783 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
784 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
785 uint32_t RESERVED2; /*!< Reserved, 0x3C */
786 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
787 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
788 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
789 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
790 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
791 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
792 uint32_t RESERVED4; /*!< Reserved, 0x5C */
793 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
794 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
795 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
796 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
797 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
798 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
799 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
800 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
801 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
802 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
803 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
804
805 } RCC_TypeDef;
806
807 /**
808 * @brief Real-Time Clock
809 */
810
811 typedef struct
812 {
813 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
814 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
815 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
816 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
817 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
818 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
819 uint32_t reserved; /*!< Reserved */
820 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
821 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
822 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
823 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
824 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
825 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
826 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
827 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
828 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
829 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
830 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
831 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
832 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
833 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
834 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
835 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
836 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
837 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
838 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
839 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
840 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
841 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
842 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
843 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
844 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
845 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
846 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
847 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
848 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
849 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
850 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
851 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
852 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
853 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
854 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
855 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
856 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
857 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
858 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
859 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
860 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
861 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
862 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
863 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
864 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
865 } RTC_TypeDef;
866
867
868 /**
869 * @brief Serial Audio Interface
870 */
871
872 typedef struct
873 {
874 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
875 } SAI_TypeDef;
876
877 typedef struct
878 {
879 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
880 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
881 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
882 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
883 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
884 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
885 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
886 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
887 } SAI_Block_TypeDef;
888
889 /**
890 * @brief SPDIF-RX Interface
891 */
892
893 typedef struct
894 {
895 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
896 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
897 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
898 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
899 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
900 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
901 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
902 } SPDIFRX_TypeDef;
903
904 /**
905 * @brief SD host Interface
906 */
907
908 typedef struct
909 {
910 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
911 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
912 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
913 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
914 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
915 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
916 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
917 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
918 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
919 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
920 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
921 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
922 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
923 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
924 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
925 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
926 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
927 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
928 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
929 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
930 } SDMMC_TypeDef;
931
932 /**
933 * @brief Serial Peripheral Interface
934 */
935
936 typedef struct
937 {
938 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
939 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
940 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
941 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
942 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
943 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
944 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
945 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
946 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
947 } SPI_TypeDef;
948
949 /**
950 * @brief QUAD Serial Peripheral Interface
951 */
952
953 typedef struct
954 {
955 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
956 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
957 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
958 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
959 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
960 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
961 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
962 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
963 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
964 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
965 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
966 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
967 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
968 } QUADSPI_TypeDef;
969
970 /**
971 * @brief TIM
972 */
973
974 typedef struct
975 {
976 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
977 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
978 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
979 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
980 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
981 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
982 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
983 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
984 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
985 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
986 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
987 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
988 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
989 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
990 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
991 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
992 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
993 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
994 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
995 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
996 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
997 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
998 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
999 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
1000 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
1001 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
1002
1003 } TIM_TypeDef;
1004
1005 /**
1006 * @brief LPTIMIMER
1007 */
1008 typedef struct
1009 {
1010 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1011 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1012 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1013 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1014 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1015 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1016 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1017 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1018 } LPTIM_TypeDef;
1019
1020
1021 /**
1022 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1023 */
1024
1025 typedef struct
1026 {
1027 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1028 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1029 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1030 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1031 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1032 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1033 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1034 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1035 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1036 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1037 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1038 } USART_TypeDef;
1039
1040
1041 /**
1042 * @brief Window WATCHDOG
1043 */
1044
1045 typedef struct
1046 {
1047 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1048 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1049 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1050 } WWDG_TypeDef;
1051
1052 /**
1053 * @brief Crypto Processor
1054 */
1055
1056 typedef struct
1057 {
1058 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
1059 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
1060 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
1061 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
1062 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
1063 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
1064 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
1065 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
1066 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
1067 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
1068 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
1069 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
1070 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
1071 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
1072 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
1073 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
1074 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
1075 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
1076 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
1077 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
1078 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
1079 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
1080 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
1081 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
1082 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
1083 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
1084 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
1085 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
1086 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
1087 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
1088 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
1089 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
1090 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
1091 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
1092 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
1093 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
1094 } CRYP_TypeDef;
1095
1096 /**
1097 * @brief HASH
1098 */
1099
1100 typedef struct
1101 {
1102 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
1103 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
1104 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
1105 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1106 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
1107 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
1108 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1109 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1110 } HASH_TypeDef;
1111
1112 /**
1113 * @brief HASH_DIGEST
1114 */
1115
1116 typedef struct
1117 {
1118 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1119 } HASH_DIGEST_TypeDef;
1120
1121 /**
1122 * @brief RNG
1123 */
1124
1125 typedef struct
1126 {
1127 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1128 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1129 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1130 } RNG_TypeDef;
1131
1132 /**
1133 * @}
1134 */
1135
1136 /**
1137 * @brief USB_OTG_Core_Registers
1138 */
1139 typedef struct
1140 {
1141 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1142 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1143 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1144 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1145 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1146 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1147 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1148 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1149 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1150 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1151 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1152 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1153 uint32_t Reserved30[2]; /*!< Reserved 030h */
1154 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1155 __IO uint32_t CID; /*!< User ID Register 03Ch */
1156 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
1157 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1158 uint32_t Reserved6; /*!< Reserved 050h */
1159 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1160 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1161 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1162 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1163 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1164 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1165 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1166 } USB_OTG_GlobalTypeDef;
1167
1168
1169 /**
1170 * @brief USB_OTG_device_Registers
1171 */
1172 typedef struct
1173 {
1174 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1175 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1176 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1177 uint32_t Reserved0C; /*!< Reserved 80Ch */
1178 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1179 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1180 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1181 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1182 uint32_t Reserved20; /*!< Reserved 820h */
1183 uint32_t Reserved9; /*!< Reserved 824h */
1184 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1185 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1186 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1187 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1188 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1189 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1190 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1191 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1192 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1193 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1194 } USB_OTG_DeviceTypeDef;
1195
1196
1197 /**
1198 * @brief USB_OTG_IN_Endpoint-Specific_Register
1199 */
1200 typedef struct
1201 {
1202 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1203 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1204 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1205 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1206 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1207 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1208 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1209 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1210 } USB_OTG_INEndpointTypeDef;
1211
1212
1213 /**
1214 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1215 */
1216 typedef struct
1217 {
1218 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1219 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1220 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1221 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1222 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1223 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1224 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1225 } USB_OTG_OUTEndpointTypeDef;
1226
1227
1228 /**
1229 * @brief USB_OTG_Host_Mode_Register_Structures
1230 */
1231 typedef struct
1232 {
1233 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1234 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1235 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1236 uint32_t Reserved40C; /*!< Reserved 40Ch */
1237 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1238 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1239 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1240 } USB_OTG_HostTypeDef;
1241
1242 /**
1243 * @brief USB_OTG_Host_Channel_Specific_Registers
1244 */
1245 typedef struct
1246 {
1247 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1248 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1249 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1250 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1251 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1252 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1253 uint32_t Reserved[2]; /*!< Reserved */
1254 } USB_OTG_HostChannelTypeDef;
1255 /**
1256 * @}
1257 */
1258
1259 /**
1260 * @brief JPEG Codec
1261 */
1262 typedef struct
1263 {
1264 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
1265 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
1266 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
1267 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
1268 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
1269 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
1270 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
1271 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
1272 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1273 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
1274 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
1275 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
1276 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1277 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
1278 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
1279 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1280 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1281 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1282 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1283 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1284 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1285 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1286 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1287 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1288 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1289 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
1290 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
1291 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
1292 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
1293
1294 } JPEG_TypeDef;
1295
1296 /**
1297 * @brief MDIOS
1298 */
1299
1300 typedef struct
1301 {
1302 __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
1303 __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
1304 __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
1305 __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
1306 __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
1307 __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
1308 __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
1309 uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
1310 __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
1311 __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
1312 __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
1313 __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
1314 __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
1315 __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
1316 __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
1317 __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
1318 __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
1319 __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
1320 __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
1321 __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
1322 __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
1323 __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
1324 __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
1325 __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
1326 __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
1327 __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
1328 __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
1329 __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
1330 __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
1331 __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
1332 __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
1333 __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
1334 __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
1335 __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
1336 __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
1337 __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
1338 __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
1339 __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
1340 __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
1341 __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
1342 __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
1343 __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
1344 __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
1345 __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
1346 __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
1347 __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
1348 __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
1349 __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
1350 __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
1351 __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
1352 __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
1353 __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
1354 __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
1355 __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
1356 __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
1357 __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
1358 __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
1359 __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
1360 __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
1361 __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
1362 __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
1363 __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
1364 __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
1365 __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
1366 __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
1367 __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
1368 __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
1369 __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
1370 __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
1371 __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
1372 __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
1373 __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
1374 } MDIOS_TypeDef;
1375
1376 /**
1377 * @brief DSI Controller
1378 */
1379
1380 typedef struct
1381 {
1382 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
1383 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
1384 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
1385 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
1386 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
1387 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
1388 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
1389 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
1390 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
1391 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
1392 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
1393 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
1394 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
1395 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
1396 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
1397 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
1398 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
1399 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
1400 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
1401 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
1402 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
1403 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
1404 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
1405 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
1406 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
1407 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
1408 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
1409 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
1410 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
1411 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
1412 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
1413 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
1414 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
1415 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
1416 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
1417 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
1418 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
1419 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
1420 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
1421 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
1422 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
1423 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
1424 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
1425 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
1426 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
1427 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
1428 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
1429 uint32_t RESERVED5; /*!< Reserved, 0x114 */
1430 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
1431 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
1432 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
1433 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
1434 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
1435 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
1436 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
1437 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
1438 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
1439 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
1440 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
1441 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
1442 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
1443 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
1444 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
1445 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
1446 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
1447 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
1448 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
1449 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
1450 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
1451 uint32_t RESERVED9; /*!< Reserved, 0x414 */
1452 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
1453 uint32_t RESERVED10; /*!< Reserved, 0x42C */
1454 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
1455 } DSI_TypeDef;
1456
1457 /** @addtogroup Peripheral_memory_map
1458 * @{
1459 */
1460 #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
1461 #define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
1462 #define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
1463 #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
1464 #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
1465 #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
1466 #define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
1467 #define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
1468 #define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
1469 #define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
1470 #define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
1471 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
1472 #define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */
1473 #define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */
1474
1475 /* Legacy define */
1476 #define FLASH_BASE FLASHAXI_BASE
1477
1478 /*!< Peripheral memory map */
1479 #define APB1PERIPH_BASE PERIPH_BASE
1480 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1481 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1482 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1483
1484 /*!< APB1 peripherals */
1485 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1486 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1487 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1488 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1489 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1490 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1491 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1492 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1493 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1494 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
1495 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1496 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1497 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1498 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
1499 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1500 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1501 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
1502 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1503 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1504 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1505 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1506 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1507 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1508 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1509 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
1510 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1511 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1512 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
1513 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1514 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1515 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1516 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1517
1518 /*!< APB2 peripherals */
1519 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1520 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1521 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1522 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1523 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
1524 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1525 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1526 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1527 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1528 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
1529 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1530 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1531 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1532 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1533 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1534 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1535 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1536 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1537 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1538 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1539 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1540 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1541 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1542 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1543 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1544 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1545 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1546 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1547 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
1548 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
1549 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
1550 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
1551 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
1552 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
1553 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
1554 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
1555 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
1556 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
1557 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
1558 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
1559 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
1560 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
1561 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
1562 /*!< AHB1 peripherals */
1563 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1564 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1565 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1566 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1567 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1568 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1569 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1570 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1571 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1572 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1573 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1574 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1575 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1576 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1577 #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
1578 #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
1579 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1580 /* Legacy define */
1581 #define PACKAGESIZE_BASE PACKAGE_BASE
1582
1583 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1584 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1585 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1586 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1587 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1588 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1589 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1590 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1591 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1592 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1593 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1594 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1595 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1596 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1597 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1598 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1599 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1600 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1601 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1602 #define ETH_MAC_BASE (ETH_BASE)
1603 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1604 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1605 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1606 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1607 /*!< AHB2 peripherals */
1608 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1609 #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
1610 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1611 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1612 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1613 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1614 /*!< FMC Bankx registers base address */
1615 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1616 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1617 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1618 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1619
1620 /* Debug MCU registers base address */
1621 #define DBGMCU_BASE 0xE0042000U
1622
1623 /*!< USB registers base address */
1624 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1625 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1626
1627 #define USB_OTG_GLOBAL_BASE 0x000U
1628 #define USB_OTG_DEVICE_BASE 0x800U
1629 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1630 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1631 #define USB_OTG_EP_REG_SIZE 0x20U
1632 #define USB_OTG_HOST_BASE 0x400U
1633 #define USB_OTG_HOST_PORT_BASE 0x440U
1634 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1635 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1636 #define USB_OTG_PCGCCTL_BASE 0xE00U
1637 #define USB_OTG_FIFO_BASE 0x1000U
1638 #define USB_OTG_FIFO_SIZE 0x1000U
1639
1640 /**
1641 * @}
1642 */
1643
1644 /** @addtogroup Peripheral_declaration
1645 * @{
1646 */
1647 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1648 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1649 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1650 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1651 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1652 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1653 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1654 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1655 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1656 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1657 #define RTC ((RTC_TypeDef *) RTC_BASE)
1658 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1659 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1660 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1661 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1662 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1663 #define USART2 ((USART_TypeDef *) USART2_BASE)
1664 #define USART3 ((USART_TypeDef *) USART3_BASE)
1665 #define UART4 ((USART_TypeDef *) UART4_BASE)
1666 #define UART5 ((USART_TypeDef *) UART5_BASE)
1667 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1668 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1669 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1670 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1671 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1672 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1673 #define CEC ((CEC_TypeDef *) CEC_BASE)
1674 #define PWR ((PWR_TypeDef *) PWR_BASE)
1675 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1676 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1677 #define UART7 ((USART_TypeDef *) UART7_BASE)
1678 #define UART8 ((USART_TypeDef *) UART8_BASE)
1679 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1680 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1681 #define USART1 ((USART_TypeDef *) USART1_BASE)
1682 #define USART6 ((USART_TypeDef *) USART6_BASE)
1683 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1684 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1685 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1686 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1687 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
1688 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1689 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1690 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1691 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1692 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1693 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1694 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1695 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1696 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1697 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1698 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1699 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1700 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1701 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1702 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1703 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1704 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1705 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1706 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1707 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1708 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1709 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1710 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1711 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1712 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1713 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1714 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1715 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1716 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1717 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1718 #define CRC ((CRC_TypeDef *) CRC_BASE)
1719 #define RCC ((RCC_TypeDef *) RCC_BASE)
1720 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1721 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1722 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1723 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1724 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1725 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1726 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1727 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1728 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1729 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1730 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1731 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1732 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1733 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1734 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1735 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1736 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1737 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1738 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1739 #define ETH ((ETH_TypeDef *) ETH_BASE)
1740 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1741 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1742 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1743 #define HASH ((HASH_TypeDef *) HASH_BASE)
1744 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1745 #define RNG ((RNG_TypeDef *) RNG_BASE)
1746 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1747 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1748 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1749 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1750 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1751 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1752 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1753 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1754 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
1755 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
1756 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
1757 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1758 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1759 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1760 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1761 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1762 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1763 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1764 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1765 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1766 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1767 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1768 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1769 #define JPEG ((JPEG_TypeDef *) JPEG_BASE)
1770 #define DSI ((DSI_TypeDef *)DSI_BASE)
1771
1772 /**
1773 * @}
1774 */
1775
1776 /** @addtogroup Exported_constants
1777 * @{
1778 */
1779
1780 /** @addtogroup Peripheral_Registers_Bits_Definition
1781 * @{
1782 */
1783
1784 /******************************************************************************/
1785 /* Peripheral Registers_Bits_Definition */
1786 /******************************************************************************/
1787
1788 /******************************************************************************/
1789 /* */
1790 /* Analog to Digital Converter */
1791 /* */
1792 /******************************************************************************/
1793 /******************** Bit definition for ADC_SR register ********************/
1794 #define ADC_SR_AWD_Pos (0U)
1795 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1796 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1797 #define ADC_SR_EOC_Pos (1U)
1798 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1799 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1800 #define ADC_SR_JEOC_Pos (2U)
1801 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1802 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1803 #define ADC_SR_JSTRT_Pos (3U)
1804 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1805 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1806 #define ADC_SR_STRT_Pos (4U)
1807 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1808 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1809 #define ADC_SR_OVR_Pos (5U)
1810 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1811 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1812
1813 /******************* Bit definition for ADC_CR1 register ********************/
1814 #define ADC_CR1_AWDCH_Pos (0U)
1815 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1816 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1817 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1818 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1819 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1820 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1821 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1822 #define ADC_CR1_EOCIE_Pos (5U)
1823 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1824 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1825 #define ADC_CR1_AWDIE_Pos (6U)
1826 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1827 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1828 #define ADC_CR1_JEOCIE_Pos (7U)
1829 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1830 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1831 #define ADC_CR1_SCAN_Pos (8U)
1832 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1833 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1834 #define ADC_CR1_AWDSGL_Pos (9U)
1835 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1836 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1837 #define ADC_CR1_JAUTO_Pos (10U)
1838 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1839 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1840 #define ADC_CR1_DISCEN_Pos (11U)
1841 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1842 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1843 #define ADC_CR1_JDISCEN_Pos (12U)
1844 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1845 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1846 #define ADC_CR1_DISCNUM_Pos (13U)
1847 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1848 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1849 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1850 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1851 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1852 #define ADC_CR1_JAWDEN_Pos (22U)
1853 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1854 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1855 #define ADC_CR1_AWDEN_Pos (23U)
1856 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1857 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1858 #define ADC_CR1_RES_Pos (24U)
1859 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1860 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1861 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1862 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1863 #define ADC_CR1_OVRIE_Pos (26U)
1864 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1865 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1866
1867 /******************* Bit definition for ADC_CR2 register ********************/
1868 #define ADC_CR2_ADON_Pos (0U)
1869 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1870 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1871 #define ADC_CR2_CONT_Pos (1U)
1872 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1873 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1874 #define ADC_CR2_DMA_Pos (8U)
1875 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1876 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1877 #define ADC_CR2_DDS_Pos (9U)
1878 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1879 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1880 #define ADC_CR2_EOCS_Pos (10U)
1881 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1882 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1883 #define ADC_CR2_ALIGN_Pos (11U)
1884 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1885 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1886 #define ADC_CR2_JEXTSEL_Pos (16U)
1887 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1888 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1889 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1890 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1891 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1892 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1893 #define ADC_CR2_JEXTEN_Pos (20U)
1894 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1895 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1896 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1897 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1898 #define ADC_CR2_JSWSTART_Pos (22U)
1899 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1900 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1901 #define ADC_CR2_EXTSEL_Pos (24U)
1902 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1903 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1904 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1905 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1906 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1907 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1908 #define ADC_CR2_EXTEN_Pos (28U)
1909 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1910 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1911 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1912 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1913 #define ADC_CR2_SWSTART_Pos (30U)
1914 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1915 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1916
1917 /****************** Bit definition for ADC_SMPR1 register *******************/
1918 #define ADC_SMPR1_SMP10_Pos (0U)
1919 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1920 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1921 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1922 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1923 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1924 #define ADC_SMPR1_SMP11_Pos (3U)
1925 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1926 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1927 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1928 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1929 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1930 #define ADC_SMPR1_SMP12_Pos (6U)
1931 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1932 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1933 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1934 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1935 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1936 #define ADC_SMPR1_SMP13_Pos (9U)
1937 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1938 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1939 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1940 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1941 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1942 #define ADC_SMPR1_SMP14_Pos (12U)
1943 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1944 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1945 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1946 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1947 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1948 #define ADC_SMPR1_SMP15_Pos (15U)
1949 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1950 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1951 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1952 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1953 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1954 #define ADC_SMPR1_SMP16_Pos (18U)
1955 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1956 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1957 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1958 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1959 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1960 #define ADC_SMPR1_SMP17_Pos (21U)
1961 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1962 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1963 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1964 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1965 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1966 #define ADC_SMPR1_SMP18_Pos (24U)
1967 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1968 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1969 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1970 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1971 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1972
1973 /****************** Bit definition for ADC_SMPR2 register *******************/
1974 #define ADC_SMPR2_SMP0_Pos (0U)
1975 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1976 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1977 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1978 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1979 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1980 #define ADC_SMPR2_SMP1_Pos (3U)
1981 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1982 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1983 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1984 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1985 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1986 #define ADC_SMPR2_SMP2_Pos (6U)
1987 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1988 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1989 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1990 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1991 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1992 #define ADC_SMPR2_SMP3_Pos (9U)
1993 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1994 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1995 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1996 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1997 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1998 #define ADC_SMPR2_SMP4_Pos (12U)
1999 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
2000 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
2001 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
2002 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
2003 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
2004 #define ADC_SMPR2_SMP5_Pos (15U)
2005 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
2006 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
2007 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
2008 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
2009 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
2010 #define ADC_SMPR2_SMP6_Pos (18U)
2011 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
2012 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
2013 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
2014 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
2015 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
2016 #define ADC_SMPR2_SMP7_Pos (21U)
2017 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
2018 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
2019 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
2020 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
2021 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
2022 #define ADC_SMPR2_SMP8_Pos (24U)
2023 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
2024 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
2025 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
2026 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
2027 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
2028 #define ADC_SMPR2_SMP9_Pos (27U)
2029 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
2030 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
2031 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
2032 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
2033 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
2034
2035 /****************** Bit definition for ADC_JOFR1 register *******************/
2036 #define ADC_JOFR1_JOFFSET1_Pos (0U)
2037 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
2038 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
2039
2040 /****************** Bit definition for ADC_JOFR2 register *******************/
2041 #define ADC_JOFR2_JOFFSET2_Pos (0U)
2042 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
2043 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
2044
2045 /****************** Bit definition for ADC_JOFR3 register *******************/
2046 #define ADC_JOFR3_JOFFSET3_Pos (0U)
2047 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
2048 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
2049
2050 /****************** Bit definition for ADC_JOFR4 register *******************/
2051 #define ADC_JOFR4_JOFFSET4_Pos (0U)
2052 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
2053 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
2054
2055 /******************* Bit definition for ADC_HTR register ********************/
2056 #define ADC_HTR_HT_Pos (0U)
2057 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
2058 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
2059
2060 /******************* Bit definition for ADC_LTR register ********************/
2061 #define ADC_LTR_LT_Pos (0U)
2062 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
2063 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
2064
2065 /******************* Bit definition for ADC_SQR1 register *******************/
2066 #define ADC_SQR1_SQ13_Pos (0U)
2067 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
2068 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
2069 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
2070 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
2071 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
2072 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
2073 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
2074 #define ADC_SQR1_SQ14_Pos (5U)
2075 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
2076 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
2077 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
2078 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
2079 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
2080 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
2081 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
2082 #define ADC_SQR1_SQ15_Pos (10U)
2083 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
2084 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
2085 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
2086 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
2087 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
2088 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
2089 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
2090 #define ADC_SQR1_SQ16_Pos (15U)
2091 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
2092 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
2093 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
2094 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
2095 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
2096 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
2097 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
2098 #define ADC_SQR1_L_Pos (20U)
2099 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
2100 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
2101 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
2102 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
2103 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
2104 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
2105
2106 /******************* Bit definition for ADC_SQR2 register *******************/
2107 #define ADC_SQR2_SQ7_Pos (0U)
2108 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
2109 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
2110 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
2111 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
2112 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
2113 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
2114 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
2115 #define ADC_SQR2_SQ8_Pos (5U)
2116 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
2117 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
2118 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
2119 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
2120 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
2121 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
2122 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
2123 #define ADC_SQR2_SQ9_Pos (10U)
2124 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
2125 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
2126 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
2127 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
2128 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
2129 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
2130 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
2131 #define ADC_SQR2_SQ10_Pos (15U)
2132 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
2133 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
2134 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
2135 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
2136 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
2137 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
2138 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
2139 #define ADC_SQR2_SQ11_Pos (20U)
2140 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
2141 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
2142 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
2143 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
2144 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
2145 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
2146 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
2147 #define ADC_SQR2_SQ12_Pos (25U)
2148 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
2149 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
2150 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
2151 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
2152 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
2153 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
2154 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
2155
2156 /******************* Bit definition for ADC_SQR3 register *******************/
2157 #define ADC_SQR3_SQ1_Pos (0U)
2158 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
2159 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
2160 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
2161 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
2162 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
2163 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
2164 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
2165 #define ADC_SQR3_SQ2_Pos (5U)
2166 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
2167 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
2168 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
2169 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
2170 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
2171 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
2172 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
2173 #define ADC_SQR3_SQ3_Pos (10U)
2174 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
2175 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
2176 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
2177 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
2178 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
2179 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
2180 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
2181 #define ADC_SQR3_SQ4_Pos (15U)
2182 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
2183 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
2184 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
2185 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
2186 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
2187 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
2188 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
2189 #define ADC_SQR3_SQ5_Pos (20U)
2190 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
2191 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
2192 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
2193 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
2194 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
2195 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
2196 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
2197 #define ADC_SQR3_SQ6_Pos (25U)
2198 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
2199 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
2200 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
2201 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
2202 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
2203 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
2204 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
2205
2206 /******************* Bit definition for ADC_JSQR register *******************/
2207 #define ADC_JSQR_JSQ1_Pos (0U)
2208 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
2209 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
2210 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
2211 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
2212 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
2213 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
2214 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
2215 #define ADC_JSQR_JSQ2_Pos (5U)
2216 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
2217 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
2218 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
2219 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
2220 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
2221 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
2222 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
2223 #define ADC_JSQR_JSQ3_Pos (10U)
2224 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
2225 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
2226 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
2227 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
2228 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
2229 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
2230 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
2231 #define ADC_JSQR_JSQ4_Pos (15U)
2232 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
2233 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
2234 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
2235 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
2236 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
2237 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
2238 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
2239 #define ADC_JSQR_JL_Pos (20U)
2240 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
2241 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
2242 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
2243 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
2244
2245 /******************* Bit definition for ADC_JDR1 register *******************/
2246 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
2247
2248 /******************* Bit definition for ADC_JDR2 register *******************/
2249 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
2250
2251 /******************* Bit definition for ADC_JDR3 register *******************/
2252 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
2253
2254 /******************* Bit definition for ADC_JDR4 register *******************/
2255 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
2256
2257 /******************** Bit definition for ADC_DR register ********************/
2258 #define ADC_DR_DATA_Pos (0U)
2259 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
2260 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
2261 #define ADC_DR_ADC2DATA_Pos (16U)
2262 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
2263 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
2264
2265 /******************* Bit definition for ADC_CSR register ********************/
2266 #define ADC_CSR_AWD1_Pos (0U)
2267 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
2268 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
2269 #define ADC_CSR_EOC1_Pos (1U)
2270 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
2271 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
2272 #define ADC_CSR_JEOC1_Pos (2U)
2273 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
2274 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
2275 #define ADC_CSR_JSTRT1_Pos (3U)
2276 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
2277 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
2278 #define ADC_CSR_STRT1_Pos (4U)
2279 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
2280 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
2281 #define ADC_CSR_OVR1_Pos (5U)
2282 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
2283 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */
2284 #define ADC_CSR_AWD2_Pos (8U)
2285 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
2286 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
2287 #define ADC_CSR_EOC2_Pos (9U)
2288 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
2289 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
2290 #define ADC_CSR_JEOC2_Pos (10U)
2291 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
2292 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
2293 #define ADC_CSR_JSTRT2_Pos (11U)
2294 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
2295 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
2296 #define ADC_CSR_STRT2_Pos (12U)
2297 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
2298 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
2299 #define ADC_CSR_OVR2_Pos (13U)
2300 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
2301 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */
2302 #define ADC_CSR_AWD3_Pos (16U)
2303 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
2304 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
2305 #define ADC_CSR_EOC3_Pos (17U)
2306 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
2307 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
2308 #define ADC_CSR_JEOC3_Pos (18U)
2309 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
2310 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
2311 #define ADC_CSR_JSTRT3_Pos (19U)
2312 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
2313 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
2314 #define ADC_CSR_STRT3_Pos (20U)
2315 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
2316 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
2317 #define ADC_CSR_OVR3_Pos (21U)
2318 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
2319 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */
2320
2321 /* Legacy defines */
2322 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
2323 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
2324 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
2325
2326
2327 /******************* Bit definition for ADC_CCR register ********************/
2328 #define ADC_CCR_MULTI_Pos (0U)
2329 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
2330 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
2331 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
2332 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
2333 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
2334 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
2335 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
2336 #define ADC_CCR_DELAY_Pos (8U)
2337 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2338 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
2339 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2340 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2341 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2342 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2343 #define ADC_CCR_DDS_Pos (13U)
2344 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
2345 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
2346 #define ADC_CCR_DMA_Pos (14U)
2347 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
2348 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
2349 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
2350 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
2351 #define ADC_CCR_ADCPRE_Pos (16U)
2352 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
2353 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
2354 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
2355 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
2356 #define ADC_CCR_VBATE_Pos (22U)
2357 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
2358 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
2359 #define ADC_CCR_TSVREFE_Pos (23U)
2360 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
2361 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
2362
2363 /******************* Bit definition for ADC_CDR register ********************/
2364 #define ADC_CDR_DATA1_Pos (0U)
2365 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
2366 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
2367 #define ADC_CDR_DATA2_Pos (16U)
2368 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
2369 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
2370
2371 /* Legacy defines */
2372 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
2373 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
2374
2375 /******************************************************************************/
2376 /* */
2377 /* Controller Area Network */
2378 /* */
2379 /******************************************************************************/
2380 /*!<CAN control and status registers */
2381 /******************* Bit definition for CAN_MCR register ********************/
2382 #define CAN_MCR_INRQ_Pos (0U)
2383 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2384 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2385 #define CAN_MCR_SLEEP_Pos (1U)
2386 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2387 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2388 #define CAN_MCR_TXFP_Pos (2U)
2389 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2390 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2391 #define CAN_MCR_RFLM_Pos (3U)
2392 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2393 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2394 #define CAN_MCR_NART_Pos (4U)
2395 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2396 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2397 #define CAN_MCR_AWUM_Pos (5U)
2398 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2399 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2400 #define CAN_MCR_ABOM_Pos (6U)
2401 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2402 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2403 #define CAN_MCR_TTCM_Pos (7U)
2404 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2405 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2406 #define CAN_MCR_RESET_Pos (15U)
2407 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2408 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2409
2410 /******************* Bit definition for CAN_MSR register ********************/
2411 #define CAN_MSR_INAK_Pos (0U)
2412 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2413 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2414 #define CAN_MSR_SLAK_Pos (1U)
2415 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2416 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2417 #define CAN_MSR_ERRI_Pos (2U)
2418 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2419 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2420 #define CAN_MSR_WKUI_Pos (3U)
2421 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2422 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2423 #define CAN_MSR_SLAKI_Pos (4U)
2424 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2425 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2426 #define CAN_MSR_TXM_Pos (8U)
2427 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2428 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2429 #define CAN_MSR_RXM_Pos (9U)
2430 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2431 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2432 #define CAN_MSR_SAMP_Pos (10U)
2433 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2434 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2435 #define CAN_MSR_RX_Pos (11U)
2436 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2437 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2438
2439 /******************* Bit definition for CAN_TSR register ********************/
2440 #define CAN_TSR_RQCP0_Pos (0U)
2441 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2442 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2443 #define CAN_TSR_TXOK0_Pos (1U)
2444 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2445 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2446 #define CAN_TSR_ALST0_Pos (2U)
2447 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2448 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2449 #define CAN_TSR_TERR0_Pos (3U)
2450 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2451 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2452 #define CAN_TSR_ABRQ0_Pos (7U)
2453 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2454 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2455 #define CAN_TSR_RQCP1_Pos (8U)
2456 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2457 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2458 #define CAN_TSR_TXOK1_Pos (9U)
2459 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2460 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2461 #define CAN_TSR_ALST1_Pos (10U)
2462 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2463 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2464 #define CAN_TSR_TERR1_Pos (11U)
2465 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2466 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2467 #define CAN_TSR_ABRQ1_Pos (15U)
2468 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2469 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2470 #define CAN_TSR_RQCP2_Pos (16U)
2471 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2472 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2473 #define CAN_TSR_TXOK2_Pos (17U)
2474 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2475 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2476 #define CAN_TSR_ALST2_Pos (18U)
2477 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2478 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2479 #define CAN_TSR_TERR2_Pos (19U)
2480 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2481 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2482 #define CAN_TSR_ABRQ2_Pos (23U)
2483 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2484 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2485 #define CAN_TSR_CODE_Pos (24U)
2486 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2487 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2488
2489 #define CAN_TSR_TME_Pos (26U)
2490 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2491 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2492 #define CAN_TSR_TME0_Pos (26U)
2493 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2494 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2495 #define CAN_TSR_TME1_Pos (27U)
2496 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2497 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2498 #define CAN_TSR_TME2_Pos (28U)
2499 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2500 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2501
2502 #define CAN_TSR_LOW_Pos (29U)
2503 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2504 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2505 #define CAN_TSR_LOW0_Pos (29U)
2506 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2507 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2508 #define CAN_TSR_LOW1_Pos (30U)
2509 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2510 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2511 #define CAN_TSR_LOW2_Pos (31U)
2512 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2513 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2514
2515 /******************* Bit definition for CAN_RF0R register *******************/
2516 #define CAN_RF0R_FMP0_Pos (0U)
2517 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2518 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2519 #define CAN_RF0R_FULL0_Pos (3U)
2520 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2521 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2522 #define CAN_RF0R_FOVR0_Pos (4U)
2523 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2524 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2525 #define CAN_RF0R_RFOM0_Pos (5U)
2526 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2527 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2528
2529 /******************* Bit definition for CAN_RF1R register *******************/
2530 #define CAN_RF1R_FMP1_Pos (0U)
2531 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2532 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2533 #define CAN_RF1R_FULL1_Pos (3U)
2534 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2535 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2536 #define CAN_RF1R_FOVR1_Pos (4U)
2537 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2538 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2539 #define CAN_RF1R_RFOM1_Pos (5U)
2540 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2541 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2542
2543 /******************** Bit definition for CAN_IER register *******************/
2544 #define CAN_IER_TMEIE_Pos (0U)
2545 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2546 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2547 #define CAN_IER_FMPIE0_Pos (1U)
2548 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2549 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2550 #define CAN_IER_FFIE0_Pos (2U)
2551 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2552 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2553 #define CAN_IER_FOVIE0_Pos (3U)
2554 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2555 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2556 #define CAN_IER_FMPIE1_Pos (4U)
2557 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2558 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2559 #define CAN_IER_FFIE1_Pos (5U)
2560 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2561 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2562 #define CAN_IER_FOVIE1_Pos (6U)
2563 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2564 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2565 #define CAN_IER_EWGIE_Pos (8U)
2566 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2567 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2568 #define CAN_IER_EPVIE_Pos (9U)
2569 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2570 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2571 #define CAN_IER_BOFIE_Pos (10U)
2572 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2573 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2574 #define CAN_IER_LECIE_Pos (11U)
2575 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2576 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2577 #define CAN_IER_ERRIE_Pos (15U)
2578 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2579 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2580 #define CAN_IER_WKUIE_Pos (16U)
2581 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2582 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2583 #define CAN_IER_SLKIE_Pos (17U)
2584 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2585 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2586
2587 /******************** Bit definition for CAN_ESR register *******************/
2588 #define CAN_ESR_EWGF_Pos (0U)
2589 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2590 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2591 #define CAN_ESR_EPVF_Pos (1U)
2592 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2593 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2594 #define CAN_ESR_BOFF_Pos (2U)
2595 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2596 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2597
2598 #define CAN_ESR_LEC_Pos (4U)
2599 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2600 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2601 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2602 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2603 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2604
2605 #define CAN_ESR_TEC_Pos (16U)
2606 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2607 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2608 #define CAN_ESR_REC_Pos (24U)
2609 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2610 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2611
2612 /******************* Bit definition for CAN_BTR register ********************/
2613 #define CAN_BTR_BRP_Pos (0U)
2614 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2615 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2616 #define CAN_BTR_TS1_Pos (16U)
2617 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2618 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2619 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2620 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2621 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2622 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2623 #define CAN_BTR_TS2_Pos (20U)
2624 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2625 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2626 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2627 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2628 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2629 #define CAN_BTR_SJW_Pos (24U)
2630 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2631 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2632 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2633 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2634 #define CAN_BTR_LBKM_Pos (30U)
2635 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2636 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2637 #define CAN_BTR_SILM_Pos (31U)
2638 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2639 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2640
2641 /*!<Mailbox registers */
2642 /****************** Bit definition for CAN_TI0R register ********************/
2643 #define CAN_TI0R_TXRQ_Pos (0U)
2644 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2645 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2646 #define CAN_TI0R_RTR_Pos (1U)
2647 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2648 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2649 #define CAN_TI0R_IDE_Pos (2U)
2650 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2651 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2652 #define CAN_TI0R_EXID_Pos (3U)
2653 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2654 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2655 #define CAN_TI0R_STID_Pos (21U)
2656 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2657 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2658
2659 /****************** Bit definition for CAN_TDT0R register *******************/
2660 #define CAN_TDT0R_DLC_Pos (0U)
2661 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2662 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2663 #define CAN_TDT0R_TGT_Pos (8U)
2664 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2665 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2666 #define CAN_TDT0R_TIME_Pos (16U)
2667 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2668 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2669
2670 /****************** Bit definition for CAN_TDL0R register *******************/
2671 #define CAN_TDL0R_DATA0_Pos (0U)
2672 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2673 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2674 #define CAN_TDL0R_DATA1_Pos (8U)
2675 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2676 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2677 #define CAN_TDL0R_DATA2_Pos (16U)
2678 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2679 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2680 #define CAN_TDL0R_DATA3_Pos (24U)
2681 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2682 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2683
2684 /****************** Bit definition for CAN_TDH0R register *******************/
2685 #define CAN_TDH0R_DATA4_Pos (0U)
2686 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2687 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2688 #define CAN_TDH0R_DATA5_Pos (8U)
2689 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2690 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2691 #define CAN_TDH0R_DATA6_Pos (16U)
2692 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2693 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2694 #define CAN_TDH0R_DATA7_Pos (24U)
2695 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2696 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2697
2698 /******************* Bit definition for CAN_TI1R register *******************/
2699 #define CAN_TI1R_TXRQ_Pos (0U)
2700 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2701 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2702 #define CAN_TI1R_RTR_Pos (1U)
2703 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2704 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2705 #define CAN_TI1R_IDE_Pos (2U)
2706 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2707 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2708 #define CAN_TI1R_EXID_Pos (3U)
2709 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2710 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2711 #define CAN_TI1R_STID_Pos (21U)
2712 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2713 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2714
2715 /******************* Bit definition for CAN_TDT1R register ******************/
2716 #define CAN_TDT1R_DLC_Pos (0U)
2717 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2718 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2719 #define CAN_TDT1R_TGT_Pos (8U)
2720 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2721 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2722 #define CAN_TDT1R_TIME_Pos (16U)
2723 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2724 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2725
2726 /******************* Bit definition for CAN_TDL1R register ******************/
2727 #define CAN_TDL1R_DATA0_Pos (0U)
2728 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2729 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2730 #define CAN_TDL1R_DATA1_Pos (8U)
2731 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2732 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2733 #define CAN_TDL1R_DATA2_Pos (16U)
2734 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2735 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2736 #define CAN_TDL1R_DATA3_Pos (24U)
2737 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2738 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2739
2740 /******************* Bit definition for CAN_TDH1R register ******************/
2741 #define CAN_TDH1R_DATA4_Pos (0U)
2742 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2743 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2744 #define CAN_TDH1R_DATA5_Pos (8U)
2745 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2746 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2747 #define CAN_TDH1R_DATA6_Pos (16U)
2748 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2749 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2750 #define CAN_TDH1R_DATA7_Pos (24U)
2751 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2752 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2753
2754 /******************* Bit definition for CAN_TI2R register *******************/
2755 #define CAN_TI2R_TXRQ_Pos (0U)
2756 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2757 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2758 #define CAN_TI2R_RTR_Pos (1U)
2759 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2760 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2761 #define CAN_TI2R_IDE_Pos (2U)
2762 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2763 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2764 #define CAN_TI2R_EXID_Pos (3U)
2765 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2766 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2767 #define CAN_TI2R_STID_Pos (21U)
2768 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2769 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2770
2771 /******************* Bit definition for CAN_TDT2R register ******************/
2772 #define CAN_TDT2R_DLC_Pos (0U)
2773 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2774 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2775 #define CAN_TDT2R_TGT_Pos (8U)
2776 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2777 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2778 #define CAN_TDT2R_TIME_Pos (16U)
2779 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2780 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2781
2782 /******************* Bit definition for CAN_TDL2R register ******************/
2783 #define CAN_TDL2R_DATA0_Pos (0U)
2784 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2785 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2786 #define CAN_TDL2R_DATA1_Pos (8U)
2787 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2788 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2789 #define CAN_TDL2R_DATA2_Pos (16U)
2790 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2791 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2792 #define CAN_TDL2R_DATA3_Pos (24U)
2793 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2794 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2795
2796 /******************* Bit definition for CAN_TDH2R register ******************/
2797 #define CAN_TDH2R_DATA4_Pos (0U)
2798 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2799 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2800 #define CAN_TDH2R_DATA5_Pos (8U)
2801 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2802 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2803 #define CAN_TDH2R_DATA6_Pos (16U)
2804 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2805 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2806 #define CAN_TDH2R_DATA7_Pos (24U)
2807 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2808 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2809
2810 /******************* Bit definition for CAN_RI0R register *******************/
2811 #define CAN_RI0R_RTR_Pos (1U)
2812 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2813 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2814 #define CAN_RI0R_IDE_Pos (2U)
2815 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2816 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2817 #define CAN_RI0R_EXID_Pos (3U)
2818 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2819 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2820 #define CAN_RI0R_STID_Pos (21U)
2821 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2822 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2823
2824 /******************* Bit definition for CAN_RDT0R register ******************/
2825 #define CAN_RDT0R_DLC_Pos (0U)
2826 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2827 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2828 #define CAN_RDT0R_FMI_Pos (8U)
2829 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2830 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2831 #define CAN_RDT0R_TIME_Pos (16U)
2832 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2833 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2834
2835 /******************* Bit definition for CAN_RDL0R register ******************/
2836 #define CAN_RDL0R_DATA0_Pos (0U)
2837 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2838 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2839 #define CAN_RDL0R_DATA1_Pos (8U)
2840 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2841 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2842 #define CAN_RDL0R_DATA2_Pos (16U)
2843 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2844 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2845 #define CAN_RDL0R_DATA3_Pos (24U)
2846 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2847 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2848
2849 /******************* Bit definition for CAN_RDH0R register ******************/
2850 #define CAN_RDH0R_DATA4_Pos (0U)
2851 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2852 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2853 #define CAN_RDH0R_DATA5_Pos (8U)
2854 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2855 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2856 #define CAN_RDH0R_DATA6_Pos (16U)
2857 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2858 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2859 #define CAN_RDH0R_DATA7_Pos (24U)
2860 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2861 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2862
2863 /******************* Bit definition for CAN_RI1R register *******************/
2864 #define CAN_RI1R_RTR_Pos (1U)
2865 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2866 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2867 #define CAN_RI1R_IDE_Pos (2U)
2868 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2869 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2870 #define CAN_RI1R_EXID_Pos (3U)
2871 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2872 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2873 #define CAN_RI1R_STID_Pos (21U)
2874 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2875 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2876
2877 /******************* Bit definition for CAN_RDT1R register ******************/
2878 #define CAN_RDT1R_DLC_Pos (0U)
2879 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2880 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2881 #define CAN_RDT1R_FMI_Pos (8U)
2882 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2883 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2884 #define CAN_RDT1R_TIME_Pos (16U)
2885 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2886 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2887
2888 /******************* Bit definition for CAN_RDL1R register ******************/
2889 #define CAN_RDL1R_DATA0_Pos (0U)
2890 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2891 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2892 #define CAN_RDL1R_DATA1_Pos (8U)
2893 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2894 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2895 #define CAN_RDL1R_DATA2_Pos (16U)
2896 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2897 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2898 #define CAN_RDL1R_DATA3_Pos (24U)
2899 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2900 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2901
2902 /******************* Bit definition for CAN_RDH1R register ******************/
2903 #define CAN_RDH1R_DATA4_Pos (0U)
2904 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2905 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2906 #define CAN_RDH1R_DATA5_Pos (8U)
2907 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2908 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2909 #define CAN_RDH1R_DATA6_Pos (16U)
2910 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2911 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2912 #define CAN_RDH1R_DATA7_Pos (24U)
2913 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2914 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2915
2916 /*!<CAN filter registers */
2917 /******************* Bit definition for CAN_FMR register ********************/
2918 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
2919 #define CAN_FMR_CAN2SB_Pos (8U)
2920 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2921 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2922
2923 /******************* Bit definition for CAN_FM1R register *******************/
2924 #define CAN_FM1R_FBM_Pos (0U)
2925 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
2926 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2927 #define CAN_FM1R_FBM0_Pos (0U)
2928 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2929 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2930 #define CAN_FM1R_FBM1_Pos (1U)
2931 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2932 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2933 #define CAN_FM1R_FBM2_Pos (2U)
2934 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2935 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2936 #define CAN_FM1R_FBM3_Pos (3U)
2937 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2938 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2939 #define CAN_FM1R_FBM4_Pos (4U)
2940 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2941 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2942 #define CAN_FM1R_FBM5_Pos (5U)
2943 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2944 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2945 #define CAN_FM1R_FBM6_Pos (6U)
2946 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2947 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2948 #define CAN_FM1R_FBM7_Pos (7U)
2949 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2950 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2951 #define CAN_FM1R_FBM8_Pos (8U)
2952 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2953 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2954 #define CAN_FM1R_FBM9_Pos (9U)
2955 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2956 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2957 #define CAN_FM1R_FBM10_Pos (10U)
2958 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2959 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2960 #define CAN_FM1R_FBM11_Pos (11U)
2961 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2962 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2963 #define CAN_FM1R_FBM12_Pos (12U)
2964 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2965 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2966 #define CAN_FM1R_FBM13_Pos (13U)
2967 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2968 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2969
2970 /******************* Bit definition for CAN_FS1R register *******************/
2971 #define CAN_FS1R_FSC_Pos (0U)
2972 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
2973 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2974 #define CAN_FS1R_FSC0_Pos (0U)
2975 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2976 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2977 #define CAN_FS1R_FSC1_Pos (1U)
2978 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2979 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2980 #define CAN_FS1R_FSC2_Pos (2U)
2981 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2982 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2983 #define CAN_FS1R_FSC3_Pos (3U)
2984 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2985 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2986 #define CAN_FS1R_FSC4_Pos (4U)
2987 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2988 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2989 #define CAN_FS1R_FSC5_Pos (5U)
2990 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2991 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2992 #define CAN_FS1R_FSC6_Pos (6U)
2993 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2994 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2995 #define CAN_FS1R_FSC7_Pos (7U)
2996 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2997 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2998 #define CAN_FS1R_FSC8_Pos (8U)
2999 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
3000 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
3001 #define CAN_FS1R_FSC9_Pos (9U)
3002 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
3003 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
3004 #define CAN_FS1R_FSC10_Pos (10U)
3005 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
3006 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
3007 #define CAN_FS1R_FSC11_Pos (11U)
3008 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
3009 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
3010 #define CAN_FS1R_FSC12_Pos (12U)
3011 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
3012 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
3013 #define CAN_FS1R_FSC13_Pos (13U)
3014 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
3015 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
3016
3017 /****************** Bit definition for CAN_FFA1R register *******************/
3018 #define CAN_FFA1R_FFA_Pos (0U)
3019 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
3020 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
3021 #define CAN_FFA1R_FFA0_Pos (0U)
3022 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
3023 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
3024 #define CAN_FFA1R_FFA1_Pos (1U)
3025 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
3026 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
3027 #define CAN_FFA1R_FFA2_Pos (2U)
3028 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
3029 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
3030 #define CAN_FFA1R_FFA3_Pos (3U)
3031 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
3032 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
3033 #define CAN_FFA1R_FFA4_Pos (4U)
3034 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
3035 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
3036 #define CAN_FFA1R_FFA5_Pos (5U)
3037 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
3038 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
3039 #define CAN_FFA1R_FFA6_Pos (6U)
3040 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
3041 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
3042 #define CAN_FFA1R_FFA7_Pos (7U)
3043 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
3044 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
3045 #define CAN_FFA1R_FFA8_Pos (8U)
3046 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
3047 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
3048 #define CAN_FFA1R_FFA9_Pos (9U)
3049 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
3050 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
3051 #define CAN_FFA1R_FFA10_Pos (10U)
3052 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
3053 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
3054 #define CAN_FFA1R_FFA11_Pos (11U)
3055 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
3056 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
3057 #define CAN_FFA1R_FFA12_Pos (12U)
3058 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
3059 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
3060 #define CAN_FFA1R_FFA13_Pos (13U)
3061 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
3062 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
3063
3064 /******************* Bit definition for CAN_FA1R register *******************/
3065 #define CAN_FA1R_FACT_Pos (0U)
3066 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
3067 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
3068 #define CAN_FA1R_FACT0_Pos (0U)
3069 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
3070 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
3071 #define CAN_FA1R_FACT1_Pos (1U)
3072 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
3073 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
3074 #define CAN_FA1R_FACT2_Pos (2U)
3075 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
3076 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
3077 #define CAN_FA1R_FACT3_Pos (3U)
3078 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
3079 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
3080 #define CAN_FA1R_FACT4_Pos (4U)
3081 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
3082 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
3083 #define CAN_FA1R_FACT5_Pos (5U)
3084 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
3085 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
3086 #define CAN_FA1R_FACT6_Pos (6U)
3087 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
3088 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
3089 #define CAN_FA1R_FACT7_Pos (7U)
3090 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
3091 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
3092 #define CAN_FA1R_FACT8_Pos (8U)
3093 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
3094 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
3095 #define CAN_FA1R_FACT9_Pos (9U)
3096 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
3097 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
3098 #define CAN_FA1R_FACT10_Pos (10U)
3099 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
3100 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
3101 #define CAN_FA1R_FACT11_Pos (11U)
3102 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
3103 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
3104 #define CAN_FA1R_FACT12_Pos (12U)
3105 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
3106 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
3107 #define CAN_FA1R_FACT13_Pos (13U)
3108 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
3109 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
3110
3111 /******************* Bit definition for CAN_F0R1 register *******************/
3112 #define CAN_F0R1_FB0_Pos (0U)
3113 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
3114 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
3115 #define CAN_F0R1_FB1_Pos (1U)
3116 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
3117 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
3118 #define CAN_F0R1_FB2_Pos (2U)
3119 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
3120 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
3121 #define CAN_F0R1_FB3_Pos (3U)
3122 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
3123 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
3124 #define CAN_F0R1_FB4_Pos (4U)
3125 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
3126 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
3127 #define CAN_F0R1_FB5_Pos (5U)
3128 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
3129 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
3130 #define CAN_F0R1_FB6_Pos (6U)
3131 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
3132 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
3133 #define CAN_F0R1_FB7_Pos (7U)
3134 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
3135 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
3136 #define CAN_F0R1_FB8_Pos (8U)
3137 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
3138 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
3139 #define CAN_F0R1_FB9_Pos (9U)
3140 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
3141 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
3142 #define CAN_F0R1_FB10_Pos (10U)
3143 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
3144 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
3145 #define CAN_F0R1_FB11_Pos (11U)
3146 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
3147 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
3148 #define CAN_F0R1_FB12_Pos (12U)
3149 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
3150 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
3151 #define CAN_F0R1_FB13_Pos (13U)
3152 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
3153 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
3154 #define CAN_F0R1_FB14_Pos (14U)
3155 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
3156 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
3157 #define CAN_F0R1_FB15_Pos (15U)
3158 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3159 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3160 #define CAN_F0R1_FB16_Pos (16U)
3161 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3162 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3163 #define CAN_F0R1_FB17_Pos (17U)
3164 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3165 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3166 #define CAN_F0R1_FB18_Pos (18U)
3167 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3168 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3169 #define CAN_F0R1_FB19_Pos (19U)
3170 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3171 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3172 #define CAN_F0R1_FB20_Pos (20U)
3173 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3174 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3175 #define CAN_F0R1_FB21_Pos (21U)
3176 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3177 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3178 #define CAN_F0R1_FB22_Pos (22U)
3179 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3180 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3181 #define CAN_F0R1_FB23_Pos (23U)
3182 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3183 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3184 #define CAN_F0R1_FB24_Pos (24U)
3185 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3186 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3187 #define CAN_F0R1_FB25_Pos (25U)
3188 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3189 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3190 #define CAN_F0R1_FB26_Pos (26U)
3191 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3192 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3193 #define CAN_F0R1_FB27_Pos (27U)
3194 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3195 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3196 #define CAN_F0R1_FB28_Pos (28U)
3197 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3198 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3199 #define CAN_F0R1_FB29_Pos (29U)
3200 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3201 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3202 #define CAN_F0R1_FB30_Pos (30U)
3203 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3204 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3205 #define CAN_F0R1_FB31_Pos (31U)
3206 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3207 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3208
3209 /******************* Bit definition for CAN_F1R1 register *******************/
3210 #define CAN_F1R1_FB0_Pos (0U)
3211 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3212 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3213 #define CAN_F1R1_FB1_Pos (1U)
3214 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3215 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3216 #define CAN_F1R1_FB2_Pos (2U)
3217 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3218 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3219 #define CAN_F1R1_FB3_Pos (3U)
3220 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3221 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3222 #define CAN_F1R1_FB4_Pos (4U)
3223 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3224 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3225 #define CAN_F1R1_FB5_Pos (5U)
3226 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3227 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3228 #define CAN_F1R1_FB6_Pos (6U)
3229 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3230 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3231 #define CAN_F1R1_FB7_Pos (7U)
3232 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3233 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3234 #define CAN_F1R1_FB8_Pos (8U)
3235 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3236 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3237 #define CAN_F1R1_FB9_Pos (9U)
3238 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3239 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3240 #define CAN_F1R1_FB10_Pos (10U)
3241 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3242 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3243 #define CAN_F1R1_FB11_Pos (11U)
3244 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3245 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3246 #define CAN_F1R1_FB12_Pos (12U)
3247 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3248 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3249 #define CAN_F1R1_FB13_Pos (13U)
3250 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3251 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3252 #define CAN_F1R1_FB14_Pos (14U)
3253 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3254 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3255 #define CAN_F1R1_FB15_Pos (15U)
3256 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3257 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3258 #define CAN_F1R1_FB16_Pos (16U)
3259 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3260 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3261 #define CAN_F1R1_FB17_Pos (17U)
3262 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3263 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3264 #define CAN_F1R1_FB18_Pos (18U)
3265 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3266 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3267 #define CAN_F1R1_FB19_Pos (19U)
3268 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3269 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3270 #define CAN_F1R1_FB20_Pos (20U)
3271 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3272 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3273 #define CAN_F1R1_FB21_Pos (21U)
3274 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3275 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3276 #define CAN_F1R1_FB22_Pos (22U)
3277 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3278 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3279 #define CAN_F1R1_FB23_Pos (23U)
3280 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3281 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3282 #define CAN_F1R1_FB24_Pos (24U)
3283 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3284 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3285 #define CAN_F1R1_FB25_Pos (25U)
3286 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3287 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3288 #define CAN_F1R1_FB26_Pos (26U)
3289 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3290 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3291 #define CAN_F1R1_FB27_Pos (27U)
3292 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3293 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3294 #define CAN_F1R1_FB28_Pos (28U)
3295 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3296 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3297 #define CAN_F1R1_FB29_Pos (29U)
3298 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3299 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3300 #define CAN_F1R1_FB30_Pos (30U)
3301 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3302 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3303 #define CAN_F1R1_FB31_Pos (31U)
3304 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3305 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3306
3307 /******************* Bit definition for CAN_F2R1 register *******************/
3308 #define CAN_F2R1_FB0_Pos (0U)
3309 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3310 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3311 #define CAN_F2R1_FB1_Pos (1U)
3312 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3313 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3314 #define CAN_F2R1_FB2_Pos (2U)
3315 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3316 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3317 #define CAN_F2R1_FB3_Pos (3U)
3318 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3319 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3320 #define CAN_F2R1_FB4_Pos (4U)
3321 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3322 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3323 #define CAN_F2R1_FB5_Pos (5U)
3324 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3325 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3326 #define CAN_F2R1_FB6_Pos (6U)
3327 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3328 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3329 #define CAN_F2R1_FB7_Pos (7U)
3330 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3331 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3332 #define CAN_F2R1_FB8_Pos (8U)
3333 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3334 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3335 #define CAN_F2R1_FB9_Pos (9U)
3336 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3337 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3338 #define CAN_F2R1_FB10_Pos (10U)
3339 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3340 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3341 #define CAN_F2R1_FB11_Pos (11U)
3342 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3343 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3344 #define CAN_F2R1_FB12_Pos (12U)
3345 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3346 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3347 #define CAN_F2R1_FB13_Pos (13U)
3348 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3349 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3350 #define CAN_F2R1_FB14_Pos (14U)
3351 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3352 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3353 #define CAN_F2R1_FB15_Pos (15U)
3354 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3355 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3356 #define CAN_F2R1_FB16_Pos (16U)
3357 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3358 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3359 #define CAN_F2R1_FB17_Pos (17U)
3360 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3361 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3362 #define CAN_F2R1_FB18_Pos (18U)
3363 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3364 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3365 #define CAN_F2R1_FB19_Pos (19U)
3366 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3367 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3368 #define CAN_F2R1_FB20_Pos (20U)
3369 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3370 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3371 #define CAN_F2R1_FB21_Pos (21U)
3372 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3373 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3374 #define CAN_F2R1_FB22_Pos (22U)
3375 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3376 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3377 #define CAN_F2R1_FB23_Pos (23U)
3378 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3379 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3380 #define CAN_F2R1_FB24_Pos (24U)
3381 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3382 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3383 #define CAN_F2R1_FB25_Pos (25U)
3384 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3385 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3386 #define CAN_F2R1_FB26_Pos (26U)
3387 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3388 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3389 #define CAN_F2R1_FB27_Pos (27U)
3390 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3391 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3392 #define CAN_F2R1_FB28_Pos (28U)
3393 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3394 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3395 #define CAN_F2R1_FB29_Pos (29U)
3396 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3397 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3398 #define CAN_F2R1_FB30_Pos (30U)
3399 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3400 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3401 #define CAN_F2R1_FB31_Pos (31U)
3402 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3403 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3404
3405 /******************* Bit definition for CAN_F3R1 register *******************/
3406 #define CAN_F3R1_FB0_Pos (0U)
3407 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3408 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3409 #define CAN_F3R1_FB1_Pos (1U)
3410 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3411 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3412 #define CAN_F3R1_FB2_Pos (2U)
3413 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3414 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3415 #define CAN_F3R1_FB3_Pos (3U)
3416 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3417 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3418 #define CAN_F3R1_FB4_Pos (4U)
3419 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3420 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3421 #define CAN_F3R1_FB5_Pos (5U)
3422 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3423 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3424 #define CAN_F3R1_FB6_Pos (6U)
3425 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3426 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3427 #define CAN_F3R1_FB7_Pos (7U)
3428 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3429 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3430 #define CAN_F3R1_FB8_Pos (8U)
3431 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3432 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3433 #define CAN_F3R1_FB9_Pos (9U)
3434 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3435 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3436 #define CAN_F3R1_FB10_Pos (10U)
3437 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3438 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3439 #define CAN_F3R1_FB11_Pos (11U)
3440 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3441 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3442 #define CAN_F3R1_FB12_Pos (12U)
3443 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3444 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3445 #define CAN_F3R1_FB13_Pos (13U)
3446 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3447 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3448 #define CAN_F3R1_FB14_Pos (14U)
3449 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3450 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3451 #define CAN_F3R1_FB15_Pos (15U)
3452 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3453 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3454 #define CAN_F3R1_FB16_Pos (16U)
3455 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3456 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3457 #define CAN_F3R1_FB17_Pos (17U)
3458 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3459 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3460 #define CAN_F3R1_FB18_Pos (18U)
3461 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3462 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3463 #define CAN_F3R1_FB19_Pos (19U)
3464 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3465 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3466 #define CAN_F3R1_FB20_Pos (20U)
3467 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3468 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3469 #define CAN_F3R1_FB21_Pos (21U)
3470 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3471 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3472 #define CAN_F3R1_FB22_Pos (22U)
3473 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3474 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3475 #define CAN_F3R1_FB23_Pos (23U)
3476 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3477 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3478 #define CAN_F3R1_FB24_Pos (24U)
3479 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3480 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3481 #define CAN_F3R1_FB25_Pos (25U)
3482 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3483 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3484 #define CAN_F3R1_FB26_Pos (26U)
3485 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3486 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3487 #define CAN_F3R1_FB27_Pos (27U)
3488 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3489 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3490 #define CAN_F3R1_FB28_Pos (28U)
3491 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3492 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3493 #define CAN_F3R1_FB29_Pos (29U)
3494 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3495 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3496 #define CAN_F3R1_FB30_Pos (30U)
3497 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3498 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3499 #define CAN_F3R1_FB31_Pos (31U)
3500 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3501 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3502
3503 /******************* Bit definition for CAN_F4R1 register *******************/
3504 #define CAN_F4R1_FB0_Pos (0U)
3505 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3506 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3507 #define CAN_F4R1_FB1_Pos (1U)
3508 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3509 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3510 #define CAN_F4R1_FB2_Pos (2U)
3511 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3512 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3513 #define CAN_F4R1_FB3_Pos (3U)
3514 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3515 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3516 #define CAN_F4R1_FB4_Pos (4U)
3517 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3518 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3519 #define CAN_F4R1_FB5_Pos (5U)
3520 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3521 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3522 #define CAN_F4R1_FB6_Pos (6U)
3523 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3524 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3525 #define CAN_F4R1_FB7_Pos (7U)
3526 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3527 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3528 #define CAN_F4R1_FB8_Pos (8U)
3529 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3530 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3531 #define CAN_F4R1_FB9_Pos (9U)
3532 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3533 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3534 #define CAN_F4R1_FB10_Pos (10U)
3535 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3536 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3537 #define CAN_F4R1_FB11_Pos (11U)
3538 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3539 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3540 #define CAN_F4R1_FB12_Pos (12U)
3541 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3542 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3543 #define CAN_F4R1_FB13_Pos (13U)
3544 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3545 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3546 #define CAN_F4R1_FB14_Pos (14U)
3547 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3548 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3549 #define CAN_F4R1_FB15_Pos (15U)
3550 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3551 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3552 #define CAN_F4R1_FB16_Pos (16U)
3553 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3554 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3555 #define CAN_F4R1_FB17_Pos (17U)
3556 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3557 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3558 #define CAN_F4R1_FB18_Pos (18U)
3559 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3560 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3561 #define CAN_F4R1_FB19_Pos (19U)
3562 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3563 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3564 #define CAN_F4R1_FB20_Pos (20U)
3565 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3566 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3567 #define CAN_F4R1_FB21_Pos (21U)
3568 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3569 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3570 #define CAN_F4R1_FB22_Pos (22U)
3571 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3572 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3573 #define CAN_F4R1_FB23_Pos (23U)
3574 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3575 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3576 #define CAN_F4R1_FB24_Pos (24U)
3577 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3578 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3579 #define CAN_F4R1_FB25_Pos (25U)
3580 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3581 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3582 #define CAN_F4R1_FB26_Pos (26U)
3583 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3584 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3585 #define CAN_F4R1_FB27_Pos (27U)
3586 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3587 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3588 #define CAN_F4R1_FB28_Pos (28U)
3589 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3590 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3591 #define CAN_F4R1_FB29_Pos (29U)
3592 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3593 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3594 #define CAN_F4R1_FB30_Pos (30U)
3595 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3596 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3597 #define CAN_F4R1_FB31_Pos (31U)
3598 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3599 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3600
3601 /******************* Bit definition for CAN_F5R1 register *******************/
3602 #define CAN_F5R1_FB0_Pos (0U)
3603 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3604 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3605 #define CAN_F5R1_FB1_Pos (1U)
3606 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3607 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3608 #define CAN_F5R1_FB2_Pos (2U)
3609 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3610 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3611 #define CAN_F5R1_FB3_Pos (3U)
3612 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3613 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3614 #define CAN_F5R1_FB4_Pos (4U)
3615 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3616 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3617 #define CAN_F5R1_FB5_Pos (5U)
3618 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3619 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3620 #define CAN_F5R1_FB6_Pos (6U)
3621 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3622 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3623 #define CAN_F5R1_FB7_Pos (7U)
3624 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3625 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3626 #define CAN_F5R1_FB8_Pos (8U)
3627 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3628 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3629 #define CAN_F5R1_FB9_Pos (9U)
3630 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3631 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3632 #define CAN_F5R1_FB10_Pos (10U)
3633 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3634 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3635 #define CAN_F5R1_FB11_Pos (11U)
3636 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3637 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3638 #define CAN_F5R1_FB12_Pos (12U)
3639 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3640 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3641 #define CAN_F5R1_FB13_Pos (13U)
3642 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3643 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3644 #define CAN_F5R1_FB14_Pos (14U)
3645 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3646 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3647 #define CAN_F5R1_FB15_Pos (15U)
3648 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3649 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3650 #define CAN_F5R1_FB16_Pos (16U)
3651 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3652 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3653 #define CAN_F5R1_FB17_Pos (17U)
3654 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3655 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3656 #define CAN_F5R1_FB18_Pos (18U)
3657 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3658 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3659 #define CAN_F5R1_FB19_Pos (19U)
3660 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3661 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3662 #define CAN_F5R1_FB20_Pos (20U)
3663 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3664 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3665 #define CAN_F5R1_FB21_Pos (21U)
3666 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3667 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3668 #define CAN_F5R1_FB22_Pos (22U)
3669 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3670 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3671 #define CAN_F5R1_FB23_Pos (23U)
3672 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3673 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3674 #define CAN_F5R1_FB24_Pos (24U)
3675 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3676 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3677 #define CAN_F5R1_FB25_Pos (25U)
3678 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3679 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3680 #define CAN_F5R1_FB26_Pos (26U)
3681 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3682 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3683 #define CAN_F5R1_FB27_Pos (27U)
3684 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3685 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3686 #define CAN_F5R1_FB28_Pos (28U)
3687 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3688 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3689 #define CAN_F5R1_FB29_Pos (29U)
3690 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3691 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3692 #define CAN_F5R1_FB30_Pos (30U)
3693 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3694 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3695 #define CAN_F5R1_FB31_Pos (31U)
3696 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3697 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3698
3699 /******************* Bit definition for CAN_F6R1 register *******************/
3700 #define CAN_F6R1_FB0_Pos (0U)
3701 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3702 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3703 #define CAN_F6R1_FB1_Pos (1U)
3704 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3705 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3706 #define CAN_F6R1_FB2_Pos (2U)
3707 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3708 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3709 #define CAN_F6R1_FB3_Pos (3U)
3710 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3711 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3712 #define CAN_F6R1_FB4_Pos (4U)
3713 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3714 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3715 #define CAN_F6R1_FB5_Pos (5U)
3716 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3717 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3718 #define CAN_F6R1_FB6_Pos (6U)
3719 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3720 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3721 #define CAN_F6R1_FB7_Pos (7U)
3722 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3723 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3724 #define CAN_F6R1_FB8_Pos (8U)
3725 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3726 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3727 #define CAN_F6R1_FB9_Pos (9U)
3728 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3729 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3730 #define CAN_F6R1_FB10_Pos (10U)
3731 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3732 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3733 #define CAN_F6R1_FB11_Pos (11U)
3734 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3735 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3736 #define CAN_F6R1_FB12_Pos (12U)
3737 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3738 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3739 #define CAN_F6R1_FB13_Pos (13U)
3740 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3741 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3742 #define CAN_F6R1_FB14_Pos (14U)
3743 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3744 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3745 #define CAN_F6R1_FB15_Pos (15U)
3746 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3747 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3748 #define CAN_F6R1_FB16_Pos (16U)
3749 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3750 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3751 #define CAN_F6R1_FB17_Pos (17U)
3752 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3753 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3754 #define CAN_F6R1_FB18_Pos (18U)
3755 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3756 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3757 #define CAN_F6R1_FB19_Pos (19U)
3758 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3759 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3760 #define CAN_F6R1_FB20_Pos (20U)
3761 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3762 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3763 #define CAN_F6R1_FB21_Pos (21U)
3764 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3765 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3766 #define CAN_F6R1_FB22_Pos (22U)
3767 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3768 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3769 #define CAN_F6R1_FB23_Pos (23U)
3770 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3771 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3772 #define CAN_F6R1_FB24_Pos (24U)
3773 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3774 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3775 #define CAN_F6R1_FB25_Pos (25U)
3776 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3777 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3778 #define CAN_F6R1_FB26_Pos (26U)
3779 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3780 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3781 #define CAN_F6R1_FB27_Pos (27U)
3782 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3783 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3784 #define CAN_F6R1_FB28_Pos (28U)
3785 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3786 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3787 #define CAN_F6R1_FB29_Pos (29U)
3788 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3789 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3790 #define CAN_F6R1_FB30_Pos (30U)
3791 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3792 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3793 #define CAN_F6R1_FB31_Pos (31U)
3794 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3795 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3796
3797 /******************* Bit definition for CAN_F7R1 register *******************/
3798 #define CAN_F7R1_FB0_Pos (0U)
3799 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3800 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3801 #define CAN_F7R1_FB1_Pos (1U)
3802 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3803 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3804 #define CAN_F7R1_FB2_Pos (2U)
3805 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3806 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3807 #define CAN_F7R1_FB3_Pos (3U)
3808 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3809 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3810 #define CAN_F7R1_FB4_Pos (4U)
3811 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3812 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3813 #define CAN_F7R1_FB5_Pos (5U)
3814 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3815 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3816 #define CAN_F7R1_FB6_Pos (6U)
3817 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3818 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3819 #define CAN_F7R1_FB7_Pos (7U)
3820 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3821 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3822 #define CAN_F7R1_FB8_Pos (8U)
3823 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3824 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3825 #define CAN_F7R1_FB9_Pos (9U)
3826 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3827 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3828 #define CAN_F7R1_FB10_Pos (10U)
3829 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3830 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3831 #define CAN_F7R1_FB11_Pos (11U)
3832 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3833 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3834 #define CAN_F7R1_FB12_Pos (12U)
3835 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3836 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3837 #define CAN_F7R1_FB13_Pos (13U)
3838 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3839 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3840 #define CAN_F7R1_FB14_Pos (14U)
3841 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3842 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3843 #define CAN_F7R1_FB15_Pos (15U)
3844 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3845 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3846 #define CAN_F7R1_FB16_Pos (16U)
3847 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3848 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3849 #define CAN_F7R1_FB17_Pos (17U)
3850 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3851 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3852 #define CAN_F7R1_FB18_Pos (18U)
3853 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3854 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3855 #define CAN_F7R1_FB19_Pos (19U)
3856 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3857 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3858 #define CAN_F7R1_FB20_Pos (20U)
3859 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3860 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3861 #define CAN_F7R1_FB21_Pos (21U)
3862 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3863 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3864 #define CAN_F7R1_FB22_Pos (22U)
3865 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3866 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3867 #define CAN_F7R1_FB23_Pos (23U)
3868 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3869 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3870 #define CAN_F7R1_FB24_Pos (24U)
3871 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3872 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3873 #define CAN_F7R1_FB25_Pos (25U)
3874 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3875 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3876 #define CAN_F7R1_FB26_Pos (26U)
3877 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3878 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3879 #define CAN_F7R1_FB27_Pos (27U)
3880 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3881 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3882 #define CAN_F7R1_FB28_Pos (28U)
3883 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3884 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3885 #define CAN_F7R1_FB29_Pos (29U)
3886 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3887 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3888 #define CAN_F7R1_FB30_Pos (30U)
3889 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3890 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3891 #define CAN_F7R1_FB31_Pos (31U)
3892 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3893 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3894
3895 /******************* Bit definition for CAN_F8R1 register *******************/
3896 #define CAN_F8R1_FB0_Pos (0U)
3897 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3898 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3899 #define CAN_F8R1_FB1_Pos (1U)
3900 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3901 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3902 #define CAN_F8R1_FB2_Pos (2U)
3903 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3904 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3905 #define CAN_F8R1_FB3_Pos (3U)
3906 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3907 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3908 #define CAN_F8R1_FB4_Pos (4U)
3909 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3910 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3911 #define CAN_F8R1_FB5_Pos (5U)
3912 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3913 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3914 #define CAN_F8R1_FB6_Pos (6U)
3915 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3916 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3917 #define CAN_F8R1_FB7_Pos (7U)
3918 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3919 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3920 #define CAN_F8R1_FB8_Pos (8U)
3921 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3922 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3923 #define CAN_F8R1_FB9_Pos (9U)
3924 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3925 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3926 #define CAN_F8R1_FB10_Pos (10U)
3927 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3928 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3929 #define CAN_F8R1_FB11_Pos (11U)
3930 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3931 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3932 #define CAN_F8R1_FB12_Pos (12U)
3933 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3934 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3935 #define CAN_F8R1_FB13_Pos (13U)
3936 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3937 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3938 #define CAN_F8R1_FB14_Pos (14U)
3939 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3940 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3941 #define CAN_F8R1_FB15_Pos (15U)
3942 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3943 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3944 #define CAN_F8R1_FB16_Pos (16U)
3945 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3946 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3947 #define CAN_F8R1_FB17_Pos (17U)
3948 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3949 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3950 #define CAN_F8R1_FB18_Pos (18U)
3951 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3952 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3953 #define CAN_F8R1_FB19_Pos (19U)
3954 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3955 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3956 #define CAN_F8R1_FB20_Pos (20U)
3957 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3958 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3959 #define CAN_F8R1_FB21_Pos (21U)
3960 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3961 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3962 #define CAN_F8R1_FB22_Pos (22U)
3963 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3964 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3965 #define CAN_F8R1_FB23_Pos (23U)
3966 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3967 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3968 #define CAN_F8R1_FB24_Pos (24U)
3969 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3970 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3971 #define CAN_F8R1_FB25_Pos (25U)
3972 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3973 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3974 #define CAN_F8R1_FB26_Pos (26U)
3975 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3976 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3977 #define CAN_F8R1_FB27_Pos (27U)
3978 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3979 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3980 #define CAN_F8R1_FB28_Pos (28U)
3981 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3982 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3983 #define CAN_F8R1_FB29_Pos (29U)
3984 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3985 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3986 #define CAN_F8R1_FB30_Pos (30U)
3987 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3988 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3989 #define CAN_F8R1_FB31_Pos (31U)
3990 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3991 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3992
3993 /******************* Bit definition for CAN_F9R1 register *******************/
3994 #define CAN_F9R1_FB0_Pos (0U)
3995 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3996 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3997 #define CAN_F9R1_FB1_Pos (1U)
3998 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3999 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
4000 #define CAN_F9R1_FB2_Pos (2U)
4001 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
4002 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
4003 #define CAN_F9R1_FB3_Pos (3U)
4004 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
4005 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
4006 #define CAN_F9R1_FB4_Pos (4U)
4007 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
4008 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
4009 #define CAN_F9R1_FB5_Pos (5U)
4010 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
4011 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
4012 #define CAN_F9R1_FB6_Pos (6U)
4013 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
4014 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
4015 #define CAN_F9R1_FB7_Pos (7U)
4016 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
4017 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
4018 #define CAN_F9R1_FB8_Pos (8U)
4019 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
4020 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
4021 #define CAN_F9R1_FB9_Pos (9U)
4022 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
4023 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
4024 #define CAN_F9R1_FB10_Pos (10U)
4025 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
4026 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
4027 #define CAN_F9R1_FB11_Pos (11U)
4028 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
4029 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
4030 #define CAN_F9R1_FB12_Pos (12U)
4031 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
4032 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
4033 #define CAN_F9R1_FB13_Pos (13U)
4034 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
4035 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
4036 #define CAN_F9R1_FB14_Pos (14U)
4037 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
4038 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
4039 #define CAN_F9R1_FB15_Pos (15U)
4040 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
4041 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
4042 #define CAN_F9R1_FB16_Pos (16U)
4043 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
4044 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
4045 #define CAN_F9R1_FB17_Pos (17U)
4046 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
4047 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
4048 #define CAN_F9R1_FB18_Pos (18U)
4049 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
4050 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
4051 #define CAN_F9R1_FB19_Pos (19U)
4052 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
4053 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
4054 #define CAN_F9R1_FB20_Pos (20U)
4055 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
4056 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
4057 #define CAN_F9R1_FB21_Pos (21U)
4058 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
4059 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
4060 #define CAN_F9R1_FB22_Pos (22U)
4061 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
4062 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
4063 #define CAN_F9R1_FB23_Pos (23U)
4064 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
4065 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
4066 #define CAN_F9R1_FB24_Pos (24U)
4067 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
4068 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
4069 #define CAN_F9R1_FB25_Pos (25U)
4070 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
4071 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
4072 #define CAN_F9R1_FB26_Pos (26U)
4073 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
4074 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
4075 #define CAN_F9R1_FB27_Pos (27U)
4076 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
4077 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
4078 #define CAN_F9R1_FB28_Pos (28U)
4079 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
4080 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
4081 #define CAN_F9R1_FB29_Pos (29U)
4082 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
4083 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
4084 #define CAN_F9R1_FB30_Pos (30U)
4085 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
4086 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
4087 #define CAN_F9R1_FB31_Pos (31U)
4088 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
4089 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
4090
4091 /******************* Bit definition for CAN_F10R1 register ******************/
4092 #define CAN_F10R1_FB0_Pos (0U)
4093 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
4094 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
4095 #define CAN_F10R1_FB1_Pos (1U)
4096 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
4097 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
4098 #define CAN_F10R1_FB2_Pos (2U)
4099 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
4100 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
4101 #define CAN_F10R1_FB3_Pos (3U)
4102 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
4103 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
4104 #define CAN_F10R1_FB4_Pos (4U)
4105 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
4106 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
4107 #define CAN_F10R1_FB5_Pos (5U)
4108 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
4109 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
4110 #define CAN_F10R1_FB6_Pos (6U)
4111 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
4112 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
4113 #define CAN_F10R1_FB7_Pos (7U)
4114 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
4115 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
4116 #define CAN_F10R1_FB8_Pos (8U)
4117 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
4118 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
4119 #define CAN_F10R1_FB9_Pos (9U)
4120 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
4121 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
4122 #define CAN_F10R1_FB10_Pos (10U)
4123 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
4124 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
4125 #define CAN_F10R1_FB11_Pos (11U)
4126 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
4127 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
4128 #define CAN_F10R1_FB12_Pos (12U)
4129 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
4130 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
4131 #define CAN_F10R1_FB13_Pos (13U)
4132 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
4133 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
4134 #define CAN_F10R1_FB14_Pos (14U)
4135 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
4136 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
4137 #define CAN_F10R1_FB15_Pos (15U)
4138 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
4139 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
4140 #define CAN_F10R1_FB16_Pos (16U)
4141 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
4142 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
4143 #define CAN_F10R1_FB17_Pos (17U)
4144 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
4145 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
4146 #define CAN_F10R1_FB18_Pos (18U)
4147 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
4148 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
4149 #define CAN_F10R1_FB19_Pos (19U)
4150 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
4151 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
4152 #define CAN_F10R1_FB20_Pos (20U)
4153 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
4154 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
4155 #define CAN_F10R1_FB21_Pos (21U)
4156 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
4157 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
4158 #define CAN_F10R1_FB22_Pos (22U)
4159 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
4160 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
4161 #define CAN_F10R1_FB23_Pos (23U)
4162 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
4163 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
4164 #define CAN_F10R1_FB24_Pos (24U)
4165 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
4166 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
4167 #define CAN_F10R1_FB25_Pos (25U)
4168 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
4169 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
4170 #define CAN_F10R1_FB26_Pos (26U)
4171 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
4172 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
4173 #define CAN_F10R1_FB27_Pos (27U)
4174 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
4175 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
4176 #define CAN_F10R1_FB28_Pos (28U)
4177 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
4178 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
4179 #define CAN_F10R1_FB29_Pos (29U)
4180 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
4181 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
4182 #define CAN_F10R1_FB30_Pos (30U)
4183 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4184 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4185 #define CAN_F10R1_FB31_Pos (31U)
4186 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4187 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4188
4189 /******************* Bit definition for CAN_F11R1 register ******************/
4190 #define CAN_F11R1_FB0_Pos (0U)
4191 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4192 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4193 #define CAN_F11R1_FB1_Pos (1U)
4194 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4195 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4196 #define CAN_F11R1_FB2_Pos (2U)
4197 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4198 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4199 #define CAN_F11R1_FB3_Pos (3U)
4200 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4201 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4202 #define CAN_F11R1_FB4_Pos (4U)
4203 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4204 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4205 #define CAN_F11R1_FB5_Pos (5U)
4206 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4207 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4208 #define CAN_F11R1_FB6_Pos (6U)
4209 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4210 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4211 #define CAN_F11R1_FB7_Pos (7U)
4212 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4213 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4214 #define CAN_F11R1_FB8_Pos (8U)
4215 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4216 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4217 #define CAN_F11R1_FB9_Pos (9U)
4218 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4219 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4220 #define CAN_F11R1_FB10_Pos (10U)
4221 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4222 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4223 #define CAN_F11R1_FB11_Pos (11U)
4224 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4225 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4226 #define CAN_F11R1_FB12_Pos (12U)
4227 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4228 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4229 #define CAN_F11R1_FB13_Pos (13U)
4230 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4231 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4232 #define CAN_F11R1_FB14_Pos (14U)
4233 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4234 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4235 #define CAN_F11R1_FB15_Pos (15U)
4236 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4237 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4238 #define CAN_F11R1_FB16_Pos (16U)
4239 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4240 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4241 #define CAN_F11R1_FB17_Pos (17U)
4242 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4243 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4244 #define CAN_F11R1_FB18_Pos (18U)
4245 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4246 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4247 #define CAN_F11R1_FB19_Pos (19U)
4248 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4249 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4250 #define CAN_F11R1_FB20_Pos (20U)
4251 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4252 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4253 #define CAN_F11R1_FB21_Pos (21U)
4254 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4255 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4256 #define CAN_F11R1_FB22_Pos (22U)
4257 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4258 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4259 #define CAN_F11R1_FB23_Pos (23U)
4260 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4261 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4262 #define CAN_F11R1_FB24_Pos (24U)
4263 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4264 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4265 #define CAN_F11R1_FB25_Pos (25U)
4266 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4267 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4268 #define CAN_F11R1_FB26_Pos (26U)
4269 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4270 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4271 #define CAN_F11R1_FB27_Pos (27U)
4272 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4273 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4274 #define CAN_F11R1_FB28_Pos (28U)
4275 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4276 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4277 #define CAN_F11R1_FB29_Pos (29U)
4278 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4279 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4280 #define CAN_F11R1_FB30_Pos (30U)
4281 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4282 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4283 #define CAN_F11R1_FB31_Pos (31U)
4284 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4285 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4286
4287 /******************* Bit definition for CAN_F12R1 register ******************/
4288 #define CAN_F12R1_FB0_Pos (0U)
4289 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4290 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4291 #define CAN_F12R1_FB1_Pos (1U)
4292 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4293 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4294 #define CAN_F12R1_FB2_Pos (2U)
4295 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4296 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4297 #define CAN_F12R1_FB3_Pos (3U)
4298 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4299 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4300 #define CAN_F12R1_FB4_Pos (4U)
4301 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4302 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4303 #define CAN_F12R1_FB5_Pos (5U)
4304 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4305 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4306 #define CAN_F12R1_FB6_Pos (6U)
4307 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4308 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4309 #define CAN_F12R1_FB7_Pos (7U)
4310 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4311 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4312 #define CAN_F12R1_FB8_Pos (8U)
4313 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4314 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4315 #define CAN_F12R1_FB9_Pos (9U)
4316 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4317 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4318 #define CAN_F12R1_FB10_Pos (10U)
4319 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4320 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4321 #define CAN_F12R1_FB11_Pos (11U)
4322 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4323 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4324 #define CAN_F12R1_FB12_Pos (12U)
4325 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4326 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4327 #define CAN_F12R1_FB13_Pos (13U)
4328 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4329 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4330 #define CAN_F12R1_FB14_Pos (14U)
4331 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4332 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4333 #define CAN_F12R1_FB15_Pos (15U)
4334 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4335 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4336 #define CAN_F12R1_FB16_Pos (16U)
4337 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4338 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4339 #define CAN_F12R1_FB17_Pos (17U)
4340 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4341 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4342 #define CAN_F12R1_FB18_Pos (18U)
4343 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4344 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4345 #define CAN_F12R1_FB19_Pos (19U)
4346 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4347 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4348 #define CAN_F12R1_FB20_Pos (20U)
4349 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4350 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4351 #define CAN_F12R1_FB21_Pos (21U)
4352 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4353 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4354 #define CAN_F12R1_FB22_Pos (22U)
4355 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4356 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4357 #define CAN_F12R1_FB23_Pos (23U)
4358 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4359 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4360 #define CAN_F12R1_FB24_Pos (24U)
4361 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4362 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4363 #define CAN_F12R1_FB25_Pos (25U)
4364 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4365 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4366 #define CAN_F12R1_FB26_Pos (26U)
4367 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4368 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4369 #define CAN_F12R1_FB27_Pos (27U)
4370 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4371 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4372 #define CAN_F12R1_FB28_Pos (28U)
4373 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4374 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4375 #define CAN_F12R1_FB29_Pos (29U)
4376 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4377 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4378 #define CAN_F12R1_FB30_Pos (30U)
4379 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4380 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4381 #define CAN_F12R1_FB31_Pos (31U)
4382 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4383 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4384
4385 /******************* Bit definition for CAN_F13R1 register ******************/
4386 #define CAN_F13R1_FB0_Pos (0U)
4387 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4388 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4389 #define CAN_F13R1_FB1_Pos (1U)
4390 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4391 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4392 #define CAN_F13R1_FB2_Pos (2U)
4393 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4394 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4395 #define CAN_F13R1_FB3_Pos (3U)
4396 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4397 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4398 #define CAN_F13R1_FB4_Pos (4U)
4399 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4400 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4401 #define CAN_F13R1_FB5_Pos (5U)
4402 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4403 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4404 #define CAN_F13R1_FB6_Pos (6U)
4405 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4406 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4407 #define CAN_F13R1_FB7_Pos (7U)
4408 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4409 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4410 #define CAN_F13R1_FB8_Pos (8U)
4411 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4412 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4413 #define CAN_F13R1_FB9_Pos (9U)
4414 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4415 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4416 #define CAN_F13R1_FB10_Pos (10U)
4417 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4418 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4419 #define CAN_F13R1_FB11_Pos (11U)
4420 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4421 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4422 #define CAN_F13R1_FB12_Pos (12U)
4423 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4424 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4425 #define CAN_F13R1_FB13_Pos (13U)
4426 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4427 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4428 #define CAN_F13R1_FB14_Pos (14U)
4429 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4430 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4431 #define CAN_F13R1_FB15_Pos (15U)
4432 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4433 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4434 #define CAN_F13R1_FB16_Pos (16U)
4435 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4436 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4437 #define CAN_F13R1_FB17_Pos (17U)
4438 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4439 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4440 #define CAN_F13R1_FB18_Pos (18U)
4441 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4442 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4443 #define CAN_F13R1_FB19_Pos (19U)
4444 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4445 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4446 #define CAN_F13R1_FB20_Pos (20U)
4447 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4448 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4449 #define CAN_F13R1_FB21_Pos (21U)
4450 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4451 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4452 #define CAN_F13R1_FB22_Pos (22U)
4453 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4454 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4455 #define CAN_F13R1_FB23_Pos (23U)
4456 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4457 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4458 #define CAN_F13R1_FB24_Pos (24U)
4459 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4460 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4461 #define CAN_F13R1_FB25_Pos (25U)
4462 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4463 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4464 #define CAN_F13R1_FB26_Pos (26U)
4465 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4466 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4467 #define CAN_F13R1_FB27_Pos (27U)
4468 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4469 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4470 #define CAN_F13R1_FB28_Pos (28U)
4471 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4472 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4473 #define CAN_F13R1_FB29_Pos (29U)
4474 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4475 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4476 #define CAN_F13R1_FB30_Pos (30U)
4477 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4478 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4479 #define CAN_F13R1_FB31_Pos (31U)
4480 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4481 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4482
4483 /******************* Bit definition for CAN_F0R2 register *******************/
4484 #define CAN_F0R2_FB0_Pos (0U)
4485 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4486 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4487 #define CAN_F0R2_FB1_Pos (1U)
4488 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4489 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4490 #define CAN_F0R2_FB2_Pos (2U)
4491 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4492 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4493 #define CAN_F0R2_FB3_Pos (3U)
4494 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4495 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4496 #define CAN_F0R2_FB4_Pos (4U)
4497 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4498 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4499 #define CAN_F0R2_FB5_Pos (5U)
4500 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4501 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4502 #define CAN_F0R2_FB6_Pos (6U)
4503 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4504 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4505 #define CAN_F0R2_FB7_Pos (7U)
4506 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4507 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4508 #define CAN_F0R2_FB8_Pos (8U)
4509 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4510 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4511 #define CAN_F0R2_FB9_Pos (9U)
4512 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4513 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4514 #define CAN_F0R2_FB10_Pos (10U)
4515 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4516 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4517 #define CAN_F0R2_FB11_Pos (11U)
4518 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4519 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4520 #define CAN_F0R2_FB12_Pos (12U)
4521 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4522 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4523 #define CAN_F0R2_FB13_Pos (13U)
4524 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4525 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4526 #define CAN_F0R2_FB14_Pos (14U)
4527 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4528 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4529 #define CAN_F0R2_FB15_Pos (15U)
4530 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4531 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4532 #define CAN_F0R2_FB16_Pos (16U)
4533 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4534 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4535 #define CAN_F0R2_FB17_Pos (17U)
4536 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4537 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4538 #define CAN_F0R2_FB18_Pos (18U)
4539 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4540 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4541 #define CAN_F0R2_FB19_Pos (19U)
4542 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4543 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4544 #define CAN_F0R2_FB20_Pos (20U)
4545 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4546 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4547 #define CAN_F0R2_FB21_Pos (21U)
4548 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4549 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4550 #define CAN_F0R2_FB22_Pos (22U)
4551 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4552 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4553 #define CAN_F0R2_FB23_Pos (23U)
4554 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4555 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4556 #define CAN_F0R2_FB24_Pos (24U)
4557 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4558 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4559 #define CAN_F0R2_FB25_Pos (25U)
4560 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4561 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4562 #define CAN_F0R2_FB26_Pos (26U)
4563 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4564 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4565 #define CAN_F0R2_FB27_Pos (27U)
4566 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4567 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4568 #define CAN_F0R2_FB28_Pos (28U)
4569 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4570 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4571 #define CAN_F0R2_FB29_Pos (29U)
4572 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4573 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4574 #define CAN_F0R2_FB30_Pos (30U)
4575 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4576 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4577 #define CAN_F0R2_FB31_Pos (31U)
4578 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4579 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4580
4581 /******************* Bit definition for CAN_F1R2 register *******************/
4582 #define CAN_F1R2_FB0_Pos (0U)
4583 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4584 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4585 #define CAN_F1R2_FB1_Pos (1U)
4586 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4587 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4588 #define CAN_F1R2_FB2_Pos (2U)
4589 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4590 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4591 #define CAN_F1R2_FB3_Pos (3U)
4592 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4593 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4594 #define CAN_F1R2_FB4_Pos (4U)
4595 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4596 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4597 #define CAN_F1R2_FB5_Pos (5U)
4598 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4599 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4600 #define CAN_F1R2_FB6_Pos (6U)
4601 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4602 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4603 #define CAN_F1R2_FB7_Pos (7U)
4604 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4605 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4606 #define CAN_F1R2_FB8_Pos (8U)
4607 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4608 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4609 #define CAN_F1R2_FB9_Pos (9U)
4610 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4611 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4612 #define CAN_F1R2_FB10_Pos (10U)
4613 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4614 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4615 #define CAN_F1R2_FB11_Pos (11U)
4616 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4617 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4618 #define CAN_F1R2_FB12_Pos (12U)
4619 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4620 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4621 #define CAN_F1R2_FB13_Pos (13U)
4622 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4623 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4624 #define CAN_F1R2_FB14_Pos (14U)
4625 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4626 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4627 #define CAN_F1R2_FB15_Pos (15U)
4628 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4629 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4630 #define CAN_F1R2_FB16_Pos (16U)
4631 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4632 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4633 #define CAN_F1R2_FB17_Pos (17U)
4634 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4635 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4636 #define CAN_F1R2_FB18_Pos (18U)
4637 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4638 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4639 #define CAN_F1R2_FB19_Pos (19U)
4640 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4641 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4642 #define CAN_F1R2_FB20_Pos (20U)
4643 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4644 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4645 #define CAN_F1R2_FB21_Pos (21U)
4646 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4647 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4648 #define CAN_F1R2_FB22_Pos (22U)
4649 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4650 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4651 #define CAN_F1R2_FB23_Pos (23U)
4652 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4653 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4654 #define CAN_F1R2_FB24_Pos (24U)
4655 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4656 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4657 #define CAN_F1R2_FB25_Pos (25U)
4658 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4659 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4660 #define CAN_F1R2_FB26_Pos (26U)
4661 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4662 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4663 #define CAN_F1R2_FB27_Pos (27U)
4664 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4665 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4666 #define CAN_F1R2_FB28_Pos (28U)
4667 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4668 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4669 #define CAN_F1R2_FB29_Pos (29U)
4670 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4671 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4672 #define CAN_F1R2_FB30_Pos (30U)
4673 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4674 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4675 #define CAN_F1R2_FB31_Pos (31U)
4676 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4677 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4678
4679 /******************* Bit definition for CAN_F2R2 register *******************/
4680 #define CAN_F2R2_FB0_Pos (0U)
4681 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4682 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4683 #define CAN_F2R2_FB1_Pos (1U)
4684 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4685 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4686 #define CAN_F2R2_FB2_Pos (2U)
4687 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4688 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4689 #define CAN_F2R2_FB3_Pos (3U)
4690 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4691 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4692 #define CAN_F2R2_FB4_Pos (4U)
4693 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4694 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4695 #define CAN_F2R2_FB5_Pos (5U)
4696 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4697 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4698 #define CAN_F2R2_FB6_Pos (6U)
4699 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4700 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4701 #define CAN_F2R2_FB7_Pos (7U)
4702 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4703 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4704 #define CAN_F2R2_FB8_Pos (8U)
4705 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4706 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4707 #define CAN_F2R2_FB9_Pos (9U)
4708 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4709 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4710 #define CAN_F2R2_FB10_Pos (10U)
4711 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4712 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4713 #define CAN_F2R2_FB11_Pos (11U)
4714 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4715 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4716 #define CAN_F2R2_FB12_Pos (12U)
4717 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4718 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4719 #define CAN_F2R2_FB13_Pos (13U)
4720 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4721 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4722 #define CAN_F2R2_FB14_Pos (14U)
4723 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4724 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4725 #define CAN_F2R2_FB15_Pos (15U)
4726 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4727 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4728 #define CAN_F2R2_FB16_Pos (16U)
4729 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4730 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4731 #define CAN_F2R2_FB17_Pos (17U)
4732 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4733 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4734 #define CAN_F2R2_FB18_Pos (18U)
4735 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4736 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4737 #define CAN_F2R2_FB19_Pos (19U)
4738 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4739 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4740 #define CAN_F2R2_FB20_Pos (20U)
4741 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4742 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4743 #define CAN_F2R2_FB21_Pos (21U)
4744 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4745 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4746 #define CAN_F2R2_FB22_Pos (22U)
4747 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4748 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4749 #define CAN_F2R2_FB23_Pos (23U)
4750 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4751 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4752 #define CAN_F2R2_FB24_Pos (24U)
4753 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4754 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4755 #define CAN_F2R2_FB25_Pos (25U)
4756 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4757 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4758 #define CAN_F2R2_FB26_Pos (26U)
4759 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4760 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4761 #define CAN_F2R2_FB27_Pos (27U)
4762 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4763 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4764 #define CAN_F2R2_FB28_Pos (28U)
4765 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4766 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4767 #define CAN_F2R2_FB29_Pos (29U)
4768 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4769 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4770 #define CAN_F2R2_FB30_Pos (30U)
4771 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4772 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4773 #define CAN_F2R2_FB31_Pos (31U)
4774 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4775 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4776
4777 /******************* Bit definition for CAN_F3R2 register *******************/
4778 #define CAN_F3R2_FB0_Pos (0U)
4779 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4780 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4781 #define CAN_F3R2_FB1_Pos (1U)
4782 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4783 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4784 #define CAN_F3R2_FB2_Pos (2U)
4785 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4786 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4787 #define CAN_F3R2_FB3_Pos (3U)
4788 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4789 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4790 #define CAN_F3R2_FB4_Pos (4U)
4791 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4792 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4793 #define CAN_F3R2_FB5_Pos (5U)
4794 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4795 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4796 #define CAN_F3R2_FB6_Pos (6U)
4797 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4798 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4799 #define CAN_F3R2_FB7_Pos (7U)
4800 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4801 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4802 #define CAN_F3R2_FB8_Pos (8U)
4803 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4804 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4805 #define CAN_F3R2_FB9_Pos (9U)
4806 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4807 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4808 #define CAN_F3R2_FB10_Pos (10U)
4809 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4810 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4811 #define CAN_F3R2_FB11_Pos (11U)
4812 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4813 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4814 #define CAN_F3R2_FB12_Pos (12U)
4815 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4816 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4817 #define CAN_F3R2_FB13_Pos (13U)
4818 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4819 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4820 #define CAN_F3R2_FB14_Pos (14U)
4821 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4822 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4823 #define CAN_F3R2_FB15_Pos (15U)
4824 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4825 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4826 #define CAN_F3R2_FB16_Pos (16U)
4827 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4828 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4829 #define CAN_F3R2_FB17_Pos (17U)
4830 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4831 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4832 #define CAN_F3R2_FB18_Pos (18U)
4833 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4834 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4835 #define CAN_F3R2_FB19_Pos (19U)
4836 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4837 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4838 #define CAN_F3R2_FB20_Pos (20U)
4839 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4840 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4841 #define CAN_F3R2_FB21_Pos (21U)
4842 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4843 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4844 #define CAN_F3R2_FB22_Pos (22U)
4845 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4846 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4847 #define CAN_F3R2_FB23_Pos (23U)
4848 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4849 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4850 #define CAN_F3R2_FB24_Pos (24U)
4851 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4852 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4853 #define CAN_F3R2_FB25_Pos (25U)
4854 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4855 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4856 #define CAN_F3R2_FB26_Pos (26U)
4857 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4858 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4859 #define CAN_F3R2_FB27_Pos (27U)
4860 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4861 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4862 #define CAN_F3R2_FB28_Pos (28U)
4863 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4864 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4865 #define CAN_F3R2_FB29_Pos (29U)
4866 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4867 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4868 #define CAN_F3R2_FB30_Pos (30U)
4869 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4870 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4871 #define CAN_F3R2_FB31_Pos (31U)
4872 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4873 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4874
4875 /******************* Bit definition for CAN_F4R2 register *******************/
4876 #define CAN_F4R2_FB0_Pos (0U)
4877 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4878 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4879 #define CAN_F4R2_FB1_Pos (1U)
4880 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4881 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4882 #define CAN_F4R2_FB2_Pos (2U)
4883 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4884 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4885 #define CAN_F4R2_FB3_Pos (3U)
4886 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4887 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4888 #define CAN_F4R2_FB4_Pos (4U)
4889 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4890 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4891 #define CAN_F4R2_FB5_Pos (5U)
4892 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4893 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4894 #define CAN_F4R2_FB6_Pos (6U)
4895 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4896 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4897 #define CAN_F4R2_FB7_Pos (7U)
4898 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4899 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4900 #define CAN_F4R2_FB8_Pos (8U)
4901 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4902 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4903 #define CAN_F4R2_FB9_Pos (9U)
4904 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4905 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4906 #define CAN_F4R2_FB10_Pos (10U)
4907 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4908 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4909 #define CAN_F4R2_FB11_Pos (11U)
4910 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4911 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4912 #define CAN_F4R2_FB12_Pos (12U)
4913 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4914 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4915 #define CAN_F4R2_FB13_Pos (13U)
4916 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4917 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4918 #define CAN_F4R2_FB14_Pos (14U)
4919 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4920 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4921 #define CAN_F4R2_FB15_Pos (15U)
4922 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4923 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4924 #define CAN_F4R2_FB16_Pos (16U)
4925 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4926 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4927 #define CAN_F4R2_FB17_Pos (17U)
4928 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4929 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4930 #define CAN_F4R2_FB18_Pos (18U)
4931 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4932 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4933 #define CAN_F4R2_FB19_Pos (19U)
4934 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4935 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4936 #define CAN_F4R2_FB20_Pos (20U)
4937 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4938 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4939 #define CAN_F4R2_FB21_Pos (21U)
4940 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4941 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4942 #define CAN_F4R2_FB22_Pos (22U)
4943 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4944 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4945 #define CAN_F4R2_FB23_Pos (23U)
4946 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4947 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4948 #define CAN_F4R2_FB24_Pos (24U)
4949 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4950 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4951 #define CAN_F4R2_FB25_Pos (25U)
4952 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4953 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4954 #define CAN_F4R2_FB26_Pos (26U)
4955 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4956 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4957 #define CAN_F4R2_FB27_Pos (27U)
4958 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4959 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4960 #define CAN_F4R2_FB28_Pos (28U)
4961 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4962 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4963 #define CAN_F4R2_FB29_Pos (29U)
4964 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4965 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4966 #define CAN_F4R2_FB30_Pos (30U)
4967 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4968 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4969 #define CAN_F4R2_FB31_Pos (31U)
4970 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4971 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4972
4973 /******************* Bit definition for CAN_F5R2 register *******************/
4974 #define CAN_F5R2_FB0_Pos (0U)
4975 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4976 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4977 #define CAN_F5R2_FB1_Pos (1U)
4978 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4979 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4980 #define CAN_F5R2_FB2_Pos (2U)
4981 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4982 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4983 #define CAN_F5R2_FB3_Pos (3U)
4984 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4985 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4986 #define CAN_F5R2_FB4_Pos (4U)
4987 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4988 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4989 #define CAN_F5R2_FB5_Pos (5U)
4990 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4991 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4992 #define CAN_F5R2_FB6_Pos (6U)
4993 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4994 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4995 #define CAN_F5R2_FB7_Pos (7U)
4996 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4997 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4998 #define CAN_F5R2_FB8_Pos (8U)
4999 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
5000 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
5001 #define CAN_F5R2_FB9_Pos (9U)
5002 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
5003 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
5004 #define CAN_F5R2_FB10_Pos (10U)
5005 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
5006 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
5007 #define CAN_F5R2_FB11_Pos (11U)
5008 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
5009 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
5010 #define CAN_F5R2_FB12_Pos (12U)
5011 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
5012 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
5013 #define CAN_F5R2_FB13_Pos (13U)
5014 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
5015 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
5016 #define CAN_F5R2_FB14_Pos (14U)
5017 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
5018 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
5019 #define CAN_F5R2_FB15_Pos (15U)
5020 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
5021 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
5022 #define CAN_F5R2_FB16_Pos (16U)
5023 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
5024 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
5025 #define CAN_F5R2_FB17_Pos (17U)
5026 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
5027 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
5028 #define CAN_F5R2_FB18_Pos (18U)
5029 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
5030 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
5031 #define CAN_F5R2_FB19_Pos (19U)
5032 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
5033 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
5034 #define CAN_F5R2_FB20_Pos (20U)
5035 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
5036 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
5037 #define CAN_F5R2_FB21_Pos (21U)
5038 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
5039 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
5040 #define CAN_F5R2_FB22_Pos (22U)
5041 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
5042 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
5043 #define CAN_F5R2_FB23_Pos (23U)
5044 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
5045 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
5046 #define CAN_F5R2_FB24_Pos (24U)
5047 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
5048 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
5049 #define CAN_F5R2_FB25_Pos (25U)
5050 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
5051 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
5052 #define CAN_F5R2_FB26_Pos (26U)
5053 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
5054 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
5055 #define CAN_F5R2_FB27_Pos (27U)
5056 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
5057 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
5058 #define CAN_F5R2_FB28_Pos (28U)
5059 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
5060 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
5061 #define CAN_F5R2_FB29_Pos (29U)
5062 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
5063 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
5064 #define CAN_F5R2_FB30_Pos (30U)
5065 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
5066 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
5067 #define CAN_F5R2_FB31_Pos (31U)
5068 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
5069 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
5070
5071 /******************* Bit definition for CAN_F6R2 register *******************/
5072 #define CAN_F6R2_FB0_Pos (0U)
5073 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
5074 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
5075 #define CAN_F6R2_FB1_Pos (1U)
5076 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
5077 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
5078 #define CAN_F6R2_FB2_Pos (2U)
5079 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
5080 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
5081 #define CAN_F6R2_FB3_Pos (3U)
5082 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
5083 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
5084 #define CAN_F6R2_FB4_Pos (4U)
5085 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
5086 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
5087 #define CAN_F6R2_FB5_Pos (5U)
5088 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
5089 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
5090 #define CAN_F6R2_FB6_Pos (6U)
5091 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
5092 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
5093 #define CAN_F6R2_FB7_Pos (7U)
5094 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
5095 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
5096 #define CAN_F6R2_FB8_Pos (8U)
5097 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
5098 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
5099 #define CAN_F6R2_FB9_Pos (9U)
5100 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
5101 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
5102 #define CAN_F6R2_FB10_Pos (10U)
5103 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
5104 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
5105 #define CAN_F6R2_FB11_Pos (11U)
5106 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
5107 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
5108 #define CAN_F6R2_FB12_Pos (12U)
5109 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
5110 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
5111 #define CAN_F6R2_FB13_Pos (13U)
5112 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
5113 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
5114 #define CAN_F6R2_FB14_Pos (14U)
5115 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
5116 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
5117 #define CAN_F6R2_FB15_Pos (15U)
5118 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
5119 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
5120 #define CAN_F6R2_FB16_Pos (16U)
5121 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
5122 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
5123 #define CAN_F6R2_FB17_Pos (17U)
5124 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
5125 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
5126 #define CAN_F6R2_FB18_Pos (18U)
5127 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
5128 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
5129 #define CAN_F6R2_FB19_Pos (19U)
5130 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
5131 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
5132 #define CAN_F6R2_FB20_Pos (20U)
5133 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
5134 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
5135 #define CAN_F6R2_FB21_Pos (21U)
5136 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
5137 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
5138 #define CAN_F6R2_FB22_Pos (22U)
5139 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
5140 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
5141 #define CAN_F6R2_FB23_Pos (23U)
5142 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
5143 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
5144 #define CAN_F6R2_FB24_Pos (24U)
5145 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
5146 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
5147 #define CAN_F6R2_FB25_Pos (25U)
5148 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
5149 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
5150 #define CAN_F6R2_FB26_Pos (26U)
5151 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
5152 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
5153 #define CAN_F6R2_FB27_Pos (27U)
5154 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
5155 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
5156 #define CAN_F6R2_FB28_Pos (28U)
5157 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
5158 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
5159 #define CAN_F6R2_FB29_Pos (29U)
5160 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
5161 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
5162 #define CAN_F6R2_FB30_Pos (30U)
5163 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
5164 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
5165 #define CAN_F6R2_FB31_Pos (31U)
5166 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
5167 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
5168
5169 /******************* Bit definition for CAN_F7R2 register *******************/
5170 #define CAN_F7R2_FB0_Pos (0U)
5171 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
5172 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
5173 #define CAN_F7R2_FB1_Pos (1U)
5174 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
5175 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
5176 #define CAN_F7R2_FB2_Pos (2U)
5177 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
5178 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
5179 #define CAN_F7R2_FB3_Pos (3U)
5180 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
5181 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
5182 #define CAN_F7R2_FB4_Pos (4U)
5183 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5184 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5185 #define CAN_F7R2_FB5_Pos (5U)
5186 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5187 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5188 #define CAN_F7R2_FB6_Pos (6U)
5189 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5190 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5191 #define CAN_F7R2_FB7_Pos (7U)
5192 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5193 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5194 #define CAN_F7R2_FB8_Pos (8U)
5195 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5196 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5197 #define CAN_F7R2_FB9_Pos (9U)
5198 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5199 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5200 #define CAN_F7R2_FB10_Pos (10U)
5201 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5202 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5203 #define CAN_F7R2_FB11_Pos (11U)
5204 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5205 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5206 #define CAN_F7R2_FB12_Pos (12U)
5207 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5208 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5209 #define CAN_F7R2_FB13_Pos (13U)
5210 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5211 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5212 #define CAN_F7R2_FB14_Pos (14U)
5213 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5214 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5215 #define CAN_F7R2_FB15_Pos (15U)
5216 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5217 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5218 #define CAN_F7R2_FB16_Pos (16U)
5219 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5220 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5221 #define CAN_F7R2_FB17_Pos (17U)
5222 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5223 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5224 #define CAN_F7R2_FB18_Pos (18U)
5225 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5226 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5227 #define CAN_F7R2_FB19_Pos (19U)
5228 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5229 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5230 #define CAN_F7R2_FB20_Pos (20U)
5231 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5232 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5233 #define CAN_F7R2_FB21_Pos (21U)
5234 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5235 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5236 #define CAN_F7R2_FB22_Pos (22U)
5237 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5238 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5239 #define CAN_F7R2_FB23_Pos (23U)
5240 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5241 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5242 #define CAN_F7R2_FB24_Pos (24U)
5243 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5244 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5245 #define CAN_F7R2_FB25_Pos (25U)
5246 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5247 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5248 #define CAN_F7R2_FB26_Pos (26U)
5249 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5250 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5251 #define CAN_F7R2_FB27_Pos (27U)
5252 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5253 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5254 #define CAN_F7R2_FB28_Pos (28U)
5255 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5256 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5257 #define CAN_F7R2_FB29_Pos (29U)
5258 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5259 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5260 #define CAN_F7R2_FB30_Pos (30U)
5261 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5262 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5263 #define CAN_F7R2_FB31_Pos (31U)
5264 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5265 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5266
5267 /******************* Bit definition for CAN_F8R2 register *******************/
5268 #define CAN_F8R2_FB0_Pos (0U)
5269 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5270 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5271 #define CAN_F8R2_FB1_Pos (1U)
5272 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5273 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5274 #define CAN_F8R2_FB2_Pos (2U)
5275 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5276 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5277 #define CAN_F8R2_FB3_Pos (3U)
5278 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5279 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5280 #define CAN_F8R2_FB4_Pos (4U)
5281 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5282 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5283 #define CAN_F8R2_FB5_Pos (5U)
5284 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5285 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5286 #define CAN_F8R2_FB6_Pos (6U)
5287 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5288 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5289 #define CAN_F8R2_FB7_Pos (7U)
5290 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5291 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5292 #define CAN_F8R2_FB8_Pos (8U)
5293 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5294 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5295 #define CAN_F8R2_FB9_Pos (9U)
5296 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5297 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5298 #define CAN_F8R2_FB10_Pos (10U)
5299 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5300 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5301 #define CAN_F8R2_FB11_Pos (11U)
5302 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5303 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5304 #define CAN_F8R2_FB12_Pos (12U)
5305 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5306 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5307 #define CAN_F8R2_FB13_Pos (13U)
5308 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5309 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5310 #define CAN_F8R2_FB14_Pos (14U)
5311 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5312 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5313 #define CAN_F8R2_FB15_Pos (15U)
5314 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5315 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5316 #define CAN_F8R2_FB16_Pos (16U)
5317 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5318 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5319 #define CAN_F8R2_FB17_Pos (17U)
5320 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5321 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5322 #define CAN_F8R2_FB18_Pos (18U)
5323 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5324 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5325 #define CAN_F8R2_FB19_Pos (19U)
5326 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5327 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5328 #define CAN_F8R2_FB20_Pos (20U)
5329 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5330 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5331 #define CAN_F8R2_FB21_Pos (21U)
5332 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5333 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5334 #define CAN_F8R2_FB22_Pos (22U)
5335 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5336 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5337 #define CAN_F8R2_FB23_Pos (23U)
5338 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5339 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5340 #define CAN_F8R2_FB24_Pos (24U)
5341 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5342 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5343 #define CAN_F8R2_FB25_Pos (25U)
5344 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5345 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5346 #define CAN_F8R2_FB26_Pos (26U)
5347 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5348 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5349 #define CAN_F8R2_FB27_Pos (27U)
5350 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5351 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5352 #define CAN_F8R2_FB28_Pos (28U)
5353 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5354 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5355 #define CAN_F8R2_FB29_Pos (29U)
5356 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5357 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5358 #define CAN_F8R2_FB30_Pos (30U)
5359 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5360 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5361 #define CAN_F8R2_FB31_Pos (31U)
5362 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5363 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5364
5365 /******************* Bit definition for CAN_F9R2 register *******************/
5366 #define CAN_F9R2_FB0_Pos (0U)
5367 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5368 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5369 #define CAN_F9R2_FB1_Pos (1U)
5370 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5371 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5372 #define CAN_F9R2_FB2_Pos (2U)
5373 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5374 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5375 #define CAN_F9R2_FB3_Pos (3U)
5376 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5377 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5378 #define CAN_F9R2_FB4_Pos (4U)
5379 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5380 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5381 #define CAN_F9R2_FB5_Pos (5U)
5382 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5383 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5384 #define CAN_F9R2_FB6_Pos (6U)
5385 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5386 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5387 #define CAN_F9R2_FB7_Pos (7U)
5388 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5389 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5390 #define CAN_F9R2_FB8_Pos (8U)
5391 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5392 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5393 #define CAN_F9R2_FB9_Pos (9U)
5394 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5395 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5396 #define CAN_F9R2_FB10_Pos (10U)
5397 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5398 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5399 #define CAN_F9R2_FB11_Pos (11U)
5400 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5401 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5402 #define CAN_F9R2_FB12_Pos (12U)
5403 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5404 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5405 #define CAN_F9R2_FB13_Pos (13U)
5406 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5407 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5408 #define CAN_F9R2_FB14_Pos (14U)
5409 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5410 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5411 #define CAN_F9R2_FB15_Pos (15U)
5412 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5413 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5414 #define CAN_F9R2_FB16_Pos (16U)
5415 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5416 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5417 #define CAN_F9R2_FB17_Pos (17U)
5418 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5419 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5420 #define CAN_F9R2_FB18_Pos (18U)
5421 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5422 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5423 #define CAN_F9R2_FB19_Pos (19U)
5424 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5425 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5426 #define CAN_F9R2_FB20_Pos (20U)
5427 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5428 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5429 #define CAN_F9R2_FB21_Pos (21U)
5430 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5431 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5432 #define CAN_F9R2_FB22_Pos (22U)
5433 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5434 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5435 #define CAN_F9R2_FB23_Pos (23U)
5436 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5437 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5438 #define CAN_F9R2_FB24_Pos (24U)
5439 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5440 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5441 #define CAN_F9R2_FB25_Pos (25U)
5442 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5443 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5444 #define CAN_F9R2_FB26_Pos (26U)
5445 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5446 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5447 #define CAN_F9R2_FB27_Pos (27U)
5448 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5449 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5450 #define CAN_F9R2_FB28_Pos (28U)
5451 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5452 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5453 #define CAN_F9R2_FB29_Pos (29U)
5454 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5455 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5456 #define CAN_F9R2_FB30_Pos (30U)
5457 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5458 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5459 #define CAN_F9R2_FB31_Pos (31U)
5460 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5461 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5462
5463 /******************* Bit definition for CAN_F10R2 register ******************/
5464 #define CAN_F10R2_FB0_Pos (0U)
5465 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5466 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5467 #define CAN_F10R2_FB1_Pos (1U)
5468 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5469 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5470 #define CAN_F10R2_FB2_Pos (2U)
5471 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5472 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5473 #define CAN_F10R2_FB3_Pos (3U)
5474 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5475 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5476 #define CAN_F10R2_FB4_Pos (4U)
5477 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5478 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5479 #define CAN_F10R2_FB5_Pos (5U)
5480 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5481 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5482 #define CAN_F10R2_FB6_Pos (6U)
5483 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5484 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5485 #define CAN_F10R2_FB7_Pos (7U)
5486 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5487 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5488 #define CAN_F10R2_FB8_Pos (8U)
5489 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5490 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5491 #define CAN_F10R2_FB9_Pos (9U)
5492 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5493 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5494 #define CAN_F10R2_FB10_Pos (10U)
5495 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5496 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5497 #define CAN_F10R2_FB11_Pos (11U)
5498 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5499 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5500 #define CAN_F10R2_FB12_Pos (12U)
5501 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5502 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5503 #define CAN_F10R2_FB13_Pos (13U)
5504 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5505 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5506 #define CAN_F10R2_FB14_Pos (14U)
5507 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5508 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5509 #define CAN_F10R2_FB15_Pos (15U)
5510 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5511 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5512 #define CAN_F10R2_FB16_Pos (16U)
5513 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5514 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5515 #define CAN_F10R2_FB17_Pos (17U)
5516 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5517 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5518 #define CAN_F10R2_FB18_Pos (18U)
5519 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5520 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5521 #define CAN_F10R2_FB19_Pos (19U)
5522 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5523 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5524 #define CAN_F10R2_FB20_Pos (20U)
5525 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5526 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5527 #define CAN_F10R2_FB21_Pos (21U)
5528 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5529 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5530 #define CAN_F10R2_FB22_Pos (22U)
5531 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5532 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5533 #define CAN_F10R2_FB23_Pos (23U)
5534 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5535 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5536 #define CAN_F10R2_FB24_Pos (24U)
5537 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5538 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5539 #define CAN_F10R2_FB25_Pos (25U)
5540 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5541 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5542 #define CAN_F10R2_FB26_Pos (26U)
5543 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5544 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5545 #define CAN_F10R2_FB27_Pos (27U)
5546 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5547 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5548 #define CAN_F10R2_FB28_Pos (28U)
5549 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5550 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5551 #define CAN_F10R2_FB29_Pos (29U)
5552 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5553 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5554 #define CAN_F10R2_FB30_Pos (30U)
5555 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5556 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5557 #define CAN_F10R2_FB31_Pos (31U)
5558 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5559 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5560
5561 /******************* Bit definition for CAN_F11R2 register ******************/
5562 #define CAN_F11R2_FB0_Pos (0U)
5563 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5564 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5565 #define CAN_F11R2_FB1_Pos (1U)
5566 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5567 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5568 #define CAN_F11R2_FB2_Pos (2U)
5569 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5570 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5571 #define CAN_F11R2_FB3_Pos (3U)
5572 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5573 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5574 #define CAN_F11R2_FB4_Pos (4U)
5575 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5576 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5577 #define CAN_F11R2_FB5_Pos (5U)
5578 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5579 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5580 #define CAN_F11R2_FB6_Pos (6U)
5581 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5582 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5583 #define CAN_F11R2_FB7_Pos (7U)
5584 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5585 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5586 #define CAN_F11R2_FB8_Pos (8U)
5587 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5588 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5589 #define CAN_F11R2_FB9_Pos (9U)
5590 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5591 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5592 #define CAN_F11R2_FB10_Pos (10U)
5593 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5594 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5595 #define CAN_F11R2_FB11_Pos (11U)
5596 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5597 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5598 #define CAN_F11R2_FB12_Pos (12U)
5599 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5600 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5601 #define CAN_F11R2_FB13_Pos (13U)
5602 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5603 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5604 #define CAN_F11R2_FB14_Pos (14U)
5605 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5606 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5607 #define CAN_F11R2_FB15_Pos (15U)
5608 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5609 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5610 #define CAN_F11R2_FB16_Pos (16U)
5611 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5612 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5613 #define CAN_F11R2_FB17_Pos (17U)
5614 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5615 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5616 #define CAN_F11R2_FB18_Pos (18U)
5617 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5618 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5619 #define CAN_F11R2_FB19_Pos (19U)
5620 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5621 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5622 #define CAN_F11R2_FB20_Pos (20U)
5623 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5624 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5625 #define CAN_F11R2_FB21_Pos (21U)
5626 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5627 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5628 #define CAN_F11R2_FB22_Pos (22U)
5629 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5630 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5631 #define CAN_F11R2_FB23_Pos (23U)
5632 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5633 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5634 #define CAN_F11R2_FB24_Pos (24U)
5635 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5636 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5637 #define CAN_F11R2_FB25_Pos (25U)
5638 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5639 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5640 #define CAN_F11R2_FB26_Pos (26U)
5641 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5642 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5643 #define CAN_F11R2_FB27_Pos (27U)
5644 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5645 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5646 #define CAN_F11R2_FB28_Pos (28U)
5647 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5648 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5649 #define CAN_F11R2_FB29_Pos (29U)
5650 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5651 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5652 #define CAN_F11R2_FB30_Pos (30U)
5653 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5654 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5655 #define CAN_F11R2_FB31_Pos (31U)
5656 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5657 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5658
5659 /******************* Bit definition for CAN_F12R2 register ******************/
5660 #define CAN_F12R2_FB0_Pos (0U)
5661 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5662 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5663 #define CAN_F12R2_FB1_Pos (1U)
5664 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5665 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5666 #define CAN_F12R2_FB2_Pos (2U)
5667 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5668 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5669 #define CAN_F12R2_FB3_Pos (3U)
5670 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5671 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5672 #define CAN_F12R2_FB4_Pos (4U)
5673 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5674 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5675 #define CAN_F12R2_FB5_Pos (5U)
5676 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5677 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5678 #define CAN_F12R2_FB6_Pos (6U)
5679 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5680 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5681 #define CAN_F12R2_FB7_Pos (7U)
5682 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5683 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5684 #define CAN_F12R2_FB8_Pos (8U)
5685 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5686 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5687 #define CAN_F12R2_FB9_Pos (9U)
5688 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5689 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5690 #define CAN_F12R2_FB10_Pos (10U)
5691 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5692 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5693 #define CAN_F12R2_FB11_Pos (11U)
5694 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5695 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5696 #define CAN_F12R2_FB12_Pos (12U)
5697 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5698 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5699 #define CAN_F12R2_FB13_Pos (13U)
5700 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5701 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5702 #define CAN_F12R2_FB14_Pos (14U)
5703 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5704 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5705 #define CAN_F12R2_FB15_Pos (15U)
5706 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5707 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5708 #define CAN_F12R2_FB16_Pos (16U)
5709 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5710 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5711 #define CAN_F12R2_FB17_Pos (17U)
5712 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5713 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5714 #define CAN_F12R2_FB18_Pos (18U)
5715 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5716 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5717 #define CAN_F12R2_FB19_Pos (19U)
5718 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5719 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5720 #define CAN_F12R2_FB20_Pos (20U)
5721 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5722 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5723 #define CAN_F12R2_FB21_Pos (21U)
5724 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5725 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5726 #define CAN_F12R2_FB22_Pos (22U)
5727 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5728 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5729 #define CAN_F12R2_FB23_Pos (23U)
5730 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5731 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5732 #define CAN_F12R2_FB24_Pos (24U)
5733 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5734 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5735 #define CAN_F12R2_FB25_Pos (25U)
5736 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5737 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5738 #define CAN_F12R2_FB26_Pos (26U)
5739 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5740 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5741 #define CAN_F12R2_FB27_Pos (27U)
5742 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5743 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5744 #define CAN_F12R2_FB28_Pos (28U)
5745 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5746 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5747 #define CAN_F12R2_FB29_Pos (29U)
5748 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5749 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5750 #define CAN_F12R2_FB30_Pos (30U)
5751 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5752 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5753 #define CAN_F12R2_FB31_Pos (31U)
5754 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5755 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5756
5757 /******************* Bit definition for CAN_F13R2 register ******************/
5758 #define CAN_F13R2_FB0_Pos (0U)
5759 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5760 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5761 #define CAN_F13R2_FB1_Pos (1U)
5762 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5763 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5764 #define CAN_F13R2_FB2_Pos (2U)
5765 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5766 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5767 #define CAN_F13R2_FB3_Pos (3U)
5768 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5769 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5770 #define CAN_F13R2_FB4_Pos (4U)
5771 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5772 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5773 #define CAN_F13R2_FB5_Pos (5U)
5774 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5775 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5776 #define CAN_F13R2_FB6_Pos (6U)
5777 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5778 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5779 #define CAN_F13R2_FB7_Pos (7U)
5780 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5781 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5782 #define CAN_F13R2_FB8_Pos (8U)
5783 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5784 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5785 #define CAN_F13R2_FB9_Pos (9U)
5786 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5787 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5788 #define CAN_F13R2_FB10_Pos (10U)
5789 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5790 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5791 #define CAN_F13R2_FB11_Pos (11U)
5792 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5793 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5794 #define CAN_F13R2_FB12_Pos (12U)
5795 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5796 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5797 #define CAN_F13R2_FB13_Pos (13U)
5798 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5799 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5800 #define CAN_F13R2_FB14_Pos (14U)
5801 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5802 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5803 #define CAN_F13R2_FB15_Pos (15U)
5804 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5805 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5806 #define CAN_F13R2_FB16_Pos (16U)
5807 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5808 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5809 #define CAN_F13R2_FB17_Pos (17U)
5810 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5811 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5812 #define CAN_F13R2_FB18_Pos (18U)
5813 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5814 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5815 #define CAN_F13R2_FB19_Pos (19U)
5816 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5817 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5818 #define CAN_F13R2_FB20_Pos (20U)
5819 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5820 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5821 #define CAN_F13R2_FB21_Pos (21U)
5822 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5823 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5824 #define CAN_F13R2_FB22_Pos (22U)
5825 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5826 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5827 #define CAN_F13R2_FB23_Pos (23U)
5828 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5829 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5830 #define CAN_F13R2_FB24_Pos (24U)
5831 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5832 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5833 #define CAN_F13R2_FB25_Pos (25U)
5834 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5835 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5836 #define CAN_F13R2_FB26_Pos (26U)
5837 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5838 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5839 #define CAN_F13R2_FB27_Pos (27U)
5840 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5841 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5842 #define CAN_F13R2_FB28_Pos (28U)
5843 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5844 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5845 #define CAN_F13R2_FB29_Pos (29U)
5846 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5847 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5848 #define CAN_F13R2_FB30_Pos (30U)
5849 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5850 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5851 #define CAN_F13R2_FB31_Pos (31U)
5852 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5853 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5854
5855 /******************************************************************************/
5856 /* */
5857 /* HDMI-CEC (CEC) */
5858 /* */
5859 /******************************************************************************/
5860
5861 /******************* Bit definition for CEC_CR register *********************/
5862 #define CEC_CR_CECEN_Pos (0U)
5863 #define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5864 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5865 #define CEC_CR_TXSOM_Pos (1U)
5866 #define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5867 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5868 #define CEC_CR_TXEOM_Pos (2U)
5869 #define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5870 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5871
5872 /******************* Bit definition for CEC_CFGR register *******************/
5873 #define CEC_CFGR_SFT_Pos (0U)
5874 #define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5875 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5876 #define CEC_CFGR_RXTOL_Pos (3U)
5877 #define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5878 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5879 #define CEC_CFGR_BRESTP_Pos (4U)
5880 #define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5881 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5882 #define CEC_CFGR_BREGEN_Pos (5U)
5883 #define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5884 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5885 #define CEC_CFGR_LBPEGEN_Pos (6U)
5886 #define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5887 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Period Error generation */
5888 #define CEC_CFGR_BRDNOGEN_Pos (7U)
5889 #define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5890 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast no Error generation */
5891 #define CEC_CFGR_SFTOPT_Pos (8U)
5892 #define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5893 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5894 #define CEC_CFGR_OAR_Pos (16U)
5895 #define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5896 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5897 #define CEC_CFGR_LSTN_Pos (31U)
5898 #define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5899 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5900
5901 /******************* Bit definition for CEC_TXDR register *******************/
5902 #define CEC_TXDR_TXD_Pos (0U)
5903 #define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5904 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5905
5906 /******************* Bit definition for CEC_RXDR register *******************/
5907 #define CEC_TXDR_RXD_Pos (0U)
5908 #define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
5909 #define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
5910
5911 /******************* Bit definition for CEC_ISR register ********************/
5912 #define CEC_ISR_RXBR_Pos (0U)
5913 #define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5914 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5915 #define CEC_ISR_RXEND_Pos (1U)
5916 #define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5917 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5918 #define CEC_ISR_RXOVR_Pos (2U)
5919 #define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5920 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5921 #define CEC_ISR_BRE_Pos (3U)
5922 #define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5923 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5924 #define CEC_ISR_SBPE_Pos (4U)
5925 #define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5926 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5927 #define CEC_ISR_LBPE_Pos (5U)
5928 #define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5929 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5930 #define CEC_ISR_RXACKE_Pos (6U)
5931 #define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5932 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5933 #define CEC_ISR_ARBLST_Pos (7U)
5934 #define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5935 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5936 #define CEC_ISR_TXBR_Pos (8U)
5937 #define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5938 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5939 #define CEC_ISR_TXEND_Pos (9U)
5940 #define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5941 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5942 #define CEC_ISR_TXUDR_Pos (10U)
5943 #define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5944 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5945 #define CEC_ISR_TXERR_Pos (11U)
5946 #define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5947 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5948 #define CEC_ISR_TXACKE_Pos (12U)
5949 #define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5950 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5951
5952 /******************* Bit definition for CEC_IER register ********************/
5953 #define CEC_IER_RXBRIE_Pos (0U)
5954 #define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5955 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5956 #define CEC_IER_RXENDIE_Pos (1U)
5957 #define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5958 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5959 #define CEC_IER_RXOVRIE_Pos (2U)
5960 #define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5961 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5962 #define CEC_IER_BREIE_Pos (3U)
5963 #define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5964 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5965 #define CEC_IER_SBPEIE_Pos (4U)
5966 #define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5967 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
5968 #define CEC_IER_LBPEIE_Pos (5U)
5969 #define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5970 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5971 #define CEC_IER_RXACKEIE_Pos (6U)
5972 #define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5973 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5974 #define CEC_IER_ARBLSTIE_Pos (7U)
5975 #define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5976 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5977 #define CEC_IER_TXBRIE_Pos (8U)
5978 #define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5979 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5980 #define CEC_IER_TXENDIE_Pos (9U)
5981 #define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5982 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5983 #define CEC_IER_TXUDRIE_Pos (10U)
5984 #define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5985 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5986 #define CEC_IER_TXERRIE_Pos (11U)
5987 #define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5988 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5989 #define CEC_IER_TXACKEIE_Pos (12U)
5990 #define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5991 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5992
5993 /******************************************************************************/
5994 /* */
5995 /* CRC calculation unit */
5996 /* */
5997 /******************************************************************************/
5998 /******************* Bit definition for CRC_DR register *********************/
5999 #define CRC_DR_DR_Pos (0U)
6000 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
6001 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
6002
6003 /******************* Bit definition for CRC_IDR register ********************/
6004 #define CRC_IDR_IDR_Pos (0U)
6005 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
6006 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
6007
6008 /******************** Bit definition for CRC_CR register ********************/
6009 #define CRC_CR_RESET_Pos (0U)
6010 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
6011 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
6012 #define CRC_CR_POLYSIZE_Pos (3U)
6013 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
6014 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
6015 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
6016 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
6017 #define CRC_CR_REV_IN_Pos (5U)
6018 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
6019 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
6020 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
6021 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
6022 #define CRC_CR_REV_OUT_Pos (7U)
6023 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
6024 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
6025
6026 /******************* Bit definition for CRC_INIT register *******************/
6027 #define CRC_INIT_INIT_Pos (0U)
6028 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
6029 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
6030
6031 /******************* Bit definition for CRC_POL register ********************/
6032 #define CRC_POL_POL_Pos (0U)
6033 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
6034 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
6035
6036 /******************************************************************************/
6037 /* */
6038 /* Crypto Processor */
6039 /* */
6040 /******************************************************************************/
6041 /******************* Bits definition for CRYP_CR register ********************/
6042 #define CRYP_CR_ALGODIR_Pos (2U)
6043 #define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
6044 #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
6045
6046 #define CRYP_CR_ALGOMODE_Pos (3U)
6047 #define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
6048 #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
6049 #define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
6050 #define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
6051 #define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
6052 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
6053 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
6054 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
6055 #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
6056 #define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
6057 #define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
6058 #define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
6059 #define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
6060 #define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
6061 #define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
6062 #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
6063 #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
6064 #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
6065 #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
6066 #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
6067 #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
6068 #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
6069 #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
6070 #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
6071 #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
6072 #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
6073 #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
6074
6075 #define CRYP_CR_DATATYPE_Pos (6U)
6076 #define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
6077 #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
6078 #define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
6079 #define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
6080 #define CRYP_CR_KEYSIZE_Pos (8U)
6081 #define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
6082 #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
6083 #define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
6084 #define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
6085 #define CRYP_CR_FFLUSH_Pos (14U)
6086 #define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
6087 #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
6088 #define CRYP_CR_CRYPEN_Pos (15U)
6089 #define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
6090 #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
6091
6092 #define CRYP_CR_GCM_CCMPH_Pos (16U)
6093 #define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
6094 #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
6095 #define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
6096 #define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
6097 #define CRYP_CR_ALGOMODE_3 0x00080000U
6098
6099 /****************** Bits definition for CRYP_SR register *********************/
6100 #define CRYP_SR_IFEM_Pos (0U)
6101 #define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
6102 #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
6103 #define CRYP_SR_IFNF_Pos (1U)
6104 #define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
6105 #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
6106 #define CRYP_SR_OFNE_Pos (2U)
6107 #define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
6108 #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
6109 #define CRYP_SR_OFFU_Pos (3U)
6110 #define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
6111 #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
6112 #define CRYP_SR_BUSY_Pos (4U)
6113 #define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
6114 #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
6115 /****************** Bits definition for CRYP_DMACR register ******************/
6116 #define CRYP_DMACR_DIEN_Pos (0U)
6117 #define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
6118 #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
6119 #define CRYP_DMACR_DOEN_Pos (1U)
6120 #define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
6121 #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
6122 /***************** Bits definition for CRYP_IMSCR register ******************/
6123 #define CRYP_IMSCR_INIM_Pos (0U)
6124 #define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
6125 #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
6126 #define CRYP_IMSCR_OUTIM_Pos (1U)
6127 #define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
6128 #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
6129 /****************** Bits definition for CRYP_RISR register *******************/
6130 #define CRYP_RISR_OUTRIS_Pos (0U)
6131 #define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
6132 #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
6133 #define CRYP_RISR_INRIS_Pos (1U)
6134 #define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
6135 #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
6136 /****************** Bits definition for CRYP_MISR register *******************/
6137 #define CRYP_MISR_INMIS_Pos (0U)
6138 #define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
6139 #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
6140 #define CRYP_MISR_OUTMIS_Pos (1U)
6141 #define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
6142 #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
6143
6144 /******************************************************************************/
6145 /* */
6146 /* Digital to Analog Converter */
6147 /* */
6148 /******************************************************************************/
6149 /******************** Bit definition for DAC_CR register ********************/
6150 #define DAC_CR_EN1_Pos (0U)
6151 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
6152 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
6153 #define DAC_CR_BOFF1_Pos (1U)
6154 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
6155 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
6156 #define DAC_CR_TEN1_Pos (2U)
6157 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
6158 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
6159 #define DAC_CR_TSEL1_Pos (3U)
6160 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
6161 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
6162 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
6163 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
6164 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
6165 #define DAC_CR_WAVE1_Pos (6U)
6166 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
6167 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
6168 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
6169 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
6170 #define DAC_CR_MAMP1_Pos (8U)
6171 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
6172 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6173 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
6174 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
6175 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
6176 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
6177 #define DAC_CR_DMAEN1_Pos (12U)
6178 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
6179 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
6180 #define DAC_CR_DMAUDRIE1_Pos (13U)
6181 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
6182 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable */
6183 #define DAC_CR_EN2_Pos (16U)
6184 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
6185 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
6186 #define DAC_CR_BOFF2_Pos (17U)
6187 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
6188 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
6189 #define DAC_CR_TEN2_Pos (18U)
6190 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
6191 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
6192 #define DAC_CR_TSEL2_Pos (19U)
6193 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
6194 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
6195 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
6196 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
6197 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
6198 #define DAC_CR_WAVE2_Pos (22U)
6199 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
6200 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6201 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
6202 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
6203 #define DAC_CR_MAMP2_Pos (24U)
6204 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
6205 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6206 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
6207 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
6208 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
6209 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
6210 #define DAC_CR_DMAEN2_Pos (28U)
6211 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
6212 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enable */
6213 #define DAC_CR_DMAUDRIE2_Pos (29U)
6214 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
6215 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
6216
6217 /***************** Bit definition for DAC_SWTRIGR register ******************/
6218 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6219 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
6220 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
6221 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6222 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
6223 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
6224
6225 /***************** Bit definition for DAC_DHR12R1 register ******************/
6226 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
6227 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
6228 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6229
6230 /***************** Bit definition for DAC_DHR12L1 register ******************/
6231 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
6232 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6233 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6234
6235 /****************** Bit definition for DAC_DHR8R1 register ******************/
6236 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
6237 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
6238 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6239
6240 /***************** Bit definition for DAC_DHR12R2 register ******************/
6241 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
6242 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
6243 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6244
6245 /***************** Bit definition for DAC_DHR12L2 register ******************/
6246 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
6247 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
6248 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6249
6250 /****************** Bit definition for DAC_DHR8R2 register ******************/
6251 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
6252 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
6253 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6254
6255 /***************** Bit definition for DAC_DHR12RD register ******************/
6256 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
6257 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
6258 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6259 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
6260 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
6261 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6262
6263 /***************** Bit definition for DAC_DHR12LD register ******************/
6264 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
6265 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6266 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6267 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
6268 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
6269 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6270
6271 /****************** Bit definition for DAC_DHR8RD register ******************/
6272 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
6273 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
6274 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6275 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
6276 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
6277 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6278
6279 /******************* Bit definition for DAC_DOR1 register *******************/
6280 #define DAC_DOR1_DACC1DOR_Pos (0U)
6281 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
6282 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
6283
6284 /******************* Bit definition for DAC_DOR2 register *******************/
6285 #define DAC_DOR2_DACC2DOR_Pos (0U)
6286 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
6287 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
6288
6289 /******************** Bit definition for DAC_SR register ********************/
6290 #define DAC_SR_DMAUDR1_Pos (13U)
6291 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
6292 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
6293 #define DAC_SR_DMAUDR2_Pos (29U)
6294 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
6295 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
6296
6297 /******************************************************************************/
6298 /* */
6299 /* Digital Filter for Sigma Delta Modulators */
6300 /* */
6301 /******************************************************************************/
6302
6303 /**************** DFSDM channel configuration registers ********************/
6304
6305 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6306 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6307 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6308 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6309 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6310 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6311 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6312 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6313 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6314 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6315 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6316 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6317 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6318 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6319 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6320 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6321 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6322 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6323 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6324 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6325 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6326 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6327 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6328 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
6329 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6330 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6331 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6332 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6333 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6334 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6335 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6336 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6337 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6338 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6339 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6340 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6341 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6342 #define DFSDM_CHCFGR1_SITP_Pos (0U)
6343 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6344 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6345 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6346 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6347
6348 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6349 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6350 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6351 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6352 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6353 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6354 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6355
6356 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6357 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6358 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6359 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6360 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6361 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6362 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6363 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6364 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6365 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6366 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6367 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6368 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6369 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6370 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6371
6372 /**************** Bit definition for DFSDM_CHWDATR register *******************/
6373 #define DFSDM_CHWDATR_WDATA_Pos (0U)
6374 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6375 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6376
6377 /**************** Bit definition for DFSDM_CHDATINR register *****************/
6378 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
6379 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6380 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6381 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
6382 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6383 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6384
6385 /************************ DFSDM module registers ****************************/
6386
6387 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
6388 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6389 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6390 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6391 #define DFSDM_FLTCR1_FAST_Pos (29U)
6392 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6393 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6394 #define DFSDM_FLTCR1_RCH_Pos (24U)
6395 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6396 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6397 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6398 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6399 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6400 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
6401 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6402 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6403 #define DFSDM_FLTCR1_RCONT_Pos (18U)
6404 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6405 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6406 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6407 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6408 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6409 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6410 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6411 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6412 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6413 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6414 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6415 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FU << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
6416 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6417 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6418 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6419 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6420 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
6421 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
6422 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6423 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6424 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6425 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
6426 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6427 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6428 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
6429 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6430 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6431 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6432 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6433 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6434 #define DFSDM_FLTCR1_DFEN_Pos (0U)
6435 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6436 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6437
6438 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
6439 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
6440 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6441 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6442 #define DFSDM_FLTCR2_EXCH_Pos (8U)
6443 #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6444 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6445 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
6446 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6447 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6448 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
6449 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6450 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6451 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
6452 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6453 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6454 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6455 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6456 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6457 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6458 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6459 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6460 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
6461 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6462 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6463 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6464 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6465 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6466
6467 /******************** Bit definition for DFSDM_FLTISR register *******************/
6468 #define DFSDM_FLTISR_SCDF_Pos (24U)
6469 #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6470 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6471 #define DFSDM_FLTISR_CKABF_Pos (16U)
6472 #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6473 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6474 #define DFSDM_FLTISR_RCIP_Pos (14U)
6475 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6476 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6477 #define DFSDM_FLTISR_JCIP_Pos (13U)
6478 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6479 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6480 #define DFSDM_FLTISR_AWDF_Pos (4U)
6481 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6482 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6483 #define DFSDM_FLTISR_ROVRF_Pos (3U)
6484 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6485 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6486 #define DFSDM_FLTISR_JOVRF_Pos (2U)
6487 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6488 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6489 #define DFSDM_FLTISR_REOCF_Pos (1U)
6490 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6491 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6492 #define DFSDM_FLTISR_JEOCF_Pos (0U)
6493 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6494 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6495
6496 /******************** Bit definition for DFSDM_FLTICR register *******************/
6497 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
6498 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
6499 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6500 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6501 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6502 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6503 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6504 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6505 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6506 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6507 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6508 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6509
6510 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6511 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6512 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6513 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6514
6515 /******************** Bit definition for DFSDM_FLTFCR register *******************/
6516 #define DFSDM_FLTFCR_FORD_Pos (29U)
6517 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6518 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6519 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6520 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6521 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6522 #define DFSDM_FLTFCR_FOSR_Pos (16U)
6523 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6524 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6525 #define DFSDM_FLTFCR_IOSR_Pos (0U)
6526 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6527 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6528
6529 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6530 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6531 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6532 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6533 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6534 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6535 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6536
6537 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6538 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6539 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6540 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6541 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6542 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6543 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6544 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6545 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6546 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6547
6548 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6549 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6550 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6551 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6552 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6553 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6554 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6555
6556 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6557 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6558 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6559 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
6560 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6561 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6562 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6563
6564 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
6565 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6566 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6567 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6568 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6569 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6570 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6571
6572 /****************** Bit definition for DFSDM_FLTAWCFR register *****************/
6573 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6574 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6575 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6576 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6577 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6578 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6579
6580 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6581 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6582 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6583 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6584 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6585 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6586 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6587
6588 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6589 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6590 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6591 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6592 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6593 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6594 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6595
6596 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6597 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6598 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6599 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6600
6601 /******************************************************************************/
6602 /* */
6603 /* Debug MCU */
6604 /* */
6605 /******************************************************************************/
6606
6607 /******************************************************************************/
6608 /* */
6609 /* DCMI */
6610 /* */
6611 /******************************************************************************/
6612 /******************** Bits definition for DCMI_CR register ******************/
6613 #define DCMI_CR_CAPTURE_Pos (0U)
6614 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
6615 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6616 #define DCMI_CR_CM_Pos (1U)
6617 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
6618 #define DCMI_CR_CM DCMI_CR_CM_Msk
6619 #define DCMI_CR_CROP_Pos (2U)
6620 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
6621 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
6622 #define DCMI_CR_JPEG_Pos (3U)
6623 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
6624 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6625 #define DCMI_CR_ESS_Pos (4U)
6626 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
6627 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
6628 #define DCMI_CR_PCKPOL_Pos (5U)
6629 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
6630 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6631 #define DCMI_CR_HSPOL_Pos (6U)
6632 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
6633 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6634 #define DCMI_CR_VSPOL_Pos (7U)
6635 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
6636 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6637 #define DCMI_CR_FCRC_0 0x00000100U
6638 #define DCMI_CR_FCRC_1 0x00000200U
6639 #define DCMI_CR_EDM_0 0x00000400U
6640 #define DCMI_CR_EDM_1 0x00000800U
6641 #define DCMI_CR_CRE_Pos (12U)
6642 #define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
6643 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
6644 #define DCMI_CR_ENABLE_Pos (14U)
6645 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
6646 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6647 #define DCMI_CR_BSM_Pos (16U)
6648 #define DCMI_CR_BSM_Msk (0x3U << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
6649 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
6650 #define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
6651 #define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
6652 #define DCMI_CR_OEBS_Pos (18U)
6653 #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
6654 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6655 #define DCMI_CR_LSM_Pos (19U)
6656 #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
6657 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
6658 #define DCMI_CR_OELS_Pos (20U)
6659 #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
6660 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
6661
6662 /******************** Bits definition for DCMI_SR register ******************/
6663 #define DCMI_SR_HSYNC_Pos (0U)
6664 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
6665 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6666 #define DCMI_SR_VSYNC_Pos (1U)
6667 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
6668 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6669 #define DCMI_SR_FNE_Pos (2U)
6670 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
6671 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
6672
6673 /******************** Bits definition for DCMI_RIS register ****************/
6674 #define DCMI_RIS_FRAME_RIS_Pos (0U)
6675 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
6676 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6677 #define DCMI_RIS_OVR_RIS_Pos (1U)
6678 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
6679 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6680 #define DCMI_RIS_ERR_RIS_Pos (2U)
6681 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
6682 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6683 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
6684 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
6685 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6686 #define DCMI_RIS_LINE_RIS_Pos (4U)
6687 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
6688 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6689
6690 /* Legacy defines */
6691 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
6692 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
6693 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
6694 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
6695 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
6696
6697 /******************** Bits definition for DCMI_IER register *****************/
6698 #define DCMI_IER_FRAME_IE_Pos (0U)
6699 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
6700 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6701 #define DCMI_IER_OVR_IE_Pos (1U)
6702 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
6703 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6704 #define DCMI_IER_ERR_IE_Pos (2U)
6705 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
6706 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6707 #define DCMI_IER_VSYNC_IE_Pos (3U)
6708 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
6709 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6710 #define DCMI_IER_LINE_IE_Pos (4U)
6711 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
6712 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6713
6714
6715 /******************** Bits definition for DCMI_MIS register *****************/
6716 #define DCMI_MIS_FRAME_MIS_Pos (0U)
6717 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
6718 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6719 #define DCMI_MIS_OVR_MIS_Pos (1U)
6720 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
6721 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6722 #define DCMI_MIS_ERR_MIS_Pos (2U)
6723 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
6724 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6725 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
6726 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6727 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6728 #define DCMI_MIS_LINE_MIS_Pos (4U)
6729 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6730 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6731
6732
6733 /******************** Bits definition for DCMI_ICR register *****************/
6734 #define DCMI_ICR_FRAME_ISC_Pos (0U)
6735 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6736 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6737 #define DCMI_ICR_OVR_ISC_Pos (1U)
6738 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6739 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6740 #define DCMI_ICR_ERR_ISC_Pos (2U)
6741 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6742 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6743 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
6744 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6745 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6746 #define DCMI_ICR_LINE_ISC_Pos (4U)
6747 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6748 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6749
6750
6751 /******************** Bits definition for DCMI_ESCR register ******************/
6752 #define DCMI_ESCR_FSC_Pos (0U)
6753 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6754 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6755 #define DCMI_ESCR_LSC_Pos (8U)
6756 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6757 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6758 #define DCMI_ESCR_LEC_Pos (16U)
6759 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6760 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6761 #define DCMI_ESCR_FEC_Pos (24U)
6762 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6763 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6764
6765 /******************** Bits definition for DCMI_ESUR register ******************/
6766 #define DCMI_ESUR_FSU_Pos (0U)
6767 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6768 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6769 #define DCMI_ESUR_LSU_Pos (8U)
6770 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6771 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6772 #define DCMI_ESUR_LEU_Pos (16U)
6773 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6774 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6775 #define DCMI_ESUR_FEU_Pos (24U)
6776 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6777 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6778
6779 /******************** Bits definition for DCMI_CWSTRT register ******************/
6780 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6781 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6782 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6783 #define DCMI_CWSTRT_VST_Pos (16U)
6784 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6785 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6786
6787 /******************** Bits definition for DCMI_CWSIZE register ******************/
6788 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
6789 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6790 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6791 #define DCMI_CWSIZE_VLINE_Pos (16U)
6792 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6793 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6794
6795 /******************** Bits definition for DCMI_DR register ******************/
6796 #define DCMI_DR_BYTE0_Pos (0U)
6797 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6798 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6799 #define DCMI_DR_BYTE1_Pos (8U)
6800 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6801 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6802 #define DCMI_DR_BYTE2_Pos (16U)
6803 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6804 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6805 #define DCMI_DR_BYTE3_Pos (24U)
6806 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6807 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6808
6809 /******************************************************************************/
6810 /* */
6811 /* DMA Controller */
6812 /* */
6813 /******************************************************************************/
6814 /******************** Bits definition for DMA_SxCR register *****************/
6815 #define DMA_SxCR_CHSEL_Pos (25U)
6816 #define DMA_SxCR_CHSEL_Msk (0xFU << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
6817 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6818 #define DMA_SxCR_CHSEL_0 (0x1U << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6819 #define DMA_SxCR_CHSEL_1 (0x2U << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6820 #define DMA_SxCR_CHSEL_2 (0x4U << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
6821 #define DMA_SxCR_CHSEL_3 (0x8U << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
6822 #define DMA_SxCR_MBURST_Pos (23U)
6823 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
6824 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6825 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6826 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6827 #define DMA_SxCR_PBURST_Pos (21U)
6828 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6829 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6830 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6831 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6832 #define DMA_SxCR_CT_Pos (19U)
6833 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6834 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
6835 #define DMA_SxCR_DBM_Pos (18U)
6836 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6837 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6838 #define DMA_SxCR_PL_Pos (16U)
6839 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6840 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
6841 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6842 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6843 #define DMA_SxCR_PINCOS_Pos (15U)
6844 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6845 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6846 #define DMA_SxCR_MSIZE_Pos (13U)
6847 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6848 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6849 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6850 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6851 #define DMA_SxCR_PSIZE_Pos (11U)
6852 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6853 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6854 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6855 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6856 #define DMA_SxCR_MINC_Pos (10U)
6857 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6858 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6859 #define DMA_SxCR_PINC_Pos (9U)
6860 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6861 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6862 #define DMA_SxCR_CIRC_Pos (8U)
6863 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6864 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6865 #define DMA_SxCR_DIR_Pos (6U)
6866 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6867 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6868 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6869 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6870 #define DMA_SxCR_PFCTRL_Pos (5U)
6871 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6872 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6873 #define DMA_SxCR_TCIE_Pos (4U)
6874 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6875 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6876 #define DMA_SxCR_HTIE_Pos (3U)
6877 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6878 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6879 #define DMA_SxCR_TEIE_Pos (2U)
6880 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6881 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6882 #define DMA_SxCR_DMEIE_Pos (1U)
6883 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6884 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6885 #define DMA_SxCR_EN_Pos (0U)
6886 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6887 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
6888
6889 /******************** Bits definition for DMA_SxCNDTR register **************/
6890 #define DMA_SxNDT_Pos (0U)
6891 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6892 #define DMA_SxNDT DMA_SxNDT_Msk
6893 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
6894 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
6895 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
6896 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
6897 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
6898 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
6899 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
6900 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
6901 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
6902 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
6903 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
6904 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
6905 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
6906 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
6907 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
6908 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
6909
6910 /******************** Bits definition for DMA_SxFCR register ****************/
6911 #define DMA_SxFCR_FEIE_Pos (7U)
6912 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6913 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6914 #define DMA_SxFCR_FS_Pos (3U)
6915 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6916 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6917 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6918 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6919 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6920 #define DMA_SxFCR_DMDIS_Pos (2U)
6921 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6922 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6923 #define DMA_SxFCR_FTH_Pos (0U)
6924 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6925 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6926 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6927 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6928
6929 /******************** Bits definition for DMA_LISR register *****************/
6930 #define DMA_LISR_TCIF3_Pos (27U)
6931 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6932 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6933 #define DMA_LISR_HTIF3_Pos (26U)
6934 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6935 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6936 #define DMA_LISR_TEIF3_Pos (25U)
6937 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6938 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6939 #define DMA_LISR_DMEIF3_Pos (24U)
6940 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6941 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6942 #define DMA_LISR_FEIF3_Pos (22U)
6943 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6944 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6945 #define DMA_LISR_TCIF2_Pos (21U)
6946 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6947 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6948 #define DMA_LISR_HTIF2_Pos (20U)
6949 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6950 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6951 #define DMA_LISR_TEIF2_Pos (19U)
6952 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6953 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6954 #define DMA_LISR_DMEIF2_Pos (18U)
6955 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6956 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6957 #define DMA_LISR_FEIF2_Pos (16U)
6958 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6959 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6960 #define DMA_LISR_TCIF1_Pos (11U)
6961 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6962 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6963 #define DMA_LISR_HTIF1_Pos (10U)
6964 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6965 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6966 #define DMA_LISR_TEIF1_Pos (9U)
6967 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6968 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6969 #define DMA_LISR_DMEIF1_Pos (8U)
6970 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6971 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6972 #define DMA_LISR_FEIF1_Pos (6U)
6973 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6974 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6975 #define DMA_LISR_TCIF0_Pos (5U)
6976 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6977 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6978 #define DMA_LISR_HTIF0_Pos (4U)
6979 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6980 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6981 #define DMA_LISR_TEIF0_Pos (3U)
6982 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6983 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6984 #define DMA_LISR_DMEIF0_Pos (2U)
6985 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6986 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6987 #define DMA_LISR_FEIF0_Pos (0U)
6988 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6989 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6990
6991 /******************** Bits definition for DMA_HISR register *****************/
6992 #define DMA_HISR_TCIF7_Pos (27U)
6993 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6994 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6995 #define DMA_HISR_HTIF7_Pos (26U)
6996 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6997 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6998 #define DMA_HISR_TEIF7_Pos (25U)
6999 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
7000 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
7001 #define DMA_HISR_DMEIF7_Pos (24U)
7002 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
7003 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
7004 #define DMA_HISR_FEIF7_Pos (22U)
7005 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
7006 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
7007 #define DMA_HISR_TCIF6_Pos (21U)
7008 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
7009 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
7010 #define DMA_HISR_HTIF6_Pos (20U)
7011 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
7012 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
7013 #define DMA_HISR_TEIF6_Pos (19U)
7014 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
7015 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
7016 #define DMA_HISR_DMEIF6_Pos (18U)
7017 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
7018 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
7019 #define DMA_HISR_FEIF6_Pos (16U)
7020 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
7021 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
7022 #define DMA_HISR_TCIF5_Pos (11U)
7023 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
7024 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
7025 #define DMA_HISR_HTIF5_Pos (10U)
7026 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
7027 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
7028 #define DMA_HISR_TEIF5_Pos (9U)
7029 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
7030 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
7031 #define DMA_HISR_DMEIF5_Pos (8U)
7032 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
7033 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
7034 #define DMA_HISR_FEIF5_Pos (6U)
7035 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
7036 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
7037 #define DMA_HISR_TCIF4_Pos (5U)
7038 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
7039 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
7040 #define DMA_HISR_HTIF4_Pos (4U)
7041 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
7042 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
7043 #define DMA_HISR_TEIF4_Pos (3U)
7044 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
7045 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
7046 #define DMA_HISR_DMEIF4_Pos (2U)
7047 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
7048 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
7049 #define DMA_HISR_FEIF4_Pos (0U)
7050 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
7051 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
7052
7053 /******************** Bits definition for DMA_LIFCR register ****************/
7054 #define DMA_LIFCR_CTCIF3_Pos (27U)
7055 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
7056 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
7057 #define DMA_LIFCR_CHTIF3_Pos (26U)
7058 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
7059 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
7060 #define DMA_LIFCR_CTEIF3_Pos (25U)
7061 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
7062 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
7063 #define DMA_LIFCR_CDMEIF3_Pos (24U)
7064 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
7065 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
7066 #define DMA_LIFCR_CFEIF3_Pos (22U)
7067 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
7068 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
7069 #define DMA_LIFCR_CTCIF2_Pos (21U)
7070 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
7071 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
7072 #define DMA_LIFCR_CHTIF2_Pos (20U)
7073 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
7074 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
7075 #define DMA_LIFCR_CTEIF2_Pos (19U)
7076 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
7077 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
7078 #define DMA_LIFCR_CDMEIF2_Pos (18U)
7079 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
7080 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
7081 #define DMA_LIFCR_CFEIF2_Pos (16U)
7082 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
7083 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
7084 #define DMA_LIFCR_CTCIF1_Pos (11U)
7085 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
7086 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
7087 #define DMA_LIFCR_CHTIF1_Pos (10U)
7088 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
7089 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
7090 #define DMA_LIFCR_CTEIF1_Pos (9U)
7091 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
7092 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
7093 #define DMA_LIFCR_CDMEIF1_Pos (8U)
7094 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
7095 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
7096 #define DMA_LIFCR_CFEIF1_Pos (6U)
7097 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
7098 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
7099 #define DMA_LIFCR_CTCIF0_Pos (5U)
7100 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
7101 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
7102 #define DMA_LIFCR_CHTIF0_Pos (4U)
7103 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
7104 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
7105 #define DMA_LIFCR_CTEIF0_Pos (3U)
7106 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
7107 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
7108 #define DMA_LIFCR_CDMEIF0_Pos (2U)
7109 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
7110 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
7111 #define DMA_LIFCR_CFEIF0_Pos (0U)
7112 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
7113 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
7114
7115 /******************** Bits definition for DMA_HIFCR register ****************/
7116 #define DMA_HIFCR_CTCIF7_Pos (27U)
7117 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
7118 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
7119 #define DMA_HIFCR_CHTIF7_Pos (26U)
7120 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
7121 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
7122 #define DMA_HIFCR_CTEIF7_Pos (25U)
7123 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
7124 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
7125 #define DMA_HIFCR_CDMEIF7_Pos (24U)
7126 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
7127 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
7128 #define DMA_HIFCR_CFEIF7_Pos (22U)
7129 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
7130 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
7131 #define DMA_HIFCR_CTCIF6_Pos (21U)
7132 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
7133 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
7134 #define DMA_HIFCR_CHTIF6_Pos (20U)
7135 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
7136 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
7137 #define DMA_HIFCR_CTEIF6_Pos (19U)
7138 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
7139 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
7140 #define DMA_HIFCR_CDMEIF6_Pos (18U)
7141 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
7142 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
7143 #define DMA_HIFCR_CFEIF6_Pos (16U)
7144 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
7145 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
7146 #define DMA_HIFCR_CTCIF5_Pos (11U)
7147 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
7148 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
7149 #define DMA_HIFCR_CHTIF5_Pos (10U)
7150 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
7151 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
7152 #define DMA_HIFCR_CTEIF5_Pos (9U)
7153 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
7154 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
7155 #define DMA_HIFCR_CDMEIF5_Pos (8U)
7156 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
7157 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
7158 #define DMA_HIFCR_CFEIF5_Pos (6U)
7159 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
7160 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
7161 #define DMA_HIFCR_CTCIF4_Pos (5U)
7162 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
7163 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
7164 #define DMA_HIFCR_CHTIF4_Pos (4U)
7165 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
7166 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
7167 #define DMA_HIFCR_CTEIF4_Pos (3U)
7168 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
7169 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
7170 #define DMA_HIFCR_CDMEIF4_Pos (2U)
7171 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
7172 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
7173 #define DMA_HIFCR_CFEIF4_Pos (0U)
7174 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
7175 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
7176
7177 /****************** Bit definition for DMA_SxPAR register ********************/
7178 #define DMA_SxPAR_PA_Pos (0U)
7179 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
7180 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
7181
7182 /****************** Bit definition for DMA_SxM0AR register ********************/
7183 #define DMA_SxM0AR_M0A_Pos (0U)
7184 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
7185 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
7186
7187 /****************** Bit definition for DMA_SxM1AR register ********************/
7188 #define DMA_SxM1AR_M1A_Pos (0U)
7189 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
7190 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
7191
7192 /******************************************************************************/
7193 /* */
7194 /* AHB Master DMA2D Controller (DMA2D) */
7195 /* */
7196 /******************************************************************************/
7197 /*
7198 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
7199 */
7200 #define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
7201 /******************** Bit definition for DMA2D_CR register ******************/
7202
7203 #define DMA2D_CR_START_Pos (0U)
7204 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
7205 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
7206 #define DMA2D_CR_SUSP_Pos (1U)
7207 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
7208 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
7209 #define DMA2D_CR_ABORT_Pos (2U)
7210 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
7211 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
7212 #define DMA2D_CR_TEIE_Pos (8U)
7213 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
7214 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
7215 #define DMA2D_CR_TCIE_Pos (9U)
7216 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
7217 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
7218 #define DMA2D_CR_TWIE_Pos (10U)
7219 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
7220 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
7221 #define DMA2D_CR_CAEIE_Pos (11U)
7222 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
7223 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
7224 #define DMA2D_CR_CTCIE_Pos (12U)
7225 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
7226 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
7227 #define DMA2D_CR_CEIE_Pos (13U)
7228 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
7229 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
7230 #define DMA2D_CR_MODE_Pos (16U)
7231 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
7232 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
7233 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
7234 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
7235
7236 /******************** Bit definition for DMA2D_ISR register *****************/
7237
7238 #define DMA2D_ISR_TEIF_Pos (0U)
7239 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
7240 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
7241 #define DMA2D_ISR_TCIF_Pos (1U)
7242 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
7243 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
7244 #define DMA2D_ISR_TWIF_Pos (2U)
7245 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
7246 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
7247 #define DMA2D_ISR_CAEIF_Pos (3U)
7248 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
7249 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
7250 #define DMA2D_ISR_CTCIF_Pos (4U)
7251 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
7252 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
7253 #define DMA2D_ISR_CEIF_Pos (5U)
7254 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
7255 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
7256
7257 /******************** Bit definition for DMA2D_IFCR register ****************/
7258
7259 #define DMA2D_IFCR_CTEIF_Pos (0U)
7260 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
7261 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
7262 #define DMA2D_IFCR_CTCIF_Pos (1U)
7263 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
7264 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
7265 #define DMA2D_IFCR_CTWIF_Pos (2U)
7266 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
7267 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
7268 #define DMA2D_IFCR_CAECIF_Pos (3U)
7269 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
7270 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
7271 #define DMA2D_IFCR_CCTCIF_Pos (4U)
7272 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
7273 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
7274 #define DMA2D_IFCR_CCEIF_Pos (5U)
7275 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
7276 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
7277
7278 /* Legacy defines */
7279 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
7280 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
7281 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
7282 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
7283 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
7284 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
7285
7286 /******************** Bit definition for DMA2D_FGMAR register ***************/
7287
7288 #define DMA2D_FGMAR_MA_Pos (0U)
7289 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7290 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
7291
7292 /******************** Bit definition for DMA2D_FGOR register ****************/
7293
7294 #define DMA2D_FGOR_LO_Pos (0U)
7295 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
7296 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
7297
7298 /******************** Bit definition for DMA2D_BGMAR register ***************/
7299
7300 #define DMA2D_BGMAR_MA_Pos (0U)
7301 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7302 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
7303
7304 /******************** Bit definition for DMA2D_BGOR register ****************/
7305
7306 #define DMA2D_BGOR_LO_Pos (0U)
7307 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
7308 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
7309
7310 /******************** Bit definition for DMA2D_FGPFCCR register *************/
7311
7312 #define DMA2D_FGPFCCR_CM_Pos (0U)
7313 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
7314 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7315 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
7316 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
7317 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
7318 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
7319 #define DMA2D_FGPFCCR_CCM_Pos (4U)
7320 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
7321 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
7322 #define DMA2D_FGPFCCR_START_Pos (5U)
7323 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
7324 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
7325 #define DMA2D_FGPFCCR_CS_Pos (8U)
7326 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7327 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
7328 #define DMA2D_FGPFCCR_AM_Pos (16U)
7329 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
7330 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7331 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
7332 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
7333 #define DMA2D_FGPFCCR_AI_Pos (20U)
7334 #define DMA2D_FGPFCCR_AI_Msk (0x1U << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
7335 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
7336 #define DMA2D_FGPFCCR_RBS_Pos (21U)
7337 #define DMA2D_FGPFCCR_RBS_Msk (0x1U << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
7338 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
7339 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
7340 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7341 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
7342
7343 /******************** Bit definition for DMA2D_FGCOLR register **************/
7344
7345 #define DMA2D_FGCOLR_BLUE_Pos (0U)
7346 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
7347 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
7348 #define DMA2D_FGCOLR_GREEN_Pos (8U)
7349 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7350 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
7351 #define DMA2D_FGCOLR_RED_Pos (16U)
7352 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
7353 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
7354
7355 /******************** Bit definition for DMA2D_BGPFCCR register *************/
7356
7357 #define DMA2D_BGPFCCR_CM_Pos (0U)
7358 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
7359 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7360 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
7361 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
7362 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
7363 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
7364 #define DMA2D_BGPFCCR_CCM_Pos (4U)
7365 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
7366 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
7367 #define DMA2D_BGPFCCR_START_Pos (5U)
7368 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
7369 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
7370 #define DMA2D_BGPFCCR_CS_Pos (8U)
7371 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7372 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
7373 #define DMA2D_BGPFCCR_AM_Pos (16U)
7374 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
7375 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7376 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
7377 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
7378 #define DMA2D_BGPFCCR_AI_Pos (20U)
7379 #define DMA2D_BGPFCCR_AI_Msk (0x1U << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
7380 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
7381 #define DMA2D_BGPFCCR_RBS_Pos (21U)
7382 #define DMA2D_BGPFCCR_RBS_Msk (0x1U << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
7383 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
7384 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
7385 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7386 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
7387
7388 /******************** Bit definition for DMA2D_BGCOLR register **************/
7389
7390 #define DMA2D_BGCOLR_BLUE_Pos (0U)
7391 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
7392 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
7393 #define DMA2D_BGCOLR_GREEN_Pos (8U)
7394 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7395 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
7396 #define DMA2D_BGCOLR_RED_Pos (16U)
7397 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
7398 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
7399
7400 /******************** Bit definition for DMA2D_FGCMAR register **************/
7401
7402 #define DMA2D_FGCMAR_MA_Pos (0U)
7403 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7404 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
7405
7406 /******************** Bit definition for DMA2D_BGCMAR register **************/
7407
7408 #define DMA2D_BGCMAR_MA_Pos (0U)
7409 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7410 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
7411
7412 /******************** Bit definition for DMA2D_OPFCCR register **************/
7413
7414 #define DMA2D_OPFCCR_CM_Pos (0U)
7415 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
7416 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
7417 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
7418 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
7419 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
7420 #define DMA2D_OPFCCR_AI_Pos (20U)
7421 #define DMA2D_OPFCCR_AI_Msk (0x1U << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
7422 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
7423 #define DMA2D_OPFCCR_RBS_Pos (21U)
7424 #define DMA2D_OPFCCR_RBS_Msk (0x1U << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
7425 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
7426
7427 /******************** Bit definition for DMA2D_OCOLR register ***************/
7428
7429 /*!<Mode_ARGB8888/RGB888 */
7430
7431 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
7432 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
7433 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
7434 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
7435
7436 /*!<Mode_RGB565 */
7437 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
7438 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
7439 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
7440
7441 /*!<Mode_ARGB1555 */
7442 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
7443 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
7444 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
7445 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
7446
7447 /*!<Mode_ARGB4444 */
7448 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
7449 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
7450 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
7451 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
7452
7453 /******************** Bit definition for DMA2D_OMAR register ****************/
7454
7455 #define DMA2D_OMAR_MA_Pos (0U)
7456 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
7457 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
7458
7459 /******************** Bit definition for DMA2D_OOR register *****************/
7460
7461 #define DMA2D_OOR_LO_Pos (0U)
7462 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
7463 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
7464
7465 /******************** Bit definition for DMA2D_NLR register *****************/
7466
7467 #define DMA2D_NLR_NL_Pos (0U)
7468 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
7469 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
7470 #define DMA2D_NLR_PL_Pos (16U)
7471 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
7472 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
7473
7474 /******************** Bit definition for DMA2D_LWR register *****************/
7475
7476 #define DMA2D_LWR_LW_Pos (0U)
7477 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
7478 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
7479
7480 /******************** Bit definition for DMA2D_AMTCR register ***************/
7481
7482 #define DMA2D_AMTCR_EN_Pos (0U)
7483 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
7484 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
7485 #define DMA2D_AMTCR_DT_Pos (8U)
7486 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
7487 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
7488
7489
7490 /******************** Bit definition for DMA2D_FGCLUT register **************/
7491
7492 /******************** Bit definition for DMA2D_BGCLUT register **************/
7493
7494 /******************************************************************************/
7495 /* */
7496 /* External Interrupt/Event Controller */
7497 /* */
7498 /******************************************************************************/
7499 /******************* Bit definition for EXTI_IMR register *******************/
7500 #define EXTI_IMR_MR0_Pos (0U)
7501 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
7502 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
7503 #define EXTI_IMR_MR1_Pos (1U)
7504 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
7505 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
7506 #define EXTI_IMR_MR2_Pos (2U)
7507 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
7508 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
7509 #define EXTI_IMR_MR3_Pos (3U)
7510 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
7511 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
7512 #define EXTI_IMR_MR4_Pos (4U)
7513 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
7514 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
7515 #define EXTI_IMR_MR5_Pos (5U)
7516 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
7517 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
7518 #define EXTI_IMR_MR6_Pos (6U)
7519 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
7520 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
7521 #define EXTI_IMR_MR7_Pos (7U)
7522 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
7523 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
7524 #define EXTI_IMR_MR8_Pos (8U)
7525 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
7526 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
7527 #define EXTI_IMR_MR9_Pos (9U)
7528 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
7529 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
7530 #define EXTI_IMR_MR10_Pos (10U)
7531 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
7532 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
7533 #define EXTI_IMR_MR11_Pos (11U)
7534 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
7535 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
7536 #define EXTI_IMR_MR12_Pos (12U)
7537 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
7538 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
7539 #define EXTI_IMR_MR13_Pos (13U)
7540 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
7541 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
7542 #define EXTI_IMR_MR14_Pos (14U)
7543 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
7544 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
7545 #define EXTI_IMR_MR15_Pos (15U)
7546 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
7547 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
7548 #define EXTI_IMR_MR16_Pos (16U)
7549 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
7550 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
7551 #define EXTI_IMR_MR17_Pos (17U)
7552 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
7553 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
7554 #define EXTI_IMR_MR18_Pos (18U)
7555 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
7556 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
7557 #define EXTI_IMR_MR19_Pos (19U)
7558 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
7559 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
7560 #define EXTI_IMR_MR20_Pos (20U)
7561 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
7562 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
7563 #define EXTI_IMR_MR21_Pos (21U)
7564 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
7565 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
7566 #define EXTI_IMR_MR22_Pos (22U)
7567 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
7568 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
7569 #define EXTI_IMR_MR23_Pos (23U)
7570 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
7571 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
7572 #define EXTI_IMR_MR24_Pos (24U)
7573 #define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
7574 #define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
7575
7576 /* Reference Defines */
7577 #define EXTI_IMR_IM0 EXTI_IMR_MR0
7578 #define EXTI_IMR_IM1 EXTI_IMR_MR1
7579 #define EXTI_IMR_IM2 EXTI_IMR_MR2
7580 #define EXTI_IMR_IM3 EXTI_IMR_MR3
7581 #define EXTI_IMR_IM4 EXTI_IMR_MR4
7582 #define EXTI_IMR_IM5 EXTI_IMR_MR5
7583 #define EXTI_IMR_IM6 EXTI_IMR_MR6
7584 #define EXTI_IMR_IM7 EXTI_IMR_MR7
7585 #define EXTI_IMR_IM8 EXTI_IMR_MR8
7586 #define EXTI_IMR_IM9 EXTI_IMR_MR9
7587 #define EXTI_IMR_IM10 EXTI_IMR_MR10
7588 #define EXTI_IMR_IM11 EXTI_IMR_MR11
7589 #define EXTI_IMR_IM12 EXTI_IMR_MR12
7590 #define EXTI_IMR_IM13 EXTI_IMR_MR13
7591 #define EXTI_IMR_IM14 EXTI_IMR_MR14
7592 #define EXTI_IMR_IM15 EXTI_IMR_MR15
7593 #define EXTI_IMR_IM16 EXTI_IMR_MR16
7594 #define EXTI_IMR_IM17 EXTI_IMR_MR17
7595 #define EXTI_IMR_IM18 EXTI_IMR_MR18
7596 #define EXTI_IMR_IM19 EXTI_IMR_MR19
7597 #define EXTI_IMR_IM20 EXTI_IMR_MR20
7598 #define EXTI_IMR_IM21 EXTI_IMR_MR21
7599 #define EXTI_IMR_IM22 EXTI_IMR_MR22
7600 #define EXTI_IMR_IM23 EXTI_IMR_MR23
7601 #define EXTI_IMR_IM24 EXTI_IMR_MR24
7602
7603 #define EXTI_IMR_IM_Pos (0U)
7604 #define EXTI_IMR_IM_Msk (0x1FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x01FFFFFF */
7605 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
7606
7607 /******************* Bit definition for EXTI_EMR register *******************/
7608 #define EXTI_EMR_MR0_Pos (0U)
7609 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
7610 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
7611 #define EXTI_EMR_MR1_Pos (1U)
7612 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
7613 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
7614 #define EXTI_EMR_MR2_Pos (2U)
7615 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
7616 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
7617 #define EXTI_EMR_MR3_Pos (3U)
7618 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
7619 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
7620 #define EXTI_EMR_MR4_Pos (4U)
7621 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
7622 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
7623 #define EXTI_EMR_MR5_Pos (5U)
7624 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
7625 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
7626 #define EXTI_EMR_MR6_Pos (6U)
7627 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
7628 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
7629 #define EXTI_EMR_MR7_Pos (7U)
7630 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
7631 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
7632 #define EXTI_EMR_MR8_Pos (8U)
7633 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
7634 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
7635 #define EXTI_EMR_MR9_Pos (9U)
7636 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
7637 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
7638 #define EXTI_EMR_MR10_Pos (10U)
7639 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
7640 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
7641 #define EXTI_EMR_MR11_Pos (11U)
7642 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
7643 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
7644 #define EXTI_EMR_MR12_Pos (12U)
7645 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
7646 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
7647 #define EXTI_EMR_MR13_Pos (13U)
7648 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
7649 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
7650 #define EXTI_EMR_MR14_Pos (14U)
7651 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
7652 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
7653 #define EXTI_EMR_MR15_Pos (15U)
7654 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
7655 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
7656 #define EXTI_EMR_MR16_Pos (16U)
7657 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
7658 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
7659 #define EXTI_EMR_MR17_Pos (17U)
7660 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
7661 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
7662 #define EXTI_EMR_MR18_Pos (18U)
7663 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
7664 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
7665 #define EXTI_EMR_MR19_Pos (19U)
7666 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
7667 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
7668 #define EXTI_EMR_MR20_Pos (20U)
7669 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
7670 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
7671 #define EXTI_EMR_MR21_Pos (21U)
7672 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
7673 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
7674 #define EXTI_EMR_MR22_Pos (22U)
7675 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
7676 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
7677 #define EXTI_EMR_MR23_Pos (23U)
7678 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
7679 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
7680 #define EXTI_EMR_MR24_Pos (24U)
7681 #define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
7682 #define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
7683
7684 /* Reference Defines */
7685 #define EXTI_EMR_EM0 EXTI_EMR_MR0
7686 #define EXTI_EMR_EM1 EXTI_EMR_MR1
7687 #define EXTI_EMR_EM2 EXTI_EMR_MR2
7688 #define EXTI_EMR_EM3 EXTI_EMR_MR3
7689 #define EXTI_EMR_EM4 EXTI_EMR_MR4
7690 #define EXTI_EMR_EM5 EXTI_EMR_MR5
7691 #define EXTI_EMR_EM6 EXTI_EMR_MR6
7692 #define EXTI_EMR_EM7 EXTI_EMR_MR7
7693 #define EXTI_EMR_EM8 EXTI_EMR_MR8
7694 #define EXTI_EMR_EM9 EXTI_EMR_MR9
7695 #define EXTI_EMR_EM10 EXTI_EMR_MR10
7696 #define EXTI_EMR_EM11 EXTI_EMR_MR11
7697 #define EXTI_EMR_EM12 EXTI_EMR_MR12
7698 #define EXTI_EMR_EM13 EXTI_EMR_MR13
7699 #define EXTI_EMR_EM14 EXTI_EMR_MR14
7700 #define EXTI_EMR_EM15 EXTI_EMR_MR15
7701 #define EXTI_EMR_EM16 EXTI_EMR_MR16
7702 #define EXTI_EMR_EM17 EXTI_EMR_MR17
7703 #define EXTI_EMR_EM18 EXTI_EMR_MR18
7704 #define EXTI_EMR_EM19 EXTI_EMR_MR19
7705 #define EXTI_EMR_EM20 EXTI_EMR_MR20
7706 #define EXTI_EMR_EM21 EXTI_EMR_MR21
7707 #define EXTI_EMR_EM22 EXTI_EMR_MR22
7708 #define EXTI_EMR_EM23 EXTI_EMR_MR23
7709 #define EXTI_EMR_EM24 EXTI_EMR_MR24
7710
7711
7712 /****************** Bit definition for EXTI_RTSR register *******************/
7713 #define EXTI_RTSR_TR0_Pos (0U)
7714 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
7715 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
7716 #define EXTI_RTSR_TR1_Pos (1U)
7717 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
7718 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
7719 #define EXTI_RTSR_TR2_Pos (2U)
7720 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
7721 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
7722 #define EXTI_RTSR_TR3_Pos (3U)
7723 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
7724 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
7725 #define EXTI_RTSR_TR4_Pos (4U)
7726 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
7727 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
7728 #define EXTI_RTSR_TR5_Pos (5U)
7729 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
7730 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
7731 #define EXTI_RTSR_TR6_Pos (6U)
7732 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
7733 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
7734 #define EXTI_RTSR_TR7_Pos (7U)
7735 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
7736 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
7737 #define EXTI_RTSR_TR8_Pos (8U)
7738 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
7739 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
7740 #define EXTI_RTSR_TR9_Pos (9U)
7741 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
7742 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
7743 #define EXTI_RTSR_TR10_Pos (10U)
7744 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
7745 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
7746 #define EXTI_RTSR_TR11_Pos (11U)
7747 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
7748 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
7749 #define EXTI_RTSR_TR12_Pos (12U)
7750 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
7751 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
7752 #define EXTI_RTSR_TR13_Pos (13U)
7753 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
7754 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
7755 #define EXTI_RTSR_TR14_Pos (14U)
7756 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
7757 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
7758 #define EXTI_RTSR_TR15_Pos (15U)
7759 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
7760 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
7761 #define EXTI_RTSR_TR16_Pos (16U)
7762 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
7763 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
7764 #define EXTI_RTSR_TR17_Pos (17U)
7765 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
7766 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
7767 #define EXTI_RTSR_TR18_Pos (18U)
7768 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
7769 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
7770 #define EXTI_RTSR_TR19_Pos (19U)
7771 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
7772 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
7773 #define EXTI_RTSR_TR20_Pos (20U)
7774 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
7775 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
7776 #define EXTI_RTSR_TR21_Pos (21U)
7777 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
7778 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
7779 #define EXTI_RTSR_TR22_Pos (22U)
7780 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
7781 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
7782 #define EXTI_RTSR_TR23_Pos (23U)
7783 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
7784 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
7785 #define EXTI_RTSR_TR24_Pos (24U)
7786 #define EXTI_RTSR_TR24_Msk (0x1U << EXTI_RTSR_TR24_Pos) /*!< 0x01000000 */
7787 #define EXTI_RTSR_TR24 EXTI_RTSR_TR24_Msk /*!< Rising trigger event configuration bit of line 24 */
7788
7789 /****************** Bit definition for EXTI_FTSR register *******************/
7790 #define EXTI_FTSR_TR0_Pos (0U)
7791 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
7792 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
7793 #define EXTI_FTSR_TR1_Pos (1U)
7794 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
7795 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
7796 #define EXTI_FTSR_TR2_Pos (2U)
7797 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
7798 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
7799 #define EXTI_FTSR_TR3_Pos (3U)
7800 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
7801 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
7802 #define EXTI_FTSR_TR4_Pos (4U)
7803 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
7804 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
7805 #define EXTI_FTSR_TR5_Pos (5U)
7806 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
7807 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
7808 #define EXTI_FTSR_TR6_Pos (6U)
7809 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
7810 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
7811 #define EXTI_FTSR_TR7_Pos (7U)
7812 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
7813 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
7814 #define EXTI_FTSR_TR8_Pos (8U)
7815 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
7816 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
7817 #define EXTI_FTSR_TR9_Pos (9U)
7818 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
7819 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
7820 #define EXTI_FTSR_TR10_Pos (10U)
7821 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
7822 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
7823 #define EXTI_FTSR_TR11_Pos (11U)
7824 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
7825 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
7826 #define EXTI_FTSR_TR12_Pos (12U)
7827 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
7828 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
7829 #define EXTI_FTSR_TR13_Pos (13U)
7830 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
7831 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
7832 #define EXTI_FTSR_TR14_Pos (14U)
7833 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
7834 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
7835 #define EXTI_FTSR_TR15_Pos (15U)
7836 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
7837 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
7838 #define EXTI_FTSR_TR16_Pos (16U)
7839 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
7840 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
7841 #define EXTI_FTSR_TR17_Pos (17U)
7842 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
7843 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
7844 #define EXTI_FTSR_TR18_Pos (18U)
7845 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
7846 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
7847 #define EXTI_FTSR_TR19_Pos (19U)
7848 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
7849 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
7850 #define EXTI_FTSR_TR20_Pos (20U)
7851 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
7852 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
7853 #define EXTI_FTSR_TR21_Pos (21U)
7854 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
7855 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
7856 #define EXTI_FTSR_TR22_Pos (22U)
7857 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
7858 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
7859 #define EXTI_FTSR_TR23_Pos (23U)
7860 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
7861 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
7862 #define EXTI_FTSR_TR24_Pos (24U)
7863 #define EXTI_FTSR_TR24_Msk (0x1U << EXTI_FTSR_TR24_Pos) /*!< 0x01000000 */
7864 #define EXTI_FTSR_TR24 EXTI_FTSR_TR24_Msk /*!< Falling trigger event configuration bit of line 24 */
7865
7866 /****************** Bit definition for EXTI_SWIER register ******************/
7867 #define EXTI_SWIER_SWIER0_Pos (0U)
7868 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
7869 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
7870 #define EXTI_SWIER_SWIER1_Pos (1U)
7871 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
7872 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
7873 #define EXTI_SWIER_SWIER2_Pos (2U)
7874 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
7875 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
7876 #define EXTI_SWIER_SWIER3_Pos (3U)
7877 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
7878 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
7879 #define EXTI_SWIER_SWIER4_Pos (4U)
7880 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
7881 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
7882 #define EXTI_SWIER_SWIER5_Pos (5U)
7883 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
7884 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
7885 #define EXTI_SWIER_SWIER6_Pos (6U)
7886 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
7887 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
7888 #define EXTI_SWIER_SWIER7_Pos (7U)
7889 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
7890 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
7891 #define EXTI_SWIER_SWIER8_Pos (8U)
7892 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
7893 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
7894 #define EXTI_SWIER_SWIER9_Pos (9U)
7895 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
7896 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
7897 #define EXTI_SWIER_SWIER10_Pos (10U)
7898 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
7899 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
7900 #define EXTI_SWIER_SWIER11_Pos (11U)
7901 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
7902 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
7903 #define EXTI_SWIER_SWIER12_Pos (12U)
7904 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
7905 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
7906 #define EXTI_SWIER_SWIER13_Pos (13U)
7907 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
7908 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
7909 #define EXTI_SWIER_SWIER14_Pos (14U)
7910 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
7911 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
7912 #define EXTI_SWIER_SWIER15_Pos (15U)
7913 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
7914 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
7915 #define EXTI_SWIER_SWIER16_Pos (16U)
7916 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
7917 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
7918 #define EXTI_SWIER_SWIER17_Pos (17U)
7919 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
7920 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
7921 #define EXTI_SWIER_SWIER18_Pos (18U)
7922 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
7923 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
7924 #define EXTI_SWIER_SWIER19_Pos (19U)
7925 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
7926 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
7927 #define EXTI_SWIER_SWIER20_Pos (20U)
7928 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
7929 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
7930 #define EXTI_SWIER_SWIER21_Pos (21U)
7931 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
7932 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
7933 #define EXTI_SWIER_SWIER22_Pos (22U)
7934 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
7935 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
7936 #define EXTI_SWIER_SWIER23_Pos (23U)
7937 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
7938 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
7939 #define EXTI_SWIER_SWIER24_Pos (24U)
7940 #define EXTI_SWIER_SWIER24_Msk (0x1U << EXTI_SWIER_SWIER24_Pos) /*!< 0x01000000 */
7941 #define EXTI_SWIER_SWIER24 EXTI_SWIER_SWIER24_Msk /*!< Software Interrupt on line 24 */
7942
7943 /******************* Bit definition for EXTI_PR register ********************/
7944 #define EXTI_PR_PR0_Pos (0U)
7945 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
7946 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
7947 #define EXTI_PR_PR1_Pos (1U)
7948 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
7949 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
7950 #define EXTI_PR_PR2_Pos (2U)
7951 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
7952 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
7953 #define EXTI_PR_PR3_Pos (3U)
7954 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
7955 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
7956 #define EXTI_PR_PR4_Pos (4U)
7957 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
7958 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
7959 #define EXTI_PR_PR5_Pos (5U)
7960 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
7961 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
7962 #define EXTI_PR_PR6_Pos (6U)
7963 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
7964 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
7965 #define EXTI_PR_PR7_Pos (7U)
7966 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
7967 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
7968 #define EXTI_PR_PR8_Pos (8U)
7969 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
7970 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
7971 #define EXTI_PR_PR9_Pos (9U)
7972 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
7973 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
7974 #define EXTI_PR_PR10_Pos (10U)
7975 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
7976 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
7977 #define EXTI_PR_PR11_Pos (11U)
7978 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
7979 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
7980 #define EXTI_PR_PR12_Pos (12U)
7981 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
7982 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
7983 #define EXTI_PR_PR13_Pos (13U)
7984 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
7985 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
7986 #define EXTI_PR_PR14_Pos (14U)
7987 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
7988 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
7989 #define EXTI_PR_PR15_Pos (15U)
7990 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
7991 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
7992 #define EXTI_PR_PR16_Pos (16U)
7993 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
7994 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
7995 #define EXTI_PR_PR17_Pos (17U)
7996 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
7997 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
7998 #define EXTI_PR_PR18_Pos (18U)
7999 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
8000 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
8001 #define EXTI_PR_PR19_Pos (19U)
8002 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
8003 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
8004 #define EXTI_PR_PR20_Pos (20U)
8005 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
8006 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
8007 #define EXTI_PR_PR21_Pos (21U)
8008 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
8009 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
8010 #define EXTI_PR_PR22_Pos (22U)
8011 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
8012 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
8013 #define EXTI_PR_PR23_Pos (23U)
8014 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
8015 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
8016 #define EXTI_PR_PR24_Pos (24U)
8017 #define EXTI_PR_PR24_Msk (0x1U << EXTI_PR_PR24_Pos) /*!< 0x01000000 */
8018 #define EXTI_PR_PR24 EXTI_PR_PR24_Msk /*!< Pending bit for line 24 */
8019
8020 /******************************************************************************/
8021 /* */
8022 /* FLASH */
8023 /* */
8024 /******************************************************************************/
8025 /*
8026 * @brief FLASH Total Sectors Number
8027 */
8028 #define FLASH_SECTOR_TOTAL 24
8029
8030 /******************* Bits definition for FLASH_ACR register *****************/
8031 #define FLASH_ACR_LATENCY_Pos (0U)
8032 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
8033 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
8034 #define FLASH_ACR_LATENCY_0WS 0x00000000U
8035 #define FLASH_ACR_LATENCY_1WS 0x00000001U
8036 #define FLASH_ACR_LATENCY_2WS 0x00000002U
8037 #define FLASH_ACR_LATENCY_3WS 0x00000003U
8038 #define FLASH_ACR_LATENCY_4WS 0x00000004U
8039 #define FLASH_ACR_LATENCY_5WS 0x00000005U
8040 #define FLASH_ACR_LATENCY_6WS 0x00000006U
8041 #define FLASH_ACR_LATENCY_7WS 0x00000007U
8042 #define FLASH_ACR_LATENCY_8WS 0x00000008U
8043 #define FLASH_ACR_LATENCY_9WS 0x00000009U
8044 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
8045 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
8046 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
8047 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
8048 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
8049 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
8050 #define FLASH_ACR_PRFTEN_Pos (8U)
8051 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
8052 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
8053 #define FLASH_ACR_ARTEN_Pos (9U)
8054 #define FLASH_ACR_ARTEN_Msk (0x1U << FLASH_ACR_ARTEN_Pos) /*!< 0x00000200 */
8055 #define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
8056 #define FLASH_ACR_ARTRST_Pos (11U)
8057 #define FLASH_ACR_ARTRST_Msk (0x1U << FLASH_ACR_ARTRST_Pos) /*!< 0x00000800 */
8058 #define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
8059
8060 /******************* Bits definition for FLASH_SR register ******************/
8061 #define FLASH_SR_EOP_Pos (0U)
8062 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
8063 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
8064 #define FLASH_SR_OPERR_Pos (1U)
8065 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
8066 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
8067 #define FLASH_SR_WRPERR_Pos (4U)
8068 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
8069 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
8070 #define FLASH_SR_PGAERR_Pos (5U)
8071 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
8072 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
8073 #define FLASH_SR_PGPERR_Pos (6U)
8074 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
8075 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
8076 #define FLASH_SR_ERSERR_Pos (7U)
8077 #define FLASH_SR_ERSERR_Msk (0x1U << FLASH_SR_ERSERR_Pos) /*!< 0x00000080 */
8078 #define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
8079 #define FLASH_SR_BSY_Pos (16U)
8080 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
8081 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
8082
8083 /******************* Bits definition for FLASH_CR register ******************/
8084 #define FLASH_CR_PG_Pos (0U)
8085 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
8086 #define FLASH_CR_PG FLASH_CR_PG_Msk
8087 #define FLASH_CR_SER_Pos (1U)
8088 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
8089 #define FLASH_CR_SER FLASH_CR_SER_Msk
8090 #define FLASH_CR_MER_Pos (2U)
8091 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
8092 #define FLASH_CR_MER FLASH_CR_MER_Msk
8093 #define FLASH_CR_MER1 FLASH_CR_MER
8094 #define FLASH_CR_SNB_Pos (3U)
8095 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
8096 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
8097 #define FLASH_CR_SNB_0 0x00000008U
8098 #define FLASH_CR_SNB_1 0x00000010U
8099 #define FLASH_CR_SNB_2 0x00000020U
8100 #define FLASH_CR_SNB_3 0x00000040U
8101 #define FLASH_CR_SNB_4 0x00000080U
8102 #define FLASH_CR_PSIZE_Pos (8U)
8103 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
8104 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
8105 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
8106 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
8107 #define FLASH_CR_MER2_Pos (15U)
8108 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
8109 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
8110 #define FLASH_CR_STRT_Pos (16U)
8111 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
8112 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
8113 #define FLASH_CR_EOPIE_Pos (24U)
8114 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
8115 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
8116 #define FLASH_CR_ERRIE_Pos (25U)
8117 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
8118 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
8119 #define FLASH_CR_LOCK_Pos (31U)
8120 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
8121 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
8122
8123 /******************* Bits definition for FLASH_OPTCR register ***************/
8124 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
8125 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
8126 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
8127 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
8128 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
8129 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
8130 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
8131 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
8132 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
8133 #define FLASH_OPTCR_BOR_LEV_0 (0x1U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000004 */
8134 #define FLASH_OPTCR_BOR_LEV_1 (0x2U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000008 */
8135 #define FLASH_OPTCR_WWDG_SW_Pos (4U)
8136 #define FLASH_OPTCR_WWDG_SW_Msk (0x1U << FLASH_OPTCR_WWDG_SW_Pos) /*!< 0x00000010 */
8137 #define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk
8138 #define FLASH_OPTCR_IWDG_SW_Pos (5U)
8139 #define FLASH_OPTCR_IWDG_SW_Msk (0x1U << FLASH_OPTCR_IWDG_SW_Pos) /*!< 0x00000020 */
8140 #define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk
8141 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
8142 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
8143 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
8144 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
8145 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
8146 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
8147 #define FLASH_OPTCR_RDP_Pos (8U)
8148 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
8149 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
8150 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
8151 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
8152 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
8153 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
8154 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
8155 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
8156 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
8157 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
8158 #define FLASH_OPTCR_nWRP_Pos (16U)
8159 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
8160 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
8161 #define FLASH_OPTCR_nWRP_0 0x00010000U
8162 #define FLASH_OPTCR_nWRP_1 0x00020000U
8163 #define FLASH_OPTCR_nWRP_2 0x00040000U
8164 #define FLASH_OPTCR_nWRP_3 0x00080000U
8165 #define FLASH_OPTCR_nWRP_4 0x00100000U
8166 #define FLASH_OPTCR_nWRP_5 0x00200000U
8167 #define FLASH_OPTCR_nWRP_6 0x00400000U
8168 #define FLASH_OPTCR_nWRP_7 0x00800000U
8169 #define FLASH_OPTCR_nWRP_8 0x01000000U
8170 #define FLASH_OPTCR_nWRP_9 0x02000000U
8171 #define FLASH_OPTCR_nWRP_10 0x04000000U
8172 #define FLASH_OPTCR_nWRP_11 0x08000000U
8173 #define FLASH_OPTCR_nDBOOT_Pos (28U)
8174 #define FLASH_OPTCR_nDBOOT_Msk (0x1U << FLASH_OPTCR_nDBOOT_Pos) /*!< 0x10000000 */
8175 #define FLASH_OPTCR_nDBOOT FLASH_OPTCR_nDBOOT_Msk
8176 #define FLASH_OPTCR_nDBANK_Pos (29U)
8177 #define FLASH_OPTCR_nDBANK_Msk (0x1U << FLASH_OPTCR_nDBANK_Pos) /*!< 0x20000000 */
8178 #define FLASH_OPTCR_nDBANK FLASH_OPTCR_nDBANK_Msk
8179 #define FLASH_OPTCR_IWDG_STDBY_Pos (30U)
8180 #define FLASH_OPTCR_IWDG_STDBY_Msk (0x1U << FLASH_OPTCR_IWDG_STDBY_Pos) /*!< 0x40000000 */
8181 #define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk
8182 #define FLASH_OPTCR_IWDG_STOP_Pos (31U)
8183 #define FLASH_OPTCR_IWDG_STOP_Msk (0x1U << FLASH_OPTCR_IWDG_STOP_Pos) /*!< 0x80000000 */
8184 #define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk
8185
8186 /******************* Bits definition for FLASH_OPTCR1 register ***************/
8187 #define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)
8188 #define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFU << FLASH_OPTCR1_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
8189 #define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk
8190 #define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)
8191 #define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFU << FLASH_OPTCR1_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
8192 #define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk
8193
8194
8195 /******************************************************************************/
8196 /* */
8197 /* Flexible Memory Controller */
8198 /* */
8199 /******************************************************************************/
8200 /****************** Bit definition for FMC_BCR1 register *******************/
8201 #define FMC_BCR1_MBKEN_Pos (0U)
8202 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
8203 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
8204 #define FMC_BCR1_MUXEN_Pos (1U)
8205 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
8206 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8207 #define FMC_BCR1_MTYP_Pos (2U)
8208 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
8209 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8210 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
8211 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
8212 #define FMC_BCR1_MWID_Pos (4U)
8213 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
8214 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8215 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
8216 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
8217 #define FMC_BCR1_FACCEN_Pos (6U)
8218 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
8219 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
8220 #define FMC_BCR1_BURSTEN_Pos (8U)
8221 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
8222 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
8223 #define FMC_BCR1_WAITPOL_Pos (9U)
8224 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
8225 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
8226 #define FMC_BCR1_WRAPMOD_Pos (10U)
8227 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
8228 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
8229 #define FMC_BCR1_WAITCFG_Pos (11U)
8230 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
8231 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
8232 #define FMC_BCR1_WREN_Pos (12U)
8233 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
8234 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
8235 #define FMC_BCR1_WAITEN_Pos (13U)
8236 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
8237 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
8238 #define FMC_BCR1_EXTMOD_Pos (14U)
8239 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
8240 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
8241 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
8242 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
8243 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
8244 #define FMC_BCR1_CPSIZE_Pos (16U)
8245 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
8246 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
8247 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
8248 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
8249 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
8250 #define FMC_BCR1_CBURSTRW_Pos (19U)
8251 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
8252 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
8253 #define FMC_BCR1_CCLKEN_Pos (20U)
8254 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
8255 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
8256 #define FMC_BCR1_WFDIS_Pos (21U)
8257 #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
8258 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
8259
8260 /****************** Bit definition for FMC_BCR2 register *******************/
8261 #define FMC_BCR2_MBKEN_Pos (0U)
8262 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
8263 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
8264 #define FMC_BCR2_MUXEN_Pos (1U)
8265 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
8266 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8267 #define FMC_BCR2_MTYP_Pos (2U)
8268 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
8269 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8270 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
8271 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
8272 #define FMC_BCR2_MWID_Pos (4U)
8273 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
8274 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8275 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
8276 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
8277 #define FMC_BCR2_FACCEN_Pos (6U)
8278 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
8279 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
8280 #define FMC_BCR2_BURSTEN_Pos (8U)
8281 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
8282 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
8283 #define FMC_BCR2_WAITPOL_Pos (9U)
8284 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
8285 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
8286 #define FMC_BCR2_WRAPMOD_Pos (10U)
8287 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
8288 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
8289 #define FMC_BCR2_WAITCFG_Pos (11U)
8290 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
8291 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
8292 #define FMC_BCR2_WREN_Pos (12U)
8293 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
8294 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
8295 #define FMC_BCR2_WAITEN_Pos (13U)
8296 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
8297 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
8298 #define FMC_BCR2_EXTMOD_Pos (14U)
8299 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
8300 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
8301 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
8302 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
8303 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
8304 #define FMC_BCR2_CPSIZE_Pos (16U)
8305 #define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
8306 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
8307 #define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
8308 #define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
8309 #define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
8310 #define FMC_BCR2_CBURSTRW_Pos (19U)
8311 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
8312 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
8313
8314 /****************** Bit definition for FMC_BCR3 register *******************/
8315 #define FMC_BCR3_MBKEN_Pos (0U)
8316 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
8317 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
8318 #define FMC_BCR3_MUXEN_Pos (1U)
8319 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
8320 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8321 #define FMC_BCR3_MTYP_Pos (2U)
8322 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
8323 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8324 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
8325 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
8326 #define FMC_BCR3_MWID_Pos (4U)
8327 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
8328 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8329 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
8330 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
8331 #define FMC_BCR3_FACCEN_Pos (6U)
8332 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
8333 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
8334 #define FMC_BCR3_BURSTEN_Pos (8U)
8335 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
8336 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
8337 #define FMC_BCR3_WAITPOL_Pos (9U)
8338 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
8339 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
8340 #define FMC_BCR3_WRAPMOD_Pos (10U)
8341 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
8342 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
8343 #define FMC_BCR3_WAITCFG_Pos (11U)
8344 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
8345 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
8346 #define FMC_BCR3_WREN_Pos (12U)
8347 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
8348 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
8349 #define FMC_BCR3_WAITEN_Pos (13U)
8350 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
8351 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
8352 #define FMC_BCR3_EXTMOD_Pos (14U)
8353 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
8354 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
8355 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
8356 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
8357 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
8358 #define FMC_BCR3_CPSIZE_Pos (16U)
8359 #define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
8360 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
8361 #define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
8362 #define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
8363 #define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
8364 #define FMC_BCR3_CBURSTRW_Pos (19U)
8365 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
8366 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
8367
8368 /****************** Bit definition for FMC_BCR4 register *******************/
8369 #define FMC_BCR4_MBKEN_Pos (0U)
8370 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
8371 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
8372 #define FMC_BCR4_MUXEN_Pos (1U)
8373 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
8374 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8375 #define FMC_BCR4_MTYP_Pos (2U)
8376 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
8377 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8378 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
8379 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
8380 #define FMC_BCR4_MWID_Pos (4U)
8381 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
8382 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8383 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
8384 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
8385 #define FMC_BCR4_FACCEN_Pos (6U)
8386 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
8387 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
8388 #define FMC_BCR4_BURSTEN_Pos (8U)
8389 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
8390 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
8391 #define FMC_BCR4_WAITPOL_Pos (9U)
8392 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
8393 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
8394 #define FMC_BCR4_WRAPMOD_Pos (10U)
8395 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
8396 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
8397 #define FMC_BCR4_WAITCFG_Pos (11U)
8398 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
8399 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
8400 #define FMC_BCR4_WREN_Pos (12U)
8401 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
8402 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
8403 #define FMC_BCR4_WAITEN_Pos (13U)
8404 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
8405 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
8406 #define FMC_BCR4_EXTMOD_Pos (14U)
8407 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
8408 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
8409 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
8410 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
8411 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
8412 #define FMC_BCR4_CPSIZE_Pos (16U)
8413 #define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
8414 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
8415 #define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
8416 #define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
8417 #define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
8418 #define FMC_BCR4_CBURSTRW_Pos (19U)
8419 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
8420 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
8421
8422 /****************** Bit definition for FMC_BTR1 register ******************/
8423 #define FMC_BTR1_ADDSET_Pos (0U)
8424 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
8425 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8426 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
8427 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
8428 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
8429 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
8430 #define FMC_BTR1_ADDHLD_Pos (4U)
8431 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
8432 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8433 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
8434 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
8435 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
8436 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
8437 #define FMC_BTR1_DATAST_Pos (8U)
8438 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
8439 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8440 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
8441 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
8442 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
8443 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
8444 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
8445 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
8446 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
8447 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
8448 #define FMC_BTR1_BUSTURN_Pos (16U)
8449 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
8450 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8451 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
8452 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
8453 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
8454 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
8455 #define FMC_BTR1_CLKDIV_Pos (20U)
8456 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
8457 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8458 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
8459 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
8460 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
8461 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
8462 #define FMC_BTR1_DATLAT_Pos (24U)
8463 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
8464 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8465 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
8466 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
8467 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
8468 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
8469 #define FMC_BTR1_ACCMOD_Pos (28U)
8470 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
8471 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8472 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
8473 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
8474
8475 /****************** Bit definition for FMC_BTR2 register *******************/
8476 #define FMC_BTR2_ADDSET_Pos (0U)
8477 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
8478 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8479 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
8480 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
8481 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
8482 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
8483 #define FMC_BTR2_ADDHLD_Pos (4U)
8484 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
8485 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8486 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
8487 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
8488 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
8489 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
8490 #define FMC_BTR2_DATAST_Pos (8U)
8491 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
8492 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8493 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
8494 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
8495 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
8496 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
8497 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
8498 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
8499 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
8500 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
8501 #define FMC_BTR2_BUSTURN_Pos (16U)
8502 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
8503 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8504 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
8505 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
8506 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
8507 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
8508 #define FMC_BTR2_CLKDIV_Pos (20U)
8509 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
8510 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8511 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
8512 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
8513 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
8514 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
8515 #define FMC_BTR2_DATLAT_Pos (24U)
8516 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
8517 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8518 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
8519 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
8520 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
8521 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
8522 #define FMC_BTR2_ACCMOD_Pos (28U)
8523 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
8524 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8525 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
8526 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
8527
8528 /******************* Bit definition for FMC_BTR3 register *******************/
8529 #define FMC_BTR3_ADDSET_Pos (0U)
8530 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
8531 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8532 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
8533 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
8534 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
8535 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
8536 #define FMC_BTR3_ADDHLD_Pos (4U)
8537 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
8538 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8539 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
8540 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
8541 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
8542 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
8543 #define FMC_BTR3_DATAST_Pos (8U)
8544 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
8545 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8546 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
8547 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
8548 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
8549 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
8550 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
8551 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
8552 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
8553 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
8554 #define FMC_BTR3_BUSTURN_Pos (16U)
8555 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
8556 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8557 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
8558 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
8559 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
8560 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
8561 #define FMC_BTR3_CLKDIV_Pos (20U)
8562 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
8563 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8564 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
8565 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
8566 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
8567 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
8568 #define FMC_BTR3_DATLAT_Pos (24U)
8569 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
8570 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8571 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
8572 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
8573 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
8574 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
8575 #define FMC_BTR3_ACCMOD_Pos (28U)
8576 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
8577 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8578 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
8579 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
8580
8581 /****************** Bit definition for FMC_BTR4 register *******************/
8582 #define FMC_BTR4_ADDSET_Pos (0U)
8583 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
8584 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8585 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
8586 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
8587 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
8588 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
8589 #define FMC_BTR4_ADDHLD_Pos (4U)
8590 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
8591 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8592 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
8593 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
8594 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
8595 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
8596 #define FMC_BTR4_DATAST_Pos (8U)
8597 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
8598 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8599 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
8600 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
8601 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
8602 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
8603 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
8604 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
8605 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
8606 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
8607 #define FMC_BTR4_BUSTURN_Pos (16U)
8608 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
8609 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8610 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
8611 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
8612 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
8613 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
8614 #define FMC_BTR4_CLKDIV_Pos (20U)
8615 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
8616 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8617 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
8618 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
8619 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
8620 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
8621 #define FMC_BTR4_DATLAT_Pos (24U)
8622 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
8623 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8624 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
8625 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
8626 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
8627 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
8628 #define FMC_BTR4_ACCMOD_Pos (28U)
8629 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
8630 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8631 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
8632 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
8633
8634 /****************** Bit definition for FMC_BWTR1 register ******************/
8635 #define FMC_BWTR1_ADDSET_Pos (0U)
8636 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
8637 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8638 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
8639 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
8640 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
8641 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
8642 #define FMC_BWTR1_ADDHLD_Pos (4U)
8643 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
8644 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8645 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
8646 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
8647 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
8648 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
8649 #define FMC_BWTR1_DATAST_Pos (8U)
8650 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
8651 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8652 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
8653 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
8654 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
8655 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
8656 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
8657 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
8658 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
8659 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
8660 #define FMC_BWTR1_BUSTURN_Pos (16U)
8661 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
8662 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8663 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
8664 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
8665 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
8666 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
8667 #define FMC_BWTR1_ACCMOD_Pos (28U)
8668 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
8669 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8670 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
8671 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
8672
8673 /****************** Bit definition for FMC_BWTR2 register ******************/
8674 #define FMC_BWTR2_ADDSET_Pos (0U)
8675 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
8676 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8677 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
8678 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
8679 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
8680 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
8681 #define FMC_BWTR2_ADDHLD_Pos (4U)
8682 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
8683 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8684 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
8685 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
8686 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
8687 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
8688 #define FMC_BWTR2_DATAST_Pos (8U)
8689 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
8690 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8691 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
8692 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
8693 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
8694 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
8695 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
8696 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
8697 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
8698 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
8699 #define FMC_BWTR2_BUSTURN_Pos (16U)
8700 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
8701 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8702 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
8703 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
8704 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
8705 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
8706 #define FMC_BWTR2_ACCMOD_Pos (28U)
8707 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
8708 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8709 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
8710 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
8711
8712 /****************** Bit definition for FMC_BWTR3 register ******************/
8713 #define FMC_BWTR3_ADDSET_Pos (0U)
8714 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
8715 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8716 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
8717 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
8718 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
8719 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
8720 #define FMC_BWTR3_ADDHLD_Pos (4U)
8721 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
8722 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8723 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
8724 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
8725 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
8726 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
8727 #define FMC_BWTR3_DATAST_Pos (8U)
8728 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
8729 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8730 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
8731 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
8732 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
8733 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
8734 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
8735 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
8736 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
8737 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
8738 #define FMC_BWTR3_BUSTURN_Pos (16U)
8739 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
8740 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8741 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
8742 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
8743 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
8744 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
8745 #define FMC_BWTR3_ACCMOD_Pos (28U)
8746 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
8747 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8748 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
8749 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
8750
8751 /****************** Bit definition for FMC_BWTR4 register ******************/
8752 #define FMC_BWTR4_ADDSET_Pos (0U)
8753 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
8754 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8755 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
8756 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
8757 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
8758 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
8759 #define FMC_BWTR4_ADDHLD_Pos (4U)
8760 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
8761 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8762 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
8763 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
8764 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
8765 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
8766 #define FMC_BWTR4_DATAST_Pos (8U)
8767 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
8768 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8769 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
8770 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
8771 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
8772 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
8773 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
8774 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
8775 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
8776 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
8777 #define FMC_BWTR4_BUSTURN_Pos (16U)
8778 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
8779 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8780 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
8781 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
8782 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
8783 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
8784 #define FMC_BWTR4_ACCMOD_Pos (28U)
8785 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
8786 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8787 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
8788 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
8789
8790 /****************** Bit definition for FMC_PCR register *******************/
8791 #define FMC_PCR_PWAITEN_Pos (1U)
8792 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
8793 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
8794 #define FMC_PCR_PBKEN_Pos (2U)
8795 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
8796 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
8797 #define FMC_PCR_PTYP_Pos (3U)
8798 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
8799 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
8800 #define FMC_PCR_PWID_Pos (4U)
8801 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
8802 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
8803 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
8804 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
8805 #define FMC_PCR_ECCEN_Pos (6U)
8806 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
8807 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
8808 #define FMC_PCR_TCLR_Pos (9U)
8809 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
8810 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
8811 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
8812 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
8813 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
8814 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
8815 #define FMC_PCR_TAR_Pos (13U)
8816 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
8817 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
8818 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
8819 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
8820 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
8821 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
8822 #define FMC_PCR_ECCPS_Pos (17U)
8823 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
8824 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
8825 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
8826 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
8827 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
8828
8829 /******************* Bit definition for FMC_SR register *******************/
8830 #define FMC_SR_IRS_Pos (0U)
8831 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
8832 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
8833 #define FMC_SR_ILS_Pos (1U)
8834 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
8835 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
8836 #define FMC_SR_IFS_Pos (2U)
8837 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
8838 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
8839 #define FMC_SR_IREN_Pos (3U)
8840 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
8841 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8842 #define FMC_SR_ILEN_Pos (4U)
8843 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
8844 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8845 #define FMC_SR_IFEN_Pos (5U)
8846 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
8847 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8848 #define FMC_SR_FEMPT_Pos (6U)
8849 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
8850 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
8851
8852 /****************** Bit definition for FMC_PMEM register ******************/
8853 #define FMC_PMEM_MEMSET3_Pos (0U)
8854 #define FMC_PMEM_MEMSET3_Msk (0xFFU << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */
8855 #define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
8856 #define FMC_PMEM_MEMSET3_0 (0x01U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */
8857 #define FMC_PMEM_MEMSET3_1 (0x02U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */
8858 #define FMC_PMEM_MEMSET3_2 (0x04U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */
8859 #define FMC_PMEM_MEMSET3_3 (0x08U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */
8860 #define FMC_PMEM_MEMSET3_4 (0x10U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */
8861 #define FMC_PMEM_MEMSET3_5 (0x20U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */
8862 #define FMC_PMEM_MEMSET3_6 (0x40U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */
8863 #define FMC_PMEM_MEMSET3_7 (0x80U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */
8864 #define FMC_PMEM_MEMWAIT3_Pos (8U)
8865 #define FMC_PMEM_MEMWAIT3_Msk (0xFFU << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */
8866 #define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
8867 #define FMC_PMEM_MEMWAIT3_0 (0x01U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */
8868 #define FMC_PMEM_MEMWAIT3_1 (0x02U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */
8869 #define FMC_PMEM_MEMWAIT3_2 (0x04U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */
8870 #define FMC_PMEM_MEMWAIT3_3 (0x08U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */
8871 #define FMC_PMEM_MEMWAIT3_4 (0x10U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */
8872 #define FMC_PMEM_MEMWAIT3_5 (0x20U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */
8873 #define FMC_PMEM_MEMWAIT3_6 (0x40U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */
8874 #define FMC_PMEM_MEMWAIT3_7 (0x80U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */
8875 #define FMC_PMEM_MEMHOLD3_Pos (16U)
8876 #define FMC_PMEM_MEMHOLD3_Msk (0xFFU << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */
8877 #define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
8878 #define FMC_PMEM_MEMHOLD3_0 (0x01U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */
8879 #define FMC_PMEM_MEMHOLD3_1 (0x02U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */
8880 #define FMC_PMEM_MEMHOLD3_2 (0x04U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */
8881 #define FMC_PMEM_MEMHOLD3_3 (0x08U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */
8882 #define FMC_PMEM_MEMHOLD3_4 (0x10U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */
8883 #define FMC_PMEM_MEMHOLD3_5 (0x20U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */
8884 #define FMC_PMEM_MEMHOLD3_6 (0x40U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */
8885 #define FMC_PMEM_MEMHOLD3_7 (0x80U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */
8886 #define FMC_PMEM_MEMHIZ3_Pos (24U)
8887 #define FMC_PMEM_MEMHIZ3_Msk (0xFFU << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */
8888 #define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
8889 #define FMC_PMEM_MEMHIZ3_0 (0x01U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */
8890 #define FMC_PMEM_MEMHIZ3_1 (0x02U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */
8891 #define FMC_PMEM_MEMHIZ3_2 (0x04U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */
8892 #define FMC_PMEM_MEMHIZ3_3 (0x08U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */
8893 #define FMC_PMEM_MEMHIZ3_4 (0x10U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */
8894 #define FMC_PMEM_MEMHIZ3_5 (0x20U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */
8895 #define FMC_PMEM_MEMHIZ3_6 (0x40U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */
8896 #define FMC_PMEM_MEMHIZ3_7 (0x80U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */
8897
8898 /****************** Bit definition for FMC_PATT register ******************/
8899 #define FMC_PATT_ATTSET3_Pos (0U)
8900 #define FMC_PATT_ATTSET3_Msk (0xFFU << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */
8901 #define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
8902 #define FMC_PATT_ATTSET3_0 (0x01U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */
8903 #define FMC_PATT_ATTSET3_1 (0x02U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */
8904 #define FMC_PATT_ATTSET3_2 (0x04U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */
8905 #define FMC_PATT_ATTSET3_3 (0x08U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */
8906 #define FMC_PATT_ATTSET3_4 (0x10U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */
8907 #define FMC_PATT_ATTSET3_5 (0x20U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */
8908 #define FMC_PATT_ATTSET3_6 (0x40U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */
8909 #define FMC_PATT_ATTSET3_7 (0x80U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */
8910 #define FMC_PATT_ATTWAIT3_Pos (8U)
8911 #define FMC_PATT_ATTWAIT3_Msk (0xFFU << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */
8912 #define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
8913 #define FMC_PATT_ATTWAIT3_0 (0x01U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */
8914 #define FMC_PATT_ATTWAIT3_1 (0x02U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */
8915 #define FMC_PATT_ATTWAIT3_2 (0x04U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */
8916 #define FMC_PATT_ATTWAIT3_3 (0x08U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */
8917 #define FMC_PATT_ATTWAIT3_4 (0x10U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */
8918 #define FMC_PATT_ATTWAIT3_5 (0x20U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */
8919 #define FMC_PATT_ATTWAIT3_6 (0x40U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */
8920 #define FMC_PATT_ATTWAIT3_7 (0x80U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */
8921 #define FMC_PATT_ATTHOLD3_Pos (16U)
8922 #define FMC_PATT_ATTHOLD3_Msk (0xFFU << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */
8923 #define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
8924 #define FMC_PATT_ATTHOLD3_0 (0x01U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */
8925 #define FMC_PATT_ATTHOLD3_1 (0x02U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */
8926 #define FMC_PATT_ATTHOLD3_2 (0x04U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */
8927 #define FMC_PATT_ATTHOLD3_3 (0x08U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */
8928 #define FMC_PATT_ATTHOLD3_4 (0x10U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */
8929 #define FMC_PATT_ATTHOLD3_5 (0x20U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */
8930 #define FMC_PATT_ATTHOLD3_6 (0x40U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */
8931 #define FMC_PATT_ATTHOLD3_7 (0x80U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */
8932 #define FMC_PATT_ATTHIZ3_Pos (24U)
8933 #define FMC_PATT_ATTHIZ3_Msk (0xFFU << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */
8934 #define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
8935 #define FMC_PATT_ATTHIZ3_0 (0x01U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */
8936 #define FMC_PATT_ATTHIZ3_1 (0x02U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */
8937 #define FMC_PATT_ATTHIZ3_2 (0x04U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */
8938 #define FMC_PATT_ATTHIZ3_3 (0x08U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */
8939 #define FMC_PATT_ATTHIZ3_4 (0x10U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */
8940 #define FMC_PATT_ATTHIZ3_5 (0x20U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */
8941 #define FMC_PATT_ATTHIZ3_6 (0x40U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */
8942 #define FMC_PATT_ATTHIZ3_7 (0x80U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */
8943
8944 /****************** Bit definition for FMC_ECCR register ******************/
8945 #define FMC_ECCR_ECC3_Pos (0U)
8946 #define FMC_ECCR_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR_ECC3_Pos) /*!< 0xFFFFFFFF */
8947 #define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk /*!<ECC result */
8948
8949 /****************** Bit definition for FMC_SDCR1 register ******************/
8950 #define FMC_SDCR1_NC_Pos (0U)
8951 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
8952 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
8953 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
8954 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
8955 #define FMC_SDCR1_NR_Pos (2U)
8956 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
8957 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
8958 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
8959 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
8960 #define FMC_SDCR1_MWID_Pos (4U)
8961 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
8962 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
8963 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
8964 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
8965 #define FMC_SDCR1_NB_Pos (6U)
8966 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
8967 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
8968 #define FMC_SDCR1_CAS_Pos (7U)
8969 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
8970 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
8971 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
8972 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
8973 #define FMC_SDCR1_WP_Pos (9U)
8974 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
8975 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
8976 #define FMC_SDCR1_SDCLK_Pos (10U)
8977 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
8978 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
8979 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
8980 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
8981 #define FMC_SDCR1_RBURST_Pos (12U)
8982 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
8983 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
8984 #define FMC_SDCR1_RPIPE_Pos (13U)
8985 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
8986 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
8987 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
8988 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
8989
8990 /****************** Bit definition for FMC_SDCR2 register ******************/
8991 #define FMC_SDCR2_NC_Pos (0U)
8992 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
8993 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
8994 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
8995 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
8996 #define FMC_SDCR2_NR_Pos (2U)
8997 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
8998 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
8999 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
9000 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
9001 #define FMC_SDCR2_MWID_Pos (4U)
9002 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
9003 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
9004 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
9005 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
9006 #define FMC_SDCR2_NB_Pos (6U)
9007 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
9008 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
9009 #define FMC_SDCR2_CAS_Pos (7U)
9010 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
9011 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
9012 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
9013 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
9014 #define FMC_SDCR2_WP_Pos (9U)
9015 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
9016 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
9017 #define FMC_SDCR2_SDCLK_Pos (10U)
9018 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
9019 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
9020 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
9021 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
9022 #define FMC_SDCR2_RBURST_Pos (12U)
9023 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
9024 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
9025 #define FMC_SDCR2_RPIPE_Pos (13U)
9026 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
9027 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
9028 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
9029 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
9030
9031 /****************** Bit definition for FMC_SDTR1 register ******************/
9032 #define FMC_SDTR1_TMRD_Pos (0U)
9033 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
9034 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
9035 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
9036 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
9037 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
9038 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
9039 #define FMC_SDTR1_TXSR_Pos (4U)
9040 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
9041 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
9042 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
9043 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
9044 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
9045 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
9046 #define FMC_SDTR1_TRAS_Pos (8U)
9047 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
9048 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
9049 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
9050 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
9051 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
9052 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
9053 #define FMC_SDTR1_TRC_Pos (12U)
9054 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
9055 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
9056 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
9057 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
9058 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
9059 #define FMC_SDTR1_TWR_Pos (16U)
9060 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
9061 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
9062 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
9063 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
9064 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
9065 #define FMC_SDTR1_TRP_Pos (20U)
9066 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
9067 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
9068 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
9069 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
9070 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
9071 #define FMC_SDTR1_TRCD_Pos (24U)
9072 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
9073 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
9074 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
9075 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
9076 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
9077
9078 /****************** Bit definition for FMC_SDTR2 register ******************/
9079 #define FMC_SDTR2_TMRD_Pos (0U)
9080 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
9081 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
9082 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
9083 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
9084 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
9085 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
9086 #define FMC_SDTR2_TXSR_Pos (4U)
9087 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
9088 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
9089 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
9090 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
9091 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
9092 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
9093 #define FMC_SDTR2_TRAS_Pos (8U)
9094 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
9095 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
9096 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
9097 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
9098 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
9099 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
9100 #define FMC_SDTR2_TRC_Pos (12U)
9101 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
9102 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
9103 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
9104 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
9105 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
9106 #define FMC_SDTR2_TWR_Pos (16U)
9107 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
9108 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
9109 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
9110 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
9111 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
9112 #define FMC_SDTR2_TRP_Pos (20U)
9113 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
9114 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
9115 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
9116 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
9117 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
9118 #define FMC_SDTR2_TRCD_Pos (24U)
9119 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
9120 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
9121 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
9122 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
9123 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
9124
9125 /****************** Bit definition for FMC_SDCMR register ******************/
9126 #define FMC_SDCMR_MODE_Pos (0U)
9127 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
9128 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
9129 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
9130 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
9131 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
9132 #define FMC_SDCMR_CTB2_Pos (3U)
9133 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
9134 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
9135 #define FMC_SDCMR_CTB1_Pos (4U)
9136 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
9137 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
9138 #define FMC_SDCMR_NRFS_Pos (5U)
9139 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
9140 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
9141 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
9142 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
9143 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
9144 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
9145 #define FMC_SDCMR_MRD_Pos (9U)
9146 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
9147 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
9148
9149 /****************** Bit definition for FMC_SDRTR register ******************/
9150 #define FMC_SDRTR_CRE_Pos (0U)
9151 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
9152 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
9153 #define FMC_SDRTR_COUNT_Pos (1U)
9154 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
9155 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
9156 #define FMC_SDRTR_REIE_Pos (14U)
9157 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
9158 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
9159
9160 /****************** Bit definition for FMC_SDSR register ******************/
9161 #define FMC_SDSR_RE_Pos (0U)
9162 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
9163 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
9164 #define FMC_SDSR_MODES1_Pos (1U)
9165 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
9166 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
9167 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
9168 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
9169 #define FMC_SDSR_MODES2_Pos (3U)
9170 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
9171 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
9172 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
9173 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
9174 #define FMC_SDSR_BUSY_Pos (5U)
9175 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
9176 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
9177
9178 /******************************************************************************/
9179 /* */
9180 /* General Purpose I/O */
9181 /* */
9182 /******************************************************************************/
9183 /****************** Bits definition for GPIO_MODER register *****************/
9184 #define GPIO_MODER_MODER0_Pos (0U)
9185 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
9186 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
9187 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
9188 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
9189 #define GPIO_MODER_MODER1_Pos (2U)
9190 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
9191 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
9192 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
9193 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
9194 #define GPIO_MODER_MODER2_Pos (4U)
9195 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
9196 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
9197 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
9198 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
9199 #define GPIO_MODER_MODER3_Pos (6U)
9200 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
9201 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
9202 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
9203 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
9204 #define GPIO_MODER_MODER4_Pos (8U)
9205 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
9206 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
9207 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
9208 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
9209 #define GPIO_MODER_MODER5_Pos (10U)
9210 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
9211 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
9212 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
9213 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
9214 #define GPIO_MODER_MODER6_Pos (12U)
9215 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
9216 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
9217 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
9218 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
9219 #define GPIO_MODER_MODER7_Pos (14U)
9220 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
9221 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
9222 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
9223 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
9224 #define GPIO_MODER_MODER8_Pos (16U)
9225 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
9226 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
9227 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
9228 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
9229 #define GPIO_MODER_MODER9_Pos (18U)
9230 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
9231 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
9232 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
9233 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
9234 #define GPIO_MODER_MODER10_Pos (20U)
9235 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
9236 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
9237 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
9238 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
9239 #define GPIO_MODER_MODER11_Pos (22U)
9240 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
9241 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
9242 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
9243 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
9244 #define GPIO_MODER_MODER12_Pos (24U)
9245 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
9246 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
9247 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
9248 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
9249 #define GPIO_MODER_MODER13_Pos (26U)
9250 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
9251 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
9252 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
9253 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
9254 #define GPIO_MODER_MODER14_Pos (28U)
9255 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
9256 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
9257 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
9258 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
9259 #define GPIO_MODER_MODER15_Pos (30U)
9260 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
9261 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
9262 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
9263 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
9264
9265 /****************** Bits definition for GPIO_OTYPER register ****************/
9266 #define GPIO_OTYPER_OT_0 0x00000001U
9267 #define GPIO_OTYPER_OT_1 0x00000002U
9268 #define GPIO_OTYPER_OT_2 0x00000004U
9269 #define GPIO_OTYPER_OT_3 0x00000008U
9270 #define GPIO_OTYPER_OT_4 0x00000010U
9271 #define GPIO_OTYPER_OT_5 0x00000020U
9272 #define GPIO_OTYPER_OT_6 0x00000040U
9273 #define GPIO_OTYPER_OT_7 0x00000080U
9274 #define GPIO_OTYPER_OT_8 0x00000100U
9275 #define GPIO_OTYPER_OT_9 0x00000200U
9276 #define GPIO_OTYPER_OT_10 0x00000400U
9277 #define GPIO_OTYPER_OT_11 0x00000800U
9278 #define GPIO_OTYPER_OT_12 0x00001000U
9279 #define GPIO_OTYPER_OT_13 0x00002000U
9280 #define GPIO_OTYPER_OT_14 0x00004000U
9281 #define GPIO_OTYPER_OT_15 0x00008000U
9282
9283 /****************** Bits definition for GPIO_OSPEEDR register ***************/
9284 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
9285 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
9286 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
9287 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
9288 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
9289 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
9290 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
9291 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
9292 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
9293 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
9294 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
9295 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
9296 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
9297 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
9298 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
9299 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
9300 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
9301 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
9302 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
9303 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
9304 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
9305 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
9306 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
9307 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
9308 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
9309 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
9310 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
9311 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
9312 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
9313 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
9314 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
9315 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
9316 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
9317 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
9318 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
9319 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
9320 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
9321 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
9322 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
9323 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
9324 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
9325 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
9326 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
9327 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
9328 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
9329 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
9330 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
9331 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
9332 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
9333 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
9334 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
9335 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
9336 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
9337 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
9338 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
9339 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
9340 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
9341 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
9342 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
9343 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
9344 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
9345 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
9346 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
9347 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
9348 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
9349 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
9350 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
9351 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
9352 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
9353 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
9354 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
9355 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
9356 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
9357 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
9358 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
9359 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
9360 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
9361 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
9362 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
9363 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
9364
9365 /****************** Bits definition for GPIO_PUPDR register *****************/
9366 #define GPIO_PUPDR_PUPDR0_Pos (0U)
9367 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
9368 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
9369 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
9370 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
9371 #define GPIO_PUPDR_PUPDR1_Pos (2U)
9372 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
9373 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
9374 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
9375 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
9376 #define GPIO_PUPDR_PUPDR2_Pos (4U)
9377 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
9378 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
9379 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
9380 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
9381 #define GPIO_PUPDR_PUPDR3_Pos (6U)
9382 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
9383 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
9384 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
9385 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
9386 #define GPIO_PUPDR_PUPDR4_Pos (8U)
9387 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
9388 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
9389 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
9390 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
9391 #define GPIO_PUPDR_PUPDR5_Pos (10U)
9392 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
9393 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
9394 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
9395 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
9396 #define GPIO_PUPDR_PUPDR6_Pos (12U)
9397 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
9398 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
9399 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
9400 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
9401 #define GPIO_PUPDR_PUPDR7_Pos (14U)
9402 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
9403 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
9404 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
9405 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
9406 #define GPIO_PUPDR_PUPDR8_Pos (16U)
9407 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
9408 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
9409 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
9410 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
9411 #define GPIO_PUPDR_PUPDR9_Pos (18U)
9412 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
9413 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
9414 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
9415 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
9416 #define GPIO_PUPDR_PUPDR10_Pos (20U)
9417 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
9418 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
9419 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
9420 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
9421 #define GPIO_PUPDR_PUPDR11_Pos (22U)
9422 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
9423 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
9424 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
9425 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
9426 #define GPIO_PUPDR_PUPDR12_Pos (24U)
9427 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
9428 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
9429 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
9430 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
9431 #define GPIO_PUPDR_PUPDR13_Pos (26U)
9432 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
9433 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
9434 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
9435 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
9436 #define GPIO_PUPDR_PUPDR14_Pos (28U)
9437 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
9438 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
9439 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
9440 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
9441 #define GPIO_PUPDR_PUPDR15_Pos (30U)
9442 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
9443 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
9444 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
9445 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
9446
9447 /****************** Bits definition for GPIO_IDR register *******************/
9448 #define GPIO_IDR_IDR_0 0x00000001U
9449 #define GPIO_IDR_IDR_1 0x00000002U
9450 #define GPIO_IDR_IDR_2 0x00000004U
9451 #define GPIO_IDR_IDR_3 0x00000008U
9452 #define GPIO_IDR_IDR_4 0x00000010U
9453 #define GPIO_IDR_IDR_5 0x00000020U
9454 #define GPIO_IDR_IDR_6 0x00000040U
9455 #define GPIO_IDR_IDR_7 0x00000080U
9456 #define GPIO_IDR_IDR_8 0x00000100U
9457 #define GPIO_IDR_IDR_9 0x00000200U
9458 #define GPIO_IDR_IDR_10 0x00000400U
9459 #define GPIO_IDR_IDR_11 0x00000800U
9460 #define GPIO_IDR_IDR_12 0x00001000U
9461 #define GPIO_IDR_IDR_13 0x00002000U
9462 #define GPIO_IDR_IDR_14 0x00004000U
9463 #define GPIO_IDR_IDR_15 0x00008000U
9464
9465 /****************** Bits definition for GPIO_ODR register *******************/
9466 #define GPIO_ODR_ODR_0 0x00000001U
9467 #define GPIO_ODR_ODR_1 0x00000002U
9468 #define GPIO_ODR_ODR_2 0x00000004U
9469 #define GPIO_ODR_ODR_3 0x00000008U
9470 #define GPIO_ODR_ODR_4 0x00000010U
9471 #define GPIO_ODR_ODR_5 0x00000020U
9472 #define GPIO_ODR_ODR_6 0x00000040U
9473 #define GPIO_ODR_ODR_7 0x00000080U
9474 #define GPIO_ODR_ODR_8 0x00000100U
9475 #define GPIO_ODR_ODR_9 0x00000200U
9476 #define GPIO_ODR_ODR_10 0x00000400U
9477 #define GPIO_ODR_ODR_11 0x00000800U
9478 #define GPIO_ODR_ODR_12 0x00001000U
9479 #define GPIO_ODR_ODR_13 0x00002000U
9480 #define GPIO_ODR_ODR_14 0x00004000U
9481 #define GPIO_ODR_ODR_15 0x00008000U
9482
9483 /****************** Bits definition for GPIO_BSRR register ******************/
9484 #define GPIO_BSRR_BS_0 0x00000001U
9485 #define GPIO_BSRR_BS_1 0x00000002U
9486 #define GPIO_BSRR_BS_2 0x00000004U
9487 #define GPIO_BSRR_BS_3 0x00000008U
9488 #define GPIO_BSRR_BS_4 0x00000010U
9489 #define GPIO_BSRR_BS_5 0x00000020U
9490 #define GPIO_BSRR_BS_6 0x00000040U
9491 #define GPIO_BSRR_BS_7 0x00000080U
9492 #define GPIO_BSRR_BS_8 0x00000100U
9493 #define GPIO_BSRR_BS_9 0x00000200U
9494 #define GPIO_BSRR_BS_10 0x00000400U
9495 #define GPIO_BSRR_BS_11 0x00000800U
9496 #define GPIO_BSRR_BS_12 0x00001000U
9497 #define GPIO_BSRR_BS_13 0x00002000U
9498 #define GPIO_BSRR_BS_14 0x00004000U
9499 #define GPIO_BSRR_BS_15 0x00008000U
9500 #define GPIO_BSRR_BR_0 0x00010000U
9501 #define GPIO_BSRR_BR_1 0x00020000U
9502 #define GPIO_BSRR_BR_2 0x00040000U
9503 #define GPIO_BSRR_BR_3 0x00080000U
9504 #define GPIO_BSRR_BR_4 0x00100000U
9505 #define GPIO_BSRR_BR_5 0x00200000U
9506 #define GPIO_BSRR_BR_6 0x00400000U
9507 #define GPIO_BSRR_BR_7 0x00800000U
9508 #define GPIO_BSRR_BR_8 0x01000000U
9509 #define GPIO_BSRR_BR_9 0x02000000U
9510 #define GPIO_BSRR_BR_10 0x04000000U
9511 #define GPIO_BSRR_BR_11 0x08000000U
9512 #define GPIO_BSRR_BR_12 0x10000000U
9513 #define GPIO_BSRR_BR_13 0x20000000U
9514 #define GPIO_BSRR_BR_14 0x40000000U
9515 #define GPIO_BSRR_BR_15 0x80000000U
9516
9517 /****************** Bit definition for GPIO_LCKR register *********************/
9518 #define GPIO_LCKR_LCK0_Pos (0U)
9519 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
9520 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
9521 #define GPIO_LCKR_LCK1_Pos (1U)
9522 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
9523 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
9524 #define GPIO_LCKR_LCK2_Pos (2U)
9525 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
9526 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
9527 #define GPIO_LCKR_LCK3_Pos (3U)
9528 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
9529 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
9530 #define GPIO_LCKR_LCK4_Pos (4U)
9531 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
9532 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
9533 #define GPIO_LCKR_LCK5_Pos (5U)
9534 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
9535 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
9536 #define GPIO_LCKR_LCK6_Pos (6U)
9537 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
9538 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
9539 #define GPIO_LCKR_LCK7_Pos (7U)
9540 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
9541 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
9542 #define GPIO_LCKR_LCK8_Pos (8U)
9543 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
9544 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
9545 #define GPIO_LCKR_LCK9_Pos (9U)
9546 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
9547 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
9548 #define GPIO_LCKR_LCK10_Pos (10U)
9549 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
9550 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
9551 #define GPIO_LCKR_LCK11_Pos (11U)
9552 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
9553 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
9554 #define GPIO_LCKR_LCK12_Pos (12U)
9555 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
9556 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
9557 #define GPIO_LCKR_LCK13_Pos (13U)
9558 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
9559 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
9560 #define GPIO_LCKR_LCK14_Pos (14U)
9561 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
9562 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
9563 #define GPIO_LCKR_LCK15_Pos (15U)
9564 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
9565 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
9566 #define GPIO_LCKR_LCKK_Pos (16U)
9567 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
9568 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
9569
9570 /****************** Bit definition for GPIO_AFRL register *********************/
9571 #define GPIO_AFRL_AFRL0_Pos (0U)
9572 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
9573 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
9574 #define GPIO_AFRL_AFRL0_0 (0x1U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000001 */
9575 #define GPIO_AFRL_AFRL0_1 (0x2U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000002 */
9576 #define GPIO_AFRL_AFRL0_2 (0x4U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000004 */
9577 #define GPIO_AFRL_AFRL0_3 (0x8U << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000008 */
9578 #define GPIO_AFRL_AFRL1_Pos (4U)
9579 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
9580 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
9581 #define GPIO_AFRL_AFRL1_0 (0x1U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000010 */
9582 #define GPIO_AFRL_AFRL1_1 (0x2U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000020 */
9583 #define GPIO_AFRL_AFRL1_2 (0x4U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000040 */
9584 #define GPIO_AFRL_AFRL1_3 (0x8U << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000080 */
9585 #define GPIO_AFRL_AFRL2_Pos (8U)
9586 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
9587 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
9588 #define GPIO_AFRL_AFRL2_0 (0x1U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000100 */
9589 #define GPIO_AFRL_AFRL2_1 (0x2U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000200 */
9590 #define GPIO_AFRL_AFRL2_2 (0x4U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000400 */
9591 #define GPIO_AFRL_AFRL2_3 (0x8U << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000800 */
9592 #define GPIO_AFRL_AFRL3_Pos (12U)
9593 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
9594 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
9595 #define GPIO_AFRL_AFRL3_0 (0x1U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00001000 */
9596 #define GPIO_AFRL_AFRL3_1 (0x2U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00002000 */
9597 #define GPIO_AFRL_AFRL3_2 (0x4U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00004000 */
9598 #define GPIO_AFRL_AFRL3_3 (0x8U << GPIO_AFRL_AFRL3_Pos) /*!< 0x00008000 */
9599 #define GPIO_AFRL_AFRL4_Pos (16U)
9600 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
9601 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
9602 #define GPIO_AFRL_AFRL4_0 (0x1U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00010000 */
9603 #define GPIO_AFRL_AFRL4_1 (0x2U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00020000 */
9604 #define GPIO_AFRL_AFRL4_2 (0x4U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00040000 */
9605 #define GPIO_AFRL_AFRL4_3 (0x8U << GPIO_AFRL_AFRL4_Pos) /*!< 0x00080000 */
9606 #define GPIO_AFRL_AFRL5_Pos (20U)
9607 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
9608 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
9609 #define GPIO_AFRL_AFRL5_0 (0x1U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00100000 */
9610 #define GPIO_AFRL_AFRL5_1 (0x2U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00200000 */
9611 #define GPIO_AFRL_AFRL5_2 (0x4U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00400000 */
9612 #define GPIO_AFRL_AFRL5_3 (0x8U << GPIO_AFRL_AFRL5_Pos) /*!< 0x00800000 */
9613 #define GPIO_AFRL_AFRL6_Pos (24U)
9614 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
9615 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
9616 #define GPIO_AFRL_AFRL6_0 (0x1U << GPIO_AFRL_AFRL6_Pos) /*!< 0x01000000 */
9617 #define GPIO_AFRL_AFRL6_1 (0x2U << GPIO_AFRL_AFRL6_Pos) /*!< 0x02000000 */
9618 #define GPIO_AFRL_AFRL6_2 (0x4U << GPIO_AFRL_AFRL6_Pos) /*!< 0x04000000 */
9619 #define GPIO_AFRL_AFRL6_3 (0x8U << GPIO_AFRL_AFRL6_Pos) /*!< 0x08000000 */
9620 #define GPIO_AFRL_AFRL7_Pos (28U)
9621 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
9622 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
9623 #define GPIO_AFRL_AFRL7_0 (0x1U << GPIO_AFRL_AFRL7_Pos) /*!< 0x10000000 */
9624 #define GPIO_AFRL_AFRL7_1 (0x2U << GPIO_AFRL_AFRL7_Pos) /*!< 0x20000000 */
9625 #define GPIO_AFRL_AFRL7_2 (0x4U << GPIO_AFRL_AFRL7_Pos) /*!< 0x40000000 */
9626 #define GPIO_AFRL_AFRL7_3 (0x8U << GPIO_AFRL_AFRL7_Pos) /*!< 0x80000000 */
9627
9628 /****************** Bit definition for GPIO_AFRH register *********************/
9629 #define GPIO_AFRH_AFRH0_Pos (0U)
9630 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
9631 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
9632 #define GPIO_AFRH_AFRH0_0 (0x1U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000001 */
9633 #define GPIO_AFRH_AFRH0_1 (0x2U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000002 */
9634 #define GPIO_AFRH_AFRH0_2 (0x4U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000004 */
9635 #define GPIO_AFRH_AFRH0_3 (0x8U << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000008 */
9636 #define GPIO_AFRH_AFRH1_Pos (4U)
9637 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
9638 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
9639 #define GPIO_AFRH_AFRH1_0 (0x1U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000010 */
9640 #define GPIO_AFRH_AFRH1_1 (0x2U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000020 */
9641 #define GPIO_AFRH_AFRH1_2 (0x4U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000040 */
9642 #define GPIO_AFRH_AFRH1_3 (0x8U << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000080 */
9643 #define GPIO_AFRH_AFRH2_Pos (8U)
9644 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
9645 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
9646 #define GPIO_AFRH_AFRH2_0 (0x1U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000100 */
9647 #define GPIO_AFRH_AFRH2_1 (0x2U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000200 */
9648 #define GPIO_AFRH_AFRH2_2 (0x4U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000400 */
9649 #define GPIO_AFRH_AFRH2_3 (0x8U << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000800 */
9650 #define GPIO_AFRH_AFRH3_Pos (12U)
9651 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
9652 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
9653 #define GPIO_AFRH_AFRH3_0 (0x1U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00001000 */
9654 #define GPIO_AFRH_AFRH3_1 (0x2U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00002000 */
9655 #define GPIO_AFRH_AFRH3_2 (0x4U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00004000 */
9656 #define GPIO_AFRH_AFRH3_3 (0x8U << GPIO_AFRH_AFRH3_Pos) /*!< 0x00008000 */
9657 #define GPIO_AFRH_AFRH4_Pos (16U)
9658 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
9659 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
9660 #define GPIO_AFRH_AFRH4_0 (0x1U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00010000 */
9661 #define GPIO_AFRH_AFRH4_1 (0x2U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00020000 */
9662 #define GPIO_AFRH_AFRH4_2 (0x4U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00040000 */
9663 #define GPIO_AFRH_AFRH4_3 (0x8U << GPIO_AFRH_AFRH4_Pos) /*!< 0x00080000 */
9664 #define GPIO_AFRH_AFRH5_Pos (20U)
9665 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
9666 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
9667 #define GPIO_AFRH_AFRH5_0 (0x1U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00100000 */
9668 #define GPIO_AFRH_AFRH5_1 (0x2U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00200000 */
9669 #define GPIO_AFRH_AFRH5_2 (0x4U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00400000 */
9670 #define GPIO_AFRH_AFRH5_3 (0x8U << GPIO_AFRH_AFRH5_Pos) /*!< 0x00800000 */
9671 #define GPIO_AFRH_AFRH6_Pos (24U)
9672 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
9673 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
9674 #define GPIO_AFRH_AFRH6_0 (0x1U << GPIO_AFRH_AFRH6_Pos) /*!< 0x01000000 */
9675 #define GPIO_AFRH_AFRH6_1 (0x2U << GPIO_AFRH_AFRH6_Pos) /*!< 0x02000000 */
9676 #define GPIO_AFRH_AFRH6_2 (0x4U << GPIO_AFRH_AFRH6_Pos) /*!< 0x04000000 */
9677 #define GPIO_AFRH_AFRH6_3 (0x8U << GPIO_AFRH_AFRH6_Pos) /*!< 0x08000000 */
9678 #define GPIO_AFRH_AFRH7_Pos (28U)
9679 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
9680 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
9681 #define GPIO_AFRH_AFRH7_0 (0x1U << GPIO_AFRH_AFRH7_Pos) /*!< 0x10000000 */
9682 #define GPIO_AFRH_AFRH7_1 (0x2U << GPIO_AFRH_AFRH7_Pos) /*!< 0x20000000 */
9683 #define GPIO_AFRH_AFRH7_2 (0x4U << GPIO_AFRH_AFRH7_Pos) /*!< 0x40000000 */
9684 #define GPIO_AFRH_AFRH7_3 (0x8U << GPIO_AFRH_AFRH7_Pos) /*!< 0x80000000 */
9685
9686 /******************************************************************************/
9687 /* */
9688 /* HASH */
9689 /* */
9690 /******************************************************************************/
9691 /****************** Bits definition for HASH_CR register ********************/
9692 #define HASH_CR_INIT_Pos (2U)
9693 #define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
9694 #define HASH_CR_INIT HASH_CR_INIT_Msk
9695 #define HASH_CR_DMAE_Pos (3U)
9696 #define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
9697 #define HASH_CR_DMAE HASH_CR_DMAE_Msk
9698 #define HASH_CR_DATATYPE_Pos (4U)
9699 #define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
9700 #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
9701 #define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
9702 #define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
9703 #define HASH_CR_MODE_Pos (6U)
9704 #define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
9705 #define HASH_CR_MODE HASH_CR_MODE_Msk
9706 #define HASH_CR_ALGO_Pos (7U)
9707 #define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
9708 #define HASH_CR_ALGO HASH_CR_ALGO_Msk
9709 #define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
9710 #define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
9711 #define HASH_CR_NBW_Pos (8U)
9712 #define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
9713 #define HASH_CR_NBW HASH_CR_NBW_Msk
9714 #define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
9715 #define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
9716 #define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
9717 #define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
9718 #define HASH_CR_DINNE_Pos (12U)
9719 #define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
9720 #define HASH_CR_DINNE HASH_CR_DINNE_Msk
9721 #define HASH_CR_MDMAT_Pos (13U)
9722 #define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
9723 #define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
9724 #define HASH_CR_LKEY_Pos (16U)
9725 #define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
9726 #define HASH_CR_LKEY HASH_CR_LKEY_Msk
9727
9728 /****************** Bits definition for HASH_STR register *******************/
9729 #define HASH_STR_NBLW_Pos (0U)
9730 #define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
9731 #define HASH_STR_NBLW HASH_STR_NBLW_Msk
9732 #define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
9733 #define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
9734 #define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
9735 #define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
9736 #define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
9737 #define HASH_STR_DCAL_Pos (8U)
9738 #define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
9739 #define HASH_STR_DCAL HASH_STR_DCAL_Msk
9740
9741 /* legacy defines */
9742 #define HASH_STR_NBW HASH_STR_NBLW
9743 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
9744 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
9745 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
9746 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
9747 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
9748
9749 /****************** Bits definition for HASH_IMR register *******************/
9750 #define HASH_IMR_DINIE_Pos (0U)
9751 #define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
9752 #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
9753 #define HASH_IMR_DCIE_Pos (1U)
9754 #define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
9755 #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
9756
9757 /* legacy defines */
9758 #define HASH_IMR_DINIM HASH_IMR_DINIE
9759 #define HASH_IMR_DCIM HASH_IMR_DCIE
9760 /****************** Bits definition for HASH_SR register ********************/
9761 #define HASH_SR_DINIS_Pos (0U)
9762 #define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
9763 #define HASH_SR_DINIS HASH_SR_DINIS_Msk
9764 #define HASH_SR_DCIS_Pos (1U)
9765 #define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
9766 #define HASH_SR_DCIS HASH_SR_DCIS_Msk
9767 #define HASH_SR_DMAS_Pos (2U)
9768 #define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
9769 #define HASH_SR_DMAS HASH_SR_DMAS_Msk
9770 #define HASH_SR_BUSY_Pos (3U)
9771 #define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
9772 #define HASH_SR_BUSY HASH_SR_BUSY_Msk
9773
9774 /******************************************************************************/
9775 /* */
9776 /* Inter-integrated Circuit Interface (I2C) */
9777 /* */
9778 /******************************************************************************/
9779 /******************* Bit definition for I2C_CR1 register *******************/
9780 #define I2C_CR1_PE_Pos (0U)
9781 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
9782 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
9783 #define I2C_CR1_TXIE_Pos (1U)
9784 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
9785 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
9786 #define I2C_CR1_RXIE_Pos (2U)
9787 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
9788 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
9789 #define I2C_CR1_ADDRIE_Pos (3U)
9790 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
9791 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
9792 #define I2C_CR1_NACKIE_Pos (4U)
9793 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
9794 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
9795 #define I2C_CR1_STOPIE_Pos (5U)
9796 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
9797 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
9798 #define I2C_CR1_TCIE_Pos (6U)
9799 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
9800 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
9801 #define I2C_CR1_ERRIE_Pos (7U)
9802 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
9803 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
9804 #define I2C_CR1_DNF_Pos (8U)
9805 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
9806 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
9807 #define I2C_CR1_ANFOFF_Pos (12U)
9808 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
9809 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
9810 #define I2C_CR1_TXDMAEN_Pos (14U)
9811 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
9812 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
9813 #define I2C_CR1_RXDMAEN_Pos (15U)
9814 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
9815 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
9816 #define I2C_CR1_SBC_Pos (16U)
9817 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
9818 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
9819 #define I2C_CR1_NOSTRETCH_Pos (17U)
9820 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
9821 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
9822 #define I2C_CR1_GCEN_Pos (19U)
9823 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
9824 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
9825 #define I2C_CR1_SMBHEN_Pos (20U)
9826 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
9827 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
9828 #define I2C_CR1_SMBDEN_Pos (21U)
9829 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
9830 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
9831 #define I2C_CR1_ALERTEN_Pos (22U)
9832 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
9833 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
9834 #define I2C_CR1_PECEN_Pos (23U)
9835 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
9836 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
9837
9838
9839 /****************** Bit definition for I2C_CR2 register ********************/
9840 #define I2C_CR2_SADD_Pos (0U)
9841 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
9842 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
9843 #define I2C_CR2_RD_WRN_Pos (10U)
9844 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
9845 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
9846 #define I2C_CR2_ADD10_Pos (11U)
9847 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
9848 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
9849 #define I2C_CR2_HEAD10R_Pos (12U)
9850 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
9851 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
9852 #define I2C_CR2_START_Pos (13U)
9853 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
9854 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
9855 #define I2C_CR2_STOP_Pos (14U)
9856 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
9857 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
9858 #define I2C_CR2_NACK_Pos (15U)
9859 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
9860 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
9861 #define I2C_CR2_NBYTES_Pos (16U)
9862 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
9863 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
9864 #define I2C_CR2_RELOAD_Pos (24U)
9865 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
9866 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
9867 #define I2C_CR2_AUTOEND_Pos (25U)
9868 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
9869 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
9870 #define I2C_CR2_PECBYTE_Pos (26U)
9871 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
9872 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
9873
9874 /******************* Bit definition for I2C_OAR1 register ******************/
9875 #define I2C_OAR1_OA1_Pos (0U)
9876 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
9877 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
9878 #define I2C_OAR1_OA1MODE_Pos (10U)
9879 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
9880 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
9881 #define I2C_OAR1_OA1EN_Pos (15U)
9882 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
9883 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
9884
9885 /******************* Bit definition for I2C_OAR2 register ******************/
9886 #define I2C_OAR2_OA2_Pos (1U)
9887 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
9888 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
9889 #define I2C_OAR2_OA2MSK_Pos (8U)
9890 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
9891 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
9892 #define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
9893 #define I2C_OAR2_OA2MASK01_Pos (8U)
9894 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
9895 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
9896 #define I2C_OAR2_OA2MASK02_Pos (9U)
9897 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
9898 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
9899 #define I2C_OAR2_OA2MASK03_Pos (8U)
9900 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
9901 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
9902 #define I2C_OAR2_OA2MASK04_Pos (10U)
9903 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
9904 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
9905 #define I2C_OAR2_OA2MASK05_Pos (8U)
9906 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
9907 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
9908 #define I2C_OAR2_OA2MASK06_Pos (9U)
9909 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
9910 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
9911 #define I2C_OAR2_OA2MASK07_Pos (8U)
9912 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
9913 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
9914 #define I2C_OAR2_OA2EN_Pos (15U)
9915 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
9916 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
9917
9918 /******************* Bit definition for I2C_TIMINGR register *******************/
9919 #define I2C_TIMINGR_SCLL_Pos (0U)
9920 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
9921 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
9922 #define I2C_TIMINGR_SCLH_Pos (8U)
9923 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
9924 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
9925 #define I2C_TIMINGR_SDADEL_Pos (16U)
9926 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
9927 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
9928 #define I2C_TIMINGR_SCLDEL_Pos (20U)
9929 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
9930 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
9931 #define I2C_TIMINGR_PRESC_Pos (28U)
9932 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
9933 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
9934
9935 /******************* Bit definition for I2C_TIMEOUTR register *******************/
9936 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9937 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
9938 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
9939 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
9940 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
9941 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
9942 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9943 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
9944 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
9945 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9946 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
9947 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
9948 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
9949 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
9950 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
9951
9952 /****************** Bit definition for I2C_ISR register *********************/
9953 #define I2C_ISR_TXE_Pos (0U)
9954 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
9955 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
9956 #define I2C_ISR_TXIS_Pos (1U)
9957 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
9958 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
9959 #define I2C_ISR_RXNE_Pos (2U)
9960 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
9961 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
9962 #define I2C_ISR_ADDR_Pos (3U)
9963 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
9964 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
9965 #define I2C_ISR_NACKF_Pos (4U)
9966 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
9967 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
9968 #define I2C_ISR_STOPF_Pos (5U)
9969 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
9970 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
9971 #define I2C_ISR_TC_Pos (6U)
9972 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
9973 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
9974 #define I2C_ISR_TCR_Pos (7U)
9975 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
9976 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
9977 #define I2C_ISR_BERR_Pos (8U)
9978 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
9979 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
9980 #define I2C_ISR_ARLO_Pos (9U)
9981 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
9982 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
9983 #define I2C_ISR_OVR_Pos (10U)
9984 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
9985 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
9986 #define I2C_ISR_PECERR_Pos (11U)
9987 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
9988 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
9989 #define I2C_ISR_TIMEOUT_Pos (12U)
9990 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
9991 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
9992 #define I2C_ISR_ALERT_Pos (13U)
9993 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
9994 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
9995 #define I2C_ISR_BUSY_Pos (15U)
9996 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
9997 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
9998 #define I2C_ISR_DIR_Pos (16U)
9999 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
10000 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
10001 #define I2C_ISR_ADDCODE_Pos (17U)
10002 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
10003 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
10004
10005 /****************** Bit definition for I2C_ICR register *********************/
10006 #define I2C_ICR_ADDRCF_Pos (3U)
10007 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
10008 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
10009 #define I2C_ICR_NACKCF_Pos (4U)
10010 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
10011 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
10012 #define I2C_ICR_STOPCF_Pos (5U)
10013 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
10014 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
10015 #define I2C_ICR_BERRCF_Pos (8U)
10016 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
10017 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
10018 #define I2C_ICR_ARLOCF_Pos (9U)
10019 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
10020 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
10021 #define I2C_ICR_OVRCF_Pos (10U)
10022 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
10023 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
10024 #define I2C_ICR_PECCF_Pos (11U)
10025 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
10026 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
10027 #define I2C_ICR_TIMOUTCF_Pos (12U)
10028 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
10029 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
10030 #define I2C_ICR_ALERTCF_Pos (13U)
10031 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
10032 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
10033
10034 /****************** Bit definition for I2C_PECR register *********************/
10035 #define I2C_PECR_PEC_Pos (0U)
10036 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
10037 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
10038
10039 /****************** Bit definition for I2C_RXDR register *********************/
10040 #define I2C_RXDR_RXDATA_Pos (0U)
10041 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
10042 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
10043
10044 /****************** Bit definition for I2C_TXDR register *********************/
10045 #define I2C_TXDR_TXDATA_Pos (0U)
10046 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
10047 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
10048
10049
10050 /******************************************************************************/
10051 /* */
10052 /* Independent WATCHDOG */
10053 /* */
10054 /******************************************************************************/
10055 /******************* Bit definition for IWDG_KR register ********************/
10056 #define IWDG_KR_KEY_Pos (0U)
10057 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
10058 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
10059
10060 /******************* Bit definition for IWDG_PR register ********************/
10061 #define IWDG_PR_PR_Pos (0U)
10062 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
10063 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
10064 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
10065 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
10066 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
10067
10068 /******************* Bit definition for IWDG_RLR register *******************/
10069 #define IWDG_RLR_RL_Pos (0U)
10070 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
10071 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
10072
10073 /******************* Bit definition for IWDG_SR register ********************/
10074 #define IWDG_SR_PVU_Pos (0U)
10075 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
10076 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
10077 #define IWDG_SR_RVU_Pos (1U)
10078 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
10079 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
10080 #define IWDG_SR_WVU_Pos (2U)
10081 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
10082 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
10083
10084 /******************* Bit definition for IWDG_KR register ********************/
10085 #define IWDG_WINR_WIN_Pos (0U)
10086 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
10087 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
10088
10089 /******************************************************************************/
10090 /* */
10091 /* LCD-TFT Display Controller (LTDC) */
10092 /* */
10093 /******************************************************************************/
10094
10095 /******************** Bit definition for LTDC_SSCR register *****************/
10096
10097 #define LTDC_SSCR_VSH_Pos (0U)
10098 #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
10099 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
10100 #define LTDC_SSCR_HSW_Pos (16U)
10101 #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
10102 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
10103
10104 /******************** Bit definition for LTDC_BPCR register *****************/
10105
10106 #define LTDC_BPCR_AVBP_Pos (0U)
10107 #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
10108 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
10109 #define LTDC_BPCR_AHBP_Pos (16U)
10110 #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
10111 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
10112
10113 /******************** Bit definition for LTDC_AWCR register *****************/
10114
10115 #define LTDC_AWCR_AAH_Pos (0U)
10116 #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
10117 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
10118 #define LTDC_AWCR_AAW_Pos (16U)
10119 #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
10120 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
10121
10122 /******************** Bit definition for LTDC_TWCR register *****************/
10123
10124 #define LTDC_TWCR_TOTALH_Pos (0U)
10125 #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
10126 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
10127 #define LTDC_TWCR_TOTALW_Pos (16U)
10128 #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
10129 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
10130
10131 /******************** Bit definition for LTDC_GCR register ******************/
10132
10133 #define LTDC_GCR_LTDCEN_Pos (0U)
10134 #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
10135 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
10136 #define LTDC_GCR_DBW_Pos (4U)
10137 #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
10138 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
10139 #define LTDC_GCR_DGW_Pos (8U)
10140 #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
10141 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
10142 #define LTDC_GCR_DRW_Pos (12U)
10143 #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
10144 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
10145 #define LTDC_GCR_DEN_Pos (16U)
10146 #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
10147 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
10148 #define LTDC_GCR_PCPOL_Pos (28U)
10149 #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
10150 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
10151 #define LTDC_GCR_DEPOL_Pos (29U)
10152 #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
10153 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
10154 #define LTDC_GCR_VSPOL_Pos (30U)
10155 #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
10156 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
10157 #define LTDC_GCR_HSPOL_Pos (31U)
10158 #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
10159 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
10160
10161
10162 /******************** Bit definition for LTDC_SRCR register *****************/
10163
10164 #define LTDC_SRCR_IMR_Pos (0U)
10165 #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
10166 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
10167 #define LTDC_SRCR_VBR_Pos (1U)
10168 #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
10169 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
10170
10171 /******************** Bit definition for LTDC_BCCR register *****************/
10172
10173 #define LTDC_BCCR_BCBLUE_Pos (0U)
10174 #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
10175 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
10176 #define LTDC_BCCR_BCGREEN_Pos (8U)
10177 #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
10178 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
10179 #define LTDC_BCCR_BCRED_Pos (16U)
10180 #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
10181 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
10182
10183 /******************** Bit definition for LTDC_IER register ******************/
10184
10185 #define LTDC_IER_LIE_Pos (0U)
10186 #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
10187 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
10188 #define LTDC_IER_FUIE_Pos (1U)
10189 #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
10190 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
10191 #define LTDC_IER_TERRIE_Pos (2U)
10192 #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
10193 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
10194 #define LTDC_IER_RRIE_Pos (3U)
10195 #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
10196 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
10197
10198 /******************** Bit definition for LTDC_ISR register ******************/
10199
10200 #define LTDC_ISR_LIF_Pos (0U)
10201 #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
10202 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
10203 #define LTDC_ISR_FUIF_Pos (1U)
10204 #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
10205 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
10206 #define LTDC_ISR_TERRIF_Pos (2U)
10207 #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
10208 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
10209 #define LTDC_ISR_RRIF_Pos (3U)
10210 #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
10211 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
10212
10213 /******************** Bit definition for LTDC_ICR register ******************/
10214
10215 #define LTDC_ICR_CLIF_Pos (0U)
10216 #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
10217 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
10218 #define LTDC_ICR_CFUIF_Pos (1U)
10219 #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
10220 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
10221 #define LTDC_ICR_CTERRIF_Pos (2U)
10222 #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
10223 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
10224 #define LTDC_ICR_CRRIF_Pos (3U)
10225 #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
10226 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
10227
10228 /******************** Bit definition for LTDC_LIPCR register ****************/
10229
10230 #define LTDC_LIPCR_LIPOS_Pos (0U)
10231 #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
10232 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
10233
10234 /******************** Bit definition for LTDC_CPSR register *****************/
10235
10236 #define LTDC_CPSR_CYPOS_Pos (0U)
10237 #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
10238 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
10239 #define LTDC_CPSR_CXPOS_Pos (16U)
10240 #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
10241 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
10242
10243 /******************** Bit definition for LTDC_CDSR register *****************/
10244
10245 #define LTDC_CDSR_VDES_Pos (0U)
10246 #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
10247 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
10248 #define LTDC_CDSR_HDES_Pos (1U)
10249 #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
10250 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
10251 #define LTDC_CDSR_VSYNCS_Pos (2U)
10252 #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
10253 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
10254 #define LTDC_CDSR_HSYNCS_Pos (3U)
10255 #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
10256 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
10257
10258 /******************** Bit definition for LTDC_LxCR register *****************/
10259
10260 #define LTDC_LxCR_LEN_Pos (0U)
10261 #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
10262 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
10263 #define LTDC_LxCR_COLKEN_Pos (1U)
10264 #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
10265 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
10266 #define LTDC_LxCR_CLUTEN_Pos (4U)
10267 #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
10268 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
10269
10270 /******************** Bit definition for LTDC_LxWHPCR register **************/
10271
10272 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
10273 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
10274 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
10275 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
10276 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
10277 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
10278
10279 /******************** Bit definition for LTDC_LxWVPCR register **************/
10280
10281 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
10282 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
10283 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
10284 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
10285 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
10286 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
10287
10288 /******************** Bit definition for LTDC_LxCKCR register ***************/
10289
10290 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
10291 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
10292 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
10293 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
10294 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
10295 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
10296 #define LTDC_LxCKCR_CKRED_Pos (16U)
10297 #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
10298 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
10299
10300 /******************** Bit definition for LTDC_LxPFCR register ***************/
10301
10302 #define LTDC_LxPFCR_PF_Pos (0U)
10303 #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
10304 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
10305
10306 /******************** Bit definition for LTDC_LxCACR register ***************/
10307
10308 #define LTDC_LxCACR_CONSTA_Pos (0U)
10309 #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
10310 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
10311
10312 /******************** Bit definition for LTDC_LxDCCR register ***************/
10313
10314 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
10315 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
10316 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
10317 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
10318 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
10319 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
10320 #define LTDC_LxDCCR_DCRED_Pos (16U)
10321 #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
10322 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
10323 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
10324 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
10325 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
10326
10327 /******************** Bit definition for LTDC_LxBFCR register ***************/
10328
10329 #define LTDC_LxBFCR_BF2_Pos (0U)
10330 #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
10331 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
10332 #define LTDC_LxBFCR_BF1_Pos (8U)
10333 #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
10334 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
10335
10336 /******************** Bit definition for LTDC_LxCFBAR register **************/
10337
10338 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
10339 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
10340 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
10341
10342 /******************** Bit definition for LTDC_LxCFBLR register **************/
10343
10344 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
10345 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
10346 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
10347 #define LTDC_LxCFBLR_CFBP_Pos (16U)
10348 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
10349 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
10350
10351 /******************** Bit definition for LTDC_LxCFBLNR register *************/
10352
10353 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
10354 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
10355 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
10356
10357 /******************** Bit definition for LTDC_LxCLUTWR register *************/
10358
10359 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
10360 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
10361 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
10362 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
10363 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
10364 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
10365 #define LTDC_LxCLUTWR_RED_Pos (16U)
10366 #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
10367 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
10368 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
10369 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
10370 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
10371
10372 /******************************************************************************/
10373 /* */
10374 /* Power Control */
10375 /* */
10376 /******************************************************************************/
10377 /******************** Bit definition for PWR_CR1 register ********************/
10378 #define PWR_CR1_LPDS_Pos (0U)
10379 #define PWR_CR1_LPDS_Msk (0x1U << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
10380 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low-Power Deepsleep */
10381 #define PWR_CR1_PDDS_Pos (1U)
10382 #define PWR_CR1_PDDS_Msk (0x1U << PWR_CR1_PDDS_Pos) /*!< 0x00000002 */
10383 #define PWR_CR1_PDDS PWR_CR1_PDDS_Msk /*!< Power Down Deepsleep */
10384 #define PWR_CR1_CSBF_Pos (3U)
10385 #define PWR_CR1_CSBF_Msk (0x1U << PWR_CR1_CSBF_Pos) /*!< 0x00000008 */
10386 #define PWR_CR1_CSBF PWR_CR1_CSBF_Msk /*!< Clear Standby Flag */
10387 #define PWR_CR1_PVDE_Pos (4U)
10388 #define PWR_CR1_PVDE_Msk (0x1U << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */
10389 #define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Power Voltage Detector Enable */
10390 #define PWR_CR1_PLS_Pos (5U)
10391 #define PWR_CR1_PLS_Msk (0x7U << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
10392 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
10393 #define PWR_CR1_PLS_0 (0x1U << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
10394 #define PWR_CR1_PLS_1 (0x2U << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
10395 #define PWR_CR1_PLS_2 (0x4U << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
10396
10397 /*!< PVD level configuration */
10398 #define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
10399 #define PWR_CR1_PLS_LEV1_Pos (5U)
10400 #define PWR_CR1_PLS_LEV1_Msk (0x1U << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
10401 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
10402 #define PWR_CR1_PLS_LEV2_Pos (6U)
10403 #define PWR_CR1_PLS_LEV2_Msk (0x1U << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
10404 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
10405 #define PWR_CR1_PLS_LEV3_Pos (5U)
10406 #define PWR_CR1_PLS_LEV3_Msk (0x3U << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
10407 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
10408 #define PWR_CR1_PLS_LEV4_Pos (7U)
10409 #define PWR_CR1_PLS_LEV4_Msk (0x1U << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
10410 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
10411 #define PWR_CR1_PLS_LEV5_Pos (5U)
10412 #define PWR_CR1_PLS_LEV5_Msk (0x5U << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
10413 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
10414 #define PWR_CR1_PLS_LEV6_Pos (6U)
10415 #define PWR_CR1_PLS_LEV6_Msk (0x3U << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
10416 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
10417 #define PWR_CR1_PLS_LEV7_Pos (5U)
10418 #define PWR_CR1_PLS_LEV7_Msk (0x7U << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
10419 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
10420 #define PWR_CR1_DBP_Pos (8U)
10421 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
10422 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */
10423 #define PWR_CR1_FPDS_Pos (9U)
10424 #define PWR_CR1_FPDS_Msk (0x1U << PWR_CR1_FPDS_Pos) /*!< 0x00000200 */
10425 #define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down in Stop mode */
10426 #define PWR_CR1_LPUDS_Pos (10U)
10427 #define PWR_CR1_LPUDS_Msk (0x1U << PWR_CR1_LPUDS_Pos) /*!< 0x00000400 */
10428 #define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk /*!< Low-power regulator in deepsleep under-drive mode */
10429 #define PWR_CR1_MRUDS_Pos (11U)
10430 #define PWR_CR1_MRUDS_Msk (0x1U << PWR_CR1_MRUDS_Pos) /*!< 0x00000800 */
10431 #define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk /*!< Main regulator in deepsleep under-drive mode */
10432 #define PWR_CR1_ADCDC1_Pos (13U)
10433 #define PWR_CR1_ADCDC1_Msk (0x1U << PWR_CR1_ADCDC1_Pos) /*!< 0x00002000 */
10434 #define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
10435 #define PWR_CR1_VOS_Pos (14U)
10436 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x0000C000 */
10437 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10438 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00004000 */
10439 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00008000 */
10440 #define PWR_CR1_ODEN_Pos (16U)
10441 #define PWR_CR1_ODEN_Msk (0x1U << PWR_CR1_ODEN_Pos) /*!< 0x00010000 */
10442 #define PWR_CR1_ODEN PWR_CR1_ODEN_Msk /*!< Over Drive enable */
10443 #define PWR_CR1_ODSWEN_Pos (17U)
10444 #define PWR_CR1_ODSWEN_Msk (0x1U << PWR_CR1_ODSWEN_Pos) /*!< 0x00020000 */
10445 #define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk /*!< Over Drive switch enabled */
10446 #define PWR_CR1_UDEN_Pos (18U)
10447 #define PWR_CR1_UDEN_Msk (0x3U << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
10448 #define PWR_CR1_UDEN PWR_CR1_UDEN_Msk /*!< Under Drive enable in stop mode */
10449 #define PWR_CR1_UDEN_0 (0x1U << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
10450 #define PWR_CR1_UDEN_1 (0x2U << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
10451
10452 /******************* Bit definition for PWR_CSR1 register ********************/
10453 #define PWR_CSR1_WUIF_Pos (0U)
10454 #define PWR_CSR1_WUIF_Msk (0x1U << PWR_CSR1_WUIF_Pos) /*!< 0x00000001 */
10455 #define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk /*!< Wake up internal Flag */
10456 #define PWR_CSR1_SBF_Pos (1U)
10457 #define PWR_CSR1_SBF_Msk (0x1U << PWR_CSR1_SBF_Pos) /*!< 0x00000002 */
10458 #define PWR_CSR1_SBF PWR_CSR1_SBF_Msk /*!< Standby Flag */
10459 #define PWR_CSR1_PVDO_Pos (2U)
10460 #define PWR_CSR1_PVDO_Msk (0x1U << PWR_CSR1_PVDO_Pos) /*!< 0x00000004 */
10461 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< PVD Output */
10462 #define PWR_CSR1_BRR_Pos (3U)
10463 #define PWR_CSR1_BRR_Msk (0x1U << PWR_CSR1_BRR_Pos) /*!< 0x00000008 */
10464 #define PWR_CSR1_BRR PWR_CSR1_BRR_Msk /*!< Backup regulator ready */
10465 #define PWR_CSR1_EIWUP_Pos (8U)
10466 #define PWR_CSR1_EIWUP_Msk (0x1U << PWR_CSR1_EIWUP_Pos) /*!< 0x00000100 */
10467 #define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk /*!< Enable internal wakeup */
10468 #define PWR_CSR1_BRE_Pos (9U)
10469 #define PWR_CSR1_BRE_Msk (0x1U << PWR_CSR1_BRE_Pos) /*!< 0x00000200 */
10470 #define PWR_CSR1_BRE PWR_CSR1_BRE_Msk /*!< Backup regulator enable */
10471 #define PWR_CSR1_VOSRDY_Pos (14U)
10472 #define PWR_CSR1_VOSRDY_Msk (0x1U << PWR_CSR1_VOSRDY_Pos) /*!< 0x00004000 */
10473 #define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
10474 #define PWR_CSR1_ODRDY_Pos (16U)
10475 #define PWR_CSR1_ODRDY_Msk (0x1U << PWR_CSR1_ODRDY_Pos) /*!< 0x00010000 */
10476 #define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk /*!< Over Drive generator ready */
10477 #define PWR_CSR1_ODSWRDY_Pos (17U)
10478 #define PWR_CSR1_ODSWRDY_Msk (0x1U << PWR_CSR1_ODSWRDY_Pos) /*!< 0x00020000 */
10479 #define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk /*!< Over Drive Switch ready */
10480 #define PWR_CSR1_UDRDY_Pos (18U)
10481 #define PWR_CSR1_UDRDY_Msk (0x3U << PWR_CSR1_UDRDY_Pos) /*!< 0x000C0000 */
10482 #define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk /*!< Under Drive ready */
10483
10484
10485 /******************** Bit definition for PWR_CR2 register ********************/
10486 #define PWR_CR2_CWUPF1_Pos (0U)
10487 #define PWR_CR2_CWUPF1_Msk (0x1U << PWR_CR2_CWUPF1_Pos) /*!< 0x00000001 */
10488 #define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk /*!< Clear Wakeup Pin Flag for PA0 */
10489 #define PWR_CR2_CWUPF2_Pos (1U)
10490 #define PWR_CR2_CWUPF2_Msk (0x1U << PWR_CR2_CWUPF2_Pos) /*!< 0x00000002 */
10491 #define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk /*!< Clear Wakeup Pin Flag for PA2 */
10492 #define PWR_CR2_CWUPF3_Pos (2U)
10493 #define PWR_CR2_CWUPF3_Msk (0x1U << PWR_CR2_CWUPF3_Pos) /*!< 0x00000004 */
10494 #define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk /*!< Clear Wakeup Pin Flag for PC1 */
10495 #define PWR_CR2_CWUPF4_Pos (3U)
10496 #define PWR_CR2_CWUPF4_Msk (0x1U << PWR_CR2_CWUPF4_Pos) /*!< 0x00000008 */
10497 #define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk /*!< Clear Wakeup Pin Flag for PC13 */
10498 #define PWR_CR2_CWUPF5_Pos (4U)
10499 #define PWR_CR2_CWUPF5_Msk (0x1U << PWR_CR2_CWUPF5_Pos) /*!< 0x00000010 */
10500 #define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk /*!< Clear Wakeup Pin Flag for PI8 */
10501 #define PWR_CR2_CWUPF6_Pos (5U)
10502 #define PWR_CR2_CWUPF6_Msk (0x1U << PWR_CR2_CWUPF6_Pos) /*!< 0x00000020 */
10503 #define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk /*!< Clear Wakeup Pin Flag for PI11 */
10504 #define PWR_CR2_WUPP1_Pos (8U)
10505 #define PWR_CR2_WUPP1_Msk (0x1U << PWR_CR2_WUPP1_Pos) /*!< 0x00000100 */
10506 #define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk /*!< Wakeup Pin Polarity bit for PA0 */
10507 #define PWR_CR2_WUPP2_Pos (9U)
10508 #define PWR_CR2_WUPP2_Msk (0x1U << PWR_CR2_WUPP2_Pos) /*!< 0x00000200 */
10509 #define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk /*!< Wakeup Pin Polarity bit for PA2 */
10510 #define PWR_CR2_WUPP3_Pos (10U)
10511 #define PWR_CR2_WUPP3_Msk (0x1U << PWR_CR2_WUPP3_Pos) /*!< 0x00000400 */
10512 #define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk /*!< Wakeup Pin Polarity bit for PC1 */
10513 #define PWR_CR2_WUPP4_Pos (11U)
10514 #define PWR_CR2_WUPP4_Msk (0x1U << PWR_CR2_WUPP4_Pos) /*!< 0x00000800 */
10515 #define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk /*!< Wakeup Pin Polarity bit for PC13 */
10516 #define PWR_CR2_WUPP5_Pos (12U)
10517 #define PWR_CR2_WUPP5_Msk (0x1U << PWR_CR2_WUPP5_Pos) /*!< 0x00001000 */
10518 #define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk /*!< Wakeup Pin Polarity bit for PI8 */
10519 #define PWR_CR2_WUPP6_Pos (13U)
10520 #define PWR_CR2_WUPP6_Msk (0x1U << PWR_CR2_WUPP6_Pos) /*!< 0x00002000 */
10521 #define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk /*!< Wakeup Pin Polarity bit for PI11 */
10522
10523 /******************* Bit definition for PWR_CSR2 register ********************/
10524 #define PWR_CSR2_WUPF1_Pos (0U)
10525 #define PWR_CSR2_WUPF1_Msk (0x1U << PWR_CSR2_WUPF1_Pos) /*!< 0x00000001 */
10526 #define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk /*!< Wakeup Pin Flag for PA0 */
10527 #define PWR_CSR2_WUPF2_Pos (1U)
10528 #define PWR_CSR2_WUPF2_Msk (0x1U << PWR_CSR2_WUPF2_Pos) /*!< 0x00000002 */
10529 #define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk /*!< Wakeup Pin Flag for PA2 */
10530 #define PWR_CSR2_WUPF3_Pos (2U)
10531 #define PWR_CSR2_WUPF3_Msk (0x1U << PWR_CSR2_WUPF3_Pos) /*!< 0x00000004 */
10532 #define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk /*!< Wakeup Pin Flag for PC1 */
10533 #define PWR_CSR2_WUPF4_Pos (3U)
10534 #define PWR_CSR2_WUPF4_Msk (0x1U << PWR_CSR2_WUPF4_Pos) /*!< 0x00000008 */
10535 #define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk /*!< Wakeup Pin Flag for PC13 */
10536 #define PWR_CSR2_WUPF5_Pos (4U)
10537 #define PWR_CSR2_WUPF5_Msk (0x1U << PWR_CSR2_WUPF5_Pos) /*!< 0x00000010 */
10538 #define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk /*!< Wakeup Pin Flag for PI8 */
10539 #define PWR_CSR2_WUPF6_Pos (5U)
10540 #define PWR_CSR2_WUPF6_Msk (0x1U << PWR_CSR2_WUPF6_Pos) /*!< 0x00000020 */
10541 #define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk /*!< Wakeup Pin Flag for PI11 */
10542 #define PWR_CSR2_EWUP1_Pos (8U)
10543 #define PWR_CSR2_EWUP1_Msk (0x1U << PWR_CSR2_EWUP1_Pos) /*!< 0x00000100 */
10544 #define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk /*!< Enable Wakeup Pin PA0 */
10545 #define PWR_CSR2_EWUP2_Pos (9U)
10546 #define PWR_CSR2_EWUP2_Msk (0x1U << PWR_CSR2_EWUP2_Pos) /*!< 0x00000200 */
10547 #define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk /*!< Enable Wakeup Pin PA2 */
10548 #define PWR_CSR2_EWUP3_Pos (10U)
10549 #define PWR_CSR2_EWUP3_Msk (0x1U << PWR_CSR2_EWUP3_Pos) /*!< 0x00000400 */
10550 #define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk /*!< Enable Wakeup Pin PC1 */
10551 #define PWR_CSR2_EWUP4_Pos (11U)
10552 #define PWR_CSR2_EWUP4_Msk (0x1U << PWR_CSR2_EWUP4_Pos) /*!< 0x00000800 */
10553 #define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk /*!< Enable Wakeup Pin PC13 */
10554 #define PWR_CSR2_EWUP5_Pos (12U)
10555 #define PWR_CSR2_EWUP5_Msk (0x1U << PWR_CSR2_EWUP5_Pos) /*!< 0x00001000 */
10556 #define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk /*!< Enable Wakeup Pin PI8 */
10557 #define PWR_CSR2_EWUP6_Pos (13U)
10558 #define PWR_CSR2_EWUP6_Msk (0x1U << PWR_CSR2_EWUP6_Pos) /*!< 0x00002000 */
10559 #define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk /*!< Enable Wakeup Pin PI11 */
10560
10561 /******************************************************************************/
10562 /* */
10563 /* QUADSPI */
10564 /* */
10565 /******************************************************************************/
10566 /***************** Bit definition for QUADSPI_CR register *******************/
10567 #define QUADSPI_CR_EN_Pos (0U)
10568 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
10569 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
10570 #define QUADSPI_CR_ABORT_Pos (1U)
10571 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
10572 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
10573 #define QUADSPI_CR_DMAEN_Pos (2U)
10574 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
10575 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
10576 #define QUADSPI_CR_TCEN_Pos (3U)
10577 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
10578 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
10579 #define QUADSPI_CR_SSHIFT_Pos (4U)
10580 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
10581 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
10582 #define QUADSPI_CR_DFM_Pos (6U)
10583 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
10584 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
10585 #define QUADSPI_CR_FSEL_Pos (7U)
10586 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
10587 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
10588 #define QUADSPI_CR_FTHRES_Pos (8U)
10589 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
10590 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */
10591 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
10592 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
10593 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
10594 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
10595 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
10596 #define QUADSPI_CR_TEIE_Pos (16U)
10597 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
10598 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
10599 #define QUADSPI_CR_TCIE_Pos (17U)
10600 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
10601 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
10602 #define QUADSPI_CR_FTIE_Pos (18U)
10603 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
10604 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
10605 #define QUADSPI_CR_SMIE_Pos (19U)
10606 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
10607 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
10608 #define QUADSPI_CR_TOIE_Pos (20U)
10609 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
10610 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
10611 #define QUADSPI_CR_APMS_Pos (22U)
10612 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
10613 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
10614 #define QUADSPI_CR_PMM_Pos (23U)
10615 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
10616 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
10617 #define QUADSPI_CR_PRESCALER_Pos (24U)
10618 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
10619 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
10620 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
10621 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
10622 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
10623 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
10624 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
10625 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
10626 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
10627 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
10628
10629 /***************** Bit definition for QUADSPI_DCR register ******************/
10630 #define QUADSPI_DCR_CKMODE_Pos (0U)
10631 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
10632 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
10633 #define QUADSPI_DCR_CSHT_Pos (8U)
10634 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
10635 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
10636 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
10637 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
10638 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
10639 #define QUADSPI_DCR_FSIZE_Pos (16U)
10640 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
10641 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
10642 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
10643 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
10644 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
10645 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
10646 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
10647
10648 /****************** Bit definition for QUADSPI_SR register *******************/
10649 #define QUADSPI_SR_TEF_Pos (0U)
10650 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
10651 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
10652 #define QUADSPI_SR_TCF_Pos (1U)
10653 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
10654 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
10655 #define QUADSPI_SR_FTF_Pos (2U)
10656 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
10657 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
10658 #define QUADSPI_SR_SMF_Pos (3U)
10659 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
10660 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
10661 #define QUADSPI_SR_TOF_Pos (4U)
10662 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
10663 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
10664 #define QUADSPI_SR_BUSY_Pos (5U)
10665 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
10666 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
10667 #define QUADSPI_SR_FLEVEL_Pos (8U)
10668 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
10669 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
10670 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
10671 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
10672 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
10673 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
10674 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
10675
10676 /****************** Bit definition for QUADSPI_FCR register ******************/
10677 #define QUADSPI_FCR_CTEF_Pos (0U)
10678 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
10679 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
10680 #define QUADSPI_FCR_CTCF_Pos (1U)
10681 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
10682 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
10683 #define QUADSPI_FCR_CSMF_Pos (3U)
10684 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
10685 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
10686 #define QUADSPI_FCR_CTOF_Pos (4U)
10687 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
10688 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
10689
10690 /****************** Bit definition for QUADSPI_DLR register ******************/
10691 #define QUADSPI_DLR_DL_Pos (0U)
10692 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
10693 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
10694
10695 /****************** Bit definition for QUADSPI_CCR register ******************/
10696 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
10697 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
10698 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
10699 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
10700 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
10701 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
10702 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
10703 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
10704 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
10705 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
10706 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
10707 #define QUADSPI_CCR_IMODE_Pos (8U)
10708 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
10709 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
10710 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
10711 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
10712 #define QUADSPI_CCR_ADMODE_Pos (10U)
10713 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
10714 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
10715 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
10716 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
10717 #define QUADSPI_CCR_ADSIZE_Pos (12U)
10718 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
10719 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
10720 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
10721 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
10722 #define QUADSPI_CCR_ABMODE_Pos (14U)
10723 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
10724 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
10725 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
10726 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
10727 #define QUADSPI_CCR_ABSIZE_Pos (16U)
10728 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
10729 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
10730 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
10731 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
10732 #define QUADSPI_CCR_DCYC_Pos (18U)
10733 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
10734 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
10735 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
10736 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
10737 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
10738 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
10739 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
10740 #define QUADSPI_CCR_DMODE_Pos (24U)
10741 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
10742 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
10743 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
10744 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
10745 #define QUADSPI_CCR_FMODE_Pos (26U)
10746 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
10747 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
10748 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
10749 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
10750 #define QUADSPI_CCR_SIOO_Pos (28U)
10751 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
10752 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
10753 #define QUADSPI_CCR_DHHC_Pos (30U)
10754 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
10755 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
10756 #define QUADSPI_CCR_DDRM_Pos (31U)
10757 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
10758 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
10759 /****************** Bit definition for QUADSPI_AR register *******************/
10760 #define QUADSPI_AR_ADDRESS_Pos (0U)
10761 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
10762 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
10763
10764 /****************** Bit definition for QUADSPI_ABR register ******************/
10765 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
10766 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
10767 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
10768
10769 /****************** Bit definition for QUADSPI_DR register *******************/
10770 #define QUADSPI_DR_DATA_Pos (0U)
10771 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
10772 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
10773
10774 /****************** Bit definition for QUADSPI_PSMKR register ****************/
10775 #define QUADSPI_PSMKR_MASK_Pos (0U)
10776 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
10777 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
10778
10779 /****************** Bit definition for QUADSPI_PSMAR register ****************/
10780 #define QUADSPI_PSMAR_MATCH_Pos (0U)
10781 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
10782 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
10783
10784 /****************** Bit definition for QUADSPI_PIR register *****************/
10785 #define QUADSPI_PIR_INTERVAL_Pos (0U)
10786 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
10787 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
10788
10789 /****************** Bit definition for QUADSPI_LPTR register *****************/
10790 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
10791 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
10792 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
10793
10794 /******************************************************************************/
10795 /* */
10796 /* Reset and Clock Control */
10797 /* */
10798 /******************************************************************************/
10799 /******************** Bit definition for RCC_CR register ********************/
10800 #define RCC_CR_HSION_Pos (0U)
10801 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
10802 #define RCC_CR_HSION RCC_CR_HSION_Msk
10803 #define RCC_CR_HSIRDY_Pos (1U)
10804 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
10805 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10806 #define RCC_CR_HSITRIM_Pos (3U)
10807 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
10808 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10809 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
10810 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
10811 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
10812 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
10813 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
10814 #define RCC_CR_HSICAL_Pos (8U)
10815 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
10816 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10817 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
10818 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
10819 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
10820 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
10821 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
10822 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
10823 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
10824 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
10825 #define RCC_CR_HSEON_Pos (16U)
10826 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
10827 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
10828 #define RCC_CR_HSERDY_Pos (17U)
10829 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
10830 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10831 #define RCC_CR_HSEBYP_Pos (18U)
10832 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
10833 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10834 #define RCC_CR_CSSON_Pos (19U)
10835 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
10836 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
10837 #define RCC_CR_PLLON_Pos (24U)
10838 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
10839 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
10840 #define RCC_CR_PLLRDY_Pos (25U)
10841 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
10842 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10843 #define RCC_CR_PLLI2SON_Pos (26U)
10844 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
10845 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
10846 #define RCC_CR_PLLI2SRDY_Pos (27U)
10847 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
10848 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
10849 #define RCC_CR_PLLSAION_Pos (28U)
10850 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
10851 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
10852 #define RCC_CR_PLLSAIRDY_Pos (29U)
10853 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
10854 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
10855
10856 /******************** Bit definition for RCC_PLLCFGR register ***************/
10857 #define RCC_PLLCFGR_PLLM_Pos (0U)
10858 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
10859 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10860 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
10861 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
10862 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
10863 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
10864 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
10865 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
10866 #define RCC_PLLCFGR_PLLN_Pos (6U)
10867 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
10868 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10869 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
10870 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
10871 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
10872 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
10873 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
10874 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
10875 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
10876 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
10877 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
10878 #define RCC_PLLCFGR_PLLP_Pos (16U)
10879 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
10880 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10881 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
10882 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
10883 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
10884 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
10885 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10886 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
10887 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
10888 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10889 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
10890 #define RCC_PLLCFGR_PLLQ_Pos (24U)
10891 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
10892 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10893 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
10894 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
10895 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
10896 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
10897
10898 #define RCC_PLLCFGR_PLLR_Pos (28U)
10899 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
10900 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
10901 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
10902 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
10903 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
10904
10905 /******************** Bit definition for RCC_CFGR register ******************/
10906 /*!< SW configuration */
10907 #define RCC_CFGR_SW_Pos (0U)
10908 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
10909 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
10910 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
10911 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
10912 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
10913 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
10914 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
10915
10916 /*!< SWS configuration */
10917 #define RCC_CFGR_SWS_Pos (2U)
10918 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
10919 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
10920 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
10921 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
10922 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
10923 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
10924 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
10925
10926 /*!< HPRE configuration */
10927 #define RCC_CFGR_HPRE_Pos (4U)
10928 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
10929 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
10930 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
10931 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
10932 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
10933 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
10934
10935 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
10936 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
10937 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
10938 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
10939 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
10940 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
10941 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
10942 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
10943 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
10944
10945 /*!< PPRE1 configuration */
10946 #define RCC_CFGR_PPRE1_Pos (10U)
10947 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
10948 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
10949 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
10950 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
10951 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
10952
10953 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
10954 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
10955 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
10956 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
10957 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
10958
10959 /*!< PPRE2 configuration */
10960 #define RCC_CFGR_PPRE2_Pos (13U)
10961 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
10962 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
10963 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
10964 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
10965 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
10966
10967 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
10968 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
10969 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
10970 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
10971 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
10972
10973 /*!< RTCPRE configuration */
10974 #define RCC_CFGR_RTCPRE_Pos (16U)
10975 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
10976 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
10977 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
10978 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
10979 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
10980 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
10981 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
10982
10983 /*!< MCO1 configuration */
10984 #define RCC_CFGR_MCO1_Pos (21U)
10985 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
10986 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
10987 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
10988 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
10989
10990 #define RCC_CFGR_I2SSRC_Pos (23U)
10991 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
10992 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
10993
10994 #define RCC_CFGR_MCO1PRE_Pos (24U)
10995 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
10996 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
10997 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
10998 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
10999 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
11000
11001 #define RCC_CFGR_MCO2PRE_Pos (27U)
11002 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
11003 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
11004 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
11005 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
11006 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
11007
11008 #define RCC_CFGR_MCO2_Pos (30U)
11009 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
11010 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
11011 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
11012 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
11013
11014 /******************** Bit definition for RCC_CIR register *******************/
11015 #define RCC_CIR_LSIRDYF_Pos (0U)
11016 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
11017 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
11018 #define RCC_CIR_LSERDYF_Pos (1U)
11019 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
11020 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
11021 #define RCC_CIR_HSIRDYF_Pos (2U)
11022 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
11023 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
11024 #define RCC_CIR_HSERDYF_Pos (3U)
11025 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
11026 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
11027 #define RCC_CIR_PLLRDYF_Pos (4U)
11028 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
11029 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
11030 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
11031 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
11032 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
11033 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
11034 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
11035 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
11036 #define RCC_CIR_CSSF_Pos (7U)
11037 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
11038 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
11039 #define RCC_CIR_LSIRDYIE_Pos (8U)
11040 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
11041 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
11042 #define RCC_CIR_LSERDYIE_Pos (9U)
11043 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
11044 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
11045 #define RCC_CIR_HSIRDYIE_Pos (10U)
11046 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
11047 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
11048 #define RCC_CIR_HSERDYIE_Pos (11U)
11049 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
11050 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
11051 #define RCC_CIR_PLLRDYIE_Pos (12U)
11052 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
11053 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
11054 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
11055 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
11056 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
11057 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
11058 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
11059 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
11060 #define RCC_CIR_LSIRDYC_Pos (16U)
11061 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
11062 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
11063 #define RCC_CIR_LSERDYC_Pos (17U)
11064 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
11065 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
11066 #define RCC_CIR_HSIRDYC_Pos (18U)
11067 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
11068 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
11069 #define RCC_CIR_HSERDYC_Pos (19U)
11070 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
11071 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
11072 #define RCC_CIR_PLLRDYC_Pos (20U)
11073 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
11074 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
11075 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
11076 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
11077 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
11078 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
11079 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
11080 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
11081 #define RCC_CIR_CSSC_Pos (23U)
11082 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
11083 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
11084
11085 /******************** Bit definition for RCC_AHB1RSTR register **************/
11086 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
11087 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
11088 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
11089 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
11090 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
11091 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
11092 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
11093 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
11094 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
11095 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
11096 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
11097 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
11098 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
11099 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
11100 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
11101 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
11102 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
11103 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
11104 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
11105 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
11106 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
11107 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
11108 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
11109 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
11110 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
11111 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
11112 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
11113 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
11114 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
11115 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
11116 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
11117 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
11118 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
11119 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
11120 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
11121 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
11122 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
11123 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
11124 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
11125 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
11126 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
11127 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
11128 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
11129 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
11130 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
11131 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
11132 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
11133 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
11134 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
11135 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
11136 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
11137
11138 /******************** Bit definition for RCC_AHB2RSTR register **************/
11139 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
11140 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
11141 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
11142 #define RCC_AHB2RSTR_JPEGRST_Pos (1U)
11143 #define RCC_AHB2RSTR_JPEGRST_Msk (0x1U << RCC_AHB2RSTR_JPEGRST_Pos) /*!< 0x00000002 */
11144 #define RCC_AHB2RSTR_JPEGRST RCC_AHB2RSTR_JPEGRST_Msk
11145 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
11146 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
11147 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
11148 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
11149 #define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
11150 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
11151 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
11152 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
11153 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
11154 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
11155 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
11156 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
11157
11158 /******************** Bit definition for RCC_AHB3RSTR register **************/
11159
11160 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
11161 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
11162 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
11163 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
11164 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
11165 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
11166
11167 /******************** Bit definition for RCC_APB1RSTR register **************/
11168 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
11169 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
11170 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
11171 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
11172 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
11173 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
11174 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
11175 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
11176 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
11177 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
11178 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
11179 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
11180 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
11181 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
11182 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
11183 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
11184 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
11185 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
11186 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
11187 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
11188 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
11189 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
11190 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
11191 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
11192 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
11193 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
11194 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
11195 #define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
11196 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
11197 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
11198 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
11199 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
11200 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
11201 #define RCC_APB1RSTR_CAN3RST_Pos (13U)
11202 #define RCC_APB1RSTR_CAN3RST_Msk (0x1U << RCC_APB1RSTR_CAN3RST_Pos) /*!< 0x00002000 */
11203 #define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
11204 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
11205 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
11206 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
11207 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
11208 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
11209 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
11210 #define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
11211 #define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1U << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
11212 #define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
11213 #define RCC_APB1RSTR_USART2RST_Pos (17U)
11214 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
11215 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
11216 #define RCC_APB1RSTR_USART3RST_Pos (18U)
11217 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
11218 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
11219 #define RCC_APB1RSTR_UART4RST_Pos (19U)
11220 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
11221 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
11222 #define RCC_APB1RSTR_UART5RST_Pos (20U)
11223 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
11224 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
11225 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
11226 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
11227 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
11228 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
11229 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
11230 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
11231 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
11232 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
11233 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
11234 #define RCC_APB1RSTR_I2C4RST_Pos (24U)
11235 #define RCC_APB1RSTR_I2C4RST_Msk (0x1U << RCC_APB1RSTR_I2C4RST_Pos) /*!< 0x01000000 */
11236 #define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk
11237 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
11238 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
11239 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
11240 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
11241 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
11242 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
11243 #define RCC_APB1RSTR_CECRST_Pos (27U)
11244 #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x08000000 */
11245 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
11246 #define RCC_APB1RSTR_PWRRST_Pos (28U)
11247 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
11248 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
11249 #define RCC_APB1RSTR_DACRST_Pos (29U)
11250 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
11251 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
11252 #define RCC_APB1RSTR_UART7RST_Pos (30U)
11253 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
11254 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
11255 #define RCC_APB1RSTR_UART8RST_Pos (31U)
11256 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
11257 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
11258
11259 /******************** Bit definition for RCC_APB2RSTR register **************/
11260 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
11261 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
11262 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
11263 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
11264 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
11265 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
11266 #define RCC_APB2RSTR_USART1RST_Pos (4U)
11267 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
11268 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
11269 #define RCC_APB2RSTR_USART6RST_Pos (5U)
11270 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
11271 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
11272 #define RCC_APB2RSTR_SDMMC2RST_Pos (7U)
11273 #define RCC_APB2RSTR_SDMMC2RST_Msk (0x1U << RCC_APB2RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
11274 #define RCC_APB2RSTR_SDMMC2RST RCC_APB2RSTR_SDMMC2RST_Msk
11275 #define RCC_APB2RSTR_ADCRST_Pos (8U)
11276 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
11277 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
11278 #define RCC_APB2RSTR_SDMMC1RST_Pos (11U)
11279 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000800 */
11280 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
11281 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
11282 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
11283 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
11284 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
11285 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
11286 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
11287 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
11288 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
11289 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
11290 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
11291 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
11292 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
11293 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
11294 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
11295 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
11296 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
11297 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
11298 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
11299 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
11300 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
11301 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
11302 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
11303 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
11304 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
11305 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
11306 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
11307 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
11308 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
11309 #define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
11310 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
11311 #define RCC_APB2RSTR_LTDCRST_Pos (26U)
11312 #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
11313 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
11314 #define RCC_APB2RSTR_DSIRST_Pos (27U)
11315 #define RCC_APB2RSTR_DSIRST_Msk (0x1U << RCC_APB2RSTR_DSIRST_Pos) /*!< 0x08000000 */
11316 #define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
11317 #define RCC_APB2RSTR_DFSDM1RST_Pos (29U)
11318 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x20000000 */
11319 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
11320 #define RCC_APB2RSTR_MDIORST_Pos (30U)
11321 #define RCC_APB2RSTR_MDIORST_Msk (0x1U << RCC_APB2RSTR_MDIORST_Pos) /*!< 0x40000000 */
11322 #define RCC_APB2RSTR_MDIORST RCC_APB2RSTR_MDIORST_Msk
11323
11324 /******************** Bit definition for RCC_AHB1ENR register ***************/
11325 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
11326 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
11327 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
11328 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
11329 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
11330 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
11331 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
11332 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
11333 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
11334 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
11335 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
11336 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
11337 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
11338 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
11339 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
11340 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
11341 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
11342 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
11343 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
11344 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
11345 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
11346 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
11347 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
11348 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
11349 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
11350 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
11351 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
11352 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
11353 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
11354 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
11355 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
11356 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
11357 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
11358 #define RCC_AHB1ENR_CRCEN_Pos (12U)
11359 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
11360 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
11361 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
11362 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
11363 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
11364 #define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)
11365 #define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1U << RCC_AHB1ENR_DTCMRAMEN_Pos) /*!< 0x00100000 */
11366 #define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk
11367 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
11368 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
11369 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
11370 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
11371 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
11372 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
11373 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
11374 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
11375 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
11376 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
11377 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
11378 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
11379 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
11380 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
11381 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
11382 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
11383 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
11384 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
11385 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
11386 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
11387 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
11388 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
11389 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
11390 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
11391 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
11392 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
11393 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
11394
11395 /******************** Bit definition for RCC_AHB2ENR register ***************/
11396 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
11397 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
11398 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
11399 #define RCC_AHB2ENR_JPEGEN_Pos (1U)
11400 #define RCC_AHB2ENR_JPEGEN_Msk (0x1U << RCC_AHB2ENR_JPEGEN_Pos) /*!< 0x00000002 */
11401 #define RCC_AHB2ENR_JPEGEN RCC_AHB2ENR_JPEGEN_Msk
11402 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
11403 #define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
11404 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
11405 #define RCC_AHB2ENR_HASHEN_Pos (5U)
11406 #define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
11407 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
11408 #define RCC_AHB2ENR_RNGEN_Pos (6U)
11409 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
11410 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11411 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
11412 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
11413 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11414
11415 /******************** Bit definition for RCC_AHB3ENR register ***************/
11416 #define RCC_AHB3ENR_FMCEN_Pos (0U)
11417 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
11418 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11419 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
11420 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
11421 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
11422
11423 /******************** Bit definition for RCC_APB1ENR register ***************/
11424 #define RCC_APB1ENR_TIM2EN_Pos (0U)
11425 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
11426 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
11427 #define RCC_APB1ENR_TIM3EN_Pos (1U)
11428 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
11429 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
11430 #define RCC_APB1ENR_TIM4EN_Pos (2U)
11431 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
11432 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
11433 #define RCC_APB1ENR_TIM5EN_Pos (3U)
11434 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
11435 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
11436 #define RCC_APB1ENR_TIM6EN_Pos (4U)
11437 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
11438 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
11439 #define RCC_APB1ENR_TIM7EN_Pos (5U)
11440 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
11441 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
11442 #define RCC_APB1ENR_TIM12EN_Pos (6U)
11443 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
11444 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
11445 #define RCC_APB1ENR_TIM13EN_Pos (7U)
11446 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
11447 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
11448 #define RCC_APB1ENR_TIM14EN_Pos (8U)
11449 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
11450 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
11451 #define RCC_APB1ENR_LPTIM1EN_Pos (9U)
11452 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
11453 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
11454 #define RCC_APB1ENR_RTCEN_Pos (10U)
11455 #define RCC_APB1ENR_RTCEN_Msk (0x1U << RCC_APB1ENR_RTCEN_Pos) /*!< 0x00000400 */
11456 #define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk
11457 #define RCC_APB1ENR_WWDGEN_Pos (11U)
11458 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
11459 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
11460 #define RCC_APB1ENR_CAN3EN_Pos (13U)
11461 #define RCC_APB1ENR_CAN3EN_Msk (0x1U << RCC_APB1ENR_CAN3EN_Pos) /*!< 0x00002000 */
11462 #define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
11463 #define RCC_APB1ENR_SPI2EN_Pos (14U)
11464 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
11465 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
11466 #define RCC_APB1ENR_SPI3EN_Pos (15U)
11467 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
11468 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
11469 #define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
11470 #define RCC_APB1ENR_SPDIFRXEN_Msk (0x1U << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
11471 #define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
11472 #define RCC_APB1ENR_USART2EN_Pos (17U)
11473 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
11474 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
11475 #define RCC_APB1ENR_USART3EN_Pos (18U)
11476 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
11477 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
11478 #define RCC_APB1ENR_UART4EN_Pos (19U)
11479 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
11480 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
11481 #define RCC_APB1ENR_UART5EN_Pos (20U)
11482 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
11483 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
11484 #define RCC_APB1ENR_I2C1EN_Pos (21U)
11485 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
11486 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
11487 #define RCC_APB1ENR_I2C2EN_Pos (22U)
11488 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
11489 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
11490 #define RCC_APB1ENR_I2C3EN_Pos (23U)
11491 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
11492 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
11493 #define RCC_APB1ENR_I2C4EN_Pos (24U)
11494 #define RCC_APB1ENR_I2C4EN_Msk (0x1U << RCC_APB1ENR_I2C4EN_Pos) /*!< 0x01000000 */
11495 #define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk
11496 #define RCC_APB1ENR_CAN1EN_Pos (25U)
11497 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
11498 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
11499 #define RCC_APB1ENR_CAN2EN_Pos (26U)
11500 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
11501 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
11502 #define RCC_APB1ENR_CECEN_Pos (27U)
11503 #define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x08000000 */
11504 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
11505 #define RCC_APB1ENR_PWREN_Pos (28U)
11506 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
11507 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
11508 #define RCC_APB1ENR_DACEN_Pos (29U)
11509 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
11510 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
11511 #define RCC_APB1ENR_UART7EN_Pos (30U)
11512 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
11513 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
11514 #define RCC_APB1ENR_UART8EN_Pos (31U)
11515 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
11516 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
11517
11518 /******************** Bit definition for RCC_APB2ENR register ***************/
11519 #define RCC_APB2ENR_TIM1EN_Pos (0U)
11520 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
11521 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11522 #define RCC_APB2ENR_TIM8EN_Pos (1U)
11523 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
11524 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11525 #define RCC_APB2ENR_USART1EN_Pos (4U)
11526 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
11527 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11528 #define RCC_APB2ENR_USART6EN_Pos (5U)
11529 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
11530 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
11531 #define RCC_APB2ENR_SDMMC2EN_Pos (7U)
11532 #define RCC_APB2ENR_SDMMC2EN_Msk (0x1U << RCC_APB2ENR_SDMMC2EN_Pos) /*!< 0x00000080 */
11533 #define RCC_APB2ENR_SDMMC2EN RCC_APB2ENR_SDMMC2EN_Msk
11534 #define RCC_APB2ENR_ADC1EN_Pos (8U)
11535 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
11536 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
11537 #define RCC_APB2ENR_ADC2EN_Pos (9U)
11538 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
11539 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
11540 #define RCC_APB2ENR_ADC3EN_Pos (10U)
11541 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
11542 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
11543 #define RCC_APB2ENR_SDMMC1EN_Pos (11U)
11544 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000800 */
11545 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
11546 #define RCC_APB2ENR_SPI1EN_Pos (12U)
11547 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
11548 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11549 #define RCC_APB2ENR_SPI4EN_Pos (13U)
11550 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
11551 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
11552 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
11553 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
11554 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11555 #define RCC_APB2ENR_TIM9EN_Pos (16U)
11556 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
11557 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
11558 #define RCC_APB2ENR_TIM10EN_Pos (17U)
11559 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
11560 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
11561 #define RCC_APB2ENR_TIM11EN_Pos (18U)
11562 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
11563 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
11564 #define RCC_APB2ENR_SPI5EN_Pos (20U)
11565 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
11566 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
11567 #define RCC_APB2ENR_SPI6EN_Pos (21U)
11568 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
11569 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
11570 #define RCC_APB2ENR_SAI1EN_Pos (22U)
11571 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
11572 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11573 #define RCC_APB2ENR_SAI2EN_Pos (23U)
11574 #define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
11575 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
11576 #define RCC_APB2ENR_LTDCEN_Pos (26U)
11577 #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
11578 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
11579 #define RCC_APB2ENR_DSIEN_Pos (27U)
11580 #define RCC_APB2ENR_DSIEN_Msk (0x1U << RCC_APB2ENR_DSIEN_Pos) /*!< 0x08000000 */
11581 #define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
11582 #define RCC_APB2ENR_DFSDM1EN_Pos (29U)
11583 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x20000000 */
11584 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
11585 #define RCC_APB2ENR_MDIOEN_Pos (30U)
11586 #define RCC_APB2ENR_MDIOEN_Msk (0x1U << RCC_APB2ENR_MDIOEN_Pos) /*!< 0x40000000 */
11587 #define RCC_APB2ENR_MDIOEN RCC_APB2ENR_MDIOEN_Msk
11588
11589 /******************** Bit definition for RCC_AHB1LPENR register *************/
11590 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
11591 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
11592 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
11593 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
11594 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
11595 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
11596 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
11597 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
11598 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
11599 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
11600 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
11601 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
11602 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
11603 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
11604 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
11605 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
11606 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
11607 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
11608 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
11609 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
11610 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
11611 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
11612 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
11613 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
11614 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
11615 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
11616 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
11617 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
11618 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
11619 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
11620 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
11621 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
11622 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
11623 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
11624 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
11625 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
11626 #define RCC_AHB1LPENR_AXILPEN_Pos (13U)
11627 #define RCC_AHB1LPENR_AXILPEN_Msk (0x1U << RCC_AHB1LPENR_AXILPEN_Pos) /*!< 0x00002000 */
11628 #define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk
11629 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
11630 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
11631 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
11632 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
11633 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
11634 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
11635 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
11636 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
11637 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
11638 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
11639 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
11640 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
11641 #define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)
11642 #define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1U << RCC_AHB1LPENR_DTCMLPEN_Pos) /*!< 0x00100000 */
11643 #define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk
11644 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
11645 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
11646 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
11647 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
11648 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
11649 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
11650 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
11651 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
11652 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
11653 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
11654 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
11655 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
11656 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
11657 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
11658 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
11659 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
11660 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
11661 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
11662 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
11663 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
11664 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
11665 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
11666 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
11667 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
11668 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
11669 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
11670 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
11671
11672 /******************** Bit definition for RCC_AHB2LPENR register *************/
11673 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
11674 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
11675 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
11676 #define RCC_AHB2LPENR_JPEGLPEN_Pos (1U)
11677 #define RCC_AHB2LPENR_JPEGLPEN_Msk (0x1U << RCC_AHB2LPENR_JPEGLPEN_Pos) /*!< 0x00000002 */
11678 #define RCC_AHB2LPENR_JPEGLPEN RCC_AHB2LPENR_JPEGLPEN_Msk
11679 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
11680 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
11681 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
11682 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
11683 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
11684 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
11685 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
11686 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
11687 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
11688 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
11689 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
11690 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
11691
11692 /******************** Bit definition for RCC_AHB3LPENR register *************/
11693 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
11694 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
11695 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
11696 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
11697 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
11698 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
11699 /******************** Bit definition for RCC_APB1LPENR register *************/
11700 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
11701 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
11702 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
11703 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
11704 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
11705 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
11706 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
11707 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
11708 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
11709 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
11710 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
11711 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
11712 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
11713 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
11714 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
11715 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
11716 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
11717 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
11718 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
11719 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
11720 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
11721 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
11722 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
11723 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
11724 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
11725 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
11726 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
11727 #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
11728 #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
11729 #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
11730 #define RCC_APB1LPENR_RTCLPEN_Pos (10U)
11731 #define RCC_APB1LPENR_RTCLPEN_Msk (0x1U << RCC_APB1LPENR_RTCLPEN_Pos) /*!< 0x00000400 */
11732 #define RCC_APB1LPENR_RTCLPEN RCC_APB1LPENR_RTCLPEN_Msk
11733 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
11734 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
11735 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
11736 #define RCC_APB1LPENR_CAN3LPEN_Pos (13U)
11737 #define RCC_APB1LPENR_CAN3LPEN_Msk (0x1U << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x00002000 */
11738 #define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
11739 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
11740 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
11741 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
11742 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
11743 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
11744 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
11745 #define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
11746 #define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1U << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
11747 #define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
11748 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
11749 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
11750 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
11751 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
11752 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
11753 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
11754 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
11755 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
11756 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
11757 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
11758 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
11759 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
11760 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
11761 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
11762 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
11763 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
11764 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
11765 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
11766 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
11767 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
11768 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
11769 #define RCC_APB1LPENR_I2C4LPEN_Pos (24U)
11770 #define RCC_APB1LPENR_I2C4LPEN_Msk (0x1U << RCC_APB1LPENR_I2C4LPEN_Pos) /*!< 0x01000000 */
11771 #define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk
11772 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
11773 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
11774 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
11775 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
11776 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
11777 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
11778 #define RCC_APB1LPENR_CECLPEN_Pos (27U)
11779 #define RCC_APB1LPENR_CECLPEN_Msk (0x1U << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
11780 #define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
11781 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
11782 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
11783 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
11784 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
11785 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
11786 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
11787 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
11788 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
11789 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
11790 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
11791 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
11792 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
11793
11794 /******************** Bit definition for RCC_APB2LPENR register *************/
11795 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
11796 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
11797 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
11798 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
11799 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
11800 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
11801 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
11802 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
11803 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
11804 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
11805 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
11806 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
11807 #define RCC_APB2LPENR_SDMMC2LPEN_Pos (7U)
11808 #define RCC_APB2LPENR_SDMMC2LPEN_Msk (0x1U << RCC_APB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
11809 #define RCC_APB2LPENR_SDMMC2LPEN RCC_APB2LPENR_SDMMC2LPEN_Msk
11810 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
11811 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
11812 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
11813 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
11814 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
11815 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
11816 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
11817 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
11818 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
11819 #define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)
11820 #define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1U << RCC_APB2LPENR_SDMMC1LPEN_Pos) /*!< 0x00000800 */
11821 #define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk
11822 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
11823 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
11824 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
11825 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
11826 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
11827 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
11828 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
11829 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
11830 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
11831 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
11832 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
11833 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
11834 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
11835 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
11836 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
11837 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
11838 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
11839 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
11840 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
11841 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
11842 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
11843 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
11844 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
11845 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
11846 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
11847 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
11848 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
11849 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
11850 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1U << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
11851 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
11852 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
11853 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
11854 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
11855 #define RCC_APB2LPENR_DSILPEN_Pos (27U)
11856 #define RCC_APB2LPENR_DSILPEN_Msk (0x1U << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */
11857 #define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
11858 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (29U)
11859 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x20000000 */
11860 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
11861 #define RCC_APB2LPENR_MDIOLPEN_Pos (30U)
11862 #define RCC_APB2LPENR_MDIOLPEN_Msk (0x1U << RCC_APB2LPENR_MDIOLPEN_Pos) /*!< 0x40000000 */
11863 #define RCC_APB2LPENR_MDIOLPEN RCC_APB2LPENR_MDIOLPEN_Msk
11864
11865 /******************** Bit definition for RCC_BDCR register ******************/
11866 #define RCC_BDCR_LSEON_Pos (0U)
11867 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
11868 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11869 #define RCC_BDCR_LSERDY_Pos (1U)
11870 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
11871 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11872 #define RCC_BDCR_LSEBYP_Pos (2U)
11873 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
11874 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11875 #define RCC_BDCR_LSEDRV_Pos (3U)
11876 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
11877 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
11878 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
11879 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
11880 #define RCC_BDCR_RTCSEL_Pos (8U)
11881 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
11882 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11883 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
11884 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
11885 #define RCC_BDCR_RTCEN_Pos (15U)
11886 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
11887 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11888 #define RCC_BDCR_BDRST_Pos (16U)
11889 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
11890 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11891
11892 /******************** Bit definition for RCC_CSR register *******************/
11893 #define RCC_CSR_LSION_Pos (0U)
11894 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
11895 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
11896 #define RCC_CSR_LSIRDY_Pos (1U)
11897 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
11898 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11899 #define RCC_CSR_RMVF_Pos (24U)
11900 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
11901 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11902 #define RCC_CSR_BORRSTF_Pos (25U)
11903 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
11904 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11905 #define RCC_CSR_PINRSTF_Pos (26U)
11906 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
11907 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11908 #define RCC_CSR_PORRSTF_Pos (27U)
11909 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
11910 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
11911 #define RCC_CSR_SFTRSTF_Pos (28U)
11912 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
11913 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11914 #define RCC_CSR_IWDGRSTF_Pos (29U)
11915 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
11916 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11917 #define RCC_CSR_WWDGRSTF_Pos (30U)
11918 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
11919 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11920 #define RCC_CSR_LPWRRSTF_Pos (31U)
11921 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
11922 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11923
11924 /******************** Bit definition for RCC_SSCGR register *****************/
11925 #define RCC_SSCGR_MODPER_Pos (0U)
11926 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
11927 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
11928 #define RCC_SSCGR_INCSTEP_Pos (13U)
11929 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
11930 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
11931 #define RCC_SSCGR_SPREADSEL_Pos (30U)
11932 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
11933 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
11934 #define RCC_SSCGR_SSCGEN_Pos (31U)
11935 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
11936 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
11937
11938 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
11939 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
11940 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
11941 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
11942 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
11943 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
11944 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
11945 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
11946 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
11947 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
11948 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
11949 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
11950 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
11951 #define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
11952 #define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
11953 #define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
11954 #define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
11955 #define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
11956 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
11957 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
11958 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
11959 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
11960 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
11961 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
11962 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
11963 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
11964 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
11965 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
11966 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
11967 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
11968 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
11969
11970 /******************** Bit definition for RCC_PLLSAICFGR register ************/
11971 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
11972 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
11973 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
11974 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
11975 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
11976 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
11977 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
11978 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
11979 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
11980 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
11981 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
11982 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
11983 #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
11984 #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
11985 #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
11986 #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
11987 #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
11988 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
11989 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
11990 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
11991 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
11992 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
11993 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
11994 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
11995 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
11996 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
11997 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
11998 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
11999 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
12000 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
12001
12002 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
12003 #define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)
12004 #define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
12005 #define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk
12006 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
12007 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
12008 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
12009 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
12010 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
12011
12012 #define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)
12013 #define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
12014 #define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk
12015 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
12016 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
12017 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
12018 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
12019 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
12020
12021 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U)
12022 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
12023 #define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk
12024 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
12025 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
12026
12027 /*
12028 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
12029 */
12030 #define RCC_SAI1SEL_PLLSRC_SUPPORT
12031 #define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
12032 #define RCC_DCKCFGR1_SAI1SEL_Msk (0x3U << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00300000 */
12033 #define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk
12034 #define RCC_DCKCFGR1_SAI1SEL_0 (0x1U << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00100000 */
12035 #define RCC_DCKCFGR1_SAI1SEL_1 (0x2U << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */
12036
12037 /*
12038 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
12039 */
12040 #define RCC_SAI2SEL_PLLSRC_SUPPORT
12041 #define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
12042 #define RCC_DCKCFGR1_SAI2SEL_Msk (0x3U << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00C00000 */
12043 #define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk
12044 #define RCC_DCKCFGR1_SAI2SEL_0 (0x1U << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00400000 */
12045 #define RCC_DCKCFGR1_SAI2SEL_1 (0x2U << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00800000 */
12046
12047 #define RCC_DCKCFGR1_TIMPRE_Pos (24U)
12048 #define RCC_DCKCFGR1_TIMPRE_Msk (0x1U << RCC_DCKCFGR1_TIMPRE_Pos) /*!< 0x01000000 */
12049 #define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk
12050 #define RCC_DCKCFGR1_DFSDM1SEL_Pos (25U)
12051 #define RCC_DCKCFGR1_DFSDM1SEL_Msk (0x1U << RCC_DCKCFGR1_DFSDM1SEL_Pos) /*!< 0x02000000 */
12052 #define RCC_DCKCFGR1_DFSDM1SEL RCC_DCKCFGR1_DFSDM1SEL_Msk
12053 #define RCC_DCKCFGR1_ADFSDM1SEL_Pos (26U)
12054 #define RCC_DCKCFGR1_ADFSDM1SEL_Msk (0x1U << RCC_DCKCFGR1_ADFSDM1SEL_Pos) /*!< 0x04000000 */
12055 #define RCC_DCKCFGR1_ADFSDM1SEL RCC_DCKCFGR1_ADFSDM1SEL_Msk
12056
12057 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
12058 #define RCC_DCKCFGR2_USART1SEL_Pos (0U)
12059 #define RCC_DCKCFGR2_USART1SEL_Msk (0x3U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000003 */
12060 #define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk
12061 #define RCC_DCKCFGR2_USART1SEL_0 (0x1U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000001 */
12062 #define RCC_DCKCFGR2_USART1SEL_1 (0x2U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000002 */
12063 #define RCC_DCKCFGR2_USART2SEL_Pos (2U)
12064 #define RCC_DCKCFGR2_USART2SEL_Msk (0x3U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x0000000C */
12065 #define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk
12066 #define RCC_DCKCFGR2_USART2SEL_0 (0x1U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000004 */
12067 #define RCC_DCKCFGR2_USART2SEL_1 (0x2U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000008 */
12068 #define RCC_DCKCFGR2_USART3SEL_Pos (4U)
12069 #define RCC_DCKCFGR2_USART3SEL_Msk (0x3U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000030 */
12070 #define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk
12071 #define RCC_DCKCFGR2_USART3SEL_0 (0x1U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000010 */
12072 #define RCC_DCKCFGR2_USART3SEL_1 (0x2U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000020 */
12073 #define RCC_DCKCFGR2_UART4SEL_Pos (6U)
12074 #define RCC_DCKCFGR2_UART4SEL_Msk (0x3U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x000000C0 */
12075 #define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk
12076 #define RCC_DCKCFGR2_UART4SEL_0 (0x1U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000040 */
12077 #define RCC_DCKCFGR2_UART4SEL_1 (0x2U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000080 */
12078 #define RCC_DCKCFGR2_UART5SEL_Pos (8U)
12079 #define RCC_DCKCFGR2_UART5SEL_Msk (0x3U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000300 */
12080 #define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk
12081 #define RCC_DCKCFGR2_UART5SEL_0 (0x1U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000100 */
12082 #define RCC_DCKCFGR2_UART5SEL_1 (0x2U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000200 */
12083 #define RCC_DCKCFGR2_USART6SEL_Pos (10U)
12084 #define RCC_DCKCFGR2_USART6SEL_Msk (0x3U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000C00 */
12085 #define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk
12086 #define RCC_DCKCFGR2_USART6SEL_0 (0x1U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000400 */
12087 #define RCC_DCKCFGR2_USART6SEL_1 (0x2U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000800 */
12088 #define RCC_DCKCFGR2_UART7SEL_Pos (12U)
12089 #define RCC_DCKCFGR2_UART7SEL_Msk (0x3U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00003000 */
12090 #define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk
12091 #define RCC_DCKCFGR2_UART7SEL_0 (0x1U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00001000 */
12092 #define RCC_DCKCFGR2_UART7SEL_1 (0x2U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00002000 */
12093 #define RCC_DCKCFGR2_UART8SEL_Pos (14U)
12094 #define RCC_DCKCFGR2_UART8SEL_Msk (0x3U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x0000C000 */
12095 #define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk
12096 #define RCC_DCKCFGR2_UART8SEL_0 (0x1U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00004000 */
12097 #define RCC_DCKCFGR2_UART8SEL_1 (0x2U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00008000 */
12098 #define RCC_DCKCFGR2_I2C1SEL_Pos (16U)
12099 #define RCC_DCKCFGR2_I2C1SEL_Msk (0x3U << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00030000 */
12100 #define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk
12101 #define RCC_DCKCFGR2_I2C1SEL_0 (0x1U << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00010000 */
12102 #define RCC_DCKCFGR2_I2C1SEL_1 (0x2U << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00020000 */
12103 #define RCC_DCKCFGR2_I2C2SEL_Pos (18U)
12104 #define RCC_DCKCFGR2_I2C2SEL_Msk (0x3U << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x000C0000 */
12105 #define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk
12106 #define RCC_DCKCFGR2_I2C2SEL_0 (0x1U << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00040000 */
12107 #define RCC_DCKCFGR2_I2C2SEL_1 (0x2U << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00080000 */
12108 #define RCC_DCKCFGR2_I2C3SEL_Pos (20U)
12109 #define RCC_DCKCFGR2_I2C3SEL_Msk (0x3U << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00300000 */
12110 #define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk
12111 #define RCC_DCKCFGR2_I2C3SEL_0 (0x1U << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00100000 */
12112 #define RCC_DCKCFGR2_I2C3SEL_1 (0x2U << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00200000 */
12113 #define RCC_DCKCFGR2_I2C4SEL_Pos (22U)
12114 #define RCC_DCKCFGR2_I2C4SEL_Msk (0x3U << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00C00000 */
12115 #define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk
12116 #define RCC_DCKCFGR2_I2C4SEL_0 (0x1U << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00400000 */
12117 #define RCC_DCKCFGR2_I2C4SEL_1 (0x2U << RCC_DCKCFGR2_I2C4SEL_Pos) /*!< 0x00800000 */
12118 #define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)
12119 #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x03000000 */
12120 #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
12121 #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x01000000 */
12122 #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x02000000 */
12123 #define RCC_DCKCFGR2_CECSEL_Pos (26U)
12124 #define RCC_DCKCFGR2_CECSEL_Msk (0x1U << RCC_DCKCFGR2_CECSEL_Pos) /*!< 0x04000000 */
12125 #define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
12126 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
12127 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
12128 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
12129 #define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)
12130 #define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1U << RCC_DCKCFGR2_SDMMC1SEL_Pos) /*!< 0x10000000 */
12131 #define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk
12132 #define RCC_DCKCFGR2_SDMMC2SEL_Pos (29U)
12133 #define RCC_DCKCFGR2_SDMMC2SEL_Msk (0x1U << RCC_DCKCFGR2_SDMMC2SEL_Pos) /*!< 0x20000000 */
12134 #define RCC_DCKCFGR2_SDMMC2SEL RCC_DCKCFGR2_SDMMC2SEL_Msk
12135 #define RCC_DCKCFGR2_DSISEL_Pos (30U)
12136 #define RCC_DCKCFGR2_DSISEL_Msk (0x1U << RCC_DCKCFGR2_DSISEL_Pos) /*!< 0x40000000 */
12137 #define RCC_DCKCFGR2_DSISEL RCC_DCKCFGR2_DSISEL_Msk
12138
12139 /******************************************************************************/
12140 /* */
12141 /* RNG */
12142 /* */
12143 /******************************************************************************/
12144 /******************** Bits definition for RNG_CR register *******************/
12145 #define RNG_CR_RNGEN_Pos (2U)
12146 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
12147 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
12148 #define RNG_CR_IE_Pos (3U)
12149 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
12150 #define RNG_CR_IE RNG_CR_IE_Msk
12151
12152 /******************** Bits definition for RNG_SR register *******************/
12153 #define RNG_SR_DRDY_Pos (0U)
12154 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
12155 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
12156 #define RNG_SR_CECS_Pos (1U)
12157 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
12158 #define RNG_SR_CECS RNG_SR_CECS_Msk
12159 #define RNG_SR_SECS_Pos (2U)
12160 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
12161 #define RNG_SR_SECS RNG_SR_SECS_Msk
12162 #define RNG_SR_CEIS_Pos (5U)
12163 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
12164 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
12165 #define RNG_SR_SEIS_Pos (6U)
12166 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
12167 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
12168
12169 /******************************************************************************/
12170 /* */
12171 /* Real-Time Clock (RTC) */
12172 /* */
12173 /******************************************************************************/
12174 /******************** Bits definition for RTC_TR register *******************/
12175 #define RTC_TR_PM_Pos (22U)
12176 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
12177 #define RTC_TR_PM RTC_TR_PM_Msk
12178 #define RTC_TR_HT_Pos (20U)
12179 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
12180 #define RTC_TR_HT RTC_TR_HT_Msk
12181 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
12182 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
12183 #define RTC_TR_HU_Pos (16U)
12184 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
12185 #define RTC_TR_HU RTC_TR_HU_Msk
12186 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
12187 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
12188 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
12189 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
12190 #define RTC_TR_MNT_Pos (12U)
12191 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
12192 #define RTC_TR_MNT RTC_TR_MNT_Msk
12193 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
12194 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
12195 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
12196 #define RTC_TR_MNU_Pos (8U)
12197 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
12198 #define RTC_TR_MNU RTC_TR_MNU_Msk
12199 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
12200 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
12201 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
12202 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
12203 #define RTC_TR_ST_Pos (4U)
12204 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
12205 #define RTC_TR_ST RTC_TR_ST_Msk
12206 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
12207 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
12208 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
12209 #define RTC_TR_SU_Pos (0U)
12210 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
12211 #define RTC_TR_SU RTC_TR_SU_Msk
12212 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
12213 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
12214 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
12215 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
12216
12217 /******************** Bits definition for RTC_DR register *******************/
12218 #define RTC_DR_YT_Pos (20U)
12219 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
12220 #define RTC_DR_YT RTC_DR_YT_Msk
12221 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
12222 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
12223 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
12224 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
12225 #define RTC_DR_YU_Pos (16U)
12226 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
12227 #define RTC_DR_YU RTC_DR_YU_Msk
12228 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
12229 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
12230 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
12231 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
12232 #define RTC_DR_WDU_Pos (13U)
12233 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
12234 #define RTC_DR_WDU RTC_DR_WDU_Msk
12235 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
12236 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
12237 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
12238 #define RTC_DR_MT_Pos (12U)
12239 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
12240 #define RTC_DR_MT RTC_DR_MT_Msk
12241 #define RTC_DR_MU_Pos (8U)
12242 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
12243 #define RTC_DR_MU RTC_DR_MU_Msk
12244 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
12245 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
12246 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
12247 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
12248 #define RTC_DR_DT_Pos (4U)
12249 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
12250 #define RTC_DR_DT RTC_DR_DT_Msk
12251 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
12252 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
12253 #define RTC_DR_DU_Pos (0U)
12254 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
12255 #define RTC_DR_DU RTC_DR_DU_Msk
12256 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
12257 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
12258 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
12259 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
12260
12261 /******************** Bits definition for RTC_CR register *******************/
12262 #define RTC_CR_ITSE_Pos (24U)
12263 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
12264 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
12265 #define RTC_CR_COE_Pos (23U)
12266 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
12267 #define RTC_CR_COE RTC_CR_COE_Msk
12268 #define RTC_CR_OSEL_Pos (21U)
12269 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
12270 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
12271 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
12272 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
12273 #define RTC_CR_POL_Pos (20U)
12274 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
12275 #define RTC_CR_POL RTC_CR_POL_Msk
12276 #define RTC_CR_COSEL_Pos (19U)
12277 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
12278 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
12279 #define RTC_CR_BKP_Pos (18U)
12280 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
12281 #define RTC_CR_BKP RTC_CR_BKP_Msk
12282 #define RTC_CR_SUB1H_Pos (17U)
12283 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
12284 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
12285 #define RTC_CR_ADD1H_Pos (16U)
12286 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
12287 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
12288 #define RTC_CR_TSIE_Pos (15U)
12289 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
12290 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
12291 #define RTC_CR_WUTIE_Pos (14U)
12292 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
12293 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
12294 #define RTC_CR_ALRBIE_Pos (13U)
12295 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
12296 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
12297 #define RTC_CR_ALRAIE_Pos (12U)
12298 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
12299 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
12300 #define RTC_CR_TSE_Pos (11U)
12301 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
12302 #define RTC_CR_TSE RTC_CR_TSE_Msk
12303 #define RTC_CR_WUTE_Pos (10U)
12304 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
12305 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
12306 #define RTC_CR_ALRBE_Pos (9U)
12307 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
12308 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
12309 #define RTC_CR_ALRAE_Pos (8U)
12310 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
12311 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
12312 #define RTC_CR_FMT_Pos (6U)
12313 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
12314 #define RTC_CR_FMT RTC_CR_FMT_Msk
12315 #define RTC_CR_BYPSHAD_Pos (5U)
12316 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
12317 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
12318 #define RTC_CR_REFCKON_Pos (4U)
12319 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
12320 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
12321 #define RTC_CR_TSEDGE_Pos (3U)
12322 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
12323 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
12324 #define RTC_CR_WUCKSEL_Pos (0U)
12325 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
12326 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
12327 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
12328 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
12329 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
12330
12331 /* Legacy define */
12332 #define RTC_CR_BCK RTC_CR_BKP
12333
12334 /******************** Bits definition for RTC_ISR register ******************/
12335 #define RTC_ISR_ITSF_Pos (17U)
12336 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
12337 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
12338 #define RTC_ISR_RECALPF_Pos (16U)
12339 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
12340 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
12341 #define RTC_ISR_TAMP3F_Pos (15U)
12342 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
12343 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
12344 #define RTC_ISR_TAMP2F_Pos (14U)
12345 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
12346 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
12347 #define RTC_ISR_TAMP1F_Pos (13U)
12348 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
12349 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
12350 #define RTC_ISR_TSOVF_Pos (12U)
12351 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
12352 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
12353 #define RTC_ISR_TSF_Pos (11U)
12354 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
12355 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
12356 #define RTC_ISR_WUTF_Pos (10U)
12357 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
12358 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
12359 #define RTC_ISR_ALRBF_Pos (9U)
12360 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
12361 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
12362 #define RTC_ISR_ALRAF_Pos (8U)
12363 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
12364 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
12365 #define RTC_ISR_INIT_Pos (7U)
12366 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
12367 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
12368 #define RTC_ISR_INITF_Pos (6U)
12369 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
12370 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
12371 #define RTC_ISR_RSF_Pos (5U)
12372 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
12373 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
12374 #define RTC_ISR_INITS_Pos (4U)
12375 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
12376 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
12377 #define RTC_ISR_SHPF_Pos (3U)
12378 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
12379 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
12380 #define RTC_ISR_WUTWF_Pos (2U)
12381 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
12382 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
12383 #define RTC_ISR_ALRBWF_Pos (1U)
12384 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
12385 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
12386 #define RTC_ISR_ALRAWF_Pos (0U)
12387 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
12388 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
12389
12390 /******************** Bits definition for RTC_PRER register *****************/
12391 #define RTC_PRER_PREDIV_A_Pos (16U)
12392 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
12393 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
12394 #define RTC_PRER_PREDIV_S_Pos (0U)
12395 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
12396 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
12397
12398 /******************** Bits definition for RTC_WUTR register *****************/
12399 #define RTC_WUTR_WUT_Pos (0U)
12400 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
12401 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
12402
12403 /******************** Bits definition for RTC_ALRMAR register ***************/
12404 #define RTC_ALRMAR_MSK4_Pos (31U)
12405 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
12406 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
12407 #define RTC_ALRMAR_WDSEL_Pos (30U)
12408 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
12409 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
12410 #define RTC_ALRMAR_DT_Pos (28U)
12411 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
12412 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
12413 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
12414 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
12415 #define RTC_ALRMAR_DU_Pos (24U)
12416 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
12417 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
12418 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
12419 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
12420 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
12421 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
12422 #define RTC_ALRMAR_MSK3_Pos (23U)
12423 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
12424 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
12425 #define RTC_ALRMAR_PM_Pos (22U)
12426 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
12427 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
12428 #define RTC_ALRMAR_HT_Pos (20U)
12429 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
12430 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
12431 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
12432 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
12433 #define RTC_ALRMAR_HU_Pos (16U)
12434 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
12435 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
12436 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
12437 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
12438 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
12439 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
12440 #define RTC_ALRMAR_MSK2_Pos (15U)
12441 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
12442 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
12443 #define RTC_ALRMAR_MNT_Pos (12U)
12444 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
12445 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
12446 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
12447 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
12448 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
12449 #define RTC_ALRMAR_MNU_Pos (8U)
12450 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
12451 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
12452 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
12453 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
12454 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
12455 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
12456 #define RTC_ALRMAR_MSK1_Pos (7U)
12457 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
12458 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
12459 #define RTC_ALRMAR_ST_Pos (4U)
12460 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
12461 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
12462 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
12463 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
12464 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
12465 #define RTC_ALRMAR_SU_Pos (0U)
12466 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
12467 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
12468 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
12469 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
12470 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
12471 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
12472
12473 /******************** Bits definition for RTC_ALRMBR register ***************/
12474 #define RTC_ALRMBR_MSK4_Pos (31U)
12475 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
12476 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
12477 #define RTC_ALRMBR_WDSEL_Pos (30U)
12478 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
12479 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
12480 #define RTC_ALRMBR_DT_Pos (28U)
12481 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
12482 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
12483 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
12484 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
12485 #define RTC_ALRMBR_DU_Pos (24U)
12486 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
12487 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
12488 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
12489 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
12490 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
12491 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
12492 #define RTC_ALRMBR_MSK3_Pos (23U)
12493 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
12494 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
12495 #define RTC_ALRMBR_PM_Pos (22U)
12496 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
12497 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
12498 #define RTC_ALRMBR_HT_Pos (20U)
12499 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
12500 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
12501 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
12502 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
12503 #define RTC_ALRMBR_HU_Pos (16U)
12504 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
12505 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
12506 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
12507 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
12508 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
12509 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
12510 #define RTC_ALRMBR_MSK2_Pos (15U)
12511 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
12512 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
12513 #define RTC_ALRMBR_MNT_Pos (12U)
12514 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
12515 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
12516 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
12517 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
12518 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
12519 #define RTC_ALRMBR_MNU_Pos (8U)
12520 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
12521 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
12522 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
12523 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
12524 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
12525 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
12526 #define RTC_ALRMBR_MSK1_Pos (7U)
12527 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
12528 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
12529 #define RTC_ALRMBR_ST_Pos (4U)
12530 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
12531 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
12532 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
12533 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
12534 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
12535 #define RTC_ALRMBR_SU_Pos (0U)
12536 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
12537 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
12538 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
12539 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
12540 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
12541 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
12542
12543 /******************** Bits definition for RTC_WPR register ******************/
12544 #define RTC_WPR_KEY_Pos (0U)
12545 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
12546 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
12547
12548 /******************** Bits definition for RTC_SSR register ******************/
12549 #define RTC_SSR_SS_Pos (0U)
12550 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
12551 #define RTC_SSR_SS RTC_SSR_SS_Msk
12552
12553 /******************** Bits definition for RTC_SHIFTR register ***************/
12554 #define RTC_SHIFTR_SUBFS_Pos (0U)
12555 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
12556 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12557 #define RTC_SHIFTR_ADD1S_Pos (31U)
12558 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
12559 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12560
12561 /******************** Bits definition for RTC_TSTR register *****************/
12562 #define RTC_TSTR_PM_Pos (22U)
12563 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
12564 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
12565 #define RTC_TSTR_HT_Pos (20U)
12566 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
12567 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
12568 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
12569 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
12570 #define RTC_TSTR_HU_Pos (16U)
12571 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
12572 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
12573 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
12574 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
12575 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
12576 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
12577 #define RTC_TSTR_MNT_Pos (12U)
12578 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
12579 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12580 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
12581 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
12582 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
12583 #define RTC_TSTR_MNU_Pos (8U)
12584 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
12585 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12586 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
12587 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
12588 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
12589 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
12590 #define RTC_TSTR_ST_Pos (4U)
12591 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
12592 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
12593 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
12594 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
12595 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
12596 #define RTC_TSTR_SU_Pos (0U)
12597 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
12598 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
12599 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
12600 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
12601 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
12602 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
12603
12604 /******************** Bits definition for RTC_TSDR register *****************/
12605 #define RTC_TSDR_WDU_Pos (13U)
12606 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
12607 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12608 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
12609 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
12610 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
12611 #define RTC_TSDR_MT_Pos (12U)
12612 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
12613 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
12614 #define RTC_TSDR_MU_Pos (8U)
12615 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
12616 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
12617 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
12618 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
12619 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
12620 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
12621 #define RTC_TSDR_DT_Pos (4U)
12622 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
12623 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
12624 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
12625 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
12626 #define RTC_TSDR_DU_Pos (0U)
12627 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
12628 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
12629 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
12630 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
12631 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
12632 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
12633
12634 /******************** Bits definition for RTC_TSSSR register ****************/
12635 #define RTC_TSSSR_SS_Pos (0U)
12636 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
12637 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12638
12639 /******************** Bits definition for RTC_CAL register *****************/
12640 #define RTC_CALR_CALP_Pos (15U)
12641 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
12642 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
12643 #define RTC_CALR_CALW8_Pos (14U)
12644 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
12645 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12646 #define RTC_CALR_CALW16_Pos (13U)
12647 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
12648 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12649 #define RTC_CALR_CALM_Pos (0U)
12650 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
12651 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
12652 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
12653 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
12654 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
12655 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
12656 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
12657 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
12658 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
12659 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
12660 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
12661
12662 /******************** Bits definition for RTC_TAMPCR register ****************/
12663 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
12664 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
12665 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
12666 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
12667 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
12668 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
12669 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
12670 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
12671 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
12672 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
12673 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
12674 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
12675 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
12676 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
12677 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
12678 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
12679 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
12680 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
12681 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
12682 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
12683 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
12684 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
12685 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
12686 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
12687 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
12688 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
12689 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
12690 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
12691 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
12692 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
12693 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
12694 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
12695 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
12696 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
12697 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
12698 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
12699 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
12700 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
12701 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
12702 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
12703 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
12704 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
12705 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
12706 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
12707 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
12708 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
12709 #define RTC_TAMPCR_TAMPTS_Pos (7U)
12710 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
12711 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
12712 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
12713 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
12714 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
12715 #define RTC_TAMPCR_TAMP3E_Pos (5U)
12716 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
12717 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
12718 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
12719 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
12720 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
12721 #define RTC_TAMPCR_TAMP2E_Pos (3U)
12722 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
12723 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
12724 #define RTC_TAMPCR_TAMPIE_Pos (2U)
12725 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
12726 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
12727 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
12728 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
12729 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
12730 #define RTC_TAMPCR_TAMP1E_Pos (0U)
12731 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
12732 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
12733
12734
12735 /******************** Bits definition for RTC_ALRMASSR register *************/
12736 #define RTC_ALRMASSR_MASKSS_Pos (24U)
12737 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
12738 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12739 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
12740 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
12741 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
12742 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
12743 #define RTC_ALRMASSR_SS_Pos (0U)
12744 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
12745 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12746
12747 /******************** Bits definition for RTC_ALRMBSSR register *************/
12748 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
12749 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
12750 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12751 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
12752 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
12753 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
12754 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
12755 #define RTC_ALRMBSSR_SS_Pos (0U)
12756 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
12757 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12758
12759 /******************** Bits definition for RTC_OR register ****************/
12760 #define RTC_OR_TSINSEL_Pos (1U)
12761 #define RTC_OR_TSINSEL_Msk (0x3U << RTC_OR_TSINSEL_Pos) /*!< 0x00000006 */
12762 #define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk
12763 #define RTC_OR_TSINSEL_0 (0x1U << RTC_OR_TSINSEL_Pos) /*!< 0x00000002 */
12764 #define RTC_OR_TSINSEL_1 (0x2U << RTC_OR_TSINSEL_Pos) /*!< 0x00000004 */
12765 #define RTC_OR_ALARMOUTTYPE_Pos (3U)
12766 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000008 */
12767 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
12768 /* Legacy defines*/
12769 #define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE
12770
12771 /******************** Bits definition for RTC_BKP0R register ****************/
12772 #define RTC_BKP0R_Pos (0U)
12773 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
12774 #define RTC_BKP0R RTC_BKP0R_Msk
12775
12776 /******************** Bits definition for RTC_BKP1R register ****************/
12777 #define RTC_BKP1R_Pos (0U)
12778 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
12779 #define RTC_BKP1R RTC_BKP1R_Msk
12780
12781 /******************** Bits definition for RTC_BKP2R register ****************/
12782 #define RTC_BKP2R_Pos (0U)
12783 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
12784 #define RTC_BKP2R RTC_BKP2R_Msk
12785
12786 /******************** Bits definition for RTC_BKP3R register ****************/
12787 #define RTC_BKP3R_Pos (0U)
12788 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
12789 #define RTC_BKP3R RTC_BKP3R_Msk
12790
12791 /******************** Bits definition for RTC_BKP4R register ****************/
12792 #define RTC_BKP4R_Pos (0U)
12793 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
12794 #define RTC_BKP4R RTC_BKP4R_Msk
12795
12796 /******************** Bits definition for RTC_BKP5R register ****************/
12797 #define RTC_BKP5R_Pos (0U)
12798 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
12799 #define RTC_BKP5R RTC_BKP5R_Msk
12800
12801 /******************** Bits definition for RTC_BKP6R register ****************/
12802 #define RTC_BKP6R_Pos (0U)
12803 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
12804 #define RTC_BKP6R RTC_BKP6R_Msk
12805
12806 /******************** Bits definition for RTC_BKP7R register ****************/
12807 #define RTC_BKP7R_Pos (0U)
12808 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
12809 #define RTC_BKP7R RTC_BKP7R_Msk
12810
12811 /******************** Bits definition for RTC_BKP8R register ****************/
12812 #define RTC_BKP8R_Pos (0U)
12813 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
12814 #define RTC_BKP8R RTC_BKP8R_Msk
12815
12816 /******************** Bits definition for RTC_BKP9R register ****************/
12817 #define RTC_BKP9R_Pos (0U)
12818 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
12819 #define RTC_BKP9R RTC_BKP9R_Msk
12820
12821 /******************** Bits definition for RTC_BKP10R register ***************/
12822 #define RTC_BKP10R_Pos (0U)
12823 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
12824 #define RTC_BKP10R RTC_BKP10R_Msk
12825
12826 /******************** Bits definition for RTC_BKP11R register ***************/
12827 #define RTC_BKP11R_Pos (0U)
12828 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
12829 #define RTC_BKP11R RTC_BKP11R_Msk
12830
12831 /******************** Bits definition for RTC_BKP12R register ***************/
12832 #define RTC_BKP12R_Pos (0U)
12833 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
12834 #define RTC_BKP12R RTC_BKP12R_Msk
12835
12836 /******************** Bits definition for RTC_BKP13R register ***************/
12837 #define RTC_BKP13R_Pos (0U)
12838 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
12839 #define RTC_BKP13R RTC_BKP13R_Msk
12840
12841 /******************** Bits definition for RTC_BKP14R register ***************/
12842 #define RTC_BKP14R_Pos (0U)
12843 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
12844 #define RTC_BKP14R RTC_BKP14R_Msk
12845
12846 /******************** Bits definition for RTC_BKP15R register ***************/
12847 #define RTC_BKP15R_Pos (0U)
12848 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
12849 #define RTC_BKP15R RTC_BKP15R_Msk
12850
12851 /******************** Bits definition for RTC_BKP16R register ***************/
12852 #define RTC_BKP16R_Pos (0U)
12853 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
12854 #define RTC_BKP16R RTC_BKP16R_Msk
12855
12856 /******************** Bits definition for RTC_BKP17R register ***************/
12857 #define RTC_BKP17R_Pos (0U)
12858 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
12859 #define RTC_BKP17R RTC_BKP17R_Msk
12860
12861 /******************** Bits definition for RTC_BKP18R register ***************/
12862 #define RTC_BKP18R_Pos (0U)
12863 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
12864 #define RTC_BKP18R RTC_BKP18R_Msk
12865
12866 /******************** Bits definition for RTC_BKP19R register ***************/
12867 #define RTC_BKP19R_Pos (0U)
12868 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
12869 #define RTC_BKP19R RTC_BKP19R_Msk
12870
12871 /******************** Bits definition for RTC_BKP20R register ***************/
12872 #define RTC_BKP20R_Pos (0U)
12873 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
12874 #define RTC_BKP20R RTC_BKP20R_Msk
12875
12876 /******************** Bits definition for RTC_BKP21R register ***************/
12877 #define RTC_BKP21R_Pos (0U)
12878 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
12879 #define RTC_BKP21R RTC_BKP21R_Msk
12880
12881 /******************** Bits definition for RTC_BKP22R register ***************/
12882 #define RTC_BKP22R_Pos (0U)
12883 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
12884 #define RTC_BKP22R RTC_BKP22R_Msk
12885
12886 /******************** Bits definition for RTC_BKP23R register ***************/
12887 #define RTC_BKP23R_Pos (0U)
12888 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
12889 #define RTC_BKP23R RTC_BKP23R_Msk
12890
12891 /******************** Bits definition for RTC_BKP24R register ***************/
12892 #define RTC_BKP24R_Pos (0U)
12893 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
12894 #define RTC_BKP24R RTC_BKP24R_Msk
12895
12896 /******************** Bits definition for RTC_BKP25R register ***************/
12897 #define RTC_BKP25R_Pos (0U)
12898 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
12899 #define RTC_BKP25R RTC_BKP25R_Msk
12900
12901 /******************** Bits definition for RTC_BKP26R register ***************/
12902 #define RTC_BKP26R_Pos (0U)
12903 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
12904 #define RTC_BKP26R RTC_BKP26R_Msk
12905
12906 /******************** Bits definition for RTC_BKP27R register ***************/
12907 #define RTC_BKP27R_Pos (0U)
12908 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
12909 #define RTC_BKP27R RTC_BKP27R_Msk
12910
12911 /******************** Bits definition for RTC_BKP28R register ***************/
12912 #define RTC_BKP28R_Pos (0U)
12913 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
12914 #define RTC_BKP28R RTC_BKP28R_Msk
12915
12916 /******************** Bits definition for RTC_BKP29R register ***************/
12917 #define RTC_BKP29R_Pos (0U)
12918 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
12919 #define RTC_BKP29R RTC_BKP29R_Msk
12920
12921 /******************** Bits definition for RTC_BKP30R register ***************/
12922 #define RTC_BKP30R_Pos (0U)
12923 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
12924 #define RTC_BKP30R RTC_BKP30R_Msk
12925
12926 /******************** Bits definition for RTC_BKP31R register ***************/
12927 #define RTC_BKP31R_Pos (0U)
12928 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
12929 #define RTC_BKP31R RTC_BKP31R_Msk
12930
12931 /******************** Number of backup registers ******************************/
12932 #define RTC_BKP_NUMBER 0x00000020U
12933
12934 /******************************************************************************/
12935 /* */
12936 /* Serial Audio Interface */
12937 /* */
12938 /******************************************************************************/
12939 /******************** Bit definition for SAI_GCR register *******************/
12940 #define SAI_GCR_SYNCIN_Pos (0U)
12941 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
12942 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
12943 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
12944 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
12945
12946 #define SAI_GCR_SYNCOUT_Pos (4U)
12947 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
12948 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
12949 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
12950 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
12951
12952 /******************* Bit definition for SAI_xCR1 register *******************/
12953 #define SAI_xCR1_MODE_Pos (0U)
12954 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
12955 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
12956 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
12957 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
12958
12959 #define SAI_xCR1_PRTCFG_Pos (2U)
12960 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
12961 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
12962 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
12963 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
12964
12965 #define SAI_xCR1_DS_Pos (5U)
12966 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
12967 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
12968 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
12969 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
12970 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
12971
12972 #define SAI_xCR1_LSBFIRST_Pos (8U)
12973 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
12974 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
12975 #define SAI_xCR1_CKSTR_Pos (9U)
12976 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
12977 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
12978
12979 #define SAI_xCR1_SYNCEN_Pos (10U)
12980 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
12981 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
12982 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
12983 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
12984
12985 #define SAI_xCR1_MONO_Pos (12U)
12986 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
12987 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
12988 #define SAI_xCR1_OUTDRIV_Pos (13U)
12989 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
12990 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
12991 #define SAI_xCR1_SAIEN_Pos (16U)
12992 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
12993 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
12994 #define SAI_xCR1_DMAEN_Pos (17U)
12995 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
12996 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
12997 #define SAI_xCR1_NODIV_Pos (19U)
12998 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
12999 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
13000
13001 #define SAI_xCR1_MCKDIV_Pos (20U)
13002 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
13003 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
13004 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
13005 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
13006 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
13007 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
13008
13009 /******************* Bit definition for SAI_xCR2 register *******************/
13010 #define SAI_xCR2_FTH_Pos (0U)
13011 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
13012 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
13013 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
13014 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
13015 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
13016
13017 #define SAI_xCR2_FFLUSH_Pos (3U)
13018 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
13019 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
13020 #define SAI_xCR2_TRIS_Pos (4U)
13021 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
13022 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
13023 #define SAI_xCR2_MUTE_Pos (5U)
13024 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
13025 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
13026 #define SAI_xCR2_MUTEVAL_Pos (6U)
13027 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
13028 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
13029
13030 #define SAI_xCR2_MUTECNT_Pos (7U)
13031 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
13032 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
13033 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
13034 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
13035 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
13036 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
13037 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
13038 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
13039
13040 #define SAI_xCR2_CPL_Pos (13U)
13041 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
13042 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
13043
13044 #define SAI_xCR2_COMP_Pos (14U)
13045 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
13046 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
13047 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
13048 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
13049
13050 /****************** Bit definition for SAI_xFRCR register *******************/
13051 #define SAI_xFRCR_FRL_Pos (0U)
13052 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
13053 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
13054 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
13055 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
13056 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
13057 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
13058 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
13059 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
13060 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
13061 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
13062
13063 #define SAI_xFRCR_FSALL_Pos (8U)
13064 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
13065 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
13066 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
13067 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
13068 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
13069 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
13070 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
13071 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
13072 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
13073
13074 #define SAI_xFRCR_FSDEF_Pos (16U)
13075 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
13076 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
13077 #define SAI_xFRCR_FSPOL_Pos (17U)
13078 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
13079 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
13080 #define SAI_xFRCR_FSOFF_Pos (18U)
13081 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
13082 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
13083
13084 /* Legacy define */
13085 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
13086
13087 /****************** Bit definition for SAI_xSLOTR register *******************/
13088 #define SAI_xSLOTR_FBOFF_Pos (0U)
13089 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
13090 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
13091 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
13092 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
13093 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
13094 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
13095 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
13096
13097 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
13098 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
13099 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
13100 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
13101 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
13102
13103 #define SAI_xSLOTR_NBSLOT_Pos (8U)
13104 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
13105 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
13106 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
13107 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
13108 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
13109 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
13110
13111 #define SAI_xSLOTR_SLOTEN_Pos (16U)
13112 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
13113 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
13114
13115 /******************* Bit definition for SAI_xIMR register *******************/
13116 #define SAI_xIMR_OVRUDRIE_Pos (0U)
13117 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
13118 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
13119 #define SAI_xIMR_MUTEDETIE_Pos (1U)
13120 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
13121 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
13122 #define SAI_xIMR_WCKCFGIE_Pos (2U)
13123 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
13124 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
13125 #define SAI_xIMR_FREQIE_Pos (3U)
13126 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
13127 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
13128 #define SAI_xIMR_CNRDYIE_Pos (4U)
13129 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
13130 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
13131 #define SAI_xIMR_AFSDETIE_Pos (5U)
13132 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
13133 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
13134 #define SAI_xIMR_LFSDETIE_Pos (6U)
13135 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
13136 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
13137
13138 /******************** Bit definition for SAI_xSR register *******************/
13139 #define SAI_xSR_OVRUDR_Pos (0U)
13140 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
13141 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
13142 #define SAI_xSR_MUTEDET_Pos (1U)
13143 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
13144 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
13145 #define SAI_xSR_WCKCFG_Pos (2U)
13146 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
13147 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
13148 #define SAI_xSR_FREQ_Pos (3U)
13149 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
13150 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
13151 #define SAI_xSR_CNRDY_Pos (4U)
13152 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
13153 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
13154 #define SAI_xSR_AFSDET_Pos (5U)
13155 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
13156 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
13157 #define SAI_xSR_LFSDET_Pos (6U)
13158 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
13159 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
13160
13161 #define SAI_xSR_FLVL_Pos (16U)
13162 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
13163 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
13164 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
13165 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
13166 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
13167
13168 /****************** Bit definition for SAI_xCLRFR register ******************/
13169 #define SAI_xCLRFR_COVRUDR_Pos (0U)
13170 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
13171 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
13172 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
13173 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
13174 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
13175 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
13176 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
13177 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
13178 #define SAI_xCLRFR_CFREQ_Pos (3U)
13179 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
13180 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
13181 #define SAI_xCLRFR_CCNRDY_Pos (4U)
13182 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
13183 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
13184 #define SAI_xCLRFR_CAFSDET_Pos (5U)
13185 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
13186 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
13187 #define SAI_xCLRFR_CLFSDET_Pos (6U)
13188 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
13189 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
13190
13191 /****************** Bit definition for SAI_xDR register *********************/
13192 #define SAI_xDR_DATA_Pos (0U)
13193 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
13194 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
13195
13196 /******************************************************************************/
13197 /* */
13198 /* SPDIF-RX Interface */
13199 /* */
13200 /******************************************************************************/
13201 /******************** Bit definition for SPDIF_CR register *******************/
13202 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
13203 #define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
13204 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
13205 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
13206 #define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
13207 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
13208 #define SPDIFRX_CR_RXSTEO_Pos (3U)
13209 #define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
13210 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
13211 #define SPDIFRX_CR_DRFMT_Pos (4U)
13212 #define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
13213 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
13214 #define SPDIFRX_CR_PMSK_Pos (6U)
13215 #define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
13216 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
13217 #define SPDIFRX_CR_VMSK_Pos (7U)
13218 #define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
13219 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
13220 #define SPDIFRX_CR_CUMSK_Pos (8U)
13221 #define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
13222 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
13223 #define SPDIFRX_CR_PTMSK_Pos (9U)
13224 #define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
13225 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
13226 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
13227 #define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
13228 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
13229 #define SPDIFRX_CR_CHSEL_Pos (11U)
13230 #define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
13231 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
13232 #define SPDIFRX_CR_NBTR_Pos (12U)
13233 #define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
13234 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
13235 #define SPDIFRX_CR_WFA_Pos (14U)
13236 #define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
13237 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
13238 #define SPDIFRX_CR_INSEL_Pos (16U)
13239 #define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
13240 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
13241
13242 /******************* Bit definition for SPDIFRX_IMR register *******************/
13243 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
13244 #define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
13245 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
13246 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
13247 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
13248 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
13249 #define SPDIFRX_IMR_PERRIE_Pos (2U)
13250 #define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
13251 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
13252 #define SPDIFRX_IMR_OVRIE_Pos (3U)
13253 #define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
13254 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
13255 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
13256 #define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
13257 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
13258 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
13259 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
13260 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
13261 #define SPDIFRX_IMR_IFEIE_Pos (6U)
13262 #define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
13263 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
13264
13265 /******************* Bit definition for SPDIFRX_SR register *******************/
13266 #define SPDIFRX_SR_RXNE_Pos (0U)
13267 #define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
13268 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
13269 #define SPDIFRX_SR_CSRNE_Pos (1U)
13270 #define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
13271 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
13272 #define SPDIFRX_SR_PERR_Pos (2U)
13273 #define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
13274 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
13275 #define SPDIFRX_SR_OVR_Pos (3U)
13276 #define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
13277 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
13278 #define SPDIFRX_SR_SBD_Pos (4U)
13279 #define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
13280 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
13281 #define SPDIFRX_SR_SYNCD_Pos (5U)
13282 #define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
13283 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
13284 #define SPDIFRX_SR_FERR_Pos (6U)
13285 #define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
13286 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
13287 #define SPDIFRX_SR_SERR_Pos (7U)
13288 #define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
13289 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
13290 #define SPDIFRX_SR_TERR_Pos (8U)
13291 #define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
13292 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
13293 #define SPDIFRX_SR_WIDTH5_Pos (16U)
13294 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
13295 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
13296
13297 /******************* Bit definition for SPDIFRX_IFCR register *******************/
13298 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
13299 #define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
13300 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
13301 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
13302 #define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
13303 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
13304 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
13305 #define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
13306 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
13307 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
13308 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
13309 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
13310
13311 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
13312 #define SPDIFRX_DR0_DR_Pos (0U)
13313 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
13314 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
13315 #define SPDIFRX_DR0_PE_Pos (24U)
13316 #define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
13317 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
13318 #define SPDIFRX_DR0_V_Pos (25U)
13319 #define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
13320 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
13321 #define SPDIFRX_DR0_U_Pos (26U)
13322 #define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
13323 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
13324 #define SPDIFRX_DR0_C_Pos (27U)
13325 #define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
13326 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
13327 #define SPDIFRX_DR0_PT_Pos (28U)
13328 #define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
13329 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
13330
13331 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
13332 #define SPDIFRX_DR1_DR_Pos (8U)
13333 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
13334 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
13335 #define SPDIFRX_DR1_PT_Pos (4U)
13336 #define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
13337 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
13338 #define SPDIFRX_DR1_C_Pos (3U)
13339 #define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
13340 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
13341 #define SPDIFRX_DR1_U_Pos (2U)
13342 #define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
13343 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
13344 #define SPDIFRX_DR1_V_Pos (1U)
13345 #define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
13346 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
13347 #define SPDIFRX_DR1_PE_Pos (0U)
13348 #define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
13349 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
13350
13351 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
13352 #define SPDIFRX_DR1_DRNL1_Pos (16U)
13353 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
13354 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
13355 #define SPDIFRX_DR1_DRNL2_Pos (0U)
13356 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
13357 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
13358
13359 /******************* Bit definition for SPDIFRX_CSR register *******************/
13360 #define SPDIFRX_CSR_USR_Pos (0U)
13361 #define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
13362 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
13363 #define SPDIFRX_CSR_CS_Pos (16U)
13364 #define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
13365 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
13366 #define SPDIFRX_CSR_SOB_Pos (24U)
13367 #define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
13368 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
13369
13370 /******************* Bit definition for SPDIFRX_DIR register *******************/
13371 #define SPDIFRX_DIR_THI_Pos (0U)
13372 #define SPDIFRX_DIR_THI_Msk (0x13FFU << SPDIFRX_DIR_THI_Pos) /*!< 0x000013FF */
13373 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
13374 #define SPDIFRX_DIR_TLO_Pos (16U)
13375 #define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
13376 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
13377
13378 /******************************************************************************/
13379 /* */
13380 /* SD host Interface */
13381 /* */
13382 /******************************************************************************/
13383 /****************** Bit definition for SDMMC_POWER register ******************/
13384 #define SDMMC_POWER_PWRCTRL_Pos (0U)
13385 #define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
13386 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
13387 #define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x01 */
13388 #define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x02 */
13389
13390 /****************** Bit definition for SDMMC_CLKCR register ******************/
13391 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
13392 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
13393 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
13394 #define SDMMC_CLKCR_CLKEN_Pos (8U)
13395 #define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
13396 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
13397 #define SDMMC_CLKCR_PWRSAV_Pos (9U)
13398 #define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
13399 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
13400 #define SDMMC_CLKCR_BYPASS_Pos (10U)
13401 #define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
13402 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
13403
13404 #define SDMMC_CLKCR_WIDBUS_Pos (11U)
13405 #define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
13406 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
13407 #define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
13408 #define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
13409
13410 #define SDMMC_CLKCR_NEGEDGE_Pos (13U)
13411 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
13412 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
13413 #define SDMMC_CLKCR_HWFC_EN_Pos (14U)
13414 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
13415 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
13416
13417 /******************* Bit definition for SDMMC_ARG register *******************/
13418 #define SDMMC_ARG_CMDARG_Pos (0U)
13419 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
13420 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
13421
13422 /******************* Bit definition for SDMMC_CMD register *******************/
13423 #define SDMMC_CMD_CMDINDEX_Pos (0U)
13424 #define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
13425 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
13426
13427 #define SDMMC_CMD_WAITRESP_Pos (6U)
13428 #define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
13429 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
13430 #define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0040 */
13431 #define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0080 */
13432
13433 #define SDMMC_CMD_WAITINT_Pos (8U)
13434 #define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
13435 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
13436 #define SDMMC_CMD_WAITPEND_Pos (9U)
13437 #define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
13438 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
13439 #define SDMMC_CMD_CPSMEN_Pos (10U)
13440 #define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
13441 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
13442 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
13443 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
13444 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
13445
13446 /***************** Bit definition for SDMMC_RESPCMD register *****************/
13447 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
13448 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
13449 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
13450
13451 /****************** Bit definition for SDMMC_RESP0 register ******************/
13452 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
13453 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
13454 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
13455
13456 /****************** Bit definition for SDMMC_RESP1 register ******************/
13457 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
13458 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
13459 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
13460
13461 /****************** Bit definition for SDMMC_RESP2 register ******************/
13462 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
13463 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
13464 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
13465
13466 /****************** Bit definition for SDMMC_RESP3 register ******************/
13467 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
13468 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
13469 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
13470
13471 /****************** Bit definition for SDMMC_RESP4 register ******************/
13472 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
13473 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
13474 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
13475
13476 /****************** Bit definition for SDMMC_DTIMER register *****************/
13477 #define SDMMC_DTIMER_DATATIME_Pos (0U)
13478 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
13479 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
13480
13481 /****************** Bit definition for SDMMC_DLEN register *******************/
13482 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
13483 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
13484 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
13485
13486 /****************** Bit definition for SDMMC_DCTRL register ******************/
13487 #define SDMMC_DCTRL_DTEN_Pos (0U)
13488 #define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
13489 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
13490 #define SDMMC_DCTRL_DTDIR_Pos (1U)
13491 #define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
13492 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
13493 #define SDMMC_DCTRL_DTMODE_Pos (2U)
13494 #define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
13495 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
13496 #define SDMMC_DCTRL_DMAEN_Pos (3U)
13497 #define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
13498 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
13499
13500 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
13501 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
13502 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
13503 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
13504 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
13505 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
13506 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
13507
13508 #define SDMMC_DCTRL_RWSTART_Pos (8U)
13509 #define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
13510 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
13511 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
13512 #define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
13513 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
13514 #define SDMMC_DCTRL_RWMOD_Pos (10U)
13515 #define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
13516 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
13517 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
13518 #define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
13519 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
13520
13521 /****************** Bit definition for SDMMC_DCOUNT register *****************/
13522 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
13523 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
13524 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
13525
13526 /****************** Bit definition for SDMMC_STA registe ********************/
13527 #define SDMMC_STA_CCRCFAIL_Pos (0U)
13528 #define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
13529 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
13530 #define SDMMC_STA_DCRCFAIL_Pos (1U)
13531 #define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
13532 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
13533 #define SDMMC_STA_CTIMEOUT_Pos (2U)
13534 #define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
13535 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
13536 #define SDMMC_STA_DTIMEOUT_Pos (3U)
13537 #define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
13538 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
13539 #define SDMMC_STA_TXUNDERR_Pos (4U)
13540 #define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
13541 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
13542 #define SDMMC_STA_RXOVERR_Pos (5U)
13543 #define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
13544 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
13545 #define SDMMC_STA_CMDREND_Pos (6U)
13546 #define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
13547 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
13548 #define SDMMC_STA_CMDSENT_Pos (7U)
13549 #define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
13550 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
13551 #define SDMMC_STA_DATAEND_Pos (8U)
13552 #define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
13553 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
13554 #define SDMMC_STA_DBCKEND_Pos (10U)
13555 #define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
13556 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
13557 #define SDMMC_STA_CMDACT_Pos (11U)
13558 #define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
13559 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
13560 #define SDMMC_STA_TXACT_Pos (12U)
13561 #define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
13562 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
13563 #define SDMMC_STA_RXACT_Pos (13U)
13564 #define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
13565 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
13566 #define SDMMC_STA_TXFIFOHE_Pos (14U)
13567 #define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
13568 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
13569 #define SDMMC_STA_RXFIFOHF_Pos (15U)
13570 #define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
13571 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
13572 #define SDMMC_STA_TXFIFOF_Pos (16U)
13573 #define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
13574 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
13575 #define SDMMC_STA_RXFIFOF_Pos (17U)
13576 #define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
13577 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
13578 #define SDMMC_STA_TXFIFOE_Pos (18U)
13579 #define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
13580 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
13581 #define SDMMC_STA_RXFIFOE_Pos (19U)
13582 #define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
13583 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
13584 #define SDMMC_STA_TXDAVL_Pos (20U)
13585 #define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
13586 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
13587 #define SDMMC_STA_RXDAVL_Pos (21U)
13588 #define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
13589 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
13590 #define SDMMC_STA_SDIOIT_Pos (22U)
13591 #define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
13592 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDMMC interrupt received */
13593
13594 /******************* Bit definition for SDMMC_ICR register *******************/
13595 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
13596 #define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
13597 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
13598 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
13599 #define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13600 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
13601 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
13602 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
13603 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
13604 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
13605 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
13606 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
13607 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
13608 #define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
13609 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
13610 #define SDMMC_ICR_RXOVERRC_Pos (5U)
13611 #define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
13612 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
13613 #define SDMMC_ICR_CMDRENDC_Pos (6U)
13614 #define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
13615 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
13616 #define SDMMC_ICR_CMDSENTC_Pos (7U)
13617 #define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
13618 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
13619 #define SDMMC_ICR_DATAENDC_Pos (8U)
13620 #define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
13621 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
13622 #define SDMMC_ICR_DBCKENDC_Pos (10U)
13623 #define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
13624 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
13625 #define SDMMC_ICR_SDIOITC_Pos (22U)
13626 #define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
13627 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDMMCIT flag clear bit */
13628
13629 /****************** Bit definition for SDMMC_MASK register *******************/
13630 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
13631 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
13632 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
13633 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
13634 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
13635 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
13636 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
13637 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
13638 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
13639 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
13640 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
13641 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
13642 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
13643 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
13644 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
13645 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
13646 #define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
13647 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
13648 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
13649 #define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
13650 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
13651 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
13652 #define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
13653 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
13654 #define SDMMC_MASK_DATAENDIE_Pos (8U)
13655 #define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
13656 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
13657 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
13658 #define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
13659 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
13660 #define SDMMC_MASK_CMDACTIE_Pos (11U)
13661 #define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
13662 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
13663 #define SDMMC_MASK_TXACTIE_Pos (12U)
13664 #define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
13665 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
13666 #define SDMMC_MASK_RXACTIE_Pos (13U)
13667 #define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
13668 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
13669 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
13670 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
13671 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
13672 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
13673 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
13674 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
13675 #define SDMMC_MASK_TXFIFOFIE_Pos (16U)
13676 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
13677 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
13678 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
13679 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
13680 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
13681 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
13682 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
13683 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
13684 #define SDMMC_MASK_RXFIFOEIE_Pos (19U)
13685 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
13686 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
13687 #define SDMMC_MASK_TXDAVLIE_Pos (20U)
13688 #define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
13689 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
13690 #define SDMMC_MASK_RXDAVLIE_Pos (21U)
13691 #define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
13692 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
13693 #define SDMMC_MASK_SDIOITIE_Pos (22U)
13694 #define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
13695 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
13696
13697 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
13698 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
13699 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
13700 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
13701
13702 /****************** Bit definition for SDMMC_FIFO register *******************/
13703 #define SDMMC_FIFO_FIFODATA_Pos (0U)
13704 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
13705 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
13706
13707 /******************************************************************************/
13708 /* */
13709 /* Serial Peripheral Interface (SPI) */
13710 /* */
13711 /******************************************************************************/
13712 /******************* Bit definition for SPI_CR1 register ********************/
13713 #define SPI_CR1_CPHA_Pos (0U)
13714 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
13715 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
13716 #define SPI_CR1_CPOL_Pos (1U)
13717 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
13718 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
13719 #define SPI_CR1_MSTR_Pos (2U)
13720 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
13721 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
13722 #define SPI_CR1_BR_Pos (3U)
13723 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
13724 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
13725 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
13726 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
13727 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
13728 #define SPI_CR1_SPE_Pos (6U)
13729 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
13730 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
13731 #define SPI_CR1_LSBFIRST_Pos (7U)
13732 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
13733 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
13734 #define SPI_CR1_SSI_Pos (8U)
13735 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
13736 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
13737 #define SPI_CR1_SSM_Pos (9U)
13738 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
13739 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
13740 #define SPI_CR1_RXONLY_Pos (10U)
13741 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
13742 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
13743 #define SPI_CR1_CRCL_Pos (11U)
13744 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
13745 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
13746 #define SPI_CR1_CRCNEXT_Pos (12U)
13747 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
13748 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
13749 #define SPI_CR1_CRCEN_Pos (13U)
13750 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
13751 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
13752 #define SPI_CR1_BIDIOE_Pos (14U)
13753 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
13754 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
13755 #define SPI_CR1_BIDIMODE_Pos (15U)
13756 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
13757 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
13758
13759 /******************* Bit definition for SPI_CR2 register ********************/
13760 #define SPI_CR2_RXDMAEN_Pos (0U)
13761 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
13762 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
13763 #define SPI_CR2_TXDMAEN_Pos (1U)
13764 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
13765 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
13766 #define SPI_CR2_SSOE_Pos (2U)
13767 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
13768 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
13769 #define SPI_CR2_NSSP_Pos (3U)
13770 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
13771 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
13772 #define SPI_CR2_FRF_Pos (4U)
13773 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
13774 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
13775 #define SPI_CR2_ERRIE_Pos (5U)
13776 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
13777 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
13778 #define SPI_CR2_RXNEIE_Pos (6U)
13779 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
13780 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
13781 #define SPI_CR2_TXEIE_Pos (7U)
13782 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
13783 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
13784 #define SPI_CR2_DS_Pos (8U)
13785 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
13786 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
13787 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
13788 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
13789 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
13790 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
13791 #define SPI_CR2_FRXTH_Pos (12U)
13792 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
13793 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
13794 #define SPI_CR2_LDMARX_Pos (13U)
13795 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
13796 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
13797 #define SPI_CR2_LDMATX_Pos (14U)
13798 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
13799 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
13800
13801 /******************** Bit definition for SPI_SR register ********************/
13802 #define SPI_SR_RXNE_Pos (0U)
13803 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
13804 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
13805 #define SPI_SR_TXE_Pos (1U)
13806 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
13807 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
13808 #define SPI_SR_CHSIDE_Pos (2U)
13809 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
13810 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
13811 #define SPI_SR_UDR_Pos (3U)
13812 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
13813 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
13814 #define SPI_SR_CRCERR_Pos (4U)
13815 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
13816 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
13817 #define SPI_SR_MODF_Pos (5U)
13818 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
13819 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
13820 #define SPI_SR_OVR_Pos (6U)
13821 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
13822 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
13823 #define SPI_SR_BSY_Pos (7U)
13824 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
13825 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
13826 #define SPI_SR_FRE_Pos (8U)
13827 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
13828 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
13829 #define SPI_SR_FRLVL_Pos (9U)
13830 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
13831 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
13832 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
13833 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
13834 #define SPI_SR_FTLVL_Pos (11U)
13835 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
13836 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
13837 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
13838 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
13839
13840 /******************** Bit definition for SPI_DR register ********************/
13841 #define SPI_DR_DR_Pos (0U)
13842 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
13843 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
13844
13845 /******************* Bit definition for SPI_CRCPR register ******************/
13846 #define SPI_CRCPR_CRCPOLY_Pos (0U)
13847 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
13848 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
13849
13850 /****************** Bit definition for SPI_RXCRCR register ******************/
13851 #define SPI_RXCRCR_RXCRC_Pos (0U)
13852 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
13853 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
13854
13855 /****************** Bit definition for SPI_TXCRCR register ******************/
13856 #define SPI_TXCRCR_TXCRC_Pos (0U)
13857 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
13858 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
13859
13860 /****************** Bit definition for SPI_I2SCFGR register *****************/
13861 #define SPI_I2SCFGR_CHLEN_Pos (0U)
13862 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
13863 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
13864 #define SPI_I2SCFGR_DATLEN_Pos (1U)
13865 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
13866 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
13867 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
13868 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
13869 #define SPI_I2SCFGR_CKPOL_Pos (3U)
13870 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
13871 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
13872 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
13873 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
13874 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
13875 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
13876 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
13877 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
13878 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
13879 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
13880 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
13881 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
13882 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
13883 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
13884 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
13885 #define SPI_I2SCFGR_I2SE_Pos (10U)
13886 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
13887 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
13888 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
13889 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
13890 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
13891 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
13892 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
13893 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
13894
13895 /****************** Bit definition for SPI_I2SPR register *******************/
13896 #define SPI_I2SPR_I2SDIV_Pos (0U)
13897 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
13898 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
13899 #define SPI_I2SPR_ODD_Pos (8U)
13900 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
13901 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
13902 #define SPI_I2SPR_MCKOE_Pos (9U)
13903 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
13904 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
13905
13906
13907 /******************************************************************************/
13908 /* */
13909 /* SYSCFG */
13910 /* */
13911 /******************************************************************************/
13912 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
13913 #define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)
13914 #define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1U << SYSCFG_MEMRMP_MEM_BOOT_Pos) /*!< 0x00000001 */
13915 #define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk /*!< Boot information after Reset */
13916
13917 #define SYSCFG_MEMRMP_SWP_FB_Pos (8U)
13918 #define SYSCFG_MEMRMP_SWP_FB_Msk (0x1U << SYSCFG_MEMRMP_SWP_FB_Pos) /*!< 0x00000100 */
13919 #define SYSCFG_MEMRMP_SWP_FB SYSCFG_MEMRMP_SWP_FB_Msk /*!< User Flash Bank swap */
13920
13921 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
13922 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
13923 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC Memory Mapping swapping */
13924 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
13925 #define SYSCFG_MEMRMP_SWP_FMC_1 (0x2U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */
13926
13927 /****************** Bit definition for SYSCFG_PMC register ******************/
13928 #define SYSCFG_PMC_I2C1_FMP_Pos (0U)
13929 #define SYSCFG_PMC_I2C1_FMP_Msk (0x1U << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */
13930 #define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */
13931 #define SYSCFG_PMC_I2C2_FMP_Pos (1U)
13932 #define SYSCFG_PMC_I2C2_FMP_Msk (0x1U << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */
13933 #define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */
13934 #define SYSCFG_PMC_I2C3_FMP_Pos (2U)
13935 #define SYSCFG_PMC_I2C3_FMP_Msk (0x1U << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */
13936 #define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */
13937 #define SYSCFG_PMC_I2C4_FMP_Pos (3U)
13938 #define SYSCFG_PMC_I2C4_FMP_Msk (0x1U << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */
13939 #define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */
13940 #define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
13941 #define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
13942 #define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */
13943 #define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
13944 #define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
13945 #define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */
13946 #define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
13947 #define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
13948 #define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */
13949 #define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
13950 #define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
13951 #define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */
13952
13953 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
13954 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
13955 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
13956 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
13957 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
13958 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
13959 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
13960 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
13961 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
13962 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
13963 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
13964 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
13965
13966 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
13967 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
13968 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
13969
13970 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13971 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13972 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
13973 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
13974 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13975 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
13976 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
13977 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13978 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
13979 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
13980 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13981 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
13982 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
13983 /**
13984 * @brief EXTI0 configuration
13985 */
13986 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
13987 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
13988 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
13989 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
13990 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
13991 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
13992 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
13993 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
13994 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
13995 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
13996 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
13997
13998 /**
13999 * @brief EXTI1 configuration
14000 */
14001 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
14002 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
14003 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
14004 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
14005 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
14006 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
14007 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
14008 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
14009 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
14010 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
14011 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
14012
14013 /**
14014 * @brief EXTI2 configuration
14015 */
14016 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
14017 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
14018 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
14019 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
14020 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
14021 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
14022 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
14023 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
14024 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
14025 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
14026 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
14027
14028 /**
14029 * @brief EXTI3 configuration
14030 */
14031 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
14032 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
14033 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
14034 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
14035 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
14036 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
14037 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
14038 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
14039 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
14040 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
14041 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
14042
14043 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
14044 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
14045 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
14046 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
14047 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
14048 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
14049 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
14050 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
14051 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
14052 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
14053 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
14054 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
14055 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
14056 /**
14057 * @brief EXTI4 configuration
14058 */
14059 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
14060 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
14061 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
14062 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
14063 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
14064 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
14065 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
14066 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
14067 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
14068 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
14069 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
14070
14071 /**
14072 * @brief EXTI5 configuration
14073 */
14074 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
14075 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
14076 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
14077 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
14078 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
14079 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
14080 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
14081 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
14082 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
14083 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
14084 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
14085
14086 /**
14087 * @brief EXTI6 configuration
14088 */
14089 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
14090 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
14091 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
14092 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
14093 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
14094 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
14095 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
14096 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
14097 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
14098 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
14099 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
14100
14101 /**
14102 * @brief EXTI7 configuration
14103 */
14104 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
14105 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
14106 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
14107 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
14108 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
14109 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
14110 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
14111 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
14112 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
14113 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
14114 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
14115
14116 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
14117 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
14118 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
14119 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
14120 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
14121 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
14122 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
14123 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
14124 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
14125 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
14126 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
14127 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
14128 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
14129
14130 /**
14131 * @brief EXTI8 configuration
14132 */
14133 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
14134 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
14135 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
14136 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
14137 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
14138 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
14139 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
14140 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
14141 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
14142 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
14143
14144 /**
14145 * @brief EXTI9 configuration
14146 */
14147 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
14148 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
14149 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
14150 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
14151 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
14152 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
14153 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
14154 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
14155 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
14156 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
14157
14158 /**
14159 * @brief EXTI10 configuration
14160 */
14161 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
14162 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
14163 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
14164 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
14165 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
14166 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
14167 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
14168 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
14169 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
14170 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
14171
14172 /**
14173 * @brief EXTI11 configuration
14174 */
14175 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
14176 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
14177 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
14178 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
14179 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
14180 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
14181 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
14182 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
14183 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
14184 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
14185
14186
14187 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
14188 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
14189 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
14190 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
14191 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
14192 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
14193 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
14194 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
14195 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
14196 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
14197 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
14198 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
14199 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
14200 /**
14201 * @brief EXTI12 configuration
14202 */
14203 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
14204 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
14205 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
14206 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
14207 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
14208 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
14209 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
14210 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
14211 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
14212 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
14213
14214 /**
14215 * @brief EXTI13 configuration
14216 */
14217 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
14218 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
14219 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
14220 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
14221 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
14222 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
14223 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
14224 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
14225 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
14226 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
14227
14228 /**
14229 * @brief EXTI14 configuration
14230 */
14231 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
14232 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
14233 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
14234 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
14235 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
14236 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
14237 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
14238 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
14239 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
14240 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
14241
14242 /**
14243 * @brief EXTI15 configuration
14244 */
14245 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
14246 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
14247 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
14248 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
14249 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
14250 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
14251 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
14252 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
14253 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
14254 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
14255
14256 /****************** Bit definition for SYSCFG_CBR register ******************/
14257 #define SYSCFG_CBR_CLL_Pos (0U)
14258 #define SYSCFG_CBR_CLL_Msk (0x1U << SYSCFG_CBR_CLL_Pos) /*!< 0x00000001 */
14259 #define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!<Core Lockup Lock */
14260 #define SYSCFG_CBR_PVDL_Pos (2U)
14261 #define SYSCFG_CBR_PVDL_Msk (0x1U << SYSCFG_CBR_PVDL_Pos) /*!< 0x00000004 */
14262 #define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk /*!<PVD Lock */
14263
14264 /****************** Bit definition for SYSCFG_CMPCR register ****************/
14265 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
14266 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
14267 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell power-down */
14268 #define SYSCFG_CMPCR_READY_Pos (8U)
14269 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
14270 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell ready flag */
14271
14272 /******************************************************************************/
14273 /* */
14274 /* TIM */
14275 /* */
14276 /******************************************************************************/
14277 /*
14278 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
14279 */
14280 #define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature available on specific devices */
14281 /******************* Bit definition for TIM_CR1 register ********************/
14282 #define TIM_CR1_CEN_Pos (0U)
14283 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
14284 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
14285 #define TIM_CR1_UDIS_Pos (1U)
14286 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
14287 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
14288 #define TIM_CR1_URS_Pos (2U)
14289 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
14290 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
14291 #define TIM_CR1_OPM_Pos (3U)
14292 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
14293 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
14294 #define TIM_CR1_DIR_Pos (4U)
14295 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
14296 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
14297
14298 #define TIM_CR1_CMS_Pos (5U)
14299 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
14300 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
14301 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
14302 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
14303
14304 #define TIM_CR1_ARPE_Pos (7U)
14305 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
14306 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
14307
14308 #define TIM_CR1_CKD_Pos (8U)
14309 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
14310 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
14311 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
14312 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
14313 #define TIM_CR1_UIFREMAP_Pos (11U)
14314 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
14315 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<UIF status bit */
14316
14317 /******************* Bit definition for TIM_CR2 register ********************/
14318 #define TIM_CR2_CCPC_Pos (0U)
14319 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
14320 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
14321 #define TIM_CR2_CCUS_Pos (2U)
14322 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
14323 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
14324 #define TIM_CR2_CCDS_Pos (3U)
14325 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
14326 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
14327
14328 #define TIM_CR2_OIS5_Pos (16U)
14329 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
14330 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
14331 #define TIM_CR2_OIS6_Pos (18U)
14332 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
14333 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
14334
14335 #define TIM_CR2_MMS_Pos (4U)
14336 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
14337 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
14338 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
14339 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
14340 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
14341
14342 #define TIM_CR2_MMS2_Pos (20U)
14343 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
14344 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
14345 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
14346 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
14347 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
14348 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
14349
14350 #define TIM_CR2_TI1S_Pos (7U)
14351 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
14352 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
14353 #define TIM_CR2_OIS1_Pos (8U)
14354 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
14355 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
14356 #define TIM_CR2_OIS1N_Pos (9U)
14357 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
14358 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
14359 #define TIM_CR2_OIS2_Pos (10U)
14360 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
14361 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
14362 #define TIM_CR2_OIS2N_Pos (11U)
14363 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
14364 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
14365 #define TIM_CR2_OIS3_Pos (12U)
14366 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
14367 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
14368 #define TIM_CR2_OIS3N_Pos (13U)
14369 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
14370 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
14371 #define TIM_CR2_OIS4_Pos (14U)
14372 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
14373 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
14374
14375 /******************* Bit definition for TIM_SMCR register *******************/
14376 #define TIM_SMCR_SMS_Pos (0U)
14377 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
14378 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
14379 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
14380 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
14381 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
14382 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
14383
14384 #define TIM_SMCR_TS_Pos (4U)
14385 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
14386 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
14387 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
14388 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
14389 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
14390
14391 #define TIM_SMCR_MSM_Pos (7U)
14392 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
14393 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
14394
14395 #define TIM_SMCR_ETF_Pos (8U)
14396 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
14397 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
14398 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
14399 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
14400 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
14401 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
14402
14403 #define TIM_SMCR_ETPS_Pos (12U)
14404 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
14405 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
14406 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
14407 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
14408
14409 #define TIM_SMCR_ECE_Pos (14U)
14410 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
14411 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
14412 #define TIM_SMCR_ETP_Pos (15U)
14413 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
14414 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
14415
14416 /******************* Bit definition for TIM_DIER register *******************/
14417 #define TIM_DIER_UIE_Pos (0U)
14418 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
14419 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
14420 #define TIM_DIER_CC1IE_Pos (1U)
14421 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
14422 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
14423 #define TIM_DIER_CC2IE_Pos (2U)
14424 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
14425 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
14426 #define TIM_DIER_CC3IE_Pos (3U)
14427 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
14428 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
14429 #define TIM_DIER_CC4IE_Pos (4U)
14430 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
14431 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
14432 #define TIM_DIER_COMIE_Pos (5U)
14433 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
14434 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
14435 #define TIM_DIER_TIE_Pos (6U)
14436 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
14437 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
14438 #define TIM_DIER_BIE_Pos (7U)
14439 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
14440 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
14441 #define TIM_DIER_UDE_Pos (8U)
14442 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
14443 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
14444 #define TIM_DIER_CC1DE_Pos (9U)
14445 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
14446 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
14447 #define TIM_DIER_CC2DE_Pos (10U)
14448 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
14449 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
14450 #define TIM_DIER_CC3DE_Pos (11U)
14451 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
14452 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
14453 #define TIM_DIER_CC4DE_Pos (12U)
14454 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
14455 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
14456 #define TIM_DIER_COMDE_Pos (13U)
14457 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
14458 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
14459 #define TIM_DIER_TDE_Pos (14U)
14460 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
14461 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
14462
14463 /******************** Bit definition for TIM_SR register ********************/
14464 #define TIM_SR_UIF_Pos (0U)
14465 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
14466 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
14467 #define TIM_SR_CC1IF_Pos (1U)
14468 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
14469 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
14470 #define TIM_SR_CC2IF_Pos (2U)
14471 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
14472 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
14473 #define TIM_SR_CC3IF_Pos (3U)
14474 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
14475 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
14476 #define TIM_SR_CC4IF_Pos (4U)
14477 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
14478 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
14479 #define TIM_SR_COMIF_Pos (5U)
14480 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
14481 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
14482 #define TIM_SR_TIF_Pos (6U)
14483 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
14484 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
14485 #define TIM_SR_BIF_Pos (7U)
14486 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
14487 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
14488 #define TIM_SR_B2IF_Pos (8U)
14489 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
14490 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
14491 #define TIM_SR_CC1OF_Pos (9U)
14492 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
14493 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
14494 #define TIM_SR_CC2OF_Pos (10U)
14495 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
14496 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
14497 #define TIM_SR_CC3OF_Pos (11U)
14498 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
14499 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
14500 #define TIM_SR_CC4OF_Pos (12U)
14501 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
14502 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
14503 #define TIM_SR_SBIF_Pos (13U)
14504 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
14505 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
14506 #define TIM_SR_CC5IF_Pos (16U)
14507 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
14508 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
14509 #define TIM_SR_CC6IF_Pos (17U)
14510 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
14511 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
14512
14513 /******************* Bit definition for TIM_EGR register ********************/
14514 #define TIM_EGR_UG_Pos (0U)
14515 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
14516 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
14517 #define TIM_EGR_CC1G_Pos (1U)
14518 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
14519 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
14520 #define TIM_EGR_CC2G_Pos (2U)
14521 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
14522 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
14523 #define TIM_EGR_CC3G_Pos (3U)
14524 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
14525 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
14526 #define TIM_EGR_CC4G_Pos (4U)
14527 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
14528 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
14529 #define TIM_EGR_COMG_Pos (5U)
14530 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
14531 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
14532 #define TIM_EGR_TG_Pos (6U)
14533 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
14534 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
14535 #define TIM_EGR_BG_Pos (7U)
14536 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
14537 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
14538 #define TIM_EGR_B2G_Pos (8U)
14539 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
14540 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break2 Generation */
14541
14542 /****************** Bit definition for TIM_CCMR1 register *******************/
14543 #define TIM_CCMR1_CC1S_Pos (0U)
14544 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
14545 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
14546 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
14547 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
14548
14549 #define TIM_CCMR1_OC1FE_Pos (2U)
14550 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
14551 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
14552 #define TIM_CCMR1_OC1PE_Pos (3U)
14553 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
14554 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
14555
14556 #define TIM_CCMR1_OC1M_Pos (4U)
14557 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
14558 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
14559 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
14560 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
14561 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
14562 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
14563
14564 #define TIM_CCMR1_OC1CE_Pos (7U)
14565 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
14566 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
14567
14568 #define TIM_CCMR1_CC2S_Pos (8U)
14569 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
14570 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
14571 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
14572 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
14573
14574 #define TIM_CCMR1_OC2FE_Pos (10U)
14575 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
14576 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
14577 #define TIM_CCMR1_OC2PE_Pos (11U)
14578 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
14579 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
14580
14581 #define TIM_CCMR1_OC2M_Pos (12U)
14582 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
14583 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
14584 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
14585 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
14586 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
14587 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
14588
14589 #define TIM_CCMR1_OC2CE_Pos (15U)
14590 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
14591 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
14592
14593 /*----------------------------------------------------------------------------*/
14594
14595 #define TIM_CCMR1_IC1PSC_Pos (2U)
14596 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
14597 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
14598 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
14599 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
14600
14601 #define TIM_CCMR1_IC1F_Pos (4U)
14602 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
14603 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
14604 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
14605 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
14606 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
14607 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
14608
14609 #define TIM_CCMR1_IC2PSC_Pos (10U)
14610 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
14611 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
14612 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
14613 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
14614
14615 #define TIM_CCMR1_IC2F_Pos (12U)
14616 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
14617 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
14618 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
14619 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
14620 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
14621 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
14622
14623 /****************** Bit definition for TIM_CCMR2 register *******************/
14624 #define TIM_CCMR2_CC3S_Pos (0U)
14625 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
14626 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
14627 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
14628 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
14629
14630 #define TIM_CCMR2_OC3FE_Pos (2U)
14631 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
14632 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
14633 #define TIM_CCMR2_OC3PE_Pos (3U)
14634 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
14635 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
14636
14637 #define TIM_CCMR2_OC3M_Pos (4U)
14638 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
14639 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
14640 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
14641 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
14642 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
14643 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
14644
14645
14646
14647 #define TIM_CCMR2_OC3CE_Pos (7U)
14648 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
14649 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
14650
14651 #define TIM_CCMR2_CC4S_Pos (8U)
14652 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
14653 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
14654 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
14655 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
14656
14657 #define TIM_CCMR2_OC4FE_Pos (10U)
14658 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
14659 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
14660 #define TIM_CCMR2_OC4PE_Pos (11U)
14661 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
14662 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
14663
14664 #define TIM_CCMR2_OC4M_Pos (12U)
14665 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
14666 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
14667 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
14668 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
14669 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
14670 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
14671
14672 #define TIM_CCMR2_OC4CE_Pos (15U)
14673 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
14674 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
14675
14676 /*----------------------------------------------------------------------------*/
14677
14678 #define TIM_CCMR2_IC3PSC_Pos (2U)
14679 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
14680 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
14681 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
14682 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
14683
14684 #define TIM_CCMR2_IC3F_Pos (4U)
14685 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
14686 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
14687 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
14688 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
14689 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
14690 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
14691
14692 #define TIM_CCMR2_IC4PSC_Pos (10U)
14693 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
14694 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
14695 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
14696 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
14697
14698 #define TIM_CCMR2_IC4F_Pos (12U)
14699 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
14700 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
14701 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
14702 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
14703 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
14704 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
14705
14706 /******************* Bit definition for TIM_CCER register *******************/
14707 #define TIM_CCER_CC1E_Pos (0U)
14708 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
14709 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
14710 #define TIM_CCER_CC1P_Pos (1U)
14711 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
14712 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
14713 #define TIM_CCER_CC1NE_Pos (2U)
14714 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
14715 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
14716 #define TIM_CCER_CC1NP_Pos (3U)
14717 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
14718 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
14719 #define TIM_CCER_CC2E_Pos (4U)
14720 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
14721 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
14722 #define TIM_CCER_CC2P_Pos (5U)
14723 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
14724 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
14725 #define TIM_CCER_CC2NE_Pos (6U)
14726 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
14727 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
14728 #define TIM_CCER_CC2NP_Pos (7U)
14729 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
14730 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
14731 #define TIM_CCER_CC3E_Pos (8U)
14732 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
14733 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
14734 #define TIM_CCER_CC3P_Pos (9U)
14735 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
14736 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
14737 #define TIM_CCER_CC3NE_Pos (10U)
14738 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
14739 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
14740 #define TIM_CCER_CC3NP_Pos (11U)
14741 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
14742 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
14743 #define TIM_CCER_CC4E_Pos (12U)
14744 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
14745 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
14746 #define TIM_CCER_CC4P_Pos (13U)
14747 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
14748 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
14749 #define TIM_CCER_CC4NP_Pos (15U)
14750 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
14751 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
14752 #define TIM_CCER_CC5E_Pos (16U)
14753 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
14754 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
14755 #define TIM_CCER_CC5P_Pos (17U)
14756 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
14757 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
14758 #define TIM_CCER_CC6E_Pos (20U)
14759 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
14760 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
14761 #define TIM_CCER_CC6P_Pos (21U)
14762 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
14763 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
14764
14765
14766 /******************* Bit definition for TIM_CNT register ********************/
14767 #define TIM_CNT_CNT_Pos (0U)
14768 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
14769 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
14770 #define TIM_CNT_UIFCPY_Pos (31U)
14771 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
14772 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
14773
14774 /******************* Bit definition for TIM_PSC register ********************/
14775 #define TIM_PSC_PSC_Pos (0U)
14776 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
14777 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
14778
14779 /******************* Bit definition for TIM_ARR register ********************/
14780 #define TIM_ARR_ARR_Pos (0U)
14781 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
14782 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
14783
14784 /******************* Bit definition for TIM_RCR register ********************/
14785 #define TIM_RCR_REP_Pos (0U)
14786 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
14787 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
14788
14789 /******************* Bit definition for TIM_CCR1 register *******************/
14790 #define TIM_CCR1_CCR1_Pos (0U)
14791 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
14792 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
14793
14794 /******************* Bit definition for TIM_CCR2 register *******************/
14795 #define TIM_CCR2_CCR2_Pos (0U)
14796 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
14797 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
14798
14799 /******************* Bit definition for TIM_CCR3 register *******************/
14800 #define TIM_CCR3_CCR3_Pos (0U)
14801 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
14802 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
14803
14804 /******************* Bit definition for TIM_CCR4 register *******************/
14805 #define TIM_CCR4_CCR4_Pos (0U)
14806 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
14807 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
14808
14809 /******************* Bit definition for TIM_BDTR register *******************/
14810 #define TIM_BDTR_DTG_Pos (0U)
14811 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
14812 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
14813 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
14814 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
14815 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
14816 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
14817 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
14818 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
14819 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
14820 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
14821
14822 #define TIM_BDTR_LOCK_Pos (8U)
14823 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
14824 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
14825 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
14826 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
14827
14828 #define TIM_BDTR_OSSI_Pos (10U)
14829 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
14830 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
14831 #define TIM_BDTR_OSSR_Pos (11U)
14832 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
14833 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
14834 #define TIM_BDTR_BKE_Pos (12U)
14835 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
14836 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
14837 #define TIM_BDTR_BKP_Pos (13U)
14838 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
14839 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
14840 #define TIM_BDTR_AOE_Pos (14U)
14841 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
14842 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
14843 #define TIM_BDTR_MOE_Pos (15U)
14844 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
14845 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
14846 #define TIM_BDTR_BKF_Pos (16U)
14847 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
14848 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
14849 #define TIM_BDTR_BK2F_Pos (20U)
14850 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
14851 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
14852 #define TIM_BDTR_BK2E_Pos (24U)
14853 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
14854 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
14855 #define TIM_BDTR_BK2P_Pos (25U)
14856 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
14857 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
14858
14859 /******************* Bit definition for TIM_DCR register ********************/
14860 #define TIM_DCR_DBA_Pos (0U)
14861 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
14862 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
14863 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
14864 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
14865 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
14866 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
14867 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
14868
14869 #define TIM_DCR_DBL_Pos (8U)
14870 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
14871 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
14872 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
14873 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
14874 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
14875 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
14876 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
14877
14878 /******************* Bit definition for TIM_DMAR register *******************/
14879 #define TIM_DMAR_DMAB_Pos (0U)
14880 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
14881 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
14882
14883 /******************* Bit definition for TIM_OR regiter *********************/
14884 #define TIM_OR_TI4_RMP_Pos (6U)
14885 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
14886 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
14887 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
14888 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
14889 #define TIM_OR_ITR1_RMP_Pos (10U)
14890 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
14891 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
14892 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
14893 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
14894
14895 /******************* Bit definition for TIM2_OR register *******************/
14896 #define TIM2_OR_ITR1_RMP_Pos (10U)
14897 #define TIM2_OR_ITR1_RMP_Msk (0x3U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
14898 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
14899 #define TIM2_OR_ITR1_RMP_0 (0x1U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000400 */
14900 #define TIM2_OR_ITR1_RMP_1 (0x2U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000800 */
14901
14902 /******************* Bit definition for TIM5_OR register *******************/
14903 #define TIM5_OR_TI4_RMP_Pos (6U)
14904 #define TIM5_OR_TI4_RMP_Msk (0x3U << TIM5_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
14905 #define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input Capture 4 remap) */
14906 #define TIM5_OR_TI4_RMP_0 (0x1U << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000040 */
14907 #define TIM5_OR_TI4_RMP_1 (0x2U << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000080 */
14908
14909 /******************* Bit definition for TIM11_OR register *******************/
14910 #define TIM11_OR_TI1_RMP_Pos (0U)
14911 #define TIM11_OR_TI1_RMP_Msk (0x3U << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000003 */
14912 #define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
14913 #define TIM11_OR_TI1_RMP_0 (0x1U << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000001 */
14914 #define TIM11_OR_TI1_RMP_1 (0x2U << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000002 */
14915
14916 /****************** Bit definition for TIM_CCMR3 register *******************/
14917 #define TIM_CCMR3_OC5FE_Pos (2U)
14918 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
14919 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
14920 #define TIM_CCMR3_OC5PE_Pos (3U)
14921 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
14922 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
14923
14924 #define TIM_CCMR3_OC5M_Pos (4U)
14925 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
14926 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
14927 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
14928 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
14929 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
14930 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
14931
14932 #define TIM_CCMR3_OC5CE_Pos (7U)
14933 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
14934 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
14935
14936 #define TIM_CCMR3_OC6FE_Pos (10U)
14937 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
14938 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
14939 #define TIM_CCMR3_OC6PE_Pos (11U)
14940 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
14941 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
14942
14943 #define TIM_CCMR3_OC6M_Pos (12U)
14944 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
14945 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
14946 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
14947 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
14948 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
14949 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
14950
14951 #define TIM_CCMR3_OC6CE_Pos (15U)
14952 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
14953 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
14954
14955 /******************* Bit definition for TIM_CCR5 register *******************/
14956 #define TIM_CCR5_CCR5_Pos (0U)
14957 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14958 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
14959 #define TIM_CCR5_GC5C1_Pos (29U)
14960 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
14961 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
14962 #define TIM_CCR5_GC5C2_Pos (30U)
14963 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
14964 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
14965 #define TIM_CCR5_GC5C3_Pos (31U)
14966 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
14967 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
14968
14969 /******************* Bit definition for TIM_CCR6 register *******************/
14970 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
14971
14972 /******************* Bit definition for TIM1_AF1 register *******************/
14973 #define TIM1_AF1_BKINE_Pos (0U)
14974 #define TIM1_AF1_BKINE_Msk (0x1U << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
14975 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
14976 #define TIM1_AF1_BKDF1BKE_Pos (8U)
14977 #define TIM1_AF1_BKDF1BKE_Msk (0x1U << TIM1_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */
14978 #define TIM1_AF1_BKDF1BKE TIM1_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */
14979 #define TIM1_AF1_BKINP_Pos (9U)
14980 #define TIM1_AF1_BKINP_Msk (0x1U << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
14981 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
14982
14983 /******************* Bit definition for TIM1_AF2 register *******************/
14984 #define TIM1_AF2_BK2INE_Pos (0U)
14985 #define TIM1_AF2_BK2INE_Msk (0x1U << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
14986 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
14987 #define TIM1_AF2_BK2DF1BKE_Pos (8U)
14988 #define TIM1_AF2_BK2DF1BKE_Msk (0x1U << TIM1_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */
14989 #define TIM1_AF2_BK2DF1BKE TIM1_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */
14990 #define TIM1_AF2_BK2INP_Pos (9U)
14991 #define TIM1_AF2_BK2INP_Msk (0x1U << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
14992 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */
14993
14994 /******************* Bit definition for TIM8_AF1 register *******************/
14995 #define TIM8_AF1_BKINE_Pos (0U)
14996 #define TIM8_AF1_BKINE_Msk (0x1U << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
14997 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BRK BKIN input enable */
14998 #define TIM8_AF1_BKDF1BKE_Pos (8U)
14999 #define TIM8_AF1_BKDF1BKE_Msk (0x1U << TIM8_AF1_BKDF1BKE_Pos) /*!< 0x00000100 */
15000 #define TIM8_AF1_BKDF1BKE TIM8_AF1_BKDF1BKE_Msk /*!<BRK DFSDM1_BREAK enable */
15001 #define TIM8_AF1_BKINP_Pos (9U)
15002 #define TIM8_AF1_BKINP_Msk (0x1U << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
15003 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
15004
15005 /******************* Bit definition for TIM8_AF2 register *******************/
15006 #define TIM8_AF2_BK2INE_Pos (0U)
15007 #define TIM8_AF2_BK2INE_Msk (0x1U << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
15008 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
15009 #define TIM8_AF2_BK2DF1BKE_Pos (8U)
15010 #define TIM8_AF2_BK2DF1BKE_Msk (0x1U << TIM8_AF2_BK2DF1BKE_Pos) /*!< 0x00000100 */
15011 #define TIM8_AF2_BK2DF1BKE TIM8_AF2_BK2DF1BKE_Msk /*!<BRK2 DFSDM1_BREAK enable */
15012 #define TIM8_AF2_BK2INP_Pos (9U)
15013 #define TIM8_AF2_BK2INP_Msk (0x1U << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
15014 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRK BKIN input polarity */
15015
15016
15017 /******************************************************************************/
15018 /* */
15019 /* Low Power Timer (LPTIM) */
15020 /* */
15021 /******************************************************************************/
15022 /****************** Bit definition for LPTIM_ISR register *******************/
15023 #define LPTIM_ISR_CMPM_Pos (0U)
15024 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
15025 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
15026 #define LPTIM_ISR_ARRM_Pos (1U)
15027 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
15028 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
15029 #define LPTIM_ISR_EXTTRIG_Pos (2U)
15030 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
15031 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
15032 #define LPTIM_ISR_CMPOK_Pos (3U)
15033 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
15034 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
15035 #define LPTIM_ISR_ARROK_Pos (4U)
15036 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
15037 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
15038 #define LPTIM_ISR_UP_Pos (5U)
15039 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
15040 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
15041 #define LPTIM_ISR_DOWN_Pos (6U)
15042 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
15043 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
15044
15045 /****************** Bit definition for LPTIM_ICR register *******************/
15046 #define LPTIM_ICR_CMPMCF_Pos (0U)
15047 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
15048 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
15049 #define LPTIM_ICR_ARRMCF_Pos (1U)
15050 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
15051 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
15052 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
15053 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
15054 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
15055 #define LPTIM_ICR_CMPOKCF_Pos (3U)
15056 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
15057 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
15058 #define LPTIM_ICR_ARROKCF_Pos (4U)
15059 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
15060 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
15061 #define LPTIM_ICR_UPCF_Pos (5U)
15062 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
15063 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
15064 #define LPTIM_ICR_DOWNCF_Pos (6U)
15065 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
15066 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
15067
15068 /****************** Bit definition for LPTIM_IER register *******************/
15069 #define LPTIM_IER_CMPMIE_Pos (0U)
15070 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
15071 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
15072 #define LPTIM_IER_ARRMIE_Pos (1U)
15073 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
15074 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
15075 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
15076 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
15077 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
15078 #define LPTIM_IER_CMPOKIE_Pos (3U)
15079 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
15080 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
15081 #define LPTIM_IER_ARROKIE_Pos (4U)
15082 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
15083 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
15084 #define LPTIM_IER_UPIE_Pos (5U)
15085 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
15086 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
15087 #define LPTIM_IER_DOWNIE_Pos (6U)
15088 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
15089 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
15090
15091 /****************** Bit definition for LPTIM_CFGR register*******************/
15092 #define LPTIM_CFGR_CKSEL_Pos (0U)
15093 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
15094 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
15095
15096 #define LPTIM_CFGR_CKPOL_Pos (1U)
15097 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
15098 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
15099 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
15100 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
15101
15102 #define LPTIM_CFGR_CKFLT_Pos (3U)
15103 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
15104 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
15105 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
15106 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
15107
15108 #define LPTIM_CFGR_TRGFLT_Pos (6U)
15109 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
15110 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
15111 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
15112 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
15113
15114 #define LPTIM_CFGR_PRESC_Pos (9U)
15115 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
15116 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
15117 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
15118 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
15119 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
15120
15121 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
15122 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
15123 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
15124 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
15125 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
15126 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
15127
15128 #define LPTIM_CFGR_TRIGEN_Pos (17U)
15129 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
15130 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
15131 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
15132 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
15133
15134 #define LPTIM_CFGR_TIMOUT_Pos (19U)
15135 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
15136 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
15137 #define LPTIM_CFGR_WAVE_Pos (20U)
15138 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
15139 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
15140 #define LPTIM_CFGR_WAVPOL_Pos (21U)
15141 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
15142 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
15143 #define LPTIM_CFGR_PRELOAD_Pos (22U)
15144 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
15145 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
15146 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
15147 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
15148 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
15149 #define LPTIM_CFGR_ENC_Pos (24U)
15150 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
15151 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
15152
15153 /****************** Bit definition for LPTIM_CR register ********************/
15154 #define LPTIM_CR_ENABLE_Pos (0U)
15155 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
15156 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
15157 #define LPTIM_CR_SNGSTRT_Pos (1U)
15158 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
15159 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
15160 #define LPTIM_CR_CNTSTRT_Pos (2U)
15161 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
15162 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
15163
15164 /****************** Bit definition for LPTIM_CMP register *******************/
15165 #define LPTIM_CMP_CMP_Pos (0U)
15166 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
15167 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
15168
15169 /****************** Bit definition for LPTIM_ARR register *******************/
15170 #define LPTIM_ARR_ARR_Pos (0U)
15171 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
15172 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
15173
15174 /****************** Bit definition for LPTIM_CNT register *******************/
15175 #define LPTIM_CNT_CNT_Pos (0U)
15176 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
15177 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
15178 /******************************************************************************/
15179 /* */
15180 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
15181 /* */
15182 /******************************************************************************/
15183 /****************** Bit definition for USART_CR1 register *******************/
15184 #define USART_CR1_UE_Pos (0U)
15185 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
15186 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
15187 #define USART_CR1_RE_Pos (2U)
15188 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
15189 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
15190 #define USART_CR1_TE_Pos (3U)
15191 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
15192 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
15193 #define USART_CR1_IDLEIE_Pos (4U)
15194 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
15195 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
15196 #define USART_CR1_RXNEIE_Pos (5U)
15197 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
15198 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
15199 #define USART_CR1_TCIE_Pos (6U)
15200 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
15201 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
15202 #define USART_CR1_TXEIE_Pos (7U)
15203 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
15204 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
15205 #define USART_CR1_PEIE_Pos (8U)
15206 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
15207 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
15208 #define USART_CR1_PS_Pos (9U)
15209 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
15210 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
15211 #define USART_CR1_PCE_Pos (10U)
15212 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
15213 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
15214 #define USART_CR1_WAKE_Pos (11U)
15215 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
15216 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
15217 #define USART_CR1_M_Pos (12U)
15218 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
15219 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
15220 #define USART_CR1_M0 (0x00001U << USART_CR1_M_Pos) /*!< 0x00001000 */
15221 #define USART_CR1_MME_Pos (13U)
15222 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
15223 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
15224 #define USART_CR1_CMIE_Pos (14U)
15225 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
15226 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
15227 #define USART_CR1_OVER8_Pos (15U)
15228 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
15229 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
15230 #define USART_CR1_DEDT_Pos (16U)
15231 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
15232 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
15233 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
15234 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
15235 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
15236 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
15237 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
15238 #define USART_CR1_DEAT_Pos (21U)
15239 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
15240 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
15241 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
15242 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
15243 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
15244 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
15245 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
15246 #define USART_CR1_RTOIE_Pos (26U)
15247 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
15248 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
15249 #define USART_CR1_EOBIE_Pos (27U)
15250 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
15251 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
15252 #define USART_CR1_M1 0x10000000U /*!< Word length - Bit 1 */
15253
15254 /* Legacy defines */
15255 #define USART_CR1_M_0 USART_CR1_M0 /*!< Word length - Bit 0 */
15256 #define USART_CR1_M_1 USART_CR1_M1 /*!< Word length - Bit 1 */
15257
15258 /****************** Bit definition for USART_CR2 register *******************/
15259 #define USART_CR2_ADDM7_Pos (4U)
15260 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
15261 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
15262 #define USART_CR2_LBDL_Pos (5U)
15263 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
15264 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
15265 #define USART_CR2_LBDIE_Pos (6U)
15266 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
15267 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
15268 #define USART_CR2_LBCL_Pos (8U)
15269 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
15270 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
15271 #define USART_CR2_CPHA_Pos (9U)
15272 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
15273 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
15274 #define USART_CR2_CPOL_Pos (10U)
15275 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
15276 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
15277 #define USART_CR2_CLKEN_Pos (11U)
15278 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
15279 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
15280 #define USART_CR2_STOP_Pos (12U)
15281 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
15282 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
15283 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
15284 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
15285 #define USART_CR2_LINEN_Pos (14U)
15286 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
15287 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
15288 #define USART_CR2_SWAP_Pos (15U)
15289 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
15290 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
15291 #define USART_CR2_RXINV_Pos (16U)
15292 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
15293 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
15294 #define USART_CR2_TXINV_Pos (17U)
15295 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
15296 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
15297 #define USART_CR2_DATAINV_Pos (18U)
15298 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
15299 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
15300 #define USART_CR2_MSBFIRST_Pos (19U)
15301 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
15302 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
15303 #define USART_CR2_ABREN_Pos (20U)
15304 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
15305 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable */
15306 #define USART_CR2_ABRMODE_Pos (21U)
15307 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
15308 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
15309 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
15310 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
15311 #define USART_CR2_RTOEN_Pos (23U)
15312 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
15313 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
15314 #define USART_CR2_ADD_Pos (24U)
15315 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
15316 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
15317
15318 /****************** Bit definition for USART_CR3 register *******************/
15319 #define USART_CR3_EIE_Pos (0U)
15320 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
15321 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
15322 #define USART_CR3_IREN_Pos (1U)
15323 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
15324 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
15325 #define USART_CR3_IRLP_Pos (2U)
15326 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
15327 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
15328 #define USART_CR3_HDSEL_Pos (3U)
15329 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
15330 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
15331 #define USART_CR3_NACK_Pos (4U)
15332 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
15333 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
15334 #define USART_CR3_SCEN_Pos (5U)
15335 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
15336 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
15337 #define USART_CR3_DMAR_Pos (6U)
15338 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
15339 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
15340 #define USART_CR3_DMAT_Pos (7U)
15341 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
15342 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
15343 #define USART_CR3_RTSE_Pos (8U)
15344 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
15345 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
15346 #define USART_CR3_CTSE_Pos (9U)
15347 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
15348 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
15349 #define USART_CR3_CTSIE_Pos (10U)
15350 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
15351 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
15352 #define USART_CR3_ONEBIT_Pos (11U)
15353 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
15354 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
15355 #define USART_CR3_OVRDIS_Pos (12U)
15356 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
15357 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
15358 #define USART_CR3_DDRE_Pos (13U)
15359 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
15360 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
15361 #define USART_CR3_DEM_Pos (14U)
15362 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
15363 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
15364 #define USART_CR3_DEP_Pos (15U)
15365 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
15366 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
15367 #define USART_CR3_SCARCNT_Pos (17U)
15368 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
15369 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
15370 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
15371 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
15372 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
15373
15374 /****************** Bit definition for USART_BRR register *******************/
15375 #define USART_BRR_DIV_FRACTION_Pos (0U)
15376 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
15377 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
15378 #define USART_BRR_DIV_MANTISSA_Pos (4U)
15379 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
15380 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
15381
15382 /****************** Bit definition for USART_GTPR register ******************/
15383 #define USART_GTPR_PSC_Pos (0U)
15384 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
15385 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
15386 #define USART_GTPR_GT_Pos (8U)
15387 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
15388 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
15389
15390
15391 /******************* Bit definition for USART_RTOR register *****************/
15392 #define USART_RTOR_RTO_Pos (0U)
15393 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
15394 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
15395 #define USART_RTOR_BLEN_Pos (24U)
15396 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
15397 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
15398
15399 /******************* Bit definition for USART_RQR register ******************/
15400 #define USART_RQR_ABRRQ_Pos (0U)
15401 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
15402 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
15403 #define USART_RQR_SBKRQ_Pos (1U)
15404 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
15405 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
15406 #define USART_RQR_MMRQ_Pos (2U)
15407 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
15408 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
15409 #define USART_RQR_RXFRQ_Pos (3U)
15410 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
15411 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
15412 #define USART_RQR_TXFRQ_Pos (4U)
15413 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
15414 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
15415
15416 /******************* Bit definition for USART_ISR register ******************/
15417 #define USART_ISR_PE_Pos (0U)
15418 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
15419 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
15420 #define USART_ISR_FE_Pos (1U)
15421 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
15422 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
15423 #define USART_ISR_NE_Pos (2U)
15424 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
15425 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
15426 #define USART_ISR_ORE_Pos (3U)
15427 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
15428 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
15429 #define USART_ISR_IDLE_Pos (4U)
15430 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
15431 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
15432 #define USART_ISR_RXNE_Pos (5U)
15433 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
15434 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
15435 #define USART_ISR_TC_Pos (6U)
15436 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
15437 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
15438 #define USART_ISR_TXE_Pos (7U)
15439 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
15440 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
15441 #define USART_ISR_LBDF_Pos (8U)
15442 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
15443 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
15444 #define USART_ISR_CTSIF_Pos (9U)
15445 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
15446 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
15447 #define USART_ISR_CTS_Pos (10U)
15448 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
15449 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
15450 #define USART_ISR_RTOF_Pos (11U)
15451 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
15452 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
15453 #define USART_ISR_EOBF_Pos (12U)
15454 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
15455 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
15456 #define USART_ISR_ABRE_Pos (14U)
15457 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
15458 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
15459 #define USART_ISR_ABRF_Pos (15U)
15460 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
15461 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
15462 #define USART_ISR_BUSY_Pos (16U)
15463 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
15464 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
15465 #define USART_ISR_CMF_Pos (17U)
15466 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
15467 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
15468 #define USART_ISR_SBKF_Pos (18U)
15469 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
15470 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
15471 #define USART_ISR_RWU_Pos (19U)
15472 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
15473 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
15474 #define USART_ISR_TEACK_Pos (21U)
15475 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
15476 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
15477
15478 /******************* Bit definition for USART_ICR register ******************/
15479 #define USART_ICR_PECF_Pos (0U)
15480 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
15481 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
15482 #define USART_ICR_FECF_Pos (1U)
15483 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
15484 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
15485 #define USART_ICR_NCF_Pos (2U)
15486 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
15487 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
15488 #define USART_ICR_ORECF_Pos (3U)
15489 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
15490 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
15491 #define USART_ICR_IDLECF_Pos (4U)
15492 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
15493 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
15494 #define USART_ICR_TCCF_Pos (6U)
15495 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
15496 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
15497 #define USART_ICR_LBDCF_Pos (8U)
15498 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
15499 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
15500 #define USART_ICR_CTSCF_Pos (9U)
15501 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
15502 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
15503 #define USART_ICR_RTOCF_Pos (11U)
15504 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
15505 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
15506 #define USART_ICR_EOBCF_Pos (12U)
15507 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
15508 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
15509 #define USART_ICR_CMCF_Pos (17U)
15510 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
15511 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
15512
15513 /******************* Bit definition for USART_RDR register ******************/
15514 #define USART_RDR_RDR_Pos (0U)
15515 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
15516 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
15517
15518 /******************* Bit definition for USART_TDR register ******************/
15519 #define USART_TDR_TDR_Pos (0U)
15520 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
15521 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
15522
15523 /******************************************************************************/
15524 /* */
15525 /* Window WATCHDOG */
15526 /* */
15527 /******************************************************************************/
15528 /******************* Bit definition for WWDG_CR register ********************/
15529 #define WWDG_CR_T_Pos (0U)
15530 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
15531 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
15532 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
15533 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
15534 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
15535 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
15536 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
15537 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
15538 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
15539
15540
15541 #define WWDG_CR_WDGA_Pos (7U)
15542 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
15543 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
15544
15545 /******************* Bit definition for WWDG_CFR register *******************/
15546 #define WWDG_CFR_W_Pos (0U)
15547 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
15548 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
15549 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
15550 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
15551 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
15552 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
15553 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
15554 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
15555 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
15556
15557
15558 #define WWDG_CFR_WDGTB_Pos (7U)
15559 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
15560 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
15561 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
15562 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
15563
15564
15565 #define WWDG_CFR_EWI_Pos (9U)
15566 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
15567 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
15568
15569 /******************* Bit definition for WWDG_SR register ********************/
15570 #define WWDG_SR_EWIF_Pos (0U)
15571 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
15572 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
15573
15574 /******************************************************************************/
15575 /* */
15576 /* DBG */
15577 /* */
15578 /******************************************************************************/
15579 /******************** Bit definition for DBGMCU_IDCODE register *************/
15580 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
15581 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
15582 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
15583 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
15584 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
15585 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
15586
15587 /******************** Bit definition for DBGMCU_CR register *****************/
15588 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
15589 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
15590 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
15591 #define DBGMCU_CR_DBG_STOP_Pos (1U)
15592 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
15593 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
15594 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
15595 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
15596 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
15597 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
15598 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
15599 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
15600
15601 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
15602 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
15603 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
15604 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
15605 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
15606
15607 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
15608 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
15609 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
15610 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
15611 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
15612 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
15613 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
15614 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
15615 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
15616 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
15617 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
15618 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
15619 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
15620 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
15621 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
15622 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
15623 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
15624 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
15625 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
15626 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
15627 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
15628 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
15629 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
15630 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
15631 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
15632 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
15633 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
15634 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
15635 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
15636 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
15637 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
15638 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
15639 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
15640 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
15641 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
15642 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
15643 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
15644 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
15645 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
15646 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
15647 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (13U)
15648 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x00002000 */
15649 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
15650 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
15651 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
15652 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
15653 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
15654 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
15655 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
15656 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
15657 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
15658 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
15659 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
15660 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
15661 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
15662 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
15663 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
15664 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
15665 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
15666 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
15667 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
15668
15669 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
15670 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
15671 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
15672 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
15673 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
15674 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
15675 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
15676 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
15677 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
15678 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
15679 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
15680 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
15681 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
15682 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
15683 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
15684 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
15685
15686 /******************************************************************************/
15687 /* */
15688 /* Ethernet MAC Registers bits definitions */
15689 /* */
15690 /******************************************************************************/
15691 /* Bit definition for Ethernet MAC Control Register register */
15692 #define ETH_MACCR_WD_Pos (23U)
15693 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
15694 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
15695 #define ETH_MACCR_JD_Pos (22U)
15696 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
15697 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
15698 #define ETH_MACCR_IFG_Pos (17U)
15699 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
15700 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
15701 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
15702 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
15703 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
15704 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
15705 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
15706 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
15707 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
15708 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
15709 #define ETH_MACCR_CSD_Pos (16U)
15710 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
15711 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
15712 #define ETH_MACCR_FES_Pos (14U)
15713 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
15714 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
15715 #define ETH_MACCR_ROD_Pos (13U)
15716 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
15717 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
15718 #define ETH_MACCR_LM_Pos (12U)
15719 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
15720 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
15721 #define ETH_MACCR_DM_Pos (11U)
15722 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
15723 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
15724 #define ETH_MACCR_IPCO_Pos (10U)
15725 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
15726 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
15727 #define ETH_MACCR_RD_Pos (9U)
15728 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
15729 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
15730 #define ETH_MACCR_APCS_Pos (7U)
15731 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
15732 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
15733 #define ETH_MACCR_BL_Pos (5U)
15734 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
15735 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
15736 a transmission attempt during retries after a collision: 0 =< r <2^k */
15737 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
15738 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
15739 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
15740 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
15741 #define ETH_MACCR_DC_Pos (4U)
15742 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
15743 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
15744 #define ETH_MACCR_TE_Pos (3U)
15745 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
15746 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
15747 #define ETH_MACCR_RE_Pos (2U)
15748 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
15749 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
15750
15751 /* Bit definition for Ethernet MAC Frame Filter Register */
15752 #define ETH_MACFFR_RA_Pos (31U)
15753 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
15754 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
15755 #define ETH_MACFFR_HPF_Pos (10U)
15756 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
15757 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
15758 #define ETH_MACFFR_SAF_Pos (9U)
15759 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
15760 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
15761 #define ETH_MACFFR_SAIF_Pos (8U)
15762 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
15763 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
15764 #define ETH_MACFFR_PCF_Pos (6U)
15765 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
15766 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
15767 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
15768 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
15769 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
15770 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
15771 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
15772 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
15773 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
15774 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
15775 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
15776 #define ETH_MACFFR_BFD_Pos (5U)
15777 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
15778 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
15779 #define ETH_MACFFR_PAM_Pos (4U)
15780 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
15781 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
15782 #define ETH_MACFFR_DAIF_Pos (3U)
15783 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
15784 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
15785 #define ETH_MACFFR_HM_Pos (2U)
15786 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
15787 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
15788 #define ETH_MACFFR_HU_Pos (1U)
15789 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
15790 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
15791 #define ETH_MACFFR_PM_Pos (0U)
15792 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
15793 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
15794
15795 /* Bit definition for Ethernet MAC Hash Table High Register */
15796 #define ETH_MACHTHR_HTH_Pos (0U)
15797 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
15798 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
15799
15800 /* Bit definition for Ethernet MAC Hash Table Low Register */
15801 #define ETH_MACHTLR_HTL_Pos (0U)
15802 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
15803 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
15804
15805 /* Bit definition for Ethernet MAC MII Address Register */
15806 #define ETH_MACMIIAR_PA_Pos (11U)
15807 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
15808 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
15809 #define ETH_MACMIIAR_MR_Pos (6U)
15810 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
15811 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
15812 #define ETH_MACMIIAR_CR_Pos (2U)
15813 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
15814 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
15815 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
15816 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
15817 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
15818 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
15819 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
15820 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
15821 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
15822 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
15823 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
15824 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
15825 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
15826 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
15827 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
15828 #define ETH_MACMIIAR_MW_Pos (1U)
15829 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
15830 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
15831 #define ETH_MACMIIAR_MB_Pos (0U)
15832 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
15833 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
15834
15835 /* Bit definition for Ethernet MAC MII Data Register */
15836 #define ETH_MACMIIDR_MD_Pos (0U)
15837 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
15838 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
15839
15840 /* Bit definition for Ethernet MAC Flow Control Register */
15841 #define ETH_MACFCR_PT_Pos (16U)
15842 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
15843 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
15844 #define ETH_MACFCR_ZQPD_Pos (7U)
15845 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
15846 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
15847 #define ETH_MACFCR_PLT_Pos (4U)
15848 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
15849 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
15850 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
15851 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
15852 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
15853 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
15854 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
15855 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
15856 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
15857 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
15858 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
15859 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
15860 #define ETH_MACFCR_UPFD_Pos (3U)
15861 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
15862 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
15863 #define ETH_MACFCR_RFCE_Pos (2U)
15864 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
15865 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
15866 #define ETH_MACFCR_TFCE_Pos (1U)
15867 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
15868 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
15869 #define ETH_MACFCR_FCBBPA_Pos (0U)
15870 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
15871 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
15872
15873 /* Bit definition for Ethernet MAC VLAN Tag Register */
15874 #define ETH_MACVLANTR_VLANTC_Pos (16U)
15875 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
15876 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
15877 #define ETH_MACVLANTR_VLANTI_Pos (0U)
15878 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
15879 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
15880
15881 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
15882 #define ETH_MACRWUFFR_D_Pos (0U)
15883 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
15884 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
15885 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
15886 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
15887 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
15888 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
15889 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
15890 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
15891 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
15892 RSVD - Filter1 Command - RSVD - Filter0 Command
15893 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
15894 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
15895 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
15896
15897 /* Bit definition for Ethernet MAC PMT Control and Status Register */
15898 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
15899 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
15900 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
15901 #define ETH_MACPMTCSR_GU_Pos (9U)
15902 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
15903 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
15904 #define ETH_MACPMTCSR_WFR_Pos (6U)
15905 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
15906 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
15907 #define ETH_MACPMTCSR_MPR_Pos (5U)
15908 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
15909 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
15910 #define ETH_MACPMTCSR_WFE_Pos (2U)
15911 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
15912 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
15913 #define ETH_MACPMTCSR_MPE_Pos (1U)
15914 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
15915 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
15916 #define ETH_MACPMTCSR_PD_Pos (0U)
15917 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
15918 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
15919
15920 /* Bit definition for Ethernet MAC debug Register */
15921 #define ETH_MACDBGR_TFF_Pos (25U)
15922 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
15923 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
15924 #define ETH_MACDBGR_TFNE_Pos (24U)
15925 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
15926 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
15927 #define ETH_MACDBGR_TPWA_Pos (22U)
15928 #define ETH_MACDBGR_TPWA_Msk (0x1U << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */
15929 #define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
15930 #define ETH_MACDBGR_TFRS_Pos (20U)
15931 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
15932 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
15933 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
15934 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
15935 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
15936 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
15937 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
15938 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
15939 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
15940 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
15941 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
15942 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
15943 #define ETH_MACDBGR_MTP_Pos (19U)
15944 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
15945 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
15946 #define ETH_MACDBGR_MTFCS_Pos (17U)
15947 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
15948 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
15949 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
15950 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
15951 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
15952 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
15953 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
15954 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
15955 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
15956 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
15957 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
15958 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
15959 #define ETH_MACDBGR_MMTEA_Pos (16U)
15960 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
15961 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
15962 #define ETH_MACDBGR_RFFL_Pos (8U)
15963 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
15964 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
15965 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
15966 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
15967 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
15968 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
15969 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
15970 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
15971 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
15972 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
15973 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
15974 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
15975 #define ETH_MACDBGR_RFRCS_Pos (5U)
15976 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
15977 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
15978 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
15979 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
15980 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
15981 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
15982 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
15983 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
15984 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
15985 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
15986 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
15987 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
15988 #define ETH_MACDBGR_RFWRA_Pos (4U)
15989 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
15990 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
15991 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
15992 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
15993 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
15994 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
15995 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
15996 #define ETH_MACDBGR_MMRPEA_Pos (0U)
15997 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
15998 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
15999
16000 /* Bit definition for Ethernet MAC Status Register */
16001 #define ETH_MACSR_TSTS_Pos (9U)
16002 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
16003 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
16004 #define ETH_MACSR_MMCTS_Pos (6U)
16005 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
16006 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
16007 #define ETH_MACSR_MMMCRS_Pos (5U)
16008 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
16009 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
16010 #define ETH_MACSR_MMCS_Pos (4U)
16011 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
16012 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
16013 #define ETH_MACSR_PMTS_Pos (3U)
16014 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
16015 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
16016
16017 /* Bit definition for Ethernet MAC Interrupt Mask Register */
16018 #define ETH_MACIMR_TSTIM_Pos (9U)
16019 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
16020 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
16021 #define ETH_MACIMR_PMTIM_Pos (3U)
16022 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
16023 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
16024
16025 /* Bit definition for Ethernet MAC Address0 High Register */
16026 #define ETH_MACA0HR_MACA0H_Pos (0U)
16027 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
16028 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
16029
16030 /* Bit definition for Ethernet MAC Address0 Low Register */
16031 #define ETH_MACA0LR_MACA0L_Pos (0U)
16032 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
16033 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
16034
16035 /* Bit definition for Ethernet MAC Address1 High Register */
16036 #define ETH_MACA1HR_AE_Pos (31U)
16037 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
16038 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
16039 #define ETH_MACA1HR_SA_Pos (30U)
16040 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
16041 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
16042 #define ETH_MACA1HR_MBC_Pos (24U)
16043 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
16044 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
16045 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
16046 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
16047 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
16048 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
16049 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
16050 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
16051 #define ETH_MACA1HR_MACA1H_Pos (0U)
16052 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
16053 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
16054
16055 /* Bit definition for Ethernet MAC Address1 Low Register */
16056 #define ETH_MACA1LR_MACA1L_Pos (0U)
16057 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
16058 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
16059
16060 /* Bit definition for Ethernet MAC Address2 High Register */
16061 #define ETH_MACA2HR_AE_Pos (31U)
16062 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
16063 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
16064 #define ETH_MACA2HR_SA_Pos (30U)
16065 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
16066 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
16067 #define ETH_MACA2HR_MBC_Pos (24U)
16068 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
16069 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
16070 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
16071 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
16072 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
16073 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
16074 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
16075 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
16076 #define ETH_MACA2HR_MACA2H_Pos (0U)
16077 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
16078 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
16079
16080 /* Bit definition for Ethernet MAC Address2 Low Register */
16081 #define ETH_MACA2LR_MACA2L_Pos (0U)
16082 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
16083 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
16084
16085 /* Bit definition for Ethernet MAC Address3 High Register */
16086 #define ETH_MACA3HR_AE_Pos (31U)
16087 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
16088 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
16089 #define ETH_MACA3HR_SA_Pos (30U)
16090 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
16091 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
16092 #define ETH_MACA3HR_MBC_Pos (24U)
16093 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
16094 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
16095 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
16096 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
16097 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
16098 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
16099 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
16100 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
16101 #define ETH_MACA3HR_MACA3H_Pos (0U)
16102 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
16103 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
16104
16105 /* Bit definition for Ethernet MAC Address3 Low Register */
16106 #define ETH_MACA3LR_MACA3L_Pos (0U)
16107 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
16108 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
16109
16110 /******************************************************************************/
16111 /* Ethernet MMC Registers bits definition */
16112 /******************************************************************************/
16113
16114 /* Bit definition for Ethernet MMC Contol Register */
16115 #define ETH_MMCCR_MCFHP_Pos (5U)
16116 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
16117 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
16118 #define ETH_MMCCR_MCP_Pos (4U)
16119 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
16120 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
16121 #define ETH_MMCCR_MCF_Pos (3U)
16122 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
16123 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
16124 #define ETH_MMCCR_ROR_Pos (2U)
16125 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
16126 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
16127 #define ETH_MMCCR_CSR_Pos (1U)
16128 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
16129 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
16130 #define ETH_MMCCR_CR_Pos (0U)
16131 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
16132 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
16133
16134 /* Bit definition for Ethernet MMC Receive Interrupt Register */
16135 #define ETH_MMCRIR_RGUFS_Pos (17U)
16136 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
16137 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
16138 #define ETH_MMCRIR_RFAES_Pos (6U)
16139 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
16140 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
16141 #define ETH_MMCRIR_RFCES_Pos (5U)
16142 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
16143 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
16144
16145 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
16146 #define ETH_MMCTIR_TGFS_Pos (21U)
16147 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
16148 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
16149 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
16150 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
16151 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
16152 #define ETH_MMCTIR_TGFSCS_Pos (14U)
16153 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
16154 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
16155
16156 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
16157 #define ETH_MMCRIMR_RGUFM_Pos (17U)
16158 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
16159 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
16160 #define ETH_MMCRIMR_RFAEM_Pos (6U)
16161 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
16162 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
16163 #define ETH_MMCRIMR_RFCEM_Pos (5U)
16164 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
16165 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
16166
16167 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
16168 #define ETH_MMCTIMR_TGFM_Pos (21U)
16169 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
16170 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
16171 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
16172 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
16173 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
16174 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
16175 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
16176 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
16177
16178 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
16179 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
16180 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
16181 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
16182
16183 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
16184 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
16185 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
16186 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
16187
16188 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
16189 #define ETH_MMCTGFCR_TGFC_Pos (0U)
16190 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
16191 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
16192
16193 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
16194 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
16195 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
16196 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
16197
16198 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
16199 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
16200 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
16201 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
16202
16203 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
16204 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
16205 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
16206 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
16207
16208 /******************************************************************************/
16209 /* Ethernet PTP Registers bits definition */
16210 /******************************************************************************/
16211
16212 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
16213 #define ETH_PTPTSCR_TSCNT_Pos (16U)
16214 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
16215 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
16216 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
16217 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
16218 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
16219 #define ETH_PTPTSSR_TSSEME_Pos (14U)
16220 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
16221 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
16222 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
16223 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
16224 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
16225 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
16226 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
16227 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
16228 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
16229 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
16230 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
16231 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
16232 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
16233 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
16234 #define ETH_PTPTSSR_TSSSR_Pos (9U)
16235 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
16236 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
16237 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
16238 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
16239 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
16240
16241 #define ETH_PTPTSCR_TSARU_Pos (5U)
16242 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
16243 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
16244 #define ETH_PTPTSCR_TSITE_Pos (4U)
16245 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
16246 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
16247 #define ETH_PTPTSCR_TSSTU_Pos (3U)
16248 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
16249 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
16250 #define ETH_PTPTSCR_TSSTI_Pos (2U)
16251 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
16252 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
16253 #define ETH_PTPTSCR_TSFCU_Pos (1U)
16254 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
16255 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
16256 #define ETH_PTPTSCR_TSE_Pos (0U)
16257 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
16258 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
16259
16260 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
16261 #define ETH_PTPSSIR_STSSI_Pos (0U)
16262 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
16263 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
16264
16265 /* Bit definition for Ethernet PTP Time Stamp High Register */
16266 #define ETH_PTPTSHR_STS_Pos (0U)
16267 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
16268 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
16269
16270 /* Bit definition for Ethernet PTP Time Stamp Low Register */
16271 #define ETH_PTPTSLR_STPNS_Pos (31U)
16272 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
16273 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
16274 #define ETH_PTPTSLR_STSS_Pos (0U)
16275 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
16276 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
16277
16278 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
16279 #define ETH_PTPTSHUR_TSUS_Pos (0U)
16280 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
16281 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
16282
16283 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
16284 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
16285 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
16286 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
16287 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
16288 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
16289 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
16290
16291 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
16292 #define ETH_PTPTSAR_TSA_Pos (0U)
16293 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
16294 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
16295
16296 /* Bit definition for Ethernet PTP Target Time High Register */
16297 #define ETH_PTPTTHR_TTSH_Pos (0U)
16298 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
16299 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
16300
16301 /* Bit definition for Ethernet PTP Target Time Low Register */
16302 #define ETH_PTPTTLR_TTSL_Pos (0U)
16303 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
16304 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
16305
16306 /* Bit definition for Ethernet PTP Time Stamp Status Register */
16307 #define ETH_PTPTSSR_TSTTR_Pos (5U)
16308 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
16309 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
16310 #define ETH_PTPTSSR_TSSO_Pos (4U)
16311 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
16312 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
16313
16314 /******************************************************************************/
16315 /* Ethernet DMA Registers bits definition */
16316 /******************************************************************************/
16317
16318 /* Bit definition for Ethernet DMA Bus Mode Register */
16319 #define ETH_DMABMR_AAB_Pos (25U)
16320 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
16321 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
16322 #define ETH_DMABMR_FPM_Pos (24U)
16323 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
16324 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
16325 #define ETH_DMABMR_USP_Pos (23U)
16326 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
16327 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
16328 #define ETH_DMABMR_RDP_Pos (17U)
16329 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
16330 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
16331 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
16332 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
16333 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
16334 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
16335 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
16336 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
16337 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
16338 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
16339 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
16340 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
16341 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
16342 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
16343 #define ETH_DMABMR_FB_Pos (16U)
16344 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
16345 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
16346 #define ETH_DMABMR_RTPR_Pos (14U)
16347 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
16348 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
16349 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
16350 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
16351 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
16352 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
16353 #define ETH_DMABMR_PBL_Pos (8U)
16354 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
16355 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
16356 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
16357 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
16358 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
16359 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
16360 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
16361 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
16362 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
16363 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
16364 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
16365 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
16366 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
16367 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
16368 #define ETH_DMABMR_EDE_Pos (7U)
16369 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
16370 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
16371 #define ETH_DMABMR_DSL_Pos (2U)
16372 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
16373 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
16374 #define ETH_DMABMR_DA_Pos (1U)
16375 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
16376 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
16377 #define ETH_DMABMR_SR_Pos (0U)
16378 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
16379 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
16380
16381 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
16382 #define ETH_DMATPDR_TPD_Pos (0U)
16383 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
16384 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
16385
16386 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
16387 #define ETH_DMARPDR_RPD_Pos (0U)
16388 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
16389 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
16390
16391 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
16392 #define ETH_DMARDLAR_SRL_Pos (0U)
16393 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
16394 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
16395
16396 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
16397 #define ETH_DMATDLAR_STL_Pos (0U)
16398 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
16399 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
16400
16401 /* Bit definition for Ethernet DMA Status Register */
16402 #define ETH_DMASR_TSTS_Pos (29U)
16403 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
16404 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
16405 #define ETH_DMASR_PMTS_Pos (28U)
16406 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
16407 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
16408 #define ETH_DMASR_MMCS_Pos (27U)
16409 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
16410 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
16411 #define ETH_DMASR_EBS_Pos (23U)
16412 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
16413 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
16414 /* combination with EBS[2:0] for GetFlagStatus function */
16415 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
16416 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
16417 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
16418 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
16419 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
16420 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
16421 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
16422 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
16423 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
16424 #define ETH_DMASR_TPS_Pos (20U)
16425 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
16426 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
16427 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
16428 #define ETH_DMASR_TPS_Fetching_Pos (20U)
16429 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
16430 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
16431 #define ETH_DMASR_TPS_Waiting_Pos (21U)
16432 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
16433 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
16434 #define ETH_DMASR_TPS_Reading_Pos (20U)
16435 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
16436 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
16437 #define ETH_DMASR_TPS_Suspended_Pos (21U)
16438 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
16439 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
16440 #define ETH_DMASR_TPS_Closing_Pos (20U)
16441 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
16442 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
16443 #define ETH_DMASR_RPS_Pos (17U)
16444 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
16445 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
16446 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
16447 #define ETH_DMASR_RPS_Fetching_Pos (17U)
16448 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
16449 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
16450 #define ETH_DMASR_RPS_Waiting_Pos (17U)
16451 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
16452 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
16453 #define ETH_DMASR_RPS_Suspended_Pos (19U)
16454 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
16455 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
16456 #define ETH_DMASR_RPS_Closing_Pos (17U)
16457 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
16458 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
16459 #define ETH_DMASR_RPS_Queuing_Pos (17U)
16460 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
16461 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
16462 #define ETH_DMASR_NIS_Pos (16U)
16463 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
16464 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
16465 #define ETH_DMASR_AIS_Pos (15U)
16466 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
16467 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
16468 #define ETH_DMASR_ERS_Pos (14U)
16469 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
16470 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
16471 #define ETH_DMASR_FBES_Pos (13U)
16472 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
16473 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
16474 #define ETH_DMASR_ETS_Pos (10U)
16475 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
16476 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
16477 #define ETH_DMASR_RWTS_Pos (9U)
16478 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
16479 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
16480 #define ETH_DMASR_RPSS_Pos (8U)
16481 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
16482 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
16483 #define ETH_DMASR_RBUS_Pos (7U)
16484 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
16485 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
16486 #define ETH_DMASR_RS_Pos (6U)
16487 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
16488 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
16489 #define ETH_DMASR_TUS_Pos (5U)
16490 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
16491 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
16492 #define ETH_DMASR_ROS_Pos (4U)
16493 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
16494 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
16495 #define ETH_DMASR_TJTS_Pos (3U)
16496 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
16497 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
16498 #define ETH_DMASR_TBUS_Pos (2U)
16499 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
16500 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
16501 #define ETH_DMASR_TPSS_Pos (1U)
16502 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
16503 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
16504 #define ETH_DMASR_TS_Pos (0U)
16505 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
16506 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
16507
16508 /* Bit definition for Ethernet DMA Operation Mode Register */
16509 #define ETH_DMAOMR_DTCEFD_Pos (26U)
16510 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
16511 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
16512 #define ETH_DMAOMR_RSF_Pos (25U)
16513 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
16514 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
16515 #define ETH_DMAOMR_DFRF_Pos (24U)
16516 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
16517 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
16518 #define ETH_DMAOMR_TSF_Pos (21U)
16519 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
16520 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
16521 #define ETH_DMAOMR_FTF_Pos (20U)
16522 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
16523 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
16524 #define ETH_DMAOMR_TTC_Pos (14U)
16525 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
16526 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
16527 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
16528 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
16529 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
16530 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
16531 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
16532 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
16533 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
16534 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
16535 #define ETH_DMAOMR_ST_Pos (13U)
16536 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
16537 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
16538 #define ETH_DMAOMR_FEF_Pos (7U)
16539 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
16540 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
16541 #define ETH_DMAOMR_FUGF_Pos (6U)
16542 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
16543 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
16544 #define ETH_DMAOMR_RTC_Pos (3U)
16545 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
16546 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
16547 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
16548 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
16549 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
16550 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
16551 #define ETH_DMAOMR_OSF_Pos (2U)
16552 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
16553 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
16554 #define ETH_DMAOMR_SR_Pos (1U)
16555 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
16556 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
16557
16558 /* Bit definition for Ethernet DMA Interrupt Enable Register */
16559 #define ETH_DMAIER_NISE_Pos (16U)
16560 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
16561 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
16562 #define ETH_DMAIER_AISE_Pos (15U)
16563 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
16564 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
16565 #define ETH_DMAIER_ERIE_Pos (14U)
16566 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
16567 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
16568 #define ETH_DMAIER_FBEIE_Pos (13U)
16569 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
16570 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
16571 #define ETH_DMAIER_ETIE_Pos (10U)
16572 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
16573 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
16574 #define ETH_DMAIER_RWTIE_Pos (9U)
16575 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
16576 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
16577 #define ETH_DMAIER_RPSIE_Pos (8U)
16578 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
16579 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
16580 #define ETH_DMAIER_RBUIE_Pos (7U)
16581 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
16582 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
16583 #define ETH_DMAIER_RIE_Pos (6U)
16584 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
16585 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
16586 #define ETH_DMAIER_TUIE_Pos (5U)
16587 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
16588 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
16589 #define ETH_DMAIER_ROIE_Pos (4U)
16590 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
16591 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
16592 #define ETH_DMAIER_TJTIE_Pos (3U)
16593 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
16594 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
16595 #define ETH_DMAIER_TBUIE_Pos (2U)
16596 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
16597 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
16598 #define ETH_DMAIER_TPSIE_Pos (1U)
16599 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
16600 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
16601 #define ETH_DMAIER_TIE_Pos (0U)
16602 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
16603 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
16604
16605 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
16606 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
16607 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
16608 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
16609 #define ETH_DMAMFBOCR_MFA_Pos (17U)
16610 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
16611 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
16612 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
16613 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
16614 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
16615 #define ETH_DMAMFBOCR_MFC_Pos (0U)
16616 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
16617 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
16618
16619 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
16620 #define ETH_DMACHTDR_HTDAP_Pos (0U)
16621 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
16622 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
16623
16624 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
16625 #define ETH_DMACHRDR_HRDAP_Pos (0U)
16626 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
16627 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
16628
16629 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
16630 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
16631 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
16632 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
16633
16634 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
16635 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
16636 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
16637 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
16638
16639 /******************************************************************************/
16640 /* */
16641 /* USB_OTG */
16642 /* */
16643 /******************************************************************************/
16644 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
16645 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
16646 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
16647 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
16648 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
16649 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
16650 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
16651 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
16652 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
16653 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
16654 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
16655 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
16656 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
16657 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
16658 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
16659 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
16660 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
16661 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
16662 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
16663 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
16664 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
16665 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
16666 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
16667 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
16668 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
16669 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
16670 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
16671 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
16672 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
16673 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
16674 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
16675 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
16676 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
16677 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
16678 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
16679 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
16680 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
16681 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
16682 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
16683 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
16684 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
16685 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
16686 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
16687 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
16688 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
16689 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
16690 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
16691 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
16692 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
16693 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
16694 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
16695 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
16696 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
16697 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
16698 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
16699
16700 /******************** Bit definition for USB_OTG_HCFG register ********************/
16701 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
16702 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
16703 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
16704 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
16705 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
16706 #define USB_OTG_HCFG_FSLSS_Pos (2U)
16707 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
16708 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
16709
16710 /******************** Bit definition for USB_OTG_DCFG register ********************/
16711 #define USB_OTG_DCFG_DSPD_Pos (0U)
16712 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
16713 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
16714 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
16715 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
16716 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
16717 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
16718 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
16719
16720 #define USB_OTG_DCFG_DAD_Pos (4U)
16721 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
16722 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
16723 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
16724 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
16725 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
16726 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
16727 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
16728 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
16729 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
16730
16731 #define USB_OTG_DCFG_PFIVL_Pos (11U)
16732 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
16733 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
16734 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
16735 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
16736
16737 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
16738 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
16739 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
16740 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
16741 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
16742
16743 /******************** Bit definition for USB_OTG_PCGCR register ********************/
16744 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
16745 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
16746 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
16747 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
16748 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
16749 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
16750 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
16751 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
16752 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
16753
16754 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
16755 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
16756 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
16757 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
16758 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
16759 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
16760 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
16761 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
16762 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
16763 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
16764 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
16765 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
16766 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
16767 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
16768 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
16769 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
16770 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
16771 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
16772 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
16773 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
16774 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
16775 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
16776
16777 /******************** Bit definition for USB_OTG_DCTL register ********************/
16778 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
16779 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
16780 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
16781 #define USB_OTG_DCTL_SDIS_Pos (1U)
16782 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
16783 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
16784 #define USB_OTG_DCTL_GINSTS_Pos (2U)
16785 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
16786 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
16787 #define USB_OTG_DCTL_GONSTS_Pos (3U)
16788 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
16789 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
16790
16791 #define USB_OTG_DCTL_TCTL_Pos (4U)
16792 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
16793 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
16794 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
16795 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
16796 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
16797 #define USB_OTG_DCTL_SGINAK_Pos (7U)
16798 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
16799 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
16800 #define USB_OTG_DCTL_CGINAK_Pos (8U)
16801 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
16802 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
16803 #define USB_OTG_DCTL_SGONAK_Pos (9U)
16804 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
16805 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
16806 #define USB_OTG_DCTL_CGONAK_Pos (10U)
16807 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
16808 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
16809 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
16810 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
16811 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
16812
16813 /******************** Bit definition for USB_OTG_HFIR register ********************/
16814 #define USB_OTG_HFIR_FRIVL_Pos (0U)
16815 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
16816 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
16817
16818 /******************** Bit definition for USB_OTG_HFNUM register ********************/
16819 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
16820 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
16821 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
16822 #define USB_OTG_HFNUM_FTREM_Pos (16U)
16823 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
16824 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
16825
16826 /******************** Bit definition for USB_OTG_DSTS register ********************/
16827 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
16828 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
16829 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
16830
16831 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
16832 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
16833 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
16834 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
16835 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
16836 #define USB_OTG_DSTS_EERR_Pos (3U)
16837 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
16838 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
16839 #define USB_OTG_DSTS_FNSOF_Pos (8U)
16840 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
16841 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
16842
16843 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
16844 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
16845 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
16846 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
16847 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
16848 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
16849 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
16850 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
16851 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
16852 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
16853 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
16854 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
16855 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
16856 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
16857 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
16858 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
16859 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
16860 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
16861 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
16862 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
16863 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
16864
16865 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
16866 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
16867 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
16868 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
16869 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
16870 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
16871 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
16872 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
16873 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
16874 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
16875 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
16876 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
16877 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
16878 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
16879 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
16880 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
16881 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
16882 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
16883 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
16884 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
16885 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
16886 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
16887 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
16888 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
16889 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
16890 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
16891 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
16892 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
16893 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
16894 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
16895 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
16896 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
16897 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
16898 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
16899 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
16900 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
16901 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
16902 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
16903 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
16904 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
16905 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
16906 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
16907 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
16908 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
16909 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
16910 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
16911 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
16912 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
16913 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
16914 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
16915 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
16916 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
16917 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
16918 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
16919 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
16920 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
16921 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
16922 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
16923 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
16924 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
16925 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
16926 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
16927
16928 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
16929 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
16930 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
16931 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
16932 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
16933 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
16934 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
16935 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
16936 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
16937 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
16938 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
16939 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
16940 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
16941 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
16942 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
16943 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
16944 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
16945 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
16946 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
16947 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
16948 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
16949 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
16950 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
16951 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
16952 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
16953 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
16954 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
16955 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
16956 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
16957 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
16958
16959 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
16960 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
16961 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
16962 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
16963 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
16964 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
16965 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
16966 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
16967 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
16968 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
16969 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
16970 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
16971 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
16972 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
16973 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
16974 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
16975 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
16976 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
16977 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
16978 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
16979 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
16980 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
16981 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
16982 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
16983 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
16984
16985 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
16986 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
16987 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
16988 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
16989 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
16990 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
16991 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
16992 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
16993 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
16994 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
16995 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
16996 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
16997 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
16998 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
16999 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
17000
17001 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
17002 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
17003 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
17004 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
17005 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
17006 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
17007 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
17008 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
17009 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
17010 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
17011 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
17012
17013 /******************** Bit definition for USB_OTG_HAINT register ********************/
17014 #define USB_OTG_HAINT_HAINT_Pos (0U)
17015 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
17016 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
17017
17018 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
17019 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
17020 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
17021 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
17022 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
17023 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
17024 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
17025 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
17026 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
17027 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
17028 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
17029 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
17030 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
17031 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
17032 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
17033 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
17034 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
17035 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
17036 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
17037 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
17038 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
17039 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
17040 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
17041 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
17042 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
17043
17044 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
17045 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
17046 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
17047 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
17048 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
17049 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
17050 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
17051 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
17052 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
17053 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
17054 #define USB_OTG_GINTSTS_SOF_Pos (3U)
17055 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
17056 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
17057 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
17058 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
17059 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
17060 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
17061 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
17062 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
17063 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
17064 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
17065 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
17066 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
17067 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
17068 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
17069 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
17070 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
17071 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
17072 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
17073 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
17074 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
17075 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
17076 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
17077 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
17078 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
17079 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
17080 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
17081 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
17082 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
17083 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
17084 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
17085 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
17086 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
17087 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
17088 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
17089 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
17090 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
17091 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
17092 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
17093 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
17094 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
17095 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
17096 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
17097 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
17098 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
17099 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
17100 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
17101 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
17102 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
17103 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
17104 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
17105 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
17106 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
17107 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
17108 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
17109 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
17110 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
17111 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
17112 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
17113 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
17114 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
17115 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
17116 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
17117 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
17118 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
17119 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
17120 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
17121 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
17122 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
17123 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
17124 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
17125 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
17126 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
17127 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
17128 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
17129
17130 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
17131 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
17132 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
17133 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
17134 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
17135 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
17136 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
17137 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
17138 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
17139 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
17140 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
17141 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
17142 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
17143 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
17144 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
17145 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
17146 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
17147 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
17148 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
17149 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
17150 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
17151 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
17152 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
17153 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
17154 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
17155 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
17156 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
17157 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
17158 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
17159 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
17160 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
17161 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
17162 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
17163 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
17164 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
17165 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
17166 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
17167 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
17168 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
17169 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
17170 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
17171 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
17172 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
17173 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
17174 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
17175 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
17176 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
17177 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
17178 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
17179 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
17180 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
17181 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
17182 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
17183 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
17184 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
17185 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
17186 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
17187 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
17188 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
17189 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
17190 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
17191 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
17192 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
17193 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
17194 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
17195 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
17196 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
17197 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
17198 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
17199 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
17200 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
17201 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
17202 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
17203 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
17204 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
17205 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
17206 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
17207 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
17208 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
17209 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
17210 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
17211 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
17212 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
17213 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
17214 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
17215
17216 /******************** Bit definition for USB_OTG_DAINT register ********************/
17217 #define USB_OTG_DAINT_IEPINT_Pos (0U)
17218 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
17219 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
17220 #define USB_OTG_DAINT_OEPINT_Pos (16U)
17221 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
17222 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
17223
17224 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
17225 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
17226 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
17227 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
17228
17229 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
17230 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
17231 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
17232 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
17233 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
17234 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
17235 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
17236 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
17237 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
17238 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
17239 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
17240 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
17241 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
17242
17243 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
17244 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
17245 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
17246 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
17247 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
17248 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
17249 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
17250
17251 /******************** Bit definition for OTG register ********************/
17252
17253 #define USB_OTG_CHNUM_Pos (0U)
17254 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
17255 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
17256 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
17257 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
17258 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
17259 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
17260 #define USB_OTG_BCNT_Pos (4U)
17261 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
17262 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
17263
17264 #define USB_OTG_DPID_Pos (15U)
17265 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
17266 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
17267 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
17268 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
17269
17270 #define USB_OTG_PKTSTS_Pos (17U)
17271 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
17272 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
17273 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
17274 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
17275 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
17276 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
17277
17278 #define USB_OTG_EPNUM_Pos (0U)
17279 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
17280 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
17281 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
17282 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
17283 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
17284 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
17285
17286 #define USB_OTG_FRMNUM_Pos (21U)
17287 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
17288 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
17289 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
17290 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
17291 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
17292 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
17293
17294 /******************** Bit definition for OTG register ********************/
17295
17296 #define USB_OTG_CHNUM_Pos (0U)
17297 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
17298 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
17299 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
17300 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
17301 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
17302 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
17303 #define USB_OTG_BCNT_Pos (4U)
17304 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
17305 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
17306
17307 #define USB_OTG_DPID_Pos (15U)
17308 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
17309 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
17310 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
17311 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
17312
17313 #define USB_OTG_PKTSTS_Pos (17U)
17314 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
17315 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
17316 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
17317 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
17318 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
17319 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
17320
17321 #define USB_OTG_EPNUM_Pos (0U)
17322 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
17323 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
17324 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
17325 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
17326 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
17327 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
17328
17329 #define USB_OTG_FRMNUM_Pos (21U)
17330 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
17331 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
17332 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
17333 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
17334 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
17335 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
17336
17337 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
17338 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
17339 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
17340 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
17341
17342 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
17343 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
17344 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
17345 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
17346
17347 /******************** Bit definition for OTG register ********************/
17348 #define USB_OTG_NPTXFSA_Pos (0U)
17349 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
17350 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
17351 #define USB_OTG_NPTXFD_Pos (16U)
17352 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
17353 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
17354 #define USB_OTG_TX0FSA_Pos (0U)
17355 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
17356 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
17357 #define USB_OTG_TX0FD_Pos (16U)
17358 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
17359 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
17360
17361 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
17362 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
17363 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
17364 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
17365
17366 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
17367 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
17368 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
17369 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
17370
17371 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
17372 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
17373 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
17374 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
17375 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
17376 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
17377 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
17378 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
17379 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
17380 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
17381 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
17382
17383 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
17384 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
17385 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
17386 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
17387 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
17388 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
17389 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
17390 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
17391 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
17392 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
17393
17394 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
17395 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
17396 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
17397 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
17398 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
17399 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
17400 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
17401
17402 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
17403 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
17404 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
17405 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
17406 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
17407 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
17408 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
17409 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
17410 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
17411 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
17412 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
17413 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
17414 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
17415 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
17416 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
17417
17418 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
17419 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
17420 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
17421 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
17422 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
17423 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
17424 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
17425 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
17426 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
17427 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
17428 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
17429 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
17430 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
17431 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
17432 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
17433
17434 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
17435 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
17436 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
17437 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
17438
17439 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
17440 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
17441 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
17442 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
17443 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
17444 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
17445 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
17446
17447 /******************** Bit definition for USB_OTG_GCCFG register ********************/
17448 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
17449 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
17450 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
17451 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
17452 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
17453 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
17454
17455 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
17456 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
17457 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1U << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
17458 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
17459 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
17460 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1U << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
17461 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
17462
17463 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
17464 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
17465 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
17466 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
17467 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
17468 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
17469 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
17470
17471 /******************** Bit definition for USB_OTG_CID register ********************/
17472 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
17473 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
17474 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
17475
17476 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
17477 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
17478 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
17479 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
17480 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
17481 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
17482 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
17483 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
17484 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
17485 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
17486 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
17487 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
17488 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
17489 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
17490 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
17491 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
17492 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
17493 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
17494 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
17495 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
17496 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
17497 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
17498 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
17499 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
17500 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
17501 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
17502 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
17503 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
17504 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
17505 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
17506 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
17507 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
17508 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
17509 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
17510 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
17511 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
17512 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
17513 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
17514 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
17515 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
17516 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
17517 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
17518 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
17519 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
17520 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
17521 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
17522
17523 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
17524 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
17525 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
17526 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
17527 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
17528 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
17529 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
17530 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
17531 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
17532 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
17533 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
17534 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
17535 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
17536 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
17537 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
17538 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
17539 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
17540 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
17541 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
17542 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
17543 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
17544 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
17545 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
17546 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
17547 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
17548 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
17549 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
17550 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
17551
17552 /******************** Bit definition for USB_OTG_HPRT register ********************/
17553 #define USB_OTG_HPRT_PCSTS_Pos (0U)
17554 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
17555 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
17556 #define USB_OTG_HPRT_PCDET_Pos (1U)
17557 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
17558 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
17559 #define USB_OTG_HPRT_PENA_Pos (2U)
17560 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
17561 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
17562 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
17563 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
17564 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
17565 #define USB_OTG_HPRT_POCA_Pos (4U)
17566 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
17567 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
17568 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
17569 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
17570 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
17571 #define USB_OTG_HPRT_PRES_Pos (6U)
17572 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
17573 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
17574 #define USB_OTG_HPRT_PSUSP_Pos (7U)
17575 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
17576 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
17577 #define USB_OTG_HPRT_PRST_Pos (8U)
17578 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
17579 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
17580
17581 #define USB_OTG_HPRT_PLSTS_Pos (10U)
17582 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
17583 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
17584 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
17585 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
17586 #define USB_OTG_HPRT_PPWR_Pos (12U)
17587 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
17588 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
17589
17590 #define USB_OTG_HPRT_PTCTL_Pos (13U)
17591 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
17592 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
17593 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
17594 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
17595 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
17596 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
17597
17598 #define USB_OTG_HPRT_PSPD_Pos (17U)
17599 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
17600 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
17601 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
17602 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
17603
17604 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
17605 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
17606 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
17607 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
17608 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
17609 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
17610 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
17611 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
17612 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
17613 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
17614 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
17615 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
17616 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
17617 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
17618 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
17619 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
17620 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
17621 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
17622 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
17623 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
17624 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
17625 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
17626 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
17627 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
17628 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
17629 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
17630 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
17631 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
17632 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
17633 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
17634 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
17635 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
17636 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
17637 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
17638
17639 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
17640 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
17641 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
17642 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
17643 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
17644 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
17645 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
17646
17647 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
17648 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
17649 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
17650 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
17651 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
17652 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
17653 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
17654 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
17655 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
17656 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
17657 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
17658 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
17659 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
17660
17661 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
17662 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
17663 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
17664 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
17665 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
17666 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
17667 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
17668 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
17669
17670 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
17671 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
17672 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
17673 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
17674 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
17675 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
17676 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
17677 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
17678 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
17679 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
17680 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
17681 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
17682 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
17683 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
17684 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
17685 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
17686 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
17687 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
17688 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
17689 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
17690 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
17691 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
17692 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
17693 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
17694 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
17695
17696 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
17697 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
17698 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
17699 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
17700
17701 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
17702 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
17703 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
17704 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
17705 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
17706 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
17707 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
17708 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
17709 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
17710 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
17711 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
17712 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
17713 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
17714
17715 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
17716 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
17717 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
17718 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
17719 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
17720
17721 #define USB_OTG_HCCHAR_MC_Pos (20U)
17722 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
17723 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
17724 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
17725 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
17726
17727 #define USB_OTG_HCCHAR_DAD_Pos (22U)
17728 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
17729 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
17730 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
17731 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
17732 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
17733 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
17734 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
17735 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
17736 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
17737 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
17738 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
17739 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
17740 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
17741 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
17742 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
17743 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
17744 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
17745 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
17746
17747 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
17748
17749 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
17750 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
17751 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
17752 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
17753 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
17754 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
17755 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
17756 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
17757 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
17758 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
17759
17760 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
17761 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
17762 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
17763 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
17764 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
17765 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
17766 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
17767 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
17768 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
17769 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
17770
17771 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
17772 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
17773 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
17774 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
17775 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
17776 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
17777 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
17778 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
17779 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
17780 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
17781 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
17782
17783 /******************** Bit definition for USB_OTG_HCINT register ********************/
17784 #define USB_OTG_HCINT_XFRC_Pos (0U)
17785 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
17786 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
17787 #define USB_OTG_HCINT_CHH_Pos (1U)
17788 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
17789 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
17790 #define USB_OTG_HCINT_AHBERR_Pos (2U)
17791 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
17792 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
17793 #define USB_OTG_HCINT_STALL_Pos (3U)
17794 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
17795 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
17796 #define USB_OTG_HCINT_NAK_Pos (4U)
17797 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
17798 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
17799 #define USB_OTG_HCINT_ACK_Pos (5U)
17800 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
17801 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
17802 #define USB_OTG_HCINT_NYET_Pos (6U)
17803 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
17804 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
17805 #define USB_OTG_HCINT_TXERR_Pos (7U)
17806 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
17807 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
17808 #define USB_OTG_HCINT_BBERR_Pos (8U)
17809 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
17810 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
17811 #define USB_OTG_HCINT_FRMOR_Pos (9U)
17812 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
17813 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
17814 #define USB_OTG_HCINT_DTERR_Pos (10U)
17815 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
17816 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
17817
17818 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
17819 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
17820 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
17821 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
17822 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
17823 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
17824 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
17825 #define USB_OTG_DIEPINT_TOC_Pos (3U)
17826 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
17827 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
17828 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
17829 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
17830 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
17831 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
17832 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
17833 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
17834 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
17835 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
17836 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
17837 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
17838 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
17839 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
17840 #define USB_OTG_DIEPINT_BNA_Pos (9U)
17841 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
17842 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
17843 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
17844 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
17845 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
17846 #define USB_OTG_DIEPINT_BERR_Pos (12U)
17847 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
17848 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
17849 #define USB_OTG_DIEPINT_NAK_Pos (13U)
17850 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
17851 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
17852
17853 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
17854 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
17855 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
17856 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
17857 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
17858 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
17859 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
17860 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
17861 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
17862 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
17863 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
17864 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
17865 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
17866 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
17867 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
17868 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
17869 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
17870 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
17871 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
17872 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
17873 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
17874 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
17875 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
17876 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
17877 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
17878 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
17879 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
17880 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
17881 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
17882 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
17883 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
17884 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
17885 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
17886 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
17887
17888 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
17889
17890 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
17891 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17892 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
17893 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
17894 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17895 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
17896 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
17897 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
17898 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
17899 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
17900 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
17901 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17902 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
17903 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
17904 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17905 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
17906 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
17907 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
17908 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
17909 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
17910 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
17911 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
17912 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
17913 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
17914
17915 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
17916 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
17917 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
17918 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
17919
17920 /******************** Bit definition for USB_OTG_HCDMA register ********************/
17921 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
17922 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
17923 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
17924
17925 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
17926 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
17927 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
17928 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
17929
17930 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
17931 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
17932 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
17933 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
17934 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
17935 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
17936 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
17937
17938 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
17939 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
17940 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
17941 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
17942 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
17943 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
17944 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
17945 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
17946 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
17947 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
17948 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
17949 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
17950 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
17951 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
17952 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
17953 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
17954 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
17955 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
17956 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
17957 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
17958 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
17959 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
17960 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
17961 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
17962 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
17963 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
17964 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
17965 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
17966 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
17967 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
17968 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
17969 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
17970 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
17971 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
17972 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
17973 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
17974 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
17975 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
17976 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
17977
17978 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
17979 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
17980 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
17981 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
17982 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
17983 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
17984 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
17985 #define USB_OTG_DOEPINT_STUP_Pos (3U)
17986 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
17987 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
17988 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
17989 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
17990 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
17991 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
17992 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
17993 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
17994 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
17995 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
17996 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
17997 #define USB_OTG_DOEPINT_NYET_Pos (14U)
17998 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
17999 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
18000
18001 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
18002 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
18003 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
18004 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
18005 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
18006 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
18007 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
18008
18009 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
18010 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
18011 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
18012 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
18013 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
18014
18015 /******************** Bit definition for PCGCCTL register ********************/
18016 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
18017 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
18018 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
18019 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
18020 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
18021 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
18022 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
18023 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
18024 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
18025
18026
18027 /******************************************************************************/
18028 /* */
18029 /* JPEG Encoder/Decoder */
18030 /* */
18031 /******************************************************************************/
18032 /******************** Bit definition for CONFR0 register ********************/
18033 #define JPEG_CONFR0_START_Pos (0U)
18034 #define JPEG_CONFR0_START_Msk (0x1U << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
18035 #define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
18036
18037 /******************** Bit definition for CONFR1 register *******************/
18038 #define JPEG_CONFR1_NF_Pos (0U)
18039 #define JPEG_CONFR1_NF_Msk (0x3U << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
18040 #define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
18041 #define JPEG_CONFR1_NF_0 (0x1U << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
18042 #define JPEG_CONFR1_NF_1 (0x2U << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
18043 #define JPEG_CONFR1_RE_Pos (2U)
18044 #define JPEG_CONFR1_RE_Msk (0x1U << JPEG_CONFR1_RE_Pos) /*!< 0x00000004 */
18045 #define JPEG_CONFR1_RE JPEG_CONFR1_RE_Msk /*!<Restart maker Enable */
18046 #define JPEG_CONFR1_DE_Pos (3U)
18047 #define JPEG_CONFR1_DE_Msk (0x1U << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
18048 #define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
18049 #define JPEG_CONFR1_COLORSPACE_Pos (4U)
18050 #define JPEG_CONFR1_COLORSPACE_Msk (0x3U << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
18051 #define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
18052 #define JPEG_CONFR1_COLORSPACE_0 (0x1U << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
18053 #define JPEG_CONFR1_COLORSPACE_1 (0x2U << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
18054 #define JPEG_CONFR1_NS_Pos (6U)
18055 #define JPEG_CONFR1_NS_Msk (0x3U << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
18056 #define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
18057 #define JPEG_CONFR1_NS_0 (0x1U << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
18058 #define JPEG_CONFR1_NS_1 (0x2U << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
18059 #define JPEG_CONFR1_HDR_Pos (8U)
18060 #define JPEG_CONFR1_HDR_Msk (0x1U << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
18061 #define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
18062 #define JPEG_CONFR1_YSIZE_Pos (16U)
18063 #define JPEG_CONFR1_YSIZE_Msk (0xFFFFU << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
18064 #define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
18065
18066 /******************** Bit definition for CONFR2 register *******************/
18067 #define JPEG_CONFR2_NMCU_Pos (0U)
18068 #define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFU << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
18069 #define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
18070
18071 /******************** Bit definition for CONFR3 register *******************/
18072 #define JPEG_CONFR3_NRST_Pos (0U)
18073 #define JPEG_CONFR3_NRST_Msk (0xFFFFU << JPEG_CONFR3_NRST_Pos) /*!< 0x0000FFFF */
18074 #define JPEG_CONFR3_NRST JPEG_CONFR3_NRST_Msk /*!<Number of MCU between two restart makers minus 1 */
18075 #define JPEG_CONFR3_XSIZE_Pos (16U)
18076 #define JPEG_CONFR3_XSIZE_Msk (0xFFFFU << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
18077 #define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
18078
18079 /******************** Bit definition for CONFR4 register *******************/
18080 #define JPEG_CONFR4_HD_Pos (0U)
18081 #define JPEG_CONFR4_HD_Msk (0x1U << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
18082 #define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
18083 #define JPEG_CONFR4_HA_Pos (1U)
18084 #define JPEG_CONFR4_HA_Msk (0x1U << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
18085 #define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
18086 #define JPEG_CONFR4_QT_Pos (2U)
18087 #define JPEG_CONFR4_QT_Msk (0x3U << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
18088 #define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
18089 #define JPEG_CONFR4_QT_0 (0x1U << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
18090 #define JPEG_CONFR4_QT_1 (0x2U << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
18091 #define JPEG_CONFR4_NB_Pos (4U)
18092 #define JPEG_CONFR4_NB_Msk (0xFU << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
18093 #define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
18094 #define JPEG_CONFR4_NB_0 (0x1U << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
18095 #define JPEG_CONFR4_NB_1 (0x2U << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
18096 #define JPEG_CONFR4_NB_2 (0x4U << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
18097 #define JPEG_CONFR4_NB_3 (0x8U << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
18098 #define JPEG_CONFR4_VSF_Pos (8U)
18099 #define JPEG_CONFR4_VSF_Msk (0xFU << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
18100 #define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
18101 #define JPEG_CONFR4_VSF_0 (0x1U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
18102 #define JPEG_CONFR4_VSF_1 (0x2U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
18103 #define JPEG_CONFR4_VSF_2 (0x4U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
18104 #define JPEG_CONFR4_VSF_3 (0x8U << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
18105 #define JPEG_CONFR4_HSF_Pos (12U)
18106 #define JPEG_CONFR4_HSF_Msk (0xFU << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
18107 #define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
18108 #define JPEG_CONFR4_HSF_0 (0x1U << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
18109 #define JPEG_CONFR4_HSF_1 (0x2U << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
18110 #define JPEG_CONFR4_HSF_2 (0x4U << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
18111 #define JPEG_CONFR4_HSF_3 (0x8U << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
18112
18113 /******************** Bit definition for CONFR5 register *******************/
18114 #define JPEG_CONFR5_HD_Pos (0U)
18115 #define JPEG_CONFR5_HD_Msk (0x1U << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
18116 #define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
18117 #define JPEG_CONFR5_HA_Pos (1U)
18118 #define JPEG_CONFR5_HA_Msk (0x1U << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
18119 #define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
18120 #define JPEG_CONFR5_QT_Pos (2U)
18121 #define JPEG_CONFR5_QT_Msk (0x3U << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
18122 #define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
18123 #define JPEG_CONFR5_QT_0 (0x1U << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
18124 #define JPEG_CONFR5_QT_1 (0x2U << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
18125 #define JPEG_CONFR5_NB_Pos (4U)
18126 #define JPEG_CONFR5_NB_Msk (0xFU << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
18127 #define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
18128 #define JPEG_CONFR5_NB_0 (0x1U << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
18129 #define JPEG_CONFR5_NB_1 (0x2U << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
18130 #define JPEG_CONFR5_NB_2 (0x4U << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
18131 #define JPEG_CONFR5_NB_3 (0x8U << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
18132 #define JPEG_CONFR5_VSF_Pos (8U)
18133 #define JPEG_CONFR5_VSF_Msk (0xFU << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
18134 #define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
18135 #define JPEG_CONFR5_VSF_0 (0x1U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
18136 #define JPEG_CONFR5_VSF_1 (0x2U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
18137 #define JPEG_CONFR5_VSF_2 (0x4U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
18138 #define JPEG_CONFR5_VSF_3 (0x8U << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
18139 #define JPEG_CONFR5_HSF_Pos (12U)
18140 #define JPEG_CONFR5_HSF_Msk (0xFU << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
18141 #define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
18142 #define JPEG_CONFR5_HSF_0 (0x1U << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
18143 #define JPEG_CONFR5_HSF_1 (0x2U << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
18144 #define JPEG_CONFR5_HSF_2 (0x4U << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
18145 #define JPEG_CONFR5_HSF_3 (0x8U << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
18146
18147 /******************** Bit definition for CONFR6 register *******************/
18148 #define JPEG_CONFR6_HD_Pos (0U)
18149 #define JPEG_CONFR6_HD_Msk (0x1U << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
18150 #define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
18151 #define JPEG_CONFR6_HA_Pos (1U)
18152 #define JPEG_CONFR6_HA_Msk (0x1U << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
18153 #define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
18154 #define JPEG_CONFR6_QT_Pos (2U)
18155 #define JPEG_CONFR6_QT_Msk (0x3U << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
18156 #define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
18157 #define JPEG_CONFR6_QT_0 (0x1U << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
18158 #define JPEG_CONFR6_QT_1 (0x2U << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
18159 #define JPEG_CONFR6_NB_Pos (4U)
18160 #define JPEG_CONFR6_NB_Msk (0xFU << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
18161 #define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
18162 #define JPEG_CONFR6_NB_0 (0x1U << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
18163 #define JPEG_CONFR6_NB_1 (0x2U << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
18164 #define JPEG_CONFR6_NB_2 (0x4U << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
18165 #define JPEG_CONFR6_NB_3 (0x8U << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
18166 #define JPEG_CONFR6_VSF_Pos (8U)
18167 #define JPEG_CONFR6_VSF_Msk (0xFU << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
18168 #define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
18169 #define JPEG_CONFR6_VSF_0 (0x1U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
18170 #define JPEG_CONFR6_VSF_1 (0x2U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
18171 #define JPEG_CONFR6_VSF_2 (0x4U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
18172 #define JPEG_CONFR6_VSF_3 (0x8U << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
18173 #define JPEG_CONFR6_HSF_Pos (12U)
18174 #define JPEG_CONFR6_HSF_Msk (0xFU << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
18175 #define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
18176 #define JPEG_CONFR6_HSF_0 (0x1U << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
18177 #define JPEG_CONFR6_HSF_1 (0x2U << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
18178 #define JPEG_CONFR6_HSF_2 (0x4U << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
18179 #define JPEG_CONFR6_HSF_3 (0x8U << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
18180
18181 /******************** Bit definition for CONFR7 register *******************/
18182 #define JPEG_CONFR7_HD_Pos (0U)
18183 #define JPEG_CONFR7_HD_Msk (0x1U << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
18184 #define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
18185 #define JPEG_CONFR7_HA_Pos (1U)
18186 #define JPEG_CONFR7_HA_Msk (0x1U << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
18187 #define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
18188 #define JPEG_CONFR7_QT_Pos (2U)
18189 #define JPEG_CONFR7_QT_Msk (0x3U << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
18190 #define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
18191 #define JPEG_CONFR7_QT_0 (0x1U << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
18192 #define JPEG_CONFR7_QT_1 (0x2U << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
18193 #define JPEG_CONFR7_NB_Pos (4U)
18194 #define JPEG_CONFR7_NB_Msk (0xFU << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
18195 #define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
18196 #define JPEG_CONFR7_NB_0 (0x1U << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
18197 #define JPEG_CONFR7_NB_1 (0x2U << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
18198 #define JPEG_CONFR7_NB_2 (0x4U << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
18199 #define JPEG_CONFR7_NB_3 (0x8U << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
18200 #define JPEG_CONFR7_VSF_Pos (8U)
18201 #define JPEG_CONFR7_VSF_Msk (0xFU << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
18202 #define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
18203 #define JPEG_CONFR7_VSF_0 (0x1U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
18204 #define JPEG_CONFR7_VSF_1 (0x2U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
18205 #define JPEG_CONFR7_VSF_2 (0x4U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
18206 #define JPEG_CONFR7_VSF_3 (0x8U << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
18207 #define JPEG_CONFR7_HSF_Pos (12U)
18208 #define JPEG_CONFR7_HSF_Msk (0xFU << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
18209 #define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
18210 #define JPEG_CONFR7_HSF_0 (0x1U << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
18211 #define JPEG_CONFR7_HSF_1 (0x2U << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
18212 #define JPEG_CONFR7_HSF_2 (0x4U << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
18213 #define JPEG_CONFR7_HSF_3 (0x8U << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
18214
18215 /******************** Bit definition for CR register *******************/
18216 #define JPEG_CR_JCEN_Pos (0U)
18217 #define JPEG_CR_JCEN_Msk (0x1U << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
18218 #define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
18219 #define JPEG_CR_IFTIE_Pos (1U)
18220 #define JPEG_CR_IFTIE_Msk (0x1U << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
18221 #define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
18222 #define JPEG_CR_IFNFIE_Pos (2U)
18223 #define JPEG_CR_IFNFIE_Msk (0x1U << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
18224 #define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
18225 #define JPEG_CR_OFTIE_Pos (3U)
18226 #define JPEG_CR_OFTIE_Msk (0x1U << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
18227 #define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
18228 #define JPEG_CR_OFNEIE_Pos (4U)
18229 #define JPEG_CR_OFNEIE_Msk (0x1U << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
18230 #define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
18231 #define JPEG_CR_EOCIE_Pos (5U)
18232 #define JPEG_CR_EOCIE_Msk (0x1U << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
18233 #define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
18234 #define JPEG_CR_HPDIE_Pos (6U)
18235 #define JPEG_CR_HPDIE_Msk (0x1U << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
18236 #define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
18237 #define JPEG_CR_IDMAEN_Pos (11U)
18238 #define JPEG_CR_IDMAEN_Msk (0x1U << JPEG_CR_IDMAEN_Pos) /*!< 0x00000800 */
18239 #define JPEG_CR_IDMAEN JPEG_CR_IDMAEN_Msk /*!<Enable the DMA request generation for the input FIFO */
18240 #define JPEG_CR_ODMAEN_Pos (12U)
18241 #define JPEG_CR_ODMAEN_Msk (0x1U << JPEG_CR_ODMAEN_Pos) /*!< 0x00001000 */
18242 #define JPEG_CR_ODMAEN JPEG_CR_ODMAEN_Msk /*!<Enable the DMA request generation for the output FIFO */
18243 #define JPEG_CR_IFF_Pos (13U)
18244 #define JPEG_CR_IFF_Msk (0x1U << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
18245 #define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
18246 #define JPEG_CR_OFF_Pos (14U)
18247 #define JPEG_CR_OFF_Msk (0x1U << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
18248 #define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
18249
18250 /******************** Bit definition for SR register *******************/
18251 #define JPEG_SR_IFTF_Pos (1U)
18252 #define JPEG_SR_IFTF_Msk (0x1U << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
18253 #define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
18254 #define JPEG_SR_IFNFF_Pos (2U)
18255 #define JPEG_SR_IFNFF_Msk (0x1U << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
18256 #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
18257 #define JPEG_SR_OFTF_Pos (3U)
18258 #define JPEG_SR_OFTF_Msk (0x1U << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
18259 #define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
18260 #define JPEG_SR_OFNEF_Pos (4U)
18261 #define JPEG_SR_OFNEF_Msk (0x1U << JPEG_SR_OFNEF_Pos) /*!< 0x00000001 */
18262 #define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
18263 #define JPEG_SR_EOCF_Pos (5U)
18264 #define JPEG_SR_EOCF_Msk (0x1U << JPEG_SR_EOCF_Pos) /*!< 0x00000002 */
18265 #define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
18266 #define JPEG_SR_HPDF_Pos (6U)
18267 #define JPEG_SR_HPDF_Msk (0x1U << JPEG_SR_HPDF_Pos) /*!< 0x00000004 */
18268 #define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
18269 #define JPEG_SR_COF_Pos (7U)
18270 #define JPEG_SR_COF_Msk (0x1U << JPEG_SR_COF_Pos) /*!< 0x00000008 */
18271 #define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
18272
18273 /******************** Bit definition for CFR register *******************/
18274 #define JPEG_CFR_CEOCF_Pos (5U)
18275 #define JPEG_CFR_CEOCF_Msk (0x1U << JPEG_CFR_CEOCF_Pos) /*!< 0x00000020 */
18276 #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
18277 #define JPEG_CFR_CHPDF_Pos (6U)
18278 #define JPEG_CFR_CHPDF_Msk (0x1U << JPEG_CFR_CHPDF_Pos) /*!< 0x00000040 */
18279 #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
18280
18281 /******************** Bit definition for DIR register ********************/
18282 #define JPEG_DIR_DATAIN_Pos (0U)
18283 #define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFU << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
18284 #define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
18285
18286 /******************** Bit definition for DOR register ********************/
18287 #define JPEG_DOR_DATAOUT_Pos (0U)
18288 #define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFU << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
18289 #define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
18290
18291 /******************************************************************************/
18292 /* */
18293 /* MDIOS */
18294 /* */
18295 /******************************************************************************/
18296 /******************** Bit definition for MDIOS_CR register *******************/
18297 #define MDIOS_CR_EN_Pos (0U)
18298 #define MDIOS_CR_EN_Msk (0x1U << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
18299 #define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!<Peripheral enable */
18300 #define MDIOS_CR_WRIE_Pos (1U)
18301 #define MDIOS_CR_WRIE_Msk (0x1U << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
18302 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!<Register write interrupt enable */
18303 #define MDIOS_CR_RDIE_Pos (2U)
18304 #define MDIOS_CR_RDIE_Msk (0x1U << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
18305 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!<Register Read Interrupt Enable */
18306 #define MDIOS_CR_EIE_Pos (3U)
18307 #define MDIOS_CR_EIE_Msk (0x1U << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
18308 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!<Error interrupt enable */
18309 #define MDIOS_CR_DPC_Pos (7U)
18310 #define MDIOS_CR_DPC_Msk (0x1U << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
18311 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!<Disable Preamble Check */
18312 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
18313 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FU << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
18314 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!<PORT_ADDRESS[4:0] bits */
18315 #define MDIOS_CR_PORT_ADDRESS_0 (0x01U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
18316 #define MDIOS_CR_PORT_ADDRESS_1 (0x02U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
18317 #define MDIOS_CR_PORT_ADDRESS_2 (0x04U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
18318 #define MDIOS_CR_PORT_ADDRESS_3 (0x08U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
18319 #define MDIOS_CR_PORT_ADDRESS_4 (0x10U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
18320
18321 /******************** Bit definition for MDIOS_WRFR register *******************/
18322 #define MDIOS_WRFR_WRF_Pos (0U)
18323 #define MDIOS_WRFR_WRF_Msk (0xFFFFFFFFU << MDIOS_WRFR_WRF_Pos) /*!< 0xFFFFFFFF */
18324 #define MDIOS_WRFR_WRF MDIOS_WRFR_WRF_Msk /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
18325
18326 /******************** Bit definition for MDIOS_CWRFR register *******************/
18327 #define MDIOS_CWRFR_CWRF_Pos (0U)
18328 #define MDIOS_CWRFR_CWRF_Msk (0xFFFFFFFFU << MDIOS_CWRFR_CWRF_Pos) /*!< 0xFFFFFFFF */
18329 #define MDIOS_CWRFR_CWRF MDIOS_CWRFR_CWRF_Msk /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
18330
18331 /******************** Bit definition for MDIOS_RDFR register *******************/
18332 #define MDIOS_RDFR_RDF_Pos (0U)
18333 #define MDIOS_RDFR_RDF_Msk (0xFFFFFFFFU << MDIOS_RDFR_RDF_Pos) /*!< 0xFFFFFFFF */
18334 #define MDIOS_RDFR_RDF MDIOS_RDFR_RDF_Msk /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
18335
18336 /******************** Bit definition for MDIOS_CRDFR register *******************/
18337 #define MDIOS_CRDFR_CRDF_Pos (0U)
18338 #define MDIOS_CRDFR_CRDF_Msk (0xFFFFFFFFU << MDIOS_CRDFR_CRDF_Pos) /*!< 0xFFFFFFFF */
18339 #define MDIOS_CRDFR_CRDF MDIOS_CRDFR_CRDF_Msk /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
18340
18341 /******************** Bit definition for MDIOS_SR register *******************/
18342 #define MDIOS_SR_PERF_Pos (0U)
18343 #define MDIOS_SR_PERF_Msk (0x1U << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
18344 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< Preamble error flag */
18345 #define MDIOS_SR_SERF_Pos (1U)
18346 #define MDIOS_SR_SERF_Msk (0x1U << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
18347 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< Start error flag */
18348 #define MDIOS_SR_TERF_Pos (2U)
18349 #define MDIOS_SR_TERF_Msk (0x1U << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
18350 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< Turnaround error flag */
18351
18352 /******************** Bit definition for MDIOS_CLRFR register *******************/
18353 #define MDIOS_CLRFR_CPERF_Pos (0U)
18354 #define MDIOS_CLRFR_CPERF_Msk (0x1U << MDIOS_CLRFR_CPERF_Pos) /*!< 0x00000001 */
18355 #define MDIOS_CLRFR_CPERF MDIOS_CLRFR_CPERF_Msk /*!< Clear the preamble error flag */
18356 #define MDIOS_CLRFR_CSERF_Pos (1U)
18357 #define MDIOS_CLRFR_CSERF_Msk (0x1U << MDIOS_CLRFR_CSERF_Pos) /*!< 0x00000002 */
18358 #define MDIOS_CLRFR_CSERF MDIOS_CLRFR_CSERF_Msk /*!< Clear the start error flag */
18359 #define MDIOS_CLRFR_CTERF_Pos (2U)
18360 #define MDIOS_CLRFR_CTERF_Msk (0x1U << MDIOS_CLRFR_CTERF_Pos) /*!< 0x00000004 */
18361 #define MDIOS_CLRFR_CTERF MDIOS_CLRFR_CTERF_Msk /*!< Clear the turnaround error flag */
18362
18363 /******************************************************************************/
18364 /* */
18365 /* Display Serial Interface (DSI) */
18366 /* */
18367 /******************************************************************************/
18368 /******************* Bit definition for DSI_VR register *****************/
18369 #define DSI_VR_Pos (1U)
18370 #define DSI_VR_Msk (0x18999815U << DSI_VR_Pos) /*!< 0x3133302A */
18371 #define DSI_VR DSI_VR_Msk /*!< DSI Host Version */
18372
18373 /******************* Bit definition for DSI_CR register *****************/
18374 #define DSI_CR_EN_Pos (0U)
18375 #define DSI_CR_EN_Msk (0x1U << DSI_CR_EN_Pos) /*!< 0x00000001 */
18376 #define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */
18377
18378 /******************* Bit definition for DSI_CCR register ****************/
18379 #define DSI_CCR_TXECKDIV_Pos (0U)
18380 #define DSI_CCR_TXECKDIV_Msk (0xFFU << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */
18381 #define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */
18382 #define DSI_CCR_TXECKDIV0_Pos (0U)
18383 #define DSI_CCR_TXECKDIV0_Msk (0x1U << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */
18384 #define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
18385 #define DSI_CCR_TXECKDIV1_Pos (1U)
18386 #define DSI_CCR_TXECKDIV1_Msk (0x1U << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */
18387 #define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
18388 #define DSI_CCR_TXECKDIV2_Pos (2U)
18389 #define DSI_CCR_TXECKDIV2_Msk (0x1U << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */
18390 #define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
18391 #define DSI_CCR_TXECKDIV3_Pos (3U)
18392 #define DSI_CCR_TXECKDIV3_Msk (0x1U << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */
18393 #define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
18394 #define DSI_CCR_TXECKDIV4_Pos (4U)
18395 #define DSI_CCR_TXECKDIV4_Msk (0x1U << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */
18396 #define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
18397 #define DSI_CCR_TXECKDIV5_Pos (5U)
18398 #define DSI_CCR_TXECKDIV5_Msk (0x1U << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */
18399 #define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
18400 #define DSI_CCR_TXECKDIV6_Pos (6U)
18401 #define DSI_CCR_TXECKDIV6_Msk (0x1U << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */
18402 #define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
18403 #define DSI_CCR_TXECKDIV7_Pos (7U)
18404 #define DSI_CCR_TXECKDIV7_Msk (0x1U << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */
18405 #define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
18406
18407 #define DSI_CCR_TOCKDIV_Pos (8U)
18408 #define DSI_CCR_TOCKDIV_Msk (0xFFU << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */
18409 #define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */
18410 #define DSI_CCR_TOCKDIV0_Pos (8U)
18411 #define DSI_CCR_TOCKDIV0_Msk (0x1U << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */
18412 #define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
18413 #define DSI_CCR_TOCKDIV1_Pos (9U)
18414 #define DSI_CCR_TOCKDIV1_Msk (0x1U << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */
18415 #define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
18416 #define DSI_CCR_TOCKDIV2_Pos (10U)
18417 #define DSI_CCR_TOCKDIV2_Msk (0x1U << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */
18418 #define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
18419 #define DSI_CCR_TOCKDIV3_Pos (11U)
18420 #define DSI_CCR_TOCKDIV3_Msk (0x1U << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */
18421 #define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
18422 #define DSI_CCR_TOCKDIV4_Pos (12U)
18423 #define DSI_CCR_TOCKDIV4_Msk (0x1U << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */
18424 #define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
18425 #define DSI_CCR_TOCKDIV5_Pos (13U)
18426 #define DSI_CCR_TOCKDIV5_Msk (0x1U << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */
18427 #define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
18428 #define DSI_CCR_TOCKDIV6_Pos (14U)
18429 #define DSI_CCR_TOCKDIV6_Msk (0x1U << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */
18430 #define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
18431 #define DSI_CCR_TOCKDIV7_Pos (15U)
18432 #define DSI_CCR_TOCKDIV7_Msk (0x1U << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */
18433 #define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
18434
18435 /******************* Bit definition for DSI_LVCIDR register *************/
18436 #define DSI_LVCIDR_VCID_Pos (0U)
18437 #define DSI_LVCIDR_VCID_Msk (0x3U << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */
18438 #define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */
18439 #define DSI_LVCIDR_VCID0_Pos (0U)
18440 #define DSI_LVCIDR_VCID0_Msk (0x1U << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */
18441 #define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
18442 #define DSI_LVCIDR_VCID1_Pos (1U)
18443 #define DSI_LVCIDR_VCID1_Msk (0x1U << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */
18444 #define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
18445
18446 /******************* Bit definition for DSI_LCOLCR register *************/
18447 #define DSI_LCOLCR_COLC_Pos (0U)
18448 #define DSI_LCOLCR_COLC_Msk (0xFU << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */
18449 #define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */
18450 #define DSI_LCOLCR_COLC0_Pos (0U)
18451 #define DSI_LCOLCR_COLC0_Msk (0x1U << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */
18452 #define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
18453 #define DSI_LCOLCR_COLC1_Pos (5U)
18454 #define DSI_LCOLCR_COLC1_Msk (0x1U << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */
18455 #define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
18456 #define DSI_LCOLCR_COLC2_Pos (6U)
18457 #define DSI_LCOLCR_COLC2_Msk (0x1U << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */
18458 #define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
18459 #define DSI_LCOLCR_COLC3_Pos (7U)
18460 #define DSI_LCOLCR_COLC3_Msk (0x1U << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */
18461 #define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
18462
18463 #define DSI_LCOLCR_LPE_Pos (8U)
18464 #define DSI_LCOLCR_LPE_Msk (0x1U << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
18465 #define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
18466
18467 /******************* Bit definition for DSI_LPCR register ***************/
18468 #define DSI_LPCR_DEP_Pos (0U)
18469 #define DSI_LPCR_DEP_Msk (0x1U << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */
18470 #define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */
18471 #define DSI_LPCR_VSP_Pos (1U)
18472 #define DSI_LPCR_VSP_Msk (0x1U << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */
18473 #define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */
18474 #define DSI_LPCR_HSP_Pos (2U)
18475 #define DSI_LPCR_HSP_Msk (0x1U << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */
18476 #define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */
18477
18478 /******************* Bit definition for DSI_LPMCR register **************/
18479 #define DSI_LPMCR_VLPSIZE_Pos (0U)
18480 #define DSI_LPMCR_VLPSIZE_Msk (0xFFU << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */
18481 #define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
18482 #define DSI_LPMCR_VLPSIZE0_Pos (0U)
18483 #define DSI_LPMCR_VLPSIZE0_Msk (0x1U << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */
18484 #define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
18485 #define DSI_LPMCR_VLPSIZE1_Pos (1U)
18486 #define DSI_LPMCR_VLPSIZE1_Msk (0x1U << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */
18487 #define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
18488 #define DSI_LPMCR_VLPSIZE2_Pos (2U)
18489 #define DSI_LPMCR_VLPSIZE2_Msk (0x1U << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */
18490 #define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
18491 #define DSI_LPMCR_VLPSIZE3_Pos (3U)
18492 #define DSI_LPMCR_VLPSIZE3_Msk (0x1U << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */
18493 #define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
18494 #define DSI_LPMCR_VLPSIZE4_Pos (4U)
18495 #define DSI_LPMCR_VLPSIZE4_Msk (0x1U << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */
18496 #define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
18497 #define DSI_LPMCR_VLPSIZE5_Pos (5U)
18498 #define DSI_LPMCR_VLPSIZE5_Msk (0x1U << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */
18499 #define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
18500 #define DSI_LPMCR_VLPSIZE6_Pos (6U)
18501 #define DSI_LPMCR_VLPSIZE6_Msk (0x1U << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */
18502 #define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
18503 #define DSI_LPMCR_VLPSIZE7_Pos (7U)
18504 #define DSI_LPMCR_VLPSIZE7_Msk (0x1U << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */
18505 #define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
18506
18507 #define DSI_LPMCR_LPSIZE_Pos (16U)
18508 #define DSI_LPMCR_LPSIZE_Msk (0xFFU << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */
18509 #define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */
18510 #define DSI_LPMCR_LPSIZE0_Pos (16U)
18511 #define DSI_LPMCR_LPSIZE0_Msk (0x1U << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */
18512 #define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
18513 #define DSI_LPMCR_LPSIZE1_Pos (17U)
18514 #define DSI_LPMCR_LPSIZE1_Msk (0x1U << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */
18515 #define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
18516 #define DSI_LPMCR_LPSIZE2_Pos (18U)
18517 #define DSI_LPMCR_LPSIZE2_Msk (0x1U << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */
18518 #define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
18519 #define DSI_LPMCR_LPSIZE3_Pos (19U)
18520 #define DSI_LPMCR_LPSIZE3_Msk (0x1U << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */
18521 #define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
18522 #define DSI_LPMCR_LPSIZE4_Pos (20U)
18523 #define DSI_LPMCR_LPSIZE4_Msk (0x1U << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */
18524 #define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
18525 #define DSI_LPMCR_LPSIZE5_Pos (21U)
18526 #define DSI_LPMCR_LPSIZE5_Msk (0x1U << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */
18527 #define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
18528 #define DSI_LPMCR_LPSIZE6_Pos (22U)
18529 #define DSI_LPMCR_LPSIZE6_Msk (0x1U << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */
18530 #define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
18531 #define DSI_LPMCR_LPSIZE7_Pos (23U)
18532 #define DSI_LPMCR_LPSIZE7_Msk (0x1U << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */
18533 #define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
18534
18535 /******************* Bit definition for DSI_PCR register ****************/
18536 #define DSI_PCR_ETTXE_Pos (0U)
18537 #define DSI_PCR_ETTXE_Msk (0x1U << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */
18538 #define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */
18539 #define DSI_PCR_ETRXE_Pos (1U)
18540 #define DSI_PCR_ETRXE_Msk (0x1U << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */
18541 #define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */
18542 #define DSI_PCR_BTAE_Pos (2U)
18543 #define DSI_PCR_BTAE_Msk (0x1U << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */
18544 #define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */
18545 #define DSI_PCR_ECCRXE_Pos (3U)
18546 #define DSI_PCR_ECCRXE_Msk (0x1U << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */
18547 #define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */
18548 #define DSI_PCR_CRCRXE_Pos (4U)
18549 #define DSI_PCR_CRCRXE_Msk (0x1U << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */
18550 #define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */
18551
18552 /******************* Bit definition for DSI_GVCIDR register *************/
18553 #define DSI_GVCIDR_VCID_Pos (0U)
18554 #define DSI_GVCIDR_VCID_Msk (0x3U << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */
18555 #define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */
18556 #define DSI_GVCIDR_VCID0_Pos (0U)
18557 #define DSI_GVCIDR_VCID0_Msk (0x1U << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */
18558 #define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
18559 #define DSI_GVCIDR_VCID1_Pos (1U)
18560 #define DSI_GVCIDR_VCID1_Msk (0x1U << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */
18561 #define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
18562
18563 /******************* Bit definition for DSI_MCR register ****************/
18564 #define DSI_MCR_CMDM_Pos (0U)
18565 #define DSI_MCR_CMDM_Msk (0x1U << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */
18566 #define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */
18567
18568 /******************* Bit definition for DSI_VMCR register ***************/
18569 #define DSI_VMCR_VMT_Pos (0U)
18570 #define DSI_VMCR_VMT_Msk (0x3U << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */
18571 #define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */
18572 #define DSI_VMCR_VMT0_Pos (0U)
18573 #define DSI_VMCR_VMT0_Msk (0x1U << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */
18574 #define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
18575 #define DSI_VMCR_VMT1_Pos (1U)
18576 #define DSI_VMCR_VMT1_Msk (0x1U << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */
18577 #define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
18578
18579 #define DSI_VMCR_LPVSAE_Pos (8U)
18580 #define DSI_VMCR_LPVSAE_Msk (0x1U << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */
18581 #define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */
18582 #define DSI_VMCR_LPVBPE_Pos (9U)
18583 #define DSI_VMCR_LPVBPE_Msk (0x1U << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */
18584 #define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */
18585 #define DSI_VMCR_LPVFPE_Pos (10U)
18586 #define DSI_VMCR_LPVFPE_Msk (0x1U << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */
18587 #define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
18588 #define DSI_VMCR_LPVAE_Pos (11U)
18589 #define DSI_VMCR_LPVAE_Msk (0x1U << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */
18590 #define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */
18591 #define DSI_VMCR_LPHBPE_Pos (12U)
18592 #define DSI_VMCR_LPHBPE_Msk (0x1U << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */
18593 #define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */
18594 #define DSI_VMCR_LPHFPE_Pos (13U)
18595 #define DSI_VMCR_LPHFPE_Msk (0x1U << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */
18596 #define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */
18597 #define DSI_VMCR_FBTAAE_Pos (14U)
18598 #define DSI_VMCR_FBTAAE_Msk (0x1U << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */
18599 #define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */
18600 #define DSI_VMCR_LPCE_Pos (15U)
18601 #define DSI_VMCR_LPCE_Msk (0x1U << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */
18602 #define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */
18603 #define DSI_VMCR_PGE_Pos (16U)
18604 #define DSI_VMCR_PGE_Msk (0x1U << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */
18605 #define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */
18606 #define DSI_VMCR_PGM_Pos (20U)
18607 #define DSI_VMCR_PGM_Msk (0x1U << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */
18608 #define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */
18609 #define DSI_VMCR_PGO_Pos (24U)
18610 #define DSI_VMCR_PGO_Msk (0x1U << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */
18611 #define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */
18612
18613 /******************* Bit definition for DSI_VPCR register ***************/
18614 #define DSI_VPCR_VPSIZE_Pos (0U)
18615 #define DSI_VPCR_VPSIZE_Msk (0x3FFFU << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */
18616 #define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */
18617 #define DSI_VPCR_VPSIZE0_Pos (0U)
18618 #define DSI_VPCR_VPSIZE0_Msk (0x1U << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */
18619 #define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
18620 #define DSI_VPCR_VPSIZE1_Pos (1U)
18621 #define DSI_VPCR_VPSIZE1_Msk (0x1U << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */
18622 #define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
18623 #define DSI_VPCR_VPSIZE2_Pos (2U)
18624 #define DSI_VPCR_VPSIZE2_Msk (0x1U << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */
18625 #define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
18626 #define DSI_VPCR_VPSIZE3_Pos (3U)
18627 #define DSI_VPCR_VPSIZE3_Msk (0x1U << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */
18628 #define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
18629 #define DSI_VPCR_VPSIZE4_Pos (4U)
18630 #define DSI_VPCR_VPSIZE4_Msk (0x1U << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */
18631 #define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
18632 #define DSI_VPCR_VPSIZE5_Pos (5U)
18633 #define DSI_VPCR_VPSIZE5_Msk (0x1U << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */
18634 #define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
18635 #define DSI_VPCR_VPSIZE6_Pos (6U)
18636 #define DSI_VPCR_VPSIZE6_Msk (0x1U << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */
18637 #define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
18638 #define DSI_VPCR_VPSIZE7_Pos (7U)
18639 #define DSI_VPCR_VPSIZE7_Msk (0x1U << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */
18640 #define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
18641 #define DSI_VPCR_VPSIZE8_Pos (8U)
18642 #define DSI_VPCR_VPSIZE8_Msk (0x1U << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */
18643 #define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
18644 #define DSI_VPCR_VPSIZE9_Pos (9U)
18645 #define DSI_VPCR_VPSIZE9_Msk (0x1U << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */
18646 #define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
18647 #define DSI_VPCR_VPSIZE10_Pos (10U)
18648 #define DSI_VPCR_VPSIZE10_Msk (0x1U << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */
18649 #define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
18650 #define DSI_VPCR_VPSIZE11_Pos (11U)
18651 #define DSI_VPCR_VPSIZE11_Msk (0x1U << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */
18652 #define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
18653 #define DSI_VPCR_VPSIZE12_Pos (12U)
18654 #define DSI_VPCR_VPSIZE12_Msk (0x1U << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */
18655 #define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
18656 #define DSI_VPCR_VPSIZE13_Pos (13U)
18657 #define DSI_VPCR_VPSIZE13_Msk (0x1U << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */
18658 #define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
18659
18660 /******************* Bit definition for DSI_VCCR register ***************/
18661 #define DSI_VCCR_NUMC_Pos (0U)
18662 #define DSI_VCCR_NUMC_Msk (0x1FFFU << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */
18663 #define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */
18664 #define DSI_VCCR_NUMC0_Pos (0U)
18665 #define DSI_VCCR_NUMC0_Msk (0x1U << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */
18666 #define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
18667 #define DSI_VCCR_NUMC1_Pos (1U)
18668 #define DSI_VCCR_NUMC1_Msk (0x1U << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */
18669 #define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
18670 #define DSI_VCCR_NUMC2_Pos (2U)
18671 #define DSI_VCCR_NUMC2_Msk (0x1U << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */
18672 #define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
18673 #define DSI_VCCR_NUMC3_Pos (3U)
18674 #define DSI_VCCR_NUMC3_Msk (0x1U << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */
18675 #define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
18676 #define DSI_VCCR_NUMC4_Pos (4U)
18677 #define DSI_VCCR_NUMC4_Msk (0x1U << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */
18678 #define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
18679 #define DSI_VCCR_NUMC5_Pos (5U)
18680 #define DSI_VCCR_NUMC5_Msk (0x1U << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */
18681 #define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
18682 #define DSI_VCCR_NUMC6_Pos (6U)
18683 #define DSI_VCCR_NUMC6_Msk (0x1U << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */
18684 #define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
18685 #define DSI_VCCR_NUMC7_Pos (7U)
18686 #define DSI_VCCR_NUMC7_Msk (0x1U << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */
18687 #define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
18688 #define DSI_VCCR_NUMC8_Pos (8U)
18689 #define DSI_VCCR_NUMC8_Msk (0x1U << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */
18690 #define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
18691 #define DSI_VCCR_NUMC9_Pos (9U)
18692 #define DSI_VCCR_NUMC9_Msk (0x1U << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */
18693 #define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
18694 #define DSI_VCCR_NUMC10_Pos (10U)
18695 #define DSI_VCCR_NUMC10_Msk (0x1U << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */
18696 #define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
18697 #define DSI_VCCR_NUMC11_Pos (11U)
18698 #define DSI_VCCR_NUMC11_Msk (0x1U << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */
18699 #define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
18700 #define DSI_VCCR_NUMC12_Pos (12U)
18701 #define DSI_VCCR_NUMC12_Msk (0x1U << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */
18702 #define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
18703
18704 /******************* Bit definition for DSI_VNPCR register **************/
18705 #define DSI_VNPCR_NPSIZE_Pos (0U)
18706 #define DSI_VNPCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */
18707 #define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */
18708 #define DSI_VNPCR_NPSIZE0_Pos (0U)
18709 #define DSI_VNPCR_NPSIZE0_Msk (0x1U << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */
18710 #define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
18711 #define DSI_VNPCR_NPSIZE1_Pos (1U)
18712 #define DSI_VNPCR_NPSIZE1_Msk (0x1U << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */
18713 #define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
18714 #define DSI_VNPCR_NPSIZE2_Pos (2U)
18715 #define DSI_VNPCR_NPSIZE2_Msk (0x1U << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */
18716 #define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
18717 #define DSI_VNPCR_NPSIZE3_Pos (3U)
18718 #define DSI_VNPCR_NPSIZE3_Msk (0x1U << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */
18719 #define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
18720 #define DSI_VNPCR_NPSIZE4_Pos (4U)
18721 #define DSI_VNPCR_NPSIZE4_Msk (0x1U << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */
18722 #define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
18723 #define DSI_VNPCR_NPSIZE5_Pos (5U)
18724 #define DSI_VNPCR_NPSIZE5_Msk (0x1U << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */
18725 #define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
18726 #define DSI_VNPCR_NPSIZE6_Pos (6U)
18727 #define DSI_VNPCR_NPSIZE6_Msk (0x1U << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */
18728 #define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
18729 #define DSI_VNPCR_NPSIZE7_Pos (7U)
18730 #define DSI_VNPCR_NPSIZE7_Msk (0x1U << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */
18731 #define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
18732 #define DSI_VNPCR_NPSIZE8_Pos (8U)
18733 #define DSI_VNPCR_NPSIZE8_Msk (0x1U << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */
18734 #define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
18735 #define DSI_VNPCR_NPSIZE9_Pos (9U)
18736 #define DSI_VNPCR_NPSIZE9_Msk (0x1U << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */
18737 #define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
18738 #define DSI_VNPCR_NPSIZE10_Pos (10U)
18739 #define DSI_VNPCR_NPSIZE10_Msk (0x1U << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */
18740 #define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
18741 #define DSI_VNPCR_NPSIZE11_Pos (11U)
18742 #define DSI_VNPCR_NPSIZE11_Msk (0x1U << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */
18743 #define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
18744 #define DSI_VNPCR_NPSIZE12_Pos (12U)
18745 #define DSI_VNPCR_NPSIZE12_Msk (0x1U << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */
18746 #define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
18747
18748 /******************* Bit definition for DSI_VHSACR register *************/
18749 #define DSI_VHSACR_HSA_Pos (0U)
18750 #define DSI_VHSACR_HSA_Msk (0xFFFU << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */
18751 #define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */
18752 #define DSI_VHSACR_HSA0_Pos (0U)
18753 #define DSI_VHSACR_HSA0_Msk (0x1U << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */
18754 #define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
18755 #define DSI_VHSACR_HSA1_Pos (1U)
18756 #define DSI_VHSACR_HSA1_Msk (0x1U << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */
18757 #define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
18758 #define DSI_VHSACR_HSA2_Pos (2U)
18759 #define DSI_VHSACR_HSA2_Msk (0x1U << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */
18760 #define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
18761 #define DSI_VHSACR_HSA3_Pos (3U)
18762 #define DSI_VHSACR_HSA3_Msk (0x1U << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */
18763 #define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
18764 #define DSI_VHSACR_HSA4_Pos (4U)
18765 #define DSI_VHSACR_HSA4_Msk (0x1U << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */
18766 #define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
18767 #define DSI_VHSACR_HSA5_Pos (5U)
18768 #define DSI_VHSACR_HSA5_Msk (0x1U << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */
18769 #define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
18770 #define DSI_VHSACR_HSA6_Pos (6U)
18771 #define DSI_VHSACR_HSA6_Msk (0x1U << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */
18772 #define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
18773 #define DSI_VHSACR_HSA7_Pos (7U)
18774 #define DSI_VHSACR_HSA7_Msk (0x1U << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */
18775 #define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
18776 #define DSI_VHSACR_HSA8_Pos (8U)
18777 #define DSI_VHSACR_HSA8_Msk (0x1U << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */
18778 #define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
18779 #define DSI_VHSACR_HSA9_Pos (9U)
18780 #define DSI_VHSACR_HSA9_Msk (0x1U << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */
18781 #define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
18782 #define DSI_VHSACR_HSA10_Pos (10U)
18783 #define DSI_VHSACR_HSA10_Msk (0x1U << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */
18784 #define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
18785 #define DSI_VHSACR_HSA11_Pos (11U)
18786 #define DSI_VHSACR_HSA11_Msk (0x1U << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */
18787 #define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
18788
18789 /******************* Bit definition for DSI_VHBPCR register *************/
18790 #define DSI_VHBPCR_HBP_Pos (0U)
18791 #define DSI_VHBPCR_HBP_Msk (0xFFFU << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */
18792 #define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
18793 #define DSI_VHBPCR_HBP0_Pos (0U)
18794 #define DSI_VHBPCR_HBP0_Msk (0x1U << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */
18795 #define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
18796 #define DSI_VHBPCR_HBP1_Pos (1U)
18797 #define DSI_VHBPCR_HBP1_Msk (0x1U << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */
18798 #define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
18799 #define DSI_VHBPCR_HBP2_Pos (2U)
18800 #define DSI_VHBPCR_HBP2_Msk (0x1U << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */
18801 #define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
18802 #define DSI_VHBPCR_HBP3_Pos (3U)
18803 #define DSI_VHBPCR_HBP3_Msk (0x1U << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */
18804 #define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
18805 #define DSI_VHBPCR_HBP4_Pos (4U)
18806 #define DSI_VHBPCR_HBP4_Msk (0x1U << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */
18807 #define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
18808 #define DSI_VHBPCR_HBP5_Pos (5U)
18809 #define DSI_VHBPCR_HBP5_Msk (0x1U << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */
18810 #define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
18811 #define DSI_VHBPCR_HBP6_Pos (6U)
18812 #define DSI_VHBPCR_HBP6_Msk (0x1U << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */
18813 #define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
18814 #define DSI_VHBPCR_HBP7_Pos (7U)
18815 #define DSI_VHBPCR_HBP7_Msk (0x1U << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */
18816 #define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
18817 #define DSI_VHBPCR_HBP8_Pos (8U)
18818 #define DSI_VHBPCR_HBP8_Msk (0x1U << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */
18819 #define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
18820 #define DSI_VHBPCR_HBP9_Pos (9U)
18821 #define DSI_VHBPCR_HBP9_Msk (0x1U << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */
18822 #define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
18823 #define DSI_VHBPCR_HBP10_Pos (10U)
18824 #define DSI_VHBPCR_HBP10_Msk (0x1U << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */
18825 #define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
18826 #define DSI_VHBPCR_HBP11_Pos (11U)
18827 #define DSI_VHBPCR_HBP11_Msk (0x1U << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */
18828 #define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
18829
18830 /******************* Bit definition for DSI_VLCR register ***************/
18831 #define DSI_VLCR_HLINE_Pos (0U)
18832 #define DSI_VLCR_HLINE_Msk (0x7FFFU << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */
18833 #define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */
18834 #define DSI_VLCR_HLINE0_Pos (0U)
18835 #define DSI_VLCR_HLINE0_Msk (0x1U << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */
18836 #define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
18837 #define DSI_VLCR_HLINE1_Pos (1U)
18838 #define DSI_VLCR_HLINE1_Msk (0x1U << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */
18839 #define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
18840 #define DSI_VLCR_HLINE2_Pos (2U)
18841 #define DSI_VLCR_HLINE2_Msk (0x1U << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */
18842 #define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
18843 #define DSI_VLCR_HLINE3_Pos (3U)
18844 #define DSI_VLCR_HLINE3_Msk (0x1U << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */
18845 #define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
18846 #define DSI_VLCR_HLINE4_Pos (4U)
18847 #define DSI_VLCR_HLINE4_Msk (0x1U << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */
18848 #define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
18849 #define DSI_VLCR_HLINE5_Pos (5U)
18850 #define DSI_VLCR_HLINE5_Msk (0x1U << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */
18851 #define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
18852 #define DSI_VLCR_HLINE6_Pos (6U)
18853 #define DSI_VLCR_HLINE6_Msk (0x1U << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */
18854 #define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
18855 #define DSI_VLCR_HLINE7_Pos (7U)
18856 #define DSI_VLCR_HLINE7_Msk (0x1U << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */
18857 #define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
18858 #define DSI_VLCR_HLINE8_Pos (8U)
18859 #define DSI_VLCR_HLINE8_Msk (0x1U << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */
18860 #define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
18861 #define DSI_VLCR_HLINE9_Pos (9U)
18862 #define DSI_VLCR_HLINE9_Msk (0x1U << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */
18863 #define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
18864 #define DSI_VLCR_HLINE10_Pos (10U)
18865 #define DSI_VLCR_HLINE10_Msk (0x1U << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */
18866 #define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
18867 #define DSI_VLCR_HLINE11_Pos (11U)
18868 #define DSI_VLCR_HLINE11_Msk (0x1U << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */
18869 #define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
18870 #define DSI_VLCR_HLINE12_Pos (12U)
18871 #define DSI_VLCR_HLINE12_Msk (0x1U << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */
18872 #define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
18873 #define DSI_VLCR_HLINE13_Pos (13U)
18874 #define DSI_VLCR_HLINE13_Msk (0x1U << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */
18875 #define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
18876 #define DSI_VLCR_HLINE14_Pos (14U)
18877 #define DSI_VLCR_HLINE14_Msk (0x1U << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */
18878 #define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
18879
18880 /******************* Bit definition for DSI_VVSACR register *************/
18881 #define DSI_VVSACR_VSA_Pos (0U)
18882 #define DSI_VVSACR_VSA_Msk (0x3FFU << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */
18883 #define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */
18884 #define DSI_VVSACR_VSA0_Pos (0U)
18885 #define DSI_VVSACR_VSA0_Msk (0x1U << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */
18886 #define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
18887 #define DSI_VVSACR_VSA1_Pos (1U)
18888 #define DSI_VVSACR_VSA1_Msk (0x1U << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */
18889 #define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
18890 #define DSI_VVSACR_VSA2_Pos (2U)
18891 #define DSI_VVSACR_VSA2_Msk (0x1U << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */
18892 #define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
18893 #define DSI_VVSACR_VSA3_Pos (3U)
18894 #define DSI_VVSACR_VSA3_Msk (0x1U << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */
18895 #define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
18896 #define DSI_VVSACR_VSA4_Pos (4U)
18897 #define DSI_VVSACR_VSA4_Msk (0x1U << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */
18898 #define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
18899 #define DSI_VVSACR_VSA5_Pos (5U)
18900 #define DSI_VVSACR_VSA5_Msk (0x1U << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */
18901 #define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
18902 #define DSI_VVSACR_VSA6_Pos (6U)
18903 #define DSI_VVSACR_VSA6_Msk (0x1U << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */
18904 #define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
18905 #define DSI_VVSACR_VSA7_Pos (7U)
18906 #define DSI_VVSACR_VSA7_Msk (0x1U << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */
18907 #define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
18908 #define DSI_VVSACR_VSA8_Pos (8U)
18909 #define DSI_VVSACR_VSA8_Msk (0x1U << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */
18910 #define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
18911 #define DSI_VVSACR_VSA9_Pos (9U)
18912 #define DSI_VVSACR_VSA9_Msk (0x1U << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */
18913 #define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
18914
18915 /******************* Bit definition for DSI_VVBPCR register *************/
18916 #define DSI_VVBPCR_VBP_Pos (0U)
18917 #define DSI_VVBPCR_VBP_Msk (0x3FFU << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */
18918 #define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */
18919 #define DSI_VVBPCR_VBP0_Pos (0U)
18920 #define DSI_VVBPCR_VBP0_Msk (0x1U << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */
18921 #define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
18922 #define DSI_VVBPCR_VBP1_Pos (1U)
18923 #define DSI_VVBPCR_VBP1_Msk (0x1U << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */
18924 #define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
18925 #define DSI_VVBPCR_VBP2_Pos (2U)
18926 #define DSI_VVBPCR_VBP2_Msk (0x1U << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */
18927 #define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
18928 #define DSI_VVBPCR_VBP3_Pos (3U)
18929 #define DSI_VVBPCR_VBP3_Msk (0x1U << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */
18930 #define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
18931 #define DSI_VVBPCR_VBP4_Pos (4U)
18932 #define DSI_VVBPCR_VBP4_Msk (0x1U << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */
18933 #define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
18934 #define DSI_VVBPCR_VBP5_Pos (5U)
18935 #define DSI_VVBPCR_VBP5_Msk (0x1U << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */
18936 #define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
18937 #define DSI_VVBPCR_VBP6_Pos (6U)
18938 #define DSI_VVBPCR_VBP6_Msk (0x1U << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */
18939 #define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
18940 #define DSI_VVBPCR_VBP7_Pos (7U)
18941 #define DSI_VVBPCR_VBP7_Msk (0x1U << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */
18942 #define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
18943 #define DSI_VVBPCR_VBP8_Pos (8U)
18944 #define DSI_VVBPCR_VBP8_Msk (0x1U << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */
18945 #define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
18946 #define DSI_VVBPCR_VBP9_Pos (9U)
18947 #define DSI_VVBPCR_VBP9_Msk (0x1U << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */
18948 #define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
18949
18950 /******************* Bit definition for DSI_VVFPCR register *************/
18951 #define DSI_VVFPCR_VFP_Pos (0U)
18952 #define DSI_VVFPCR_VFP_Msk (0x3FFU << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */
18953 #define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */
18954 #define DSI_VVFPCR_VFP0_Pos (0U)
18955 #define DSI_VVFPCR_VFP0_Msk (0x1U << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */
18956 #define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
18957 #define DSI_VVFPCR_VFP1_Pos (1U)
18958 #define DSI_VVFPCR_VFP1_Msk (0x1U << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */
18959 #define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
18960 #define DSI_VVFPCR_VFP2_Pos (2U)
18961 #define DSI_VVFPCR_VFP2_Msk (0x1U << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */
18962 #define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
18963 #define DSI_VVFPCR_VFP3_Pos (3U)
18964 #define DSI_VVFPCR_VFP3_Msk (0x1U << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */
18965 #define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
18966 #define DSI_VVFPCR_VFP4_Pos (4U)
18967 #define DSI_VVFPCR_VFP4_Msk (0x1U << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */
18968 #define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
18969 #define DSI_VVFPCR_VFP5_Pos (5U)
18970 #define DSI_VVFPCR_VFP5_Msk (0x1U << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */
18971 #define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
18972 #define DSI_VVFPCR_VFP6_Pos (6U)
18973 #define DSI_VVFPCR_VFP6_Msk (0x1U << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */
18974 #define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
18975 #define DSI_VVFPCR_VFP7_Pos (7U)
18976 #define DSI_VVFPCR_VFP7_Msk (0x1U << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */
18977 #define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
18978 #define DSI_VVFPCR_VFP8_Pos (8U)
18979 #define DSI_VVFPCR_VFP8_Msk (0x1U << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */
18980 #define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
18981 #define DSI_VVFPCR_VFP9_Pos (9U)
18982 #define DSI_VVFPCR_VFP9_Msk (0x1U << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */
18983 #define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
18984
18985 /******************* Bit definition for DSI_VVACR register **************/
18986 #define DSI_VVACR_VA_Pos (0U)
18987 #define DSI_VVACR_VA_Msk (0x3FFFU << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */
18988 #define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */
18989 #define DSI_VVACR_VA0_Pos (0U)
18990 #define DSI_VVACR_VA0_Msk (0x1U << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */
18991 #define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
18992 #define DSI_VVACR_VA1_Pos (1U)
18993 #define DSI_VVACR_VA1_Msk (0x1U << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */
18994 #define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
18995 #define DSI_VVACR_VA2_Pos (2U)
18996 #define DSI_VVACR_VA2_Msk (0x1U << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */
18997 #define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
18998 #define DSI_VVACR_VA3_Pos (3U)
18999 #define DSI_VVACR_VA3_Msk (0x1U << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */
19000 #define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
19001 #define DSI_VVACR_VA4_Pos (4U)
19002 #define DSI_VVACR_VA4_Msk (0x1U << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */
19003 #define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
19004 #define DSI_VVACR_VA5_Pos (5U)
19005 #define DSI_VVACR_VA5_Msk (0x1U << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */
19006 #define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
19007 #define DSI_VVACR_VA6_Pos (6U)
19008 #define DSI_VVACR_VA6_Msk (0x1U << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */
19009 #define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
19010 #define DSI_VVACR_VA7_Pos (7U)
19011 #define DSI_VVACR_VA7_Msk (0x1U << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */
19012 #define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
19013 #define DSI_VVACR_VA8_Pos (8U)
19014 #define DSI_VVACR_VA8_Msk (0x1U << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */
19015 #define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
19016 #define DSI_VVACR_VA9_Pos (9U)
19017 #define DSI_VVACR_VA9_Msk (0x1U << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */
19018 #define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
19019 #define DSI_VVACR_VA10_Pos (10U)
19020 #define DSI_VVACR_VA10_Msk (0x1U << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */
19021 #define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
19022 #define DSI_VVACR_VA11_Pos (11U)
19023 #define DSI_VVACR_VA11_Msk (0x1U << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */
19024 #define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
19025 #define DSI_VVACR_VA12_Pos (12U)
19026 #define DSI_VVACR_VA12_Msk (0x1U << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */
19027 #define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
19028 #define DSI_VVACR_VA13_Pos (13U)
19029 #define DSI_VVACR_VA13_Msk (0x1U << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */
19030 #define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
19031
19032 /******************* Bit definition for DSI_LCCR register ***************/
19033 #define DSI_LCCR_CMDSIZE_Pos (0U)
19034 #define DSI_LCCR_CMDSIZE_Msk (0xFFFFU << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */
19035 #define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */
19036 #define DSI_LCCR_CMDSIZE0_Pos (0U)
19037 #define DSI_LCCR_CMDSIZE0_Msk (0x1U << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */
19038 #define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
19039 #define DSI_LCCR_CMDSIZE1_Pos (1U)
19040 #define DSI_LCCR_CMDSIZE1_Msk (0x1U << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */
19041 #define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
19042 #define DSI_LCCR_CMDSIZE2_Pos (2U)
19043 #define DSI_LCCR_CMDSIZE2_Msk (0x1U << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */
19044 #define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
19045 #define DSI_LCCR_CMDSIZE3_Pos (3U)
19046 #define DSI_LCCR_CMDSIZE3_Msk (0x1U << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */
19047 #define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
19048 #define DSI_LCCR_CMDSIZE4_Pos (4U)
19049 #define DSI_LCCR_CMDSIZE4_Msk (0x1U << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */
19050 #define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
19051 #define DSI_LCCR_CMDSIZE5_Pos (5U)
19052 #define DSI_LCCR_CMDSIZE5_Msk (0x1U << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */
19053 #define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
19054 #define DSI_LCCR_CMDSIZE6_Pos (6U)
19055 #define DSI_LCCR_CMDSIZE6_Msk (0x1U << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */
19056 #define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
19057 #define DSI_LCCR_CMDSIZE7_Pos (7U)
19058 #define DSI_LCCR_CMDSIZE7_Msk (0x1U << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */
19059 #define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
19060 #define DSI_LCCR_CMDSIZE8_Pos (8U)
19061 #define DSI_LCCR_CMDSIZE8_Msk (0x1U << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */
19062 #define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
19063 #define DSI_LCCR_CMDSIZE9_Pos (9U)
19064 #define DSI_LCCR_CMDSIZE9_Msk (0x1U << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */
19065 #define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
19066 #define DSI_LCCR_CMDSIZE10_Pos (10U)
19067 #define DSI_LCCR_CMDSIZE10_Msk (0x1U << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */
19068 #define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
19069 #define DSI_LCCR_CMDSIZE11_Pos (11U)
19070 #define DSI_LCCR_CMDSIZE11_Msk (0x1U << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */
19071 #define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
19072 #define DSI_LCCR_CMDSIZE12_Pos (12U)
19073 #define DSI_LCCR_CMDSIZE12_Msk (0x1U << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */
19074 #define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
19075 #define DSI_LCCR_CMDSIZE13_Pos (13U)
19076 #define DSI_LCCR_CMDSIZE13_Msk (0x1U << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */
19077 #define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
19078 #define DSI_LCCR_CMDSIZE14_Pos (14U)
19079 #define DSI_LCCR_CMDSIZE14_Msk (0x1U << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */
19080 #define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
19081 #define DSI_LCCR_CMDSIZE15_Pos (15U)
19082 #define DSI_LCCR_CMDSIZE15_Msk (0x1U << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */
19083 #define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
19084
19085 /******************* Bit definition for DSI_CMCR register ***************/
19086 #define DSI_CMCR_TEARE_Pos (0U)
19087 #define DSI_CMCR_TEARE_Msk (0x1U << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */
19088 #define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */
19089 #define DSI_CMCR_ARE_Pos (1U)
19090 #define DSI_CMCR_ARE_Msk (0x1U << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */
19091 #define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */
19092 #define DSI_CMCR_GSW0TX_Pos (8U)
19093 #define DSI_CMCR_GSW0TX_Msk (0x1U << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */
19094 #define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */
19095 #define DSI_CMCR_GSW1TX_Pos (9U)
19096 #define DSI_CMCR_GSW1TX_Msk (0x1U << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */
19097 #define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */
19098 #define DSI_CMCR_GSW2TX_Pos (10U)
19099 #define DSI_CMCR_GSW2TX_Msk (0x1U << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */
19100 #define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */
19101 #define DSI_CMCR_GSR0TX_Pos (11U)
19102 #define DSI_CMCR_GSR0TX_Msk (0x1U << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */
19103 #define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */
19104 #define DSI_CMCR_GSR1TX_Pos (12U)
19105 #define DSI_CMCR_GSR1TX_Msk (0x1U << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */
19106 #define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */
19107 #define DSI_CMCR_GSR2TX_Pos (13U)
19108 #define DSI_CMCR_GSR2TX_Msk (0x1U << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */
19109 #define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */
19110 #define DSI_CMCR_GLWTX_Pos (14U)
19111 #define DSI_CMCR_GLWTX_Msk (0x1U << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */
19112 #define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */
19113 #define DSI_CMCR_DSW0TX_Pos (16U)
19114 #define DSI_CMCR_DSW0TX_Msk (0x1U << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */
19115 #define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */
19116 #define DSI_CMCR_DSW1TX_Pos (17U)
19117 #define DSI_CMCR_DSW1TX_Msk (0x1U << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */
19118 #define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */
19119 #define DSI_CMCR_DSR0TX_Pos (18U)
19120 #define DSI_CMCR_DSR0TX_Msk (0x1U << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */
19121 #define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */
19122 #define DSI_CMCR_DLWTX_Pos (19U)
19123 #define DSI_CMCR_DLWTX_Msk (0x1U << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */
19124 #define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */
19125 #define DSI_CMCR_MRDPS_Pos (24U)
19126 #define DSI_CMCR_MRDPS_Msk (0x1U << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */
19127 #define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */
19128
19129 /******************* Bit definition for DSI_GHCR register ***************/
19130 #define DSI_GHCR_DT_Pos (0U)
19131 #define DSI_GHCR_DT_Msk (0x3FU << DSI_GHCR_DT_Pos) /*!< 0x0000003F */
19132 #define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */
19133 #define DSI_GHCR_DT0_Pos (0U)
19134 #define DSI_GHCR_DT0_Msk (0x1U << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */
19135 #define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
19136 #define DSI_GHCR_DT1_Pos (1U)
19137 #define DSI_GHCR_DT1_Msk (0x1U << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */
19138 #define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
19139 #define DSI_GHCR_DT2_Pos (2U)
19140 #define DSI_GHCR_DT2_Msk (0x1U << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */
19141 #define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
19142 #define DSI_GHCR_DT3_Pos (3U)
19143 #define DSI_GHCR_DT3_Msk (0x1U << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */
19144 #define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
19145 #define DSI_GHCR_DT4_Pos (4U)
19146 #define DSI_GHCR_DT4_Msk (0x1U << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */
19147 #define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
19148 #define DSI_GHCR_DT5_Pos (5U)
19149 #define DSI_GHCR_DT5_Msk (0x1U << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */
19150 #define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
19151
19152 #define DSI_GHCR_VCID_Pos (6U)
19153 #define DSI_GHCR_VCID_Msk (0x3U << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */
19154 #define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */
19155 #define DSI_GHCR_VCID0_Pos (6U)
19156 #define DSI_GHCR_VCID0_Msk (0x1U << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */
19157 #define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
19158 #define DSI_GHCR_VCID1_Pos (7U)
19159 #define DSI_GHCR_VCID1_Msk (0x1U << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */
19160 #define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
19161
19162 #define DSI_GHCR_WCLSB_Pos (8U)
19163 #define DSI_GHCR_WCLSB_Msk (0xFFU << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */
19164 #define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */
19165 #define DSI_GHCR_WCLSB0_Pos (8U)
19166 #define DSI_GHCR_WCLSB0_Msk (0x1U << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */
19167 #define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
19168 #define DSI_GHCR_WCLSB1_Pos (9U)
19169 #define DSI_GHCR_WCLSB1_Msk (0x1U << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */
19170 #define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
19171 #define DSI_GHCR_WCLSB2_Pos (10U)
19172 #define DSI_GHCR_WCLSB2_Msk (0x1U << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */
19173 #define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
19174 #define DSI_GHCR_WCLSB3_Pos (11U)
19175 #define DSI_GHCR_WCLSB3_Msk (0x1U << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */
19176 #define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
19177 #define DSI_GHCR_WCLSB4_Pos (12U)
19178 #define DSI_GHCR_WCLSB4_Msk (0x1U << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */
19179 #define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
19180 #define DSI_GHCR_WCLSB5_Pos (13U)
19181 #define DSI_GHCR_WCLSB5_Msk (0x1U << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */
19182 #define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
19183 #define DSI_GHCR_WCLSB6_Pos (14U)
19184 #define DSI_GHCR_WCLSB6_Msk (0x1U << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */
19185 #define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
19186 #define DSI_GHCR_WCLSB7_Pos (15U)
19187 #define DSI_GHCR_WCLSB7_Msk (0x1U << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */
19188 #define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
19189
19190 #define DSI_GHCR_WCMSB_Pos (16U)
19191 #define DSI_GHCR_WCMSB_Msk (0xFFU << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */
19192 #define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */
19193 #define DSI_GHCR_WCMSB0_Pos (16U)
19194 #define DSI_GHCR_WCMSB0_Msk (0x1U << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */
19195 #define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
19196 #define DSI_GHCR_WCMSB1_Pos (17U)
19197 #define DSI_GHCR_WCMSB1_Msk (0x1U << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */
19198 #define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
19199 #define DSI_GHCR_WCMSB2_Pos (18U)
19200 #define DSI_GHCR_WCMSB2_Msk (0x1U << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */
19201 #define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
19202 #define DSI_GHCR_WCMSB3_Pos (19U)
19203 #define DSI_GHCR_WCMSB3_Msk (0x1U << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */
19204 #define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
19205 #define DSI_GHCR_WCMSB4_Pos (20U)
19206 #define DSI_GHCR_WCMSB4_Msk (0x1U << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */
19207 #define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
19208 #define DSI_GHCR_WCMSB5_Pos (21U)
19209 #define DSI_GHCR_WCMSB5_Msk (0x1U << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */
19210 #define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
19211 #define DSI_GHCR_WCMSB6_Pos (22U)
19212 #define DSI_GHCR_WCMSB6_Msk (0x1U << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */
19213 #define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
19214 #define DSI_GHCR_WCMSB7_Pos (23U)
19215 #define DSI_GHCR_WCMSB7_Msk (0x1U << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */
19216 #define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
19217
19218 /******************* Bit definition for DSI_GPDR register ***************/
19219 #define DSI_GPDR_DATA1_Pos (0U)
19220 #define DSI_GPDR_DATA1_Msk (0xFFU << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */
19221 #define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */
19222 #define DSI_GPDR_DATA1_0 (0x01U << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */
19223 #define DSI_GPDR_DATA1_1 (0x02U << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */
19224 #define DSI_GPDR_DATA1_2 (0x04U << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */
19225 #define DSI_GPDR_DATA1_3 (0x08U << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */
19226 #define DSI_GPDR_DATA1_4 (0x10U << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */
19227 #define DSI_GPDR_DATA1_5 (0x20U << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */
19228 #define DSI_GPDR_DATA1_6 (0x40U << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */
19229 #define DSI_GPDR_DATA1_7 (0x80U << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */
19230
19231 #define DSI_GPDR_DATA2_Pos (8U)
19232 #define DSI_GPDR_DATA2_Msk (0xFFU << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
19233 #define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */
19234 #define DSI_GPDR_DATA2_0 (0x01U << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
19235 #define DSI_GPDR_DATA2_1 (0x02U << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
19236 #define DSI_GPDR_DATA2_2 (0x04U << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
19237 #define DSI_GPDR_DATA2_3 (0x08U << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
19238 #define DSI_GPDR_DATA2_4 (0x10U << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
19239 #define DSI_GPDR_DATA2_5 (0x20U << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
19240 #define DSI_GPDR_DATA2_6 (0x40U << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
19241 #define DSI_GPDR_DATA2_7 (0x80U << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
19242
19243 #define DSI_GPDR_DATA3_Pos (16U)
19244 #define DSI_GPDR_DATA3_Msk (0xFFU << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
19245 #define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */
19246 #define DSI_GPDR_DATA3_0 (0x01U << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
19247 #define DSI_GPDR_DATA3_1 (0x02U << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
19248 #define DSI_GPDR_DATA3_2 (0x04U << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
19249 #define DSI_GPDR_DATA3_3 (0x08U << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
19250 #define DSI_GPDR_DATA3_4 (0x10U << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
19251 #define DSI_GPDR_DATA3_5 (0x20U << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
19252 #define DSI_GPDR_DATA3_6 (0x40U << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
19253 #define DSI_GPDR_DATA3_7 (0x80U << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
19254
19255 #define DSI_GPDR_DATA4_Pos (24U)
19256 #define DSI_GPDR_DATA4_Msk (0xFFU << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */
19257 #define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */
19258 #define DSI_GPDR_DATA4_0 (0x01U << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */
19259 #define DSI_GPDR_DATA4_1 (0x02U << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */
19260 #define DSI_GPDR_DATA4_2 (0x04U << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */
19261 #define DSI_GPDR_DATA4_3 (0x08U << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */
19262 #define DSI_GPDR_DATA4_4 (0x10U << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */
19263 #define DSI_GPDR_DATA4_5 (0x20U << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */
19264 #define DSI_GPDR_DATA4_6 (0x40U << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */
19265 #define DSI_GPDR_DATA4_7 (0x80U << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */
19266
19267 /******************* Bit definition for DSI_GPSR register ***************/
19268 #define DSI_GPSR_CMDFE_Pos (0U)
19269 #define DSI_GPSR_CMDFE_Msk (0x1U << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */
19270 #define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */
19271 #define DSI_GPSR_CMDFF_Pos (1U)
19272 #define DSI_GPSR_CMDFF_Msk (0x1U << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */
19273 #define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */
19274 #define DSI_GPSR_PWRFE_Pos (2U)
19275 #define DSI_GPSR_PWRFE_Msk (0x1U << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */
19276 #define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */
19277 #define DSI_GPSR_PWRFF_Pos (3U)
19278 #define DSI_GPSR_PWRFF_Msk (0x1U << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */
19279 #define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */
19280 #define DSI_GPSR_PRDFE_Pos (4U)
19281 #define DSI_GPSR_PRDFE_Msk (0x1U << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */
19282 #define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */
19283 #define DSI_GPSR_PRDFF_Pos (5U)
19284 #define DSI_GPSR_PRDFF_Msk (0x1U << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */
19285 #define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */
19286 #define DSI_GPSR_RCB_Pos (6U)
19287 #define DSI_GPSR_RCB_Msk (0x1U << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */
19288 #define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */
19289
19290 /******************* Bit definition for DSI_TCCR0register **************/
19291 #define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
19292 #define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */
19293 #define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */
19294 #define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
19295 #define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */
19296 #define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
19297 #define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
19298 #define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */
19299 #define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
19300 #define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
19301 #define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */
19302 #define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
19303 #define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
19304 #define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */
19305 #define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
19306 #define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
19307 #define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */
19308 #define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
19309 #define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
19310 #define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */
19311 #define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
19312 #define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
19313 #define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */
19314 #define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
19315 #define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
19316 #define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */
19317 #define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
19318 #define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
19319 #define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */
19320 #define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
19321 #define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
19322 #define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */
19323 #define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
19324 #define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
19325 #define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */
19326 #define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
19327 #define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
19328 #define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */
19329 #define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
19330 #define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
19331 #define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */
19332 #define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
19333 #define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
19334 #define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */
19335 #define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
19336 #define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
19337 #define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */
19338 #define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
19339 #define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
19340 #define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */
19341 #define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
19342
19343 #define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
19344 #define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */
19345 #define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */
19346 #define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
19347 #define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */
19348 #define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
19349 #define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
19350 #define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */
19351 #define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
19352 #define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
19353 #define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */
19354 #define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
19355 #define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
19356 #define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */
19357 #define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
19358 #define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
19359 #define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */
19360 #define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
19361 #define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
19362 #define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */
19363 #define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
19364 #define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
19365 #define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */
19366 #define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
19367 #define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
19368 #define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */
19369 #define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
19370 #define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
19371 #define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */
19372 #define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
19373 #define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
19374 #define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */
19375 #define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
19376 #define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
19377 #define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */
19378 #define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
19379 #define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
19380 #define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */
19381 #define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
19382 #define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
19383 #define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */
19384 #define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
19385 #define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
19386 #define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */
19387 #define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
19388 #define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
19389 #define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */
19390 #define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
19391 #define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
19392 #define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */
19393 #define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
19394
19395 /******************* Bit definition for DSI_TCCR1register **************/
19396 #define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
19397 #define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFU << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */
19398 #define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */
19399 #define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
19400 #define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */
19401 #define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
19402 #define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
19403 #define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */
19404 #define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
19405 #define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
19406 #define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */
19407 #define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
19408 #define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
19409 #define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */
19410 #define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
19411 #define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
19412 #define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */
19413 #define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
19414 #define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
19415 #define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */
19416 #define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
19417 #define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
19418 #define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */
19419 #define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
19420 #define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
19421 #define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */
19422 #define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
19423 #define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
19424 #define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */
19425 #define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
19426 #define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
19427 #define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */
19428 #define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
19429 #define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
19430 #define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */
19431 #define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
19432 #define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
19433 #define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */
19434 #define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
19435 #define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
19436 #define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */
19437 #define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
19438 #define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
19439 #define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */
19440 #define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
19441 #define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
19442 #define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */
19443 #define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
19444 #define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
19445 #define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */
19446 #define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
19447
19448 /******************* Bit definition for DSI_TCCR2 register **************/
19449 #define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
19450 #define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFU << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */
19451 #define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */
19452 #define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
19453 #define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */
19454 #define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
19455 #define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
19456 #define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */
19457 #define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
19458 #define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
19459 #define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */
19460 #define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
19461 #define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
19462 #define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */
19463 #define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
19464 #define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
19465 #define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */
19466 #define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
19467 #define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
19468 #define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */
19469 #define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
19470 #define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
19471 #define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */
19472 #define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
19473 #define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
19474 #define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */
19475 #define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
19476 #define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
19477 #define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */
19478 #define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
19479 #define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
19480 #define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */
19481 #define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
19482 #define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
19483 #define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */
19484 #define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
19485 #define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
19486 #define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */
19487 #define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
19488 #define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
19489 #define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */
19490 #define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
19491 #define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
19492 #define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */
19493 #define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
19494 #define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
19495 #define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */
19496 #define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
19497 #define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
19498 #define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */
19499 #define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
19500
19501 /******************* Bit definition for DSI_TCCR3 register **************/
19502 #define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
19503 #define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFU << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */
19504 #define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */
19505 #define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
19506 #define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */
19507 #define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
19508 #define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
19509 #define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */
19510 #define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
19511 #define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
19512 #define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */
19513 #define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
19514 #define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
19515 #define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */
19516 #define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
19517 #define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
19518 #define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */
19519 #define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
19520 #define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
19521 #define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */
19522 #define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
19523 #define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
19524 #define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */
19525 #define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
19526 #define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
19527 #define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */
19528 #define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
19529 #define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
19530 #define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */
19531 #define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
19532 #define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
19533 #define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */
19534 #define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
19535 #define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
19536 #define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */
19537 #define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
19538 #define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
19539 #define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */
19540 #define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
19541 #define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
19542 #define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */
19543 #define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
19544 #define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
19545 #define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */
19546 #define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
19547 #define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
19548 #define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */
19549 #define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
19550 #define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
19551 #define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */
19552 #define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
19553
19554 #define DSI_TCCR3_PM_Pos (24U)
19555 #define DSI_TCCR3_PM_Msk (0x1U << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */
19556 #define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */
19557
19558 /******************* Bit definition for DSI_TCCR4 register **************/
19559 #define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
19560 #define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFU << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */
19561 #define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */
19562 #define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
19563 #define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */
19564 #define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
19565 #define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
19566 #define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */
19567 #define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
19568 #define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
19569 #define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */
19570 #define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
19571 #define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
19572 #define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */
19573 #define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
19574 #define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
19575 #define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */
19576 #define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
19577 #define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
19578 #define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */
19579 #define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
19580 #define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
19581 #define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */
19582 #define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
19583 #define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
19584 #define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */
19585 #define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
19586 #define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
19587 #define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */
19588 #define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
19589 #define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
19590 #define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */
19591 #define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
19592 #define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
19593 #define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */
19594 #define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
19595 #define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
19596 #define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */
19597 #define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
19598 #define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
19599 #define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */
19600 #define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
19601 #define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
19602 #define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */
19603 #define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
19604 #define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
19605 #define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */
19606 #define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
19607 #define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
19608 #define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */
19609 #define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
19610
19611 /******************* Bit definition for DSI_TCCR5register **************/
19612 #define DSI_TCCR5_BTA_TOCNT_Pos (0U)
19613 #define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFU << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */
19614 #define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */
19615 #define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
19616 #define DSI_TCCR5_BTA_TOCNT0_Msk (0x1U << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */
19617 #define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
19618 #define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
19619 #define DSI_TCCR5_BTA_TOCNT1_Msk (0x1U << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */
19620 #define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
19621 #define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
19622 #define DSI_TCCR5_BTA_TOCNT2_Msk (0x1U << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */
19623 #define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
19624 #define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
19625 #define DSI_TCCR5_BTA_TOCNT3_Msk (0x1U << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */
19626 #define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
19627 #define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
19628 #define DSI_TCCR5_BTA_TOCNT4_Msk (0x1U << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */
19629 #define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
19630 #define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
19631 #define DSI_TCCR5_BTA_TOCNT5_Msk (0x1U << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */
19632 #define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
19633 #define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
19634 #define DSI_TCCR5_BTA_TOCNT6_Msk (0x1U << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */
19635 #define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
19636 #define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
19637 #define DSI_TCCR5_BTA_TOCNT7_Msk (0x1U << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */
19638 #define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
19639 #define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
19640 #define DSI_TCCR5_BTA_TOCNT8_Msk (0x1U << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */
19641 #define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
19642 #define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
19643 #define DSI_TCCR5_BTA_TOCNT9_Msk (0x1U << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */
19644 #define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
19645 #define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
19646 #define DSI_TCCR5_BTA_TOCNT10_Msk (0x1U << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */
19647 #define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
19648 #define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
19649 #define DSI_TCCR5_BTA_TOCNT11_Msk (0x1U << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */
19650 #define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
19651 #define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
19652 #define DSI_TCCR5_BTA_TOCNT12_Msk (0x1U << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */
19653 #define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
19654 #define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
19655 #define DSI_TCCR5_BTA_TOCNT13_Msk (0x1U << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */
19656 #define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
19657 #define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
19658 #define DSI_TCCR5_BTA_TOCNT14_Msk (0x1U << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */
19659 #define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
19660 #define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
19661 #define DSI_TCCR5_BTA_TOCNT15_Msk (0x1U << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */
19662 #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
19663
19664 /******************* Bit definition for DSI_TDCR register ***************/
19665 #define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
19666 #define DSI_TDCR_3DM0 0x00000001U
19667 #define DSI_TDCR_3DM1 0x00000002U
19668
19669 #define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
19670 #define DSI_TDCR_3DF0 0x00000004U
19671 #define DSI_TDCR_3DF1 0x00000008U
19672
19673 #define DSI_TDCR_SVS_Pos (4U)
19674 #define DSI_TDCR_SVS_Msk (0x1U << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
19675 #define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */
19676 #define DSI_TDCR_RF_Pos (5U)
19677 #define DSI_TDCR_RF_Msk (0x1U << DSI_TDCR_RF_Pos) /*!< 0x00000020 */
19678 #define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */
19679 #define DSI_TDCR_S3DC_Pos (16U)
19680 #define DSI_TDCR_S3DC_Msk (0x1U << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */
19681 #define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */
19682
19683 /******************* Bit definition for DSI_CLCR register ***************/
19684 #define DSI_CLCR_DPCC_Pos (0U)
19685 #define DSI_CLCR_DPCC_Msk (0x1U << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */
19686 #define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */
19687 #define DSI_CLCR_ACR_Pos (1U)
19688 #define DSI_CLCR_ACR_Msk (0x1U << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */
19689 #define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */
19690
19691 /******************* Bit definition for DSI_CLTCR register **************/
19692 #define DSI_CLTCR_LP2HS_TIME_Pos (0U)
19693 #define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFU << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */
19694 #define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
19695 #define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
19696 #define DSI_CLTCR_LP2HS_TIME0_Msk (0x1U << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */
19697 #define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
19698 #define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
19699 #define DSI_CLTCR_LP2HS_TIME1_Msk (0x1U << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */
19700 #define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
19701 #define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
19702 #define DSI_CLTCR_LP2HS_TIME2_Msk (0x1U << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */
19703 #define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
19704 #define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
19705 #define DSI_CLTCR_LP2HS_TIME3_Msk (0x1U << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */
19706 #define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
19707 #define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
19708 #define DSI_CLTCR_LP2HS_TIME4_Msk (0x1U << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */
19709 #define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
19710 #define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
19711 #define DSI_CLTCR_LP2HS_TIME5_Msk (0x1U << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */
19712 #define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
19713 #define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
19714 #define DSI_CLTCR_LP2HS_TIME6_Msk (0x1U << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */
19715 #define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
19716 #define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
19717 #define DSI_CLTCR_LP2HS_TIME7_Msk (0x1U << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */
19718 #define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
19719 #define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
19720 #define DSI_CLTCR_LP2HS_TIME8_Msk (0x1U << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */
19721 #define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
19722 #define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
19723 #define DSI_CLTCR_LP2HS_TIME9_Msk (0x1U << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */
19724 #define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
19725
19726 #define DSI_CLTCR_HS2LP_TIME_Pos (16U)
19727 #define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFU << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */
19728 #define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
19729 #define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
19730 #define DSI_CLTCR_HS2LP_TIME0_Msk (0x1U << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */
19731 #define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
19732 #define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
19733 #define DSI_CLTCR_HS2LP_TIME1_Msk (0x1U << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */
19734 #define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
19735 #define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
19736 #define DSI_CLTCR_HS2LP_TIME2_Msk (0x1U << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */
19737 #define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
19738 #define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
19739 #define DSI_CLTCR_HS2LP_TIME3_Msk (0x1U << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */
19740 #define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
19741 #define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
19742 #define DSI_CLTCR_HS2LP_TIME4_Msk (0x1U << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */
19743 #define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
19744 #define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
19745 #define DSI_CLTCR_HS2LP_TIME5_Msk (0x1U << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */
19746 #define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
19747 #define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
19748 #define DSI_CLTCR_HS2LP_TIME6_Msk (0x1U << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */
19749 #define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
19750 #define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
19751 #define DSI_CLTCR_HS2LP_TIME7_Msk (0x1U << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */
19752 #define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
19753 #define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
19754 #define DSI_CLTCR_HS2LP_TIME8_Msk (0x1U << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */
19755 #define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
19756 #define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
19757 #define DSI_CLTCR_HS2LP_TIME9_Msk (0x1U << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */
19758 #define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
19759
19760 /******************* Bit definition for DSI_DLTCR register **************/
19761 #define DSI_DLTCR_MRD_TIME_Pos (0U)
19762 #define DSI_DLTCR_MRD_TIME_Msk (0x7FFFU << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */
19763 #define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */
19764 #define DSI_DLTCR_MRD_TIME0_Pos (0U)
19765 #define DSI_DLTCR_MRD_TIME0_Msk (0x1U << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */
19766 #define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
19767 #define DSI_DLTCR_MRD_TIME1_Pos (1U)
19768 #define DSI_DLTCR_MRD_TIME1_Msk (0x1U << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */
19769 #define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
19770 #define DSI_DLTCR_MRD_TIME2_Pos (2U)
19771 #define DSI_DLTCR_MRD_TIME2_Msk (0x1U << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */
19772 #define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
19773 #define DSI_DLTCR_MRD_TIME3_Pos (3U)
19774 #define DSI_DLTCR_MRD_TIME3_Msk (0x1U << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */
19775 #define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
19776 #define DSI_DLTCR_MRD_TIME4_Pos (4U)
19777 #define DSI_DLTCR_MRD_TIME4_Msk (0x1U << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */
19778 #define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
19779 #define DSI_DLTCR_MRD_TIME5_Pos (5U)
19780 #define DSI_DLTCR_MRD_TIME5_Msk (0x1U << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */
19781 #define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
19782 #define DSI_DLTCR_MRD_TIME6_Pos (6U)
19783 #define DSI_DLTCR_MRD_TIME6_Msk (0x1U << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */
19784 #define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
19785 #define DSI_DLTCR_MRD_TIME7_Pos (7U)
19786 #define DSI_DLTCR_MRD_TIME7_Msk (0x1U << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */
19787 #define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
19788 #define DSI_DLTCR_MRD_TIME8_Pos (8U)
19789 #define DSI_DLTCR_MRD_TIME8_Msk (0x1U << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */
19790 #define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
19791 #define DSI_DLTCR_MRD_TIME9_Pos (9U)
19792 #define DSI_DLTCR_MRD_TIME9_Msk (0x1U << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */
19793 #define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
19794 #define DSI_DLTCR_MRD_TIME10_Pos (10U)
19795 #define DSI_DLTCR_MRD_TIME10_Msk (0x1U << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */
19796 #define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
19797 #define DSI_DLTCR_MRD_TIME11_Pos (11U)
19798 #define DSI_DLTCR_MRD_TIME11_Msk (0x1U << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */
19799 #define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
19800 #define DSI_DLTCR_MRD_TIME12_Pos (12U)
19801 #define DSI_DLTCR_MRD_TIME12_Msk (0x1U << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */
19802 #define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
19803 #define DSI_DLTCR_MRD_TIME13_Pos (13U)
19804 #define DSI_DLTCR_MRD_TIME13_Msk (0x1U << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */
19805 #define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
19806 #define DSI_DLTCR_MRD_TIME14_Pos (14U)
19807 #define DSI_DLTCR_MRD_TIME14_Msk (0x1U << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */
19808 #define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
19809
19810 #define DSI_DLTCR_LP2HS_TIME_Pos (16U)
19811 #define DSI_DLTCR_LP2HS_TIME_Msk (0xFFU << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */
19812 #define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
19813 #define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
19814 #define DSI_DLTCR_LP2HS_TIME0_Msk (0x1U << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */
19815 #define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
19816 #define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
19817 #define DSI_DLTCR_LP2HS_TIME1_Msk (0x1U << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */
19818 #define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
19819 #define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
19820 #define DSI_DLTCR_LP2HS_TIME2_Msk (0x1U << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */
19821 #define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
19822 #define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
19823 #define DSI_DLTCR_LP2HS_TIME3_Msk (0x1U << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */
19824 #define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
19825 #define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
19826 #define DSI_DLTCR_LP2HS_TIME4_Msk (0x1U << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */
19827 #define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
19828 #define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
19829 #define DSI_DLTCR_LP2HS_TIME5_Msk (0x1U << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */
19830 #define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
19831 #define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
19832 #define DSI_DLTCR_LP2HS_TIME6_Msk (0x1U << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */
19833 #define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
19834 #define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
19835 #define DSI_DLTCR_LP2HS_TIME7_Msk (0x1U << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */
19836 #define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
19837
19838 #define DSI_DLTCR_HS2LP_TIME_Pos (24U)
19839 #define DSI_DLTCR_HS2LP_TIME_Msk (0xFFU << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */
19840 #define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
19841 #define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
19842 #define DSI_DLTCR_HS2LP_TIME0_Msk (0x1U << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */
19843 #define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
19844 #define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
19845 #define DSI_DLTCR_HS2LP_TIME1_Msk (0x1U << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */
19846 #define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
19847 #define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
19848 #define DSI_DLTCR_HS2LP_TIME2_Msk (0x1U << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */
19849 #define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
19850 #define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
19851 #define DSI_DLTCR_HS2LP_TIME3_Msk (0x1U << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */
19852 #define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
19853 #define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
19854 #define DSI_DLTCR_HS2LP_TIME4_Msk (0x1U << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */
19855 #define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
19856 #define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
19857 #define DSI_DLTCR_HS2LP_TIME5_Msk (0x1U << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */
19858 #define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
19859 #define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
19860 #define DSI_DLTCR_HS2LP_TIME6_Msk (0x1U << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */
19861 #define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
19862 #define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
19863 #define DSI_DLTCR_HS2LP_TIME7_Msk (0x1U << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */
19864 #define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
19865
19866 /******************* Bit definition for DSI_PCTLRregister **************/
19867 #define DSI_PCTLR_DEN_Pos (1U)
19868 #define DSI_PCTLR_DEN_Msk (0x1U << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */
19869 #define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */
19870 #define DSI_PCTLR_CKE_Pos (2U)
19871 #define DSI_PCTLR_CKE_Msk (0x1U << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */
19872 #define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */
19873
19874 /******************* Bit definition for DSI_PCONFR register *************/
19875 #define DSI_PCONFR_NL_Pos (0U)
19876 #define DSI_PCONFR_NL_Msk (0x3U << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */
19877 #define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */
19878 #define DSI_PCONFR_NL0_Pos (0U)
19879 #define DSI_PCONFR_NL0_Msk (0x1U << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */
19880 #define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
19881 #define DSI_PCONFR_NL1_Pos (1U)
19882 #define DSI_PCONFR_NL1_Msk (0x1U << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */
19883 #define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
19884
19885 #define DSI_PCONFR_SW_TIME_Pos (8U)
19886 #define DSI_PCONFR_SW_TIME_Msk (0xFFU << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */
19887 #define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */
19888 #define DSI_PCONFR_SW_TIME0_Pos (8U)
19889 #define DSI_PCONFR_SW_TIME0_Msk (0x1U << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */
19890 #define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
19891 #define DSI_PCONFR_SW_TIME1_Pos (9U)
19892 #define DSI_PCONFR_SW_TIME1_Msk (0x1U << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */
19893 #define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
19894 #define DSI_PCONFR_SW_TIME2_Pos (10U)
19895 #define DSI_PCONFR_SW_TIME2_Msk (0x1U << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */
19896 #define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
19897 #define DSI_PCONFR_SW_TIME3_Pos (11U)
19898 #define DSI_PCONFR_SW_TIME3_Msk (0x1U << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */
19899 #define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
19900 #define DSI_PCONFR_SW_TIME4_Pos (12U)
19901 #define DSI_PCONFR_SW_TIME4_Msk (0x1U << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */
19902 #define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
19903 #define DSI_PCONFR_SW_TIME5_Pos (13U)
19904 #define DSI_PCONFR_SW_TIME5_Msk (0x1U << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */
19905 #define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
19906 #define DSI_PCONFR_SW_TIME6_Pos (14U)
19907 #define DSI_PCONFR_SW_TIME6_Msk (0x1U << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */
19908 #define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
19909 #define DSI_PCONFR_SW_TIME7_Pos (15U)
19910 #define DSI_PCONFR_SW_TIME7_Msk (0x1U << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */
19911 #define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
19912
19913 /******************* Bit definition for DSI_PUCR register ***************/
19914 #define DSI_PUCR_URCL_Pos (0U)
19915 #define DSI_PUCR_URCL_Msk (0x1U << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */
19916 #define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */
19917 #define DSI_PUCR_UECL_Pos (1U)
19918 #define DSI_PUCR_UECL_Msk (0x1U << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */
19919 #define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */
19920 #define DSI_PUCR_URDL_Pos (2U)
19921 #define DSI_PUCR_URDL_Msk (0x1U << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */
19922 #define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */
19923 #define DSI_PUCR_UEDL_Pos (3U)
19924 #define DSI_PUCR_UEDL_Msk (0x1U << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */
19925 #define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */
19926
19927 /******************* Bit definition for DSI_PTTCRregister **************/
19928 #define DSI_PTTCR_TX_TRIG_Pos (0U)
19929 #define DSI_PTTCR_TX_TRIG_Msk (0xFU << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */
19930 #define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */
19931 #define DSI_PTTCR_TX_TRIG0_Pos (0U)
19932 #define DSI_PTTCR_TX_TRIG0_Msk (0x1U << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */
19933 #define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
19934 #define DSI_PTTCR_TX_TRIG1_Pos (1U)
19935 #define DSI_PTTCR_TX_TRIG1_Msk (0x1U << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */
19936 #define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
19937 #define DSI_PTTCR_TX_TRIG2_Pos (2U)
19938 #define DSI_PTTCR_TX_TRIG2_Msk (0x1U << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */
19939 #define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
19940 #define DSI_PTTCR_TX_TRIG3_Pos (3U)
19941 #define DSI_PTTCR_TX_TRIG3_Msk (0x1U << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */
19942 #define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
19943
19944 /******************* Bit definition for DSI_PSR register ****************/
19945 #define DSI_PSR_PD_Pos (1U)
19946 #define DSI_PSR_PD_Msk (0x1U << DSI_PSR_PD_Pos) /*!< 0x00000002 */
19947 #define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */
19948 #define DSI_PSR_PSSC_Pos (2U)
19949 #define DSI_PSR_PSSC_Msk (0x1U << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */
19950 #define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */
19951 #define DSI_PSR_UANC_Pos (3U)
19952 #define DSI_PSR_UANC_Msk (0x1U << DSI_PSR_UANC_Pos) /*!< 0x00000008 */
19953 #define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */
19954 #define DSI_PSR_PSS0_Pos (4U)
19955 #define DSI_PSR_PSS0_Msk (0x1U << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */
19956 #define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */
19957 #define DSI_PSR_UAN0_Pos (5U)
19958 #define DSI_PSR_UAN0_Msk (0x1U << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */
19959 #define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */
19960 #define DSI_PSR_RUE0_Pos (6U)
19961 #define DSI_PSR_RUE0_Msk (0x1U << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */
19962 #define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */
19963 #define DSI_PSR_PSS1_Pos (7U)
19964 #define DSI_PSR_PSS1_Msk (0x1U << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */
19965 #define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */
19966 #define DSI_PSR_UAN1_Pos (8U)
19967 #define DSI_PSR_UAN1_Msk (0x1U << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */
19968 #define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */
19969
19970 /******************* Bit definition for DSI_ISR0 register ***************/
19971 #define DSI_ISR0_AE0_Pos (0U)
19972 #define DSI_ISR0_AE0_Msk (0x1U << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */
19973 #define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */
19974 #define DSI_ISR0_AE1_Pos (1U)
19975 #define DSI_ISR0_AE1_Msk (0x1U << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */
19976 #define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */
19977 #define DSI_ISR0_AE2_Pos (2U)
19978 #define DSI_ISR0_AE2_Msk (0x1U << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */
19979 #define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */
19980 #define DSI_ISR0_AE3_Pos (3U)
19981 #define DSI_ISR0_AE3_Msk (0x1U << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */
19982 #define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */
19983 #define DSI_ISR0_AE4_Pos (4U)
19984 #define DSI_ISR0_AE4_Msk (0x1U << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */
19985 #define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */
19986 #define DSI_ISR0_AE5_Pos (5U)
19987 #define DSI_ISR0_AE5_Msk (0x1U << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */
19988 #define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */
19989 #define DSI_ISR0_AE6_Pos (6U)
19990 #define DSI_ISR0_AE6_Msk (0x1U << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */
19991 #define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */
19992 #define DSI_ISR0_AE7_Pos (7U)
19993 #define DSI_ISR0_AE7_Msk (0x1U << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */
19994 #define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */
19995 #define DSI_ISR0_AE8_Pos (8U)
19996 #define DSI_ISR0_AE8_Msk (0x1U << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */
19997 #define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */
19998 #define DSI_ISR0_AE9_Pos (9U)
19999 #define DSI_ISR0_AE9_Msk (0x1U << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */
20000 #define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */
20001 #define DSI_ISR0_AE10_Pos (10U)
20002 #define DSI_ISR0_AE10_Msk (0x1U << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */
20003 #define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */
20004 #define DSI_ISR0_AE11_Pos (11U)
20005 #define DSI_ISR0_AE11_Msk (0x1U << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */
20006 #define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */
20007 #define DSI_ISR0_AE12_Pos (12U)
20008 #define DSI_ISR0_AE12_Msk (0x1U << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */
20009 #define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */
20010 #define DSI_ISR0_AE13_Pos (13U)
20011 #define DSI_ISR0_AE13_Msk (0x1U << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */
20012 #define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */
20013 #define DSI_ISR0_AE14_Pos (14U)
20014 #define DSI_ISR0_AE14_Msk (0x1U << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */
20015 #define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */
20016 #define DSI_ISR0_AE15_Pos (15U)
20017 #define DSI_ISR0_AE15_Msk (0x1U << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */
20018 #define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */
20019 #define DSI_ISR0_PE0_Pos (16U)
20020 #define DSI_ISR0_PE0_Msk (0x1U << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */
20021 #define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */
20022 #define DSI_ISR0_PE1_Pos (17U)
20023 #define DSI_ISR0_PE1_Msk (0x1U << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */
20024 #define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */
20025 #define DSI_ISR0_PE2_Pos (18U)
20026 #define DSI_ISR0_PE2_Msk (0x1U << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */
20027 #define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */
20028 #define DSI_ISR0_PE3_Pos (19U)
20029 #define DSI_ISR0_PE3_Msk (0x1U << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */
20030 #define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */
20031 #define DSI_ISR0_PE4_Pos (20U)
20032 #define DSI_ISR0_PE4_Msk (0x1U << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */
20033 #define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */
20034
20035 /******************* Bit definition for DSI_ISR1 register ***************/
20036 #define DSI_ISR1_TOHSTX_Pos (0U)
20037 #define DSI_ISR1_TOHSTX_Msk (0x1U << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */
20038 #define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */
20039 #define DSI_ISR1_TOLPRX_Pos (1U)
20040 #define DSI_ISR1_TOLPRX_Msk (0x1U << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */
20041 #define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */
20042 #define DSI_ISR1_ECCSE_Pos (2U)
20043 #define DSI_ISR1_ECCSE_Msk (0x1U << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */
20044 #define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */
20045 #define DSI_ISR1_ECCME_Pos (3U)
20046 #define DSI_ISR1_ECCME_Msk (0x1U << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */
20047 #define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */
20048 #define DSI_ISR1_CRCE_Pos (4U)
20049 #define DSI_ISR1_CRCE_Msk (0x1U << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */
20050 #define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */
20051 #define DSI_ISR1_PSE_Pos (5U)
20052 #define DSI_ISR1_PSE_Msk (0x1U << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */
20053 #define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */
20054 #define DSI_ISR1_EOTPE_Pos (6U)
20055 #define DSI_ISR1_EOTPE_Msk (0x1U << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */
20056 #define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */
20057 #define DSI_ISR1_LPWRE_Pos (7U)
20058 #define DSI_ISR1_LPWRE_Msk (0x1U << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */
20059 #define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */
20060 #define DSI_ISR1_GCWRE_Pos (8U)
20061 #define DSI_ISR1_GCWRE_Msk (0x1U << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */
20062 #define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */
20063 #define DSI_ISR1_GPWRE_Pos (9U)
20064 #define DSI_ISR1_GPWRE_Msk (0x1U << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */
20065 #define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */
20066 #define DSI_ISR1_GPTXE_Pos (10U)
20067 #define DSI_ISR1_GPTXE_Msk (0x1U << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */
20068 #define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */
20069 #define DSI_ISR1_GPRDE_Pos (11U)
20070 #define DSI_ISR1_GPRDE_Msk (0x1U << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */
20071 #define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */
20072 #define DSI_ISR1_GPRXE_Pos (12U)
20073 #define DSI_ISR1_GPRXE_Msk (0x1U << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */
20074 #define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */
20075
20076 /******************* Bit definition for DSI_IER0 register ***************/
20077 #define DSI_IER0_AE0IE_Pos (0U)
20078 #define DSI_IER0_AE0IE_Msk (0x1U << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */
20079 #define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */
20080 #define DSI_IER0_AE1IE_Pos (1U)
20081 #define DSI_IER0_AE1IE_Msk (0x1U << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */
20082 #define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */
20083 #define DSI_IER0_AE2IE_Pos (2U)
20084 #define DSI_IER0_AE2IE_Msk (0x1U << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */
20085 #define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */
20086 #define DSI_IER0_AE3IE_Pos (3U)
20087 #define DSI_IER0_AE3IE_Msk (0x1U << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */
20088 #define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */
20089 #define DSI_IER0_AE4IE_Pos (4U)
20090 #define DSI_IER0_AE4IE_Msk (0x1U << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */
20091 #define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */
20092 #define DSI_IER0_AE5IE_Pos (5U)
20093 #define DSI_IER0_AE5IE_Msk (0x1U << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */
20094 #define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */
20095 #define DSI_IER0_AE6IE_Pos (6U)
20096 #define DSI_IER0_AE6IE_Msk (0x1U << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */
20097 #define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */
20098 #define DSI_IER0_AE7IE_Pos (7U)
20099 #define DSI_IER0_AE7IE_Msk (0x1U << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */
20100 #define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */
20101 #define DSI_IER0_AE8IE_Pos (8U)
20102 #define DSI_IER0_AE8IE_Msk (0x1U << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */
20103 #define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */
20104 #define DSI_IER0_AE9IE_Pos (9U)
20105 #define DSI_IER0_AE9IE_Msk (0x1U << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */
20106 #define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */
20107 #define DSI_IER0_AE10IE_Pos (10U)
20108 #define DSI_IER0_AE10IE_Msk (0x1U << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */
20109 #define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */
20110 #define DSI_IER0_AE11IE_Pos (11U)
20111 #define DSI_IER0_AE11IE_Msk (0x1U << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */
20112 #define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */
20113 #define DSI_IER0_AE12IE_Pos (12U)
20114 #define DSI_IER0_AE12IE_Msk (0x1U << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */
20115 #define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */
20116 #define DSI_IER0_AE13IE_Pos (13U)
20117 #define DSI_IER0_AE13IE_Msk (0x1U << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */
20118 #define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */
20119 #define DSI_IER0_AE14IE_Pos (14U)
20120 #define DSI_IER0_AE14IE_Msk (0x1U << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */
20121 #define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */
20122 #define DSI_IER0_AE15IE_Pos (15U)
20123 #define DSI_IER0_AE15IE_Msk (0x1U << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */
20124 #define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */
20125 #define DSI_IER0_PE0IE_Pos (16U)
20126 #define DSI_IER0_PE0IE_Msk (0x1U << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */
20127 #define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */
20128 #define DSI_IER0_PE1IE_Pos (17U)
20129 #define DSI_IER0_PE1IE_Msk (0x1U << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */
20130 #define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */
20131 #define DSI_IER0_PE2IE_Pos (18U)
20132 #define DSI_IER0_PE2IE_Msk (0x1U << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */
20133 #define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */
20134 #define DSI_IER0_PE3IE_Pos (19U)
20135 #define DSI_IER0_PE3IE_Msk (0x1U << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */
20136 #define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */
20137 #define DSI_IER0_PE4IE_Pos (20U)
20138 #define DSI_IER0_PE4IE_Msk (0x1U << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */
20139 #define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */
20140
20141 /******************* Bit definition for DSI_IER1 register ***************/
20142 #define DSI_IER1_TOHSTXIE_Pos (0U)
20143 #define DSI_IER1_TOHSTXIE_Msk (0x1U << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */
20144 #define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */
20145 #define DSI_IER1_TOLPRXIE_Pos (1U)
20146 #define DSI_IER1_TOLPRXIE_Msk (0x1U << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */
20147 #define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */
20148 #define DSI_IER1_ECCSEIE_Pos (2U)
20149 #define DSI_IER1_ECCSEIE_Msk (0x1U << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */
20150 #define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */
20151 #define DSI_IER1_ECCMEIE_Pos (3U)
20152 #define DSI_IER1_ECCMEIE_Msk (0x1U << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */
20153 #define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */
20154 #define DSI_IER1_CRCEIE_Pos (4U)
20155 #define DSI_IER1_CRCEIE_Msk (0x1U << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */
20156 #define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */
20157 #define DSI_IER1_PSEIE_Pos (5U)
20158 #define DSI_IER1_PSEIE_Msk (0x1U << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */
20159 #define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */
20160 #define DSI_IER1_EOTPEIE_Pos (6U)
20161 #define DSI_IER1_EOTPEIE_Msk (0x1U << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */
20162 #define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */
20163 #define DSI_IER1_LPWREIE_Pos (7U)
20164 #define DSI_IER1_LPWREIE_Msk (0x1U << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */
20165 #define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */
20166 #define DSI_IER1_GCWREIE_Pos (8U)
20167 #define DSI_IER1_GCWREIE_Msk (0x1U << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */
20168 #define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */
20169 #define DSI_IER1_GPWREIE_Pos (9U)
20170 #define DSI_IER1_GPWREIE_Msk (0x1U << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */
20171 #define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */
20172 #define DSI_IER1_GPTXEIE_Pos (10U)
20173 #define DSI_IER1_GPTXEIE_Msk (0x1U << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */
20174 #define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */
20175 #define DSI_IER1_GPRDEIE_Pos (11U)
20176 #define DSI_IER1_GPRDEIE_Msk (0x1U << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */
20177 #define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */
20178 #define DSI_IER1_GPRXEIE_Pos (12U)
20179 #define DSI_IER1_GPRXEIE_Msk (0x1U << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */
20180 #define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */
20181
20182 /******************* Bit definition for DSI_FIR0 register ***************/
20183 #define DSI_FIR0_FAE0_Pos (0U)
20184 #define DSI_FIR0_FAE0_Msk (0x1U << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */
20185 #define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */
20186 #define DSI_FIR0_FAE1_Pos (1U)
20187 #define DSI_FIR0_FAE1_Msk (0x1U << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */
20188 #define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */
20189 #define DSI_FIR0_FAE2_Pos (2U)
20190 #define DSI_FIR0_FAE2_Msk (0x1U << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */
20191 #define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */
20192 #define DSI_FIR0_FAE3_Pos (3U)
20193 #define DSI_FIR0_FAE3_Msk (0x1U << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */
20194 #define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */
20195 #define DSI_FIR0_FAE4_Pos (4U)
20196 #define DSI_FIR0_FAE4_Msk (0x1U << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */
20197 #define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */
20198 #define DSI_FIR0_FAE5_Pos (5U)
20199 #define DSI_FIR0_FAE5_Msk (0x1U << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */
20200 #define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */
20201 #define DSI_FIR0_FAE6_Pos (6U)
20202 #define DSI_FIR0_FAE6_Msk (0x1U << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */
20203 #define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */
20204 #define DSI_FIR0_FAE7_Pos (7U)
20205 #define DSI_FIR0_FAE7_Msk (0x1U << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */
20206 #define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */
20207 #define DSI_FIR0_FAE8_Pos (8U)
20208 #define DSI_FIR0_FAE8_Msk (0x1U << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */
20209 #define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */
20210 #define DSI_FIR0_FAE9_Pos (9U)
20211 #define DSI_FIR0_FAE9_Msk (0x1U << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */
20212 #define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */
20213 #define DSI_FIR0_FAE10_Pos (10U)
20214 #define DSI_FIR0_FAE10_Msk (0x1U << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */
20215 #define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */
20216 #define DSI_FIR0_FAE11_Pos (11U)
20217 #define DSI_FIR0_FAE11_Msk (0x1U << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */
20218 #define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */
20219 #define DSI_FIR0_FAE12_Pos (12U)
20220 #define DSI_FIR0_FAE12_Msk (0x1U << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */
20221 #define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */
20222 #define DSI_FIR0_FAE13_Pos (13U)
20223 #define DSI_FIR0_FAE13_Msk (0x1U << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */
20224 #define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */
20225 #define DSI_FIR0_FAE14_Pos (14U)
20226 #define DSI_FIR0_FAE14_Msk (0x1U << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */
20227 #define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */
20228 #define DSI_FIR0_FAE15_Pos (15U)
20229 #define DSI_FIR0_FAE15_Msk (0x1U << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */
20230 #define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */
20231 #define DSI_FIR0_FPE0_Pos (16U)
20232 #define DSI_FIR0_FPE0_Msk (0x1U << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */
20233 #define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */
20234 #define DSI_FIR0_FPE1_Pos (17U)
20235 #define DSI_FIR0_FPE1_Msk (0x1U << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */
20236 #define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */
20237 #define DSI_FIR0_FPE2_Pos (18U)
20238 #define DSI_FIR0_FPE2_Msk (0x1U << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */
20239 #define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */
20240 #define DSI_FIR0_FPE3_Pos (19U)
20241 #define DSI_FIR0_FPE3_Msk (0x1U << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */
20242 #define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */
20243 #define DSI_FIR0_FPE4_Pos (20U)
20244 #define DSI_FIR0_FPE4_Msk (0x1U << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */
20245 #define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */
20246
20247 /******************* Bit definition for DSI_FIR1 register ***************/
20248 #define DSI_FIR1_FTOHSTX_Pos (0U)
20249 #define DSI_FIR1_FTOHSTX_Msk (0x1U << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */
20250 #define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
20251 #define DSI_FIR1_FTOLPRX_Pos (1U)
20252 #define DSI_FIR1_FTOLPRX_Msk (0x1U << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */
20253 #define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
20254 #define DSI_FIR1_FECCSE_Pos (2U)
20255 #define DSI_FIR1_FECCSE_Msk (0x1U << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */
20256 #define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
20257 #define DSI_FIR1_FECCME_Pos (3U)
20258 #define DSI_FIR1_FECCME_Msk (0x1U << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */
20259 #define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
20260 #define DSI_FIR1_FCRCE_Pos (4U)
20261 #define DSI_FIR1_FCRCE_Msk (0x1U << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */
20262 #define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */
20263 #define DSI_FIR1_FPSE_Pos (5U)
20264 #define DSI_FIR1_FPSE_Msk (0x1U << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */
20265 #define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */
20266 #define DSI_FIR1_FEOTPE_Pos (6U)
20267 #define DSI_FIR1_FEOTPE_Msk (0x1U << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */
20268 #define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */
20269 #define DSI_FIR1_FLPWRE_Pos (7U)
20270 #define DSI_FIR1_FLPWRE_Msk (0x1U << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */
20271 #define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */
20272 #define DSI_FIR1_FGCWRE_Pos (8U)
20273 #define DSI_FIR1_FGCWRE_Msk (0x1U << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */
20274 #define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */
20275 #define DSI_FIR1_FGPWRE_Pos (9U)
20276 #define DSI_FIR1_FGPWRE_Msk (0x1U << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */
20277 #define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */
20278 #define DSI_FIR1_FGPTXE_Pos (10U)
20279 #define DSI_FIR1_FGPTXE_Msk (0x1U << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */
20280 #define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */
20281 #define DSI_FIR1_FGPRDE_Pos (11U)
20282 #define DSI_FIR1_FGPRDE_Msk (0x1U << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */
20283 #define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */
20284 #define DSI_FIR1_FGPRXE_Pos (12U)
20285 #define DSI_FIR1_FGPRXE_Msk (0x1U << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */
20286 #define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */
20287
20288 /******************* Bit definition for DSI_VSCR register ***************/
20289 #define DSI_VSCR_EN_Pos (0U)
20290 #define DSI_VSCR_EN_Msk (0x1U << DSI_VSCR_EN_Pos) /*!< 0x00000001 */
20291 #define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */
20292 #define DSI_VSCR_UR_Pos (8U)
20293 #define DSI_VSCR_UR_Msk (0x1U << DSI_VSCR_UR_Pos) /*!< 0x00000100 */
20294 #define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */
20295
20296 /******************* Bit definition for DSI_LCVCIDR register ************/
20297 #define DSI_LCVCIDR_VCID_Pos (0U)
20298 #define DSI_LCVCIDR_VCID_Msk (0x3U << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */
20299 #define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */
20300 #define DSI_LCVCIDR_VCID0_Pos (0U)
20301 #define DSI_LCVCIDR_VCID0_Msk (0x1U << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */
20302 #define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
20303 #define DSI_LCVCIDR_VCID1_Pos (1U)
20304 #define DSI_LCVCIDR_VCID1_Msk (0x1U << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */
20305 #define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
20306
20307 /******************* Bit definition for DSI_LCCCR register **************/
20308 #define DSI_LCCCR_COLC_Pos (0U)
20309 #define DSI_LCCCR_COLC_Msk (0xFU << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */
20310 #define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */
20311 #define DSI_LCCCR_COLC0_Pos (0U)
20312 #define DSI_LCCCR_COLC0_Msk (0x1U << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */
20313 #define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
20314 #define DSI_LCCCR_COLC1_Pos (1U)
20315 #define DSI_LCCCR_COLC1_Msk (0x1U << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */
20316 #define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
20317 #define DSI_LCCCR_COLC2_Pos (2U)
20318 #define DSI_LCCCR_COLC2_Msk (0x1U << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */
20319 #define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
20320 #define DSI_LCCCR_COLC3_Pos (3U)
20321 #define DSI_LCCCR_COLC3_Msk (0x1U << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */
20322 #define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
20323
20324 #define DSI_LCCCR_LPE_Pos (8U)
20325 #define DSI_LCCCR_LPE_Msk (0x1U << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */
20326 #define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */
20327
20328 /******************* Bit definition for DSI_LPMCCR register *************/
20329 #define DSI_LPMCCR_VLPSIZE_Pos (0U)
20330 #define DSI_LPMCCR_VLPSIZE_Msk (0xFFU << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */
20331 #define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
20332 #define DSI_LPMCCR_VLPSIZE0_Pos (0U)
20333 #define DSI_LPMCCR_VLPSIZE0_Msk (0x1U << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */
20334 #define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
20335 #define DSI_LPMCCR_VLPSIZE1_Pos (1U)
20336 #define DSI_LPMCCR_VLPSIZE1_Msk (0x1U << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */
20337 #define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
20338 #define DSI_LPMCCR_VLPSIZE2_Pos (2U)
20339 #define DSI_LPMCCR_VLPSIZE2_Msk (0x1U << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */
20340 #define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
20341 #define DSI_LPMCCR_VLPSIZE3_Pos (3U)
20342 #define DSI_LPMCCR_VLPSIZE3_Msk (0x1U << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */
20343 #define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
20344 #define DSI_LPMCCR_VLPSIZE4_Pos (4U)
20345 #define DSI_LPMCCR_VLPSIZE4_Msk (0x1U << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */
20346 #define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
20347 #define DSI_LPMCCR_VLPSIZE5_Pos (5U)
20348 #define DSI_LPMCCR_VLPSIZE5_Msk (0x1U << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */
20349 #define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
20350 #define DSI_LPMCCR_VLPSIZE6_Pos (6U)
20351 #define DSI_LPMCCR_VLPSIZE6_Msk (0x1U << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */
20352 #define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
20353 #define DSI_LPMCCR_VLPSIZE7_Pos (7U)
20354 #define DSI_LPMCCR_VLPSIZE7_Msk (0x1U << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */
20355 #define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
20356
20357 #define DSI_LPMCCR_LPSIZE_Pos (16U)
20358 #define DSI_LPMCCR_LPSIZE_Msk (0xFFU << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */
20359 #define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */
20360 #define DSI_LPMCCR_LPSIZE0_Pos (16U)
20361 #define DSI_LPMCCR_LPSIZE0_Msk (0x1U << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */
20362 #define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
20363 #define DSI_LPMCCR_LPSIZE1_Pos (17U)
20364 #define DSI_LPMCCR_LPSIZE1_Msk (0x1U << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */
20365 #define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
20366 #define DSI_LPMCCR_LPSIZE2_Pos (18U)
20367 #define DSI_LPMCCR_LPSIZE2_Msk (0x1U << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */
20368 #define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
20369 #define DSI_LPMCCR_LPSIZE3_Pos (19U)
20370 #define DSI_LPMCCR_LPSIZE3_Msk (0x1U << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */
20371 #define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
20372 #define DSI_LPMCCR_LPSIZE4_Pos (20U)
20373 #define DSI_LPMCCR_LPSIZE4_Msk (0x1U << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */
20374 #define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
20375 #define DSI_LPMCCR_LPSIZE5_Pos (21U)
20376 #define DSI_LPMCCR_LPSIZE5_Msk (0x1U << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */
20377 #define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
20378 #define DSI_LPMCCR_LPSIZE6_Pos (22U)
20379 #define DSI_LPMCCR_LPSIZE6_Msk (0x1U << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */
20380 #define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
20381 #define DSI_LPMCCR_LPSIZE7_Pos (23U)
20382 #define DSI_LPMCCR_LPSIZE7_Msk (0x1U << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */
20383 #define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
20384
20385 /******************* Bit definition for DSI_VMCCR register **************/
20386 #define DSI_VMCCR_VMT_Pos (0U)
20387 #define DSI_VMCCR_VMT_Msk (0x3U << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */
20388 #define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */
20389 #define DSI_VMCCR_VMT0_Pos (0U)
20390 #define DSI_VMCCR_VMT0_Msk (0x1U << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */
20391 #define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
20392 #define DSI_VMCCR_VMT1_Pos (1U)
20393 #define DSI_VMCCR_VMT1_Msk (0x1U << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */
20394 #define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
20395
20396 #define DSI_VMCCR_LPVSAE_Pos (8U)
20397 #define DSI_VMCCR_LPVSAE_Msk (0x1U << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */
20398 #define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */
20399 #define DSI_VMCCR_LPVBPE_Pos (9U)
20400 #define DSI_VMCCR_LPVBPE_Msk (0x1U << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */
20401 #define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */
20402 #define DSI_VMCCR_LPVFPE_Pos (10U)
20403 #define DSI_VMCCR_LPVFPE_Msk (0x1U << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */
20404 #define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
20405 #define DSI_VMCCR_LPVAE_Pos (11U)
20406 #define DSI_VMCCR_LPVAE_Msk (0x1U << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */
20407 #define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */
20408 #define DSI_VMCCR_LPHBPE_Pos (12U)
20409 #define DSI_VMCCR_LPHBPE_Msk (0x1U << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */
20410 #define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */
20411 #define DSI_VMCCR_LPHFE_Pos (13U)
20412 #define DSI_VMCCR_LPHFE_Msk (0x1U << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */
20413 #define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */
20414 #define DSI_VMCCR_FBTAAE_Pos (14U)
20415 #define DSI_VMCCR_FBTAAE_Msk (0x1U << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */
20416 #define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */
20417 #define DSI_VMCCR_LPCE_Pos (15U)
20418 #define DSI_VMCCR_LPCE_Msk (0x1U << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */
20419 #define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */
20420
20421 /******************* Bit definition for DSI_VPCCR register **************/
20422 #define DSI_VPCCR_VPSIZE_Pos (0U)
20423 #define DSI_VPCCR_VPSIZE_Msk (0x3FFFU << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */
20424 #define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */
20425 #define DSI_VPCCR_VPSIZE0_Pos (0U)
20426 #define DSI_VPCCR_VPSIZE0_Msk (0x1U << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */
20427 #define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
20428 #define DSI_VPCCR_VPSIZE1_Pos (1U)
20429 #define DSI_VPCCR_VPSIZE1_Msk (0x1U << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */
20430 #define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
20431 #define DSI_VPCCR_VPSIZE2_Pos (2U)
20432 #define DSI_VPCCR_VPSIZE2_Msk (0x1U << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */
20433 #define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
20434 #define DSI_VPCCR_VPSIZE3_Pos (3U)
20435 #define DSI_VPCCR_VPSIZE3_Msk (0x1U << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */
20436 #define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
20437 #define DSI_VPCCR_VPSIZE4_Pos (4U)
20438 #define DSI_VPCCR_VPSIZE4_Msk (0x1U << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */
20439 #define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
20440 #define DSI_VPCCR_VPSIZE5_Pos (5U)
20441 #define DSI_VPCCR_VPSIZE5_Msk (0x1U << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */
20442 #define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
20443 #define DSI_VPCCR_VPSIZE6_Pos (6U)
20444 #define DSI_VPCCR_VPSIZE6_Msk (0x1U << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */
20445 #define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
20446 #define DSI_VPCCR_VPSIZE7_Pos (7U)
20447 #define DSI_VPCCR_VPSIZE7_Msk (0x1U << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */
20448 #define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
20449 #define DSI_VPCCR_VPSIZE8_Pos (8U)
20450 #define DSI_VPCCR_VPSIZE8_Msk (0x1U << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */
20451 #define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
20452 #define DSI_VPCCR_VPSIZE9_Pos (9U)
20453 #define DSI_VPCCR_VPSIZE9_Msk (0x1U << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */
20454 #define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
20455 #define DSI_VPCCR_VPSIZE10_Pos (10U)
20456 #define DSI_VPCCR_VPSIZE10_Msk (0x1U << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */
20457 #define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
20458 #define DSI_VPCCR_VPSIZE11_Pos (11U)
20459 #define DSI_VPCCR_VPSIZE11_Msk (0x1U << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */
20460 #define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
20461 #define DSI_VPCCR_VPSIZE12_Pos (12U)
20462 #define DSI_VPCCR_VPSIZE12_Msk (0x1U << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */
20463 #define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
20464 #define DSI_VPCCR_VPSIZE13_Pos (13U)
20465 #define DSI_VPCCR_VPSIZE13_Msk (0x1U << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */
20466 #define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
20467
20468 /******************* Bit definition for DSI_VCCCR register **************/
20469 #define DSI_VCCCR_NUMC_Pos (0U)
20470 #define DSI_VCCCR_NUMC_Msk (0x1FFFU << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */
20471 #define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */
20472 #define DSI_VCCCR_NUMC0_Pos (0U)
20473 #define DSI_VCCCR_NUMC0_Msk (0x1U << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */
20474 #define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
20475 #define DSI_VCCCR_NUMC1_Pos (1U)
20476 #define DSI_VCCCR_NUMC1_Msk (0x1U << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */
20477 #define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
20478 #define DSI_VCCCR_NUMC2_Pos (2U)
20479 #define DSI_VCCCR_NUMC2_Msk (0x1U << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */
20480 #define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
20481 #define DSI_VCCCR_NUMC3_Pos (3U)
20482 #define DSI_VCCCR_NUMC3_Msk (0x1U << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */
20483 #define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
20484 #define DSI_VCCCR_NUMC4_Pos (4U)
20485 #define DSI_VCCCR_NUMC4_Msk (0x1U << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */
20486 #define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
20487 #define DSI_VCCCR_NUMC5_Pos (5U)
20488 #define DSI_VCCCR_NUMC5_Msk (0x1U << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */
20489 #define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
20490 #define DSI_VCCCR_NUMC6_Pos (6U)
20491 #define DSI_VCCCR_NUMC6_Msk (0x1U << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */
20492 #define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
20493 #define DSI_VCCCR_NUMC7_Pos (7U)
20494 #define DSI_VCCCR_NUMC7_Msk (0x1U << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */
20495 #define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
20496 #define DSI_VCCCR_NUMC8_Pos (8U)
20497 #define DSI_VCCCR_NUMC8_Msk (0x1U << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */
20498 #define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
20499 #define DSI_VCCCR_NUMC9_Pos (9U)
20500 #define DSI_VCCCR_NUMC9_Msk (0x1U << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */
20501 #define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
20502 #define DSI_VCCCR_NUMC10_Pos (10U)
20503 #define DSI_VCCCR_NUMC10_Msk (0x1U << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */
20504 #define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
20505 #define DSI_VCCCR_NUMC11_Pos (11U)
20506 #define DSI_VCCCR_NUMC11_Msk (0x1U << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */
20507 #define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
20508 #define DSI_VCCCR_NUMC12_Pos (12U)
20509 #define DSI_VCCCR_NUMC12_Msk (0x1U << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */
20510 #define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
20511
20512 /******************* Bit definition for DSI_VNPCCR register *************/
20513 #define DSI_VNPCCR_NPSIZE_Pos (0U)
20514 #define DSI_VNPCCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */
20515 #define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */
20516 #define DSI_VNPCCR_NPSIZE0_Pos (0U)
20517 #define DSI_VNPCCR_NPSIZE0_Msk (0x1U << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */
20518 #define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
20519 #define DSI_VNPCCR_NPSIZE1_Pos (1U)
20520 #define DSI_VNPCCR_NPSIZE1_Msk (0x1U << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */
20521 #define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
20522 #define DSI_VNPCCR_NPSIZE2_Pos (2U)
20523 #define DSI_VNPCCR_NPSIZE2_Msk (0x1U << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */
20524 #define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
20525 #define DSI_VNPCCR_NPSIZE3_Pos (3U)
20526 #define DSI_VNPCCR_NPSIZE3_Msk (0x1U << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */
20527 #define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
20528 #define DSI_VNPCCR_NPSIZE4_Pos (4U)
20529 #define DSI_VNPCCR_NPSIZE4_Msk (0x1U << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */
20530 #define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
20531 #define DSI_VNPCCR_NPSIZE5_Pos (5U)
20532 #define DSI_VNPCCR_NPSIZE5_Msk (0x1U << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */
20533 #define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
20534 #define DSI_VNPCCR_NPSIZE6_Pos (6U)
20535 #define DSI_VNPCCR_NPSIZE6_Msk (0x1U << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */
20536 #define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
20537 #define DSI_VNPCCR_NPSIZE7_Pos (7U)
20538 #define DSI_VNPCCR_NPSIZE7_Msk (0x1U << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */
20539 #define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
20540 #define DSI_VNPCCR_NPSIZE8_Pos (8U)
20541 #define DSI_VNPCCR_NPSIZE8_Msk (0x1U << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */
20542 #define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
20543 #define DSI_VNPCCR_NPSIZE9_Pos (9U)
20544 #define DSI_VNPCCR_NPSIZE9_Msk (0x1U << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */
20545 #define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
20546 #define DSI_VNPCCR_NPSIZE10_Pos (10U)
20547 #define DSI_VNPCCR_NPSIZE10_Msk (0x1U << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */
20548 #define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
20549 #define DSI_VNPCCR_NPSIZE11_Pos (11U)
20550 #define DSI_VNPCCR_NPSIZE11_Msk (0x1U << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */
20551 #define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
20552 #define DSI_VNPCCR_NPSIZE12_Pos (12U)
20553 #define DSI_VNPCCR_NPSIZE12_Msk (0x1U << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */
20554 #define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
20555
20556 /******************* Bit definition for DSI_VHSACCR register ************/
20557 #define DSI_VHSACCR_HSA_Pos (0U)
20558 #define DSI_VHSACCR_HSA_Msk (0xFFFU << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */
20559 #define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */
20560 #define DSI_VHSACCR_HSA0_Pos (0U)
20561 #define DSI_VHSACCR_HSA0_Msk (0x1U << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */
20562 #define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
20563 #define DSI_VHSACCR_HSA1_Pos (1U)
20564 #define DSI_VHSACCR_HSA1_Msk (0x1U << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */
20565 #define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
20566 #define DSI_VHSACCR_HSA2_Pos (2U)
20567 #define DSI_VHSACCR_HSA2_Msk (0x1U << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */
20568 #define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
20569 #define DSI_VHSACCR_HSA3_Pos (3U)
20570 #define DSI_VHSACCR_HSA3_Msk (0x1U << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */
20571 #define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
20572 #define DSI_VHSACCR_HSA4_Pos (4U)
20573 #define DSI_VHSACCR_HSA4_Msk (0x1U << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */
20574 #define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
20575 #define DSI_VHSACCR_HSA5_Pos (5U)
20576 #define DSI_VHSACCR_HSA5_Msk (0x1U << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */
20577 #define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
20578 #define DSI_VHSACCR_HSA6_Pos (6U)
20579 #define DSI_VHSACCR_HSA6_Msk (0x1U << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */
20580 #define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
20581 #define DSI_VHSACCR_HSA7_Pos (7U)
20582 #define DSI_VHSACCR_HSA7_Msk (0x1U << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */
20583 #define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
20584 #define DSI_VHSACCR_HSA8_Pos (8U)
20585 #define DSI_VHSACCR_HSA8_Msk (0x1U << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */
20586 #define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
20587 #define DSI_VHSACCR_HSA9_Pos (9U)
20588 #define DSI_VHSACCR_HSA9_Msk (0x1U << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */
20589 #define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
20590 #define DSI_VHSACCR_HSA10_Pos (10U)
20591 #define DSI_VHSACCR_HSA10_Msk (0x1U << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */
20592 #define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
20593 #define DSI_VHSACCR_HSA11_Pos (11U)
20594 #define DSI_VHSACCR_HSA11_Msk (0x1U << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */
20595 #define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
20596
20597 /******************* Bit definition for DSI_VHBPCCR register ************/
20598 #define DSI_VHBPCCR_HBP_Pos (0U)
20599 #define DSI_VHBPCCR_HBP_Msk (0xFFFU << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */
20600 #define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
20601 #define DSI_VHBPCCR_HBP0_Pos (0U)
20602 #define DSI_VHBPCCR_HBP0_Msk (0x1U << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */
20603 #define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
20604 #define DSI_VHBPCCR_HBP1_Pos (1U)
20605 #define DSI_VHBPCCR_HBP1_Msk (0x1U << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */
20606 #define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
20607 #define DSI_VHBPCCR_HBP2_Pos (2U)
20608 #define DSI_VHBPCCR_HBP2_Msk (0x1U << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */
20609 #define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
20610 #define DSI_VHBPCCR_HBP3_Pos (3U)
20611 #define DSI_VHBPCCR_HBP3_Msk (0x1U << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */
20612 #define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
20613 #define DSI_VHBPCCR_HBP4_Pos (4U)
20614 #define DSI_VHBPCCR_HBP4_Msk (0x1U << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */
20615 #define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
20616 #define DSI_VHBPCCR_HBP5_Pos (5U)
20617 #define DSI_VHBPCCR_HBP5_Msk (0x1U << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */
20618 #define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
20619 #define DSI_VHBPCCR_HBP6_Pos (6U)
20620 #define DSI_VHBPCCR_HBP6_Msk (0x1U << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */
20621 #define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
20622 #define DSI_VHBPCCR_HBP7_Pos (7U)
20623 #define DSI_VHBPCCR_HBP7_Msk (0x1U << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */
20624 #define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
20625 #define DSI_VHBPCCR_HBP8_Pos (8U)
20626 #define DSI_VHBPCCR_HBP8_Msk (0x1U << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */
20627 #define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
20628 #define DSI_VHBPCCR_HBP9_Pos (9U)
20629 #define DSI_VHBPCCR_HBP9_Msk (0x1U << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */
20630 #define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
20631 #define DSI_VHBPCCR_HBP10_Pos (10U)
20632 #define DSI_VHBPCCR_HBP10_Msk (0x1U << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */
20633 #define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
20634 #define DSI_VHBPCCR_HBP11_Pos (11U)
20635 #define DSI_VHBPCCR_HBP11_Msk (0x1U << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */
20636 #define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
20637
20638 /******************* Bit definition for DSI_VLCCR register **************/
20639 #define DSI_VLCCR_HLINE_Pos (0U)
20640 #define DSI_VLCCR_HLINE_Msk (0x7FFFU << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */
20641 #define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */
20642 #define DSI_VLCCR_HLINE0_Pos (0U)
20643 #define DSI_VLCCR_HLINE0_Msk (0x1U << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */
20644 #define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
20645 #define DSI_VLCCR_HLINE1_Pos (1U)
20646 #define DSI_VLCCR_HLINE1_Msk (0x1U << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */
20647 #define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
20648 #define DSI_VLCCR_HLINE2_Pos (2U)
20649 #define DSI_VLCCR_HLINE2_Msk (0x1U << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */
20650 #define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
20651 #define DSI_VLCCR_HLINE3_Pos (3U)
20652 #define DSI_VLCCR_HLINE3_Msk (0x1U << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */
20653 #define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
20654 #define DSI_VLCCR_HLINE4_Pos (4U)
20655 #define DSI_VLCCR_HLINE4_Msk (0x1U << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */
20656 #define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
20657 #define DSI_VLCCR_HLINE5_Pos (5U)
20658 #define DSI_VLCCR_HLINE5_Msk (0x1U << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */
20659 #define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
20660 #define DSI_VLCCR_HLINE6_Pos (6U)
20661 #define DSI_VLCCR_HLINE6_Msk (0x1U << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */
20662 #define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
20663 #define DSI_VLCCR_HLINE7_Pos (7U)
20664 #define DSI_VLCCR_HLINE7_Msk (0x1U << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */
20665 #define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
20666 #define DSI_VLCCR_HLINE8_Pos (8U)
20667 #define DSI_VLCCR_HLINE8_Msk (0x1U << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */
20668 #define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
20669 #define DSI_VLCCR_HLINE9_Pos (9U)
20670 #define DSI_VLCCR_HLINE9_Msk (0x1U << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */
20671 #define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
20672 #define DSI_VLCCR_HLINE10_Pos (10U)
20673 #define DSI_VLCCR_HLINE10_Msk (0x1U << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */
20674 #define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
20675 #define DSI_VLCCR_HLINE11_Pos (11U)
20676 #define DSI_VLCCR_HLINE11_Msk (0x1U << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */
20677 #define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
20678 #define DSI_VLCCR_HLINE12_Pos (12U)
20679 #define DSI_VLCCR_HLINE12_Msk (0x1U << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */
20680 #define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
20681 #define DSI_VLCCR_HLINE13_Pos (13U)
20682 #define DSI_VLCCR_HLINE13_Msk (0x1U << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */
20683 #define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
20684 #define DSI_VLCCR_HLINE14_Pos (14U)
20685 #define DSI_VLCCR_HLINE14_Msk (0x1U << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */
20686 #define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
20687
20688 /******************* Bit definition for DSI_VVSACCR register ***************/
20689 #define DSI_VVSACCR_VSA_Pos (0U)
20690 #define DSI_VVSACCR_VSA_Msk (0x3FFU << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */
20691 #define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */
20692 #define DSI_VVSACCR_VSA0_Pos (0U)
20693 #define DSI_VVSACCR_VSA0_Msk (0x1U << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */
20694 #define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
20695 #define DSI_VVSACCR_VSA1_Pos (1U)
20696 #define DSI_VVSACCR_VSA1_Msk (0x1U << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */
20697 #define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
20698 #define DSI_VVSACCR_VSA2_Pos (2U)
20699 #define DSI_VVSACCR_VSA2_Msk (0x1U << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */
20700 #define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
20701 #define DSI_VVSACCR_VSA3_Pos (3U)
20702 #define DSI_VVSACCR_VSA3_Msk (0x1U << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */
20703 #define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
20704 #define DSI_VVSACCR_VSA4_Pos (4U)
20705 #define DSI_VVSACCR_VSA4_Msk (0x1U << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */
20706 #define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
20707 #define DSI_VVSACCR_VSA5_Pos (5U)
20708 #define DSI_VVSACCR_VSA5_Msk (0x1U << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */
20709 #define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
20710 #define DSI_VVSACCR_VSA6_Pos (6U)
20711 #define DSI_VVSACCR_VSA6_Msk (0x1U << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */
20712 #define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
20713 #define DSI_VVSACCR_VSA7_Pos (7U)
20714 #define DSI_VVSACCR_VSA7_Msk (0x1U << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */
20715 #define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
20716 #define DSI_VVSACCR_VSA8_Pos (8U)
20717 #define DSI_VVSACCR_VSA8_Msk (0x1U << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */
20718 #define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
20719 #define DSI_VVSACCR_VSA9_Pos (9U)
20720 #define DSI_VVSACCR_VSA9_Msk (0x1U << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */
20721 #define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
20722
20723 /******************* Bit definition for DSI_VVBPCCR register ************/
20724 #define DSI_VVBPCCR_VBP_Pos (0U)
20725 #define DSI_VVBPCCR_VBP_Msk (0x3FFU << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */
20726 #define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */
20727 #define DSI_VVBPCCR_VBP0_Pos (0U)
20728 #define DSI_VVBPCCR_VBP0_Msk (0x1U << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */
20729 #define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
20730 #define DSI_VVBPCCR_VBP1_Pos (1U)
20731 #define DSI_VVBPCCR_VBP1_Msk (0x1U << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */
20732 #define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
20733 #define DSI_VVBPCCR_VBP2_Pos (2U)
20734 #define DSI_VVBPCCR_VBP2_Msk (0x1U << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */
20735 #define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
20736 #define DSI_VVBPCCR_VBP3_Pos (3U)
20737 #define DSI_VVBPCCR_VBP3_Msk (0x1U << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */
20738 #define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
20739 #define DSI_VVBPCCR_VBP4_Pos (4U)
20740 #define DSI_VVBPCCR_VBP4_Msk (0x1U << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */
20741 #define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
20742 #define DSI_VVBPCCR_VBP5_Pos (5U)
20743 #define DSI_VVBPCCR_VBP5_Msk (0x1U << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */
20744 #define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
20745 #define DSI_VVBPCCR_VBP6_Pos (6U)
20746 #define DSI_VVBPCCR_VBP6_Msk (0x1U << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */
20747 #define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
20748 #define DSI_VVBPCCR_VBP7_Pos (7U)
20749 #define DSI_VVBPCCR_VBP7_Msk (0x1U << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */
20750 #define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
20751 #define DSI_VVBPCCR_VBP8_Pos (8U)
20752 #define DSI_VVBPCCR_VBP8_Msk (0x1U << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */
20753 #define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
20754 #define DSI_VVBPCCR_VBP9_Pos (9U)
20755 #define DSI_VVBPCCR_VBP9_Msk (0x1U << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */
20756 #define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
20757
20758 /******************* Bit definition for DSI_VVFPCCR register ************/
20759 #define DSI_VVFPCCR_VFP_Pos (0U)
20760 #define DSI_VVFPCCR_VFP_Msk (0x3FFU << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */
20761 #define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */
20762 #define DSI_VVFPCCR_VFP0_Pos (0U)
20763 #define DSI_VVFPCCR_VFP0_Msk (0x1U << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */
20764 #define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
20765 #define DSI_VVFPCCR_VFP1_Pos (1U)
20766 #define DSI_VVFPCCR_VFP1_Msk (0x1U << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */
20767 #define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
20768 #define DSI_VVFPCCR_VFP2_Pos (2U)
20769 #define DSI_VVFPCCR_VFP2_Msk (0x1U << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */
20770 #define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
20771 #define DSI_VVFPCCR_VFP3_Pos (3U)
20772 #define DSI_VVFPCCR_VFP3_Msk (0x1U << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */
20773 #define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
20774 #define DSI_VVFPCCR_VFP4_Pos (4U)
20775 #define DSI_VVFPCCR_VFP4_Msk (0x1U << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */
20776 #define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
20777 #define DSI_VVFPCCR_VFP5_Pos (5U)
20778 #define DSI_VVFPCCR_VFP5_Msk (0x1U << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */
20779 #define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
20780 #define DSI_VVFPCCR_VFP6_Pos (6U)
20781 #define DSI_VVFPCCR_VFP6_Msk (0x1U << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */
20782 #define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
20783 #define DSI_VVFPCCR_VFP7_Pos (7U)
20784 #define DSI_VVFPCCR_VFP7_Msk (0x1U << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */
20785 #define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
20786 #define DSI_VVFPCCR_VFP8_Pos (8U)
20787 #define DSI_VVFPCCR_VFP8_Msk (0x1U << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */
20788 #define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
20789 #define DSI_VVFPCCR_VFP9_Pos (9U)
20790 #define DSI_VVFPCCR_VFP9_Msk (0x1U << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */
20791 #define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
20792
20793 /******************* Bit definition for DSI_VVACCR register *************/
20794 #define DSI_VVACCR_VA_Pos (0U)
20795 #define DSI_VVACCR_VA_Msk (0x3FFFU << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */
20796 #define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */
20797 #define DSI_VVACCR_VA0_Pos (0U)
20798 #define DSI_VVACCR_VA0_Msk (0x1U << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */
20799 #define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
20800 #define DSI_VVACCR_VA1_Pos (1U)
20801 #define DSI_VVACCR_VA1_Msk (0x1U << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */
20802 #define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
20803 #define DSI_VVACCR_VA2_Pos (2U)
20804 #define DSI_VVACCR_VA2_Msk (0x1U << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */
20805 #define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
20806 #define DSI_VVACCR_VA3_Pos (3U)
20807 #define DSI_VVACCR_VA3_Msk (0x1U << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */
20808 #define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
20809 #define DSI_VVACCR_VA4_Pos (4U)
20810 #define DSI_VVACCR_VA4_Msk (0x1U << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */
20811 #define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
20812 #define DSI_VVACCR_VA5_Pos (5U)
20813 #define DSI_VVACCR_VA5_Msk (0x1U << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */
20814 #define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
20815 #define DSI_VVACCR_VA6_Pos (6U)
20816 #define DSI_VVACCR_VA6_Msk (0x1U << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */
20817 #define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
20818 #define DSI_VVACCR_VA7_Pos (7U)
20819 #define DSI_VVACCR_VA7_Msk (0x1U << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */
20820 #define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
20821 #define DSI_VVACCR_VA8_Pos (8U)
20822 #define DSI_VVACCR_VA8_Msk (0x1U << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */
20823 #define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
20824 #define DSI_VVACCR_VA9_Pos (9U)
20825 #define DSI_VVACCR_VA9_Msk (0x1U << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */
20826 #define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
20827 #define DSI_VVACCR_VA10_Pos (10U)
20828 #define DSI_VVACCR_VA10_Msk (0x1U << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */
20829 #define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
20830 #define DSI_VVACCR_VA11_Pos (11U)
20831 #define DSI_VVACCR_VA11_Msk (0x1U << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */
20832 #define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
20833 #define DSI_VVACCR_VA12_Pos (12U)
20834 #define DSI_VVACCR_VA12_Msk (0x1U << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */
20835 #define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
20836 #define DSI_VVACCR_VA13_Pos (13U)
20837 #define DSI_VVACCR_VA13_Msk (0x1U << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */
20838 #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
20839
20840 /******************* Bit definition for DSI_TDCCR register **************/
20841 #define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
20842 #define DSI_TDCCR_3DM0 0x00000001U
20843 #define DSI_TDCCR_3DM1 0x00000002U
20844
20845 #define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
20846 #define DSI_TDCCR_3DF0 0x00000004U
20847 #define DSI_TDCCR_3DF1 0x00000008U
20848
20849 #define DSI_TDCCR_SVS_Pos (4U)
20850 #define DSI_TDCCR_SVS_Msk (0x1U << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
20851 #define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */
20852 #define DSI_TDCCR_RF_Pos (5U)
20853 #define DSI_TDCCR_RF_Msk (0x1U << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */
20854 #define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */
20855 #define DSI_TDCCR_S3DC_Pos (16U)
20856 #define DSI_TDCCR_S3DC_Msk (0x1U << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */
20857 #define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */
20858
20859 /******************* Bit definition for DSI_WCFGR register ***************/
20860 #define DSI_WCFGR_DSIM_Pos (0U)
20861 #define DSI_WCFGR_DSIM_Msk (0x1U << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */
20862 #define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */
20863 #define DSI_WCFGR_COLMUX_Pos (1U)
20864 #define DSI_WCFGR_COLMUX_Msk (0x7U << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */
20865 #define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */
20866 #define DSI_WCFGR_COLMUX0_Pos (1U)
20867 #define DSI_WCFGR_COLMUX0_Msk (0x1U << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */
20868 #define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
20869 #define DSI_WCFGR_COLMUX1_Pos (2U)
20870 #define DSI_WCFGR_COLMUX1_Msk (0x1U << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */
20871 #define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
20872 #define DSI_WCFGR_COLMUX2_Pos (3U)
20873 #define DSI_WCFGR_COLMUX2_Msk (0x1U << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */
20874 #define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
20875
20876 #define DSI_WCFGR_TESRC_Pos (4U)
20877 #define DSI_WCFGR_TESRC_Msk (0x1U << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */
20878 #define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */
20879 #define DSI_WCFGR_TEPOL_Pos (5U)
20880 #define DSI_WCFGR_TEPOL_Msk (0x1U << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */
20881 #define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */
20882 #define DSI_WCFGR_AR_Pos (6U)
20883 #define DSI_WCFGR_AR_Msk (0x1U << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */
20884 #define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */
20885 #define DSI_WCFGR_VSPOL_Pos (7U)
20886 #define DSI_WCFGR_VSPOL_Msk (0x1U << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */
20887 #define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */
20888
20889 /******************* Bit definition for DSI_WCR register *****************/
20890 #define DSI_WCR_COLM_Pos (0U)
20891 #define DSI_WCR_COLM_Msk (0x1U << DSI_WCR_COLM_Pos) /*!< 0x00000001 */
20892 #define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */
20893 #define DSI_WCR_SHTDN_Pos (1U)
20894 #define DSI_WCR_SHTDN_Msk (0x1U << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */
20895 #define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */
20896 #define DSI_WCR_LTDCEN_Pos (2U)
20897 #define DSI_WCR_LTDCEN_Msk (0x1U << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */
20898 #define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */
20899 #define DSI_WCR_DSIEN_Pos (3U)
20900 #define DSI_WCR_DSIEN_Msk (0x1U << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */
20901 #define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */
20902
20903 /******************* Bit definition for DSI_WIER register ****************/
20904 #define DSI_WIER_TEIE_Pos (0U)
20905 #define DSI_WIER_TEIE_Msk (0x1U << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */
20906 #define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */
20907 #define DSI_WIER_ERIE_Pos (1U)
20908 #define DSI_WIER_ERIE_Msk (0x1U << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */
20909 #define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */
20910 #define DSI_WIER_PLLLIE_Pos (9U)
20911 #define DSI_WIER_PLLLIE_Msk (0x1U << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */
20912 #define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */
20913 #define DSI_WIER_PLLUIE_Pos (10U)
20914 #define DSI_WIER_PLLUIE_Msk (0x1U << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */
20915 #define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */
20916 #define DSI_WIER_RRIE_Pos (13U)
20917 #define DSI_WIER_RRIE_Msk (0x1U << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */
20918 #define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */
20919
20920 /******************* Bit definition for DSI_WISR register ****************/
20921 #define DSI_WISR_TEIF_Pos (0U)
20922 #define DSI_WISR_TEIF_Msk (0x1U << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */
20923 #define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */
20924 #define DSI_WISR_ERIF_Pos (1U)
20925 #define DSI_WISR_ERIF_Msk (0x1U << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */
20926 #define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */
20927 #define DSI_WISR_BUSY_Pos (2U)
20928 #define DSI_WISR_BUSY_Msk (0x1U << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */
20929 #define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */
20930 #define DSI_WISR_PLLLS_Pos (8U)
20931 #define DSI_WISR_PLLLS_Msk (0x1U << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */
20932 #define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */
20933 #define DSI_WISR_PLLLIF_Pos (9U)
20934 #define DSI_WISR_PLLLIF_Msk (0x1U << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */
20935 #define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */
20936 #define DSI_WISR_PLLUIF_Pos (10U)
20937 #define DSI_WISR_PLLUIF_Msk (0x1U << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */
20938 #define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */
20939 #define DSI_WISR_RRS_Pos (12U)
20940 #define DSI_WISR_RRS_Msk (0x1U << DSI_WISR_RRS_Pos) /*!< 0x00001000 */
20941 #define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */
20942 #define DSI_WISR_RRIF_Pos (13U)
20943 #define DSI_WISR_RRIF_Msk (0x1U << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */
20944 #define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */
20945
20946 /******************* Bit definition for DSI_WIFCR register ***************/
20947 #define DSI_WIFCR_CTEIF_Pos (0U)
20948 #define DSI_WIFCR_CTEIF_Msk (0x1U << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */
20949 #define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */
20950 #define DSI_WIFCR_CERIF_Pos (1U)
20951 #define DSI_WIFCR_CERIF_Msk (0x1U << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */
20952 #define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */
20953 #define DSI_WIFCR_CPLLLIF_Pos (9U)
20954 #define DSI_WIFCR_CPLLLIF_Msk (0x1U << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */
20955 #define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */
20956 #define DSI_WIFCR_CPLLUIF_Pos (10U)
20957 #define DSI_WIFCR_CPLLUIF_Msk (0x1U << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */
20958 #define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */
20959 #define DSI_WIFCR_CRRIF_Pos (13U)
20960 #define DSI_WIFCR_CRRIF_Msk (0x1U << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */
20961 #define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */
20962
20963 /******************* Bit definition for DSI_WPCR0 register ***************/
20964 #define DSI_WPCR0_UIX4_Pos (0U)
20965 #define DSI_WPCR0_UIX4_Msk (0x3FU << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */
20966 #define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */
20967 #define DSI_WPCR0_UIX4_0 (0x01U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */
20968 #define DSI_WPCR0_UIX4_1 (0x02U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */
20969 #define DSI_WPCR0_UIX4_2 (0x04U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */
20970 #define DSI_WPCR0_UIX4_3 (0x08U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */
20971 #define DSI_WPCR0_UIX4_4 (0x10U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */
20972 #define DSI_WPCR0_UIX4_5 (0x20U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */
20973
20974 #define DSI_WPCR0_SWCL_Pos (6U)
20975 #define DSI_WPCR0_SWCL_Msk (0x1U << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */
20976 #define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */
20977 #define DSI_WPCR0_SWDL0_Pos (7U)
20978 #define DSI_WPCR0_SWDL0_Msk (0x1U << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */
20979 #define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */
20980 #define DSI_WPCR0_SWDL1_Pos (8U)
20981 #define DSI_WPCR0_SWDL1_Msk (0x1U << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */
20982 #define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */
20983 #define DSI_WPCR0_HSICL_Pos (9U)
20984 #define DSI_WPCR0_HSICL_Msk (0x1U << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */
20985 #define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */
20986 #define DSI_WPCR0_HSIDL0_Pos (10U)
20987 #define DSI_WPCR0_HSIDL0_Msk (0x1U << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */
20988 #define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */
20989 #define DSI_WPCR0_HSIDL1_Pos (11U)
20990 #define DSI_WPCR0_HSIDL1_Msk (0x1U << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */
20991 #define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */
20992 #define DSI_WPCR0_FTXSMCL_Pos (12U)
20993 #define DSI_WPCR0_FTXSMCL_Msk (0x1U << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */
20994 #define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */
20995 #define DSI_WPCR0_FTXSMDL_Pos (13U)
20996 #define DSI_WPCR0_FTXSMDL_Msk (0x1U << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */
20997 #define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */
20998 #define DSI_WPCR0_CDOFFDL_Pos (14U)
20999 #define DSI_WPCR0_CDOFFDL_Msk (0x1U << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */
21000 #define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */
21001 #define DSI_WPCR0_TDDL_Pos (16U)
21002 #define DSI_WPCR0_TDDL_Msk (0x1U << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */
21003 #define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */
21004 #define DSI_WPCR0_PDEN_Pos (18U)
21005 #define DSI_WPCR0_PDEN_Msk (0x1U << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */
21006 #define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */
21007 #define DSI_WPCR0_TCLKPREPEN_Pos (19U)
21008 #define DSI_WPCR0_TCLKPREPEN_Msk (0x1U << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */
21009 #define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */
21010 #define DSI_WPCR0_TCLKZEROEN_Pos (20U)
21011 #define DSI_WPCR0_TCLKZEROEN_Msk (0x1U << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */
21012 #define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */
21013 #define DSI_WPCR0_THSPREPEN_Pos (21U)
21014 #define DSI_WPCR0_THSPREPEN_Msk (0x1U << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */
21015 #define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */
21016 #define DSI_WPCR0_THSTRAILEN_Pos (22U)
21017 #define DSI_WPCR0_THSTRAILEN_Msk (0x1U << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */
21018 #define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */
21019 #define DSI_WPCR0_THSZEROEN_Pos (23U)
21020 #define DSI_WPCR0_THSZEROEN_Msk (0x1U << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */
21021 #define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */
21022 #define DSI_WPCR0_TLPXDEN_Pos (24U)
21023 #define DSI_WPCR0_TLPXDEN_Msk (0x1U << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */
21024 #define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */
21025 #define DSI_WPCR0_THSEXITEN_Pos (25U)
21026 #define DSI_WPCR0_THSEXITEN_Msk (0x1U << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */
21027 #define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */
21028 #define DSI_WPCR0_TLPXCEN_Pos (26U)
21029 #define DSI_WPCR0_TLPXCEN_Msk (0x1U << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */
21030 #define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */
21031 #define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
21032 #define DSI_WPCR0_TCLKPOSTEN_Msk (0x1U << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */
21033 #define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */
21034
21035 /******************* Bit definition for DSI_WPCR1 register ***************/
21036 #define DSI_WPCR1_HSTXDCL_Pos (0U)
21037 #define DSI_WPCR1_HSTXDCL_Msk (0x3U << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */
21038 #define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
21039 #define DSI_WPCR1_HSTXDCL0_Pos (0U)
21040 #define DSI_WPCR1_HSTXDCL0_Msk (0x1U << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */
21041 #define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
21042 #define DSI_WPCR1_HSTXDCL1_Pos (1U)
21043 #define DSI_WPCR1_HSTXDCL1_Msk (0x1U << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */
21044 #define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
21045
21046 #define DSI_WPCR1_HSTXDDL_Pos (2U)
21047 #define DSI_WPCR1_HSTXDDL_Msk (0x3U << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */
21048 #define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
21049 #define DSI_WPCR1_HSTXDDL0_Pos (2U)
21050 #define DSI_WPCR1_HSTXDDL0_Msk (0x1U << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */
21051 #define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
21052 #define DSI_WPCR1_HSTXDDL1_Pos (3U)
21053 #define DSI_WPCR1_HSTXDDL1_Msk (0x1U << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */
21054 #define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
21055
21056 #define DSI_WPCR1_LPSRCCL_Pos (6U)
21057 #define DSI_WPCR1_LPSRCCL_Msk (0x3U << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */
21058 #define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
21059 #define DSI_WPCR1_LPSRCCL0_Pos (6U)
21060 #define DSI_WPCR1_LPSRCCL0_Msk (0x1U << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */
21061 #define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
21062 #define DSI_WPCR1_LPSRCCL1_Pos (7U)
21063 #define DSI_WPCR1_LPSRCCL1_Msk (0x1U << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */
21064 #define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
21065
21066 #define DSI_WPCR1_LPSRCDL_Pos (8U)
21067 #define DSI_WPCR1_LPSRCDL_Msk (0x3U << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */
21068 #define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
21069 #define DSI_WPCR1_LPSRCDL0_Pos (8U)
21070 #define DSI_WPCR1_LPSRCDL0_Msk (0x1U << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */
21071 #define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
21072 #define DSI_WPCR1_LPSRCDL1_Pos (9U)
21073 #define DSI_WPCR1_LPSRCDL1_Msk (0x1U << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */
21074 #define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
21075
21076 #define DSI_WPCR1_SDDC_Pos (12U)
21077 #define DSI_WPCR1_SDDC_Msk (0x1U << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */
21078 #define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */
21079
21080 #define DSI_WPCR1_LPRXVCDL_Pos (14U)
21081 #define DSI_WPCR1_LPRXVCDL_Msk (0x3U << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */
21082 #define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */
21083 #define DSI_WPCR1_LPRXVCDL0_Pos (14U)
21084 #define DSI_WPCR1_LPRXVCDL0_Msk (0x1U << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */
21085 #define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
21086 #define DSI_WPCR1_LPRXVCDL1_Pos (15U)
21087 #define DSI_WPCR1_LPRXVCDL1_Msk (0x1U << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */
21088 #define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
21089
21090 #define DSI_WPCR1_HSTXSRCCL_Pos (16U)
21091 #define DSI_WPCR1_HSTXSRCCL_Msk (0x3U << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */
21092 #define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
21093 #define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
21094 #define DSI_WPCR1_HSTXSRCCL0_Msk (0x1U << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */
21095 #define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
21096 #define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
21097 #define DSI_WPCR1_HSTXSRCCL1_Msk (0x1U << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */
21098 #define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
21099
21100 #define DSI_WPCR1_HSTXSRCDL_Pos (18U)
21101 #define DSI_WPCR1_HSTXSRCDL_Msk (0x3U << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */
21102 #define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
21103 #define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
21104 #define DSI_WPCR1_HSTXSRCDL0_Msk (0x1U << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */
21105 #define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
21106 #define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
21107 #define DSI_WPCR1_HSTXSRCDL1_Msk (0x1U << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */
21108 #define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
21109
21110 #define DSI_WPCR1_FLPRXLPM_Pos (22U)
21111 #define DSI_WPCR1_FLPRXLPM_Msk (0x1U << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */
21112 #define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
21113
21114 #define DSI_WPCR1_LPRXFT_Pos (25U)
21115 #define DSI_WPCR1_LPRXFT_Msk (0x3U << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */
21116 #define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */
21117 #define DSI_WPCR1_LPRXFT0_Pos (25U)
21118 #define DSI_WPCR1_LPRXFT0_Msk (0x1U << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */
21119 #define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
21120 #define DSI_WPCR1_LPRXFT1_Pos (26U)
21121 #define DSI_WPCR1_LPRXFT1_Msk (0x1U << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */
21122 #define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
21123
21124 /******************* Bit definition for DSI_WPCR2 register ***************/
21125 #define DSI_WPCR2_TCLKPREP_Pos (0U)
21126 #define DSI_WPCR2_TCLKPREP_Msk (0xFFU << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */
21127 #define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
21128 #define DSI_WPCR2_TCLKPREP0_Pos (0U)
21129 #define DSI_WPCR2_TCLKPREP0_Msk (0x1U << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */
21130 #define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
21131 #define DSI_WPCR2_TCLKPREP1_Pos (1U)
21132 #define DSI_WPCR2_TCLKPREP1_Msk (0x1U << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */
21133 #define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
21134 #define DSI_WPCR2_TCLKPREP2_Pos (2U)
21135 #define DSI_WPCR2_TCLKPREP2_Msk (0x1U << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */
21136 #define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
21137 #define DSI_WPCR2_TCLKPREP3_Pos (3U)
21138 #define DSI_WPCR2_TCLKPREP3_Msk (0x1U << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */
21139 #define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
21140 #define DSI_WPCR2_TCLKPREP4_Pos (4U)
21141 #define DSI_WPCR2_TCLKPREP4_Msk (0x1U << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */
21142 #define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
21143 #define DSI_WPCR2_TCLKPREP5_Pos (5U)
21144 #define DSI_WPCR2_TCLKPREP5_Msk (0x1U << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */
21145 #define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
21146 #define DSI_WPCR2_TCLKPREP6_Pos (6U)
21147 #define DSI_WPCR2_TCLKPREP6_Msk (0x1U << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */
21148 #define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
21149 #define DSI_WPCR2_TCLKPREP7_Pos (7U)
21150 #define DSI_WPCR2_TCLKPREP7_Msk (0x1U << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */
21151 #define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
21152
21153 #define DSI_WPCR2_TCLKZERO_Pos (8U)
21154 #define DSI_WPCR2_TCLKZERO_Msk (0xFFU << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */
21155 #define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
21156 #define DSI_WPCR2_TCLKZERO0_Pos (8U)
21157 #define DSI_WPCR2_TCLKZERO0_Msk (0x1U << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */
21158 #define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
21159 #define DSI_WPCR2_TCLKZERO1_Pos (9U)
21160 #define DSI_WPCR2_TCLKZERO1_Msk (0x1U << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */
21161 #define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
21162 #define DSI_WPCR2_TCLKZERO2_Pos (10U)
21163 #define DSI_WPCR2_TCLKZERO2_Msk (0x1U << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */
21164 #define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
21165 #define DSI_WPCR2_TCLKZERO3_Pos (11U)
21166 #define DSI_WPCR2_TCLKZERO3_Msk (0x1U << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */
21167 #define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
21168 #define DSI_WPCR2_TCLKZERO4_Pos (12U)
21169 #define DSI_WPCR2_TCLKZERO4_Msk (0x1U << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */
21170 #define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
21171 #define DSI_WPCR2_TCLKZERO5_Pos (13U)
21172 #define DSI_WPCR2_TCLKZERO5_Msk (0x1U << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */
21173 #define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
21174 #define DSI_WPCR2_TCLKZERO6_Pos (14U)
21175 #define DSI_WPCR2_TCLKZERO6_Msk (0x1U << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */
21176 #define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
21177 #define DSI_WPCR2_TCLKZERO7_Pos (15U)
21178 #define DSI_WPCR2_TCLKZERO7_Msk (0x1U << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */
21179 #define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
21180
21181 #define DSI_WPCR2_THSPREP_Pos (16U)
21182 #define DSI_WPCR2_THSPREP_Msk (0xFFU << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */
21183 #define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
21184 #define DSI_WPCR2_THSPREP0_Pos (16U)
21185 #define DSI_WPCR2_THSPREP0_Msk (0x1U << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */
21186 #define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
21187 #define DSI_WPCR2_THSPREP1_Pos (17U)
21188 #define DSI_WPCR2_THSPREP1_Msk (0x1U << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */
21189 #define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
21190 #define DSI_WPCR2_THSPREP2_Pos (18U)
21191 #define DSI_WPCR2_THSPREP2_Msk (0x1U << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */
21192 #define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
21193 #define DSI_WPCR2_THSPREP3_Pos (19U)
21194 #define DSI_WPCR2_THSPREP3_Msk (0x1U << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */
21195 #define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
21196 #define DSI_WPCR2_THSPREP4_Pos (20U)
21197 #define DSI_WPCR2_THSPREP4_Msk (0x1U << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */
21198 #define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
21199 #define DSI_WPCR2_THSPREP5_Pos (21U)
21200 #define DSI_WPCR2_THSPREP5_Msk (0x1U << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */
21201 #define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
21202 #define DSI_WPCR2_THSPREP6_Pos (22U)
21203 #define DSI_WPCR2_THSPREP6_Msk (0x1U << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */
21204 #define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
21205 #define DSI_WPCR2_THSPREP7_Pos (23U)
21206 #define DSI_WPCR2_THSPREP7_Msk (0x1U << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */
21207 #define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
21208
21209 #define DSI_WPCR2_THSTRAIL_Pos (24U)
21210 #define DSI_WPCR2_THSTRAIL_Msk (0xFFU << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */
21211 #define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
21212 #define DSI_WPCR2_THSTRAIL0_Pos (24U)
21213 #define DSI_WPCR2_THSTRAIL0_Msk (0x1U << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */
21214 #define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
21215 #define DSI_WPCR2_THSTRAIL1_Pos (25U)
21216 #define DSI_WPCR2_THSTRAIL1_Msk (0x1U << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */
21217 #define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
21218 #define DSI_WPCR2_THSTRAIL2_Pos (26U)
21219 #define DSI_WPCR2_THSTRAIL2_Msk (0x1U << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */
21220 #define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
21221 #define DSI_WPCR2_THSTRAIL3_Pos (27U)
21222 #define DSI_WPCR2_THSTRAIL3_Msk (0x1U << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */
21223 #define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
21224 #define DSI_WPCR2_THSTRAIL4_Pos (28U)
21225 #define DSI_WPCR2_THSTRAIL4_Msk (0x1U << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */
21226 #define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
21227 #define DSI_WPCR2_THSTRAIL5_Pos (29U)
21228 #define DSI_WPCR2_THSTRAIL5_Msk (0x1U << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */
21229 #define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
21230 #define DSI_WPCR2_THSTRAIL6_Pos (30U)
21231 #define DSI_WPCR2_THSTRAIL6_Msk (0x1U << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */
21232 #define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
21233 #define DSI_WPCR2_THSTRAIL7_Pos (31U)
21234 #define DSI_WPCR2_THSTRAIL7_Msk (0x1U << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */
21235 #define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
21236
21237 /******************* Bit definition for DSI_WPCR3 register ***************/
21238 #define DSI_WPCR3_THSZERO_Pos (0U)
21239 #define DSI_WPCR3_THSZERO_Msk (0xFFU << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */
21240 #define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
21241 #define DSI_WPCR3_THSZERO0_Pos (0U)
21242 #define DSI_WPCR3_THSZERO0_Msk (0x1U << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */
21243 #define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
21244 #define DSI_WPCR3_THSZERO1_Pos (1U)
21245 #define DSI_WPCR3_THSZERO1_Msk (0x1U << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */
21246 #define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
21247 #define DSI_WPCR3_THSZERO2_Pos (2U)
21248 #define DSI_WPCR3_THSZERO2_Msk (0x1U << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */
21249 #define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
21250 #define DSI_WPCR3_THSZERO3_Pos (3U)
21251 #define DSI_WPCR3_THSZERO3_Msk (0x1U << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */
21252 #define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
21253 #define DSI_WPCR3_THSZERO4_Pos (4U)
21254 #define DSI_WPCR3_THSZERO4_Msk (0x1U << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */
21255 #define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
21256 #define DSI_WPCR3_THSZERO5_Pos (5U)
21257 #define DSI_WPCR3_THSZERO5_Msk (0x1U << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */
21258 #define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
21259 #define DSI_WPCR3_THSZERO6_Pos (6U)
21260 #define DSI_WPCR3_THSZERO6_Msk (0x1U << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */
21261 #define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
21262 #define DSI_WPCR3_THSZERO7_Pos (7U)
21263 #define DSI_WPCR3_THSZERO7_Msk (0x1U << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */
21264 #define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
21265
21266 #define DSI_WPCR3_TLPXD_Pos (8U)
21267 #define DSI_WPCR3_TLPXD_Msk (0xFFU << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */
21268 #define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
21269 #define DSI_WPCR3_TLPXD0_Pos (8U)
21270 #define DSI_WPCR3_TLPXD0_Msk (0x1U << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */
21271 #define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
21272 #define DSI_WPCR3_TLPXD1_Pos (9U)
21273 #define DSI_WPCR3_TLPXD1_Msk (0x1U << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */
21274 #define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
21275 #define DSI_WPCR3_TLPXD2_Pos (10U)
21276 #define DSI_WPCR3_TLPXD2_Msk (0x1U << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */
21277 #define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
21278 #define DSI_WPCR3_TLPXD3_Pos (11U)
21279 #define DSI_WPCR3_TLPXD3_Msk (0x1U << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */
21280 #define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
21281 #define DSI_WPCR3_TLPXD4_Pos (12U)
21282 #define DSI_WPCR3_TLPXD4_Msk (0x1U << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */
21283 #define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
21284 #define DSI_WPCR3_TLPXD5_Pos (13U)
21285 #define DSI_WPCR3_TLPXD5_Msk (0x1U << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */
21286 #define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
21287 #define DSI_WPCR3_TLPXD6_Pos (14U)
21288 #define DSI_WPCR3_TLPXD6_Msk (0x1U << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */
21289 #define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
21290 #define DSI_WPCR3_TLPXD7_Pos (15U)
21291 #define DSI_WPCR3_TLPXD7_Msk (0x1U << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */
21292 #define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
21293
21294 #define DSI_WPCR3_THSEXIT_Pos (16U)
21295 #define DSI_WPCR3_THSEXIT_Msk (0xFFU << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */
21296 #define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
21297 #define DSI_WPCR3_THSEXIT0_Pos (16U)
21298 #define DSI_WPCR3_THSEXIT0_Msk (0x1U << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */
21299 #define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
21300 #define DSI_WPCR3_THSEXIT1_Pos (17U)
21301 #define DSI_WPCR3_THSEXIT1_Msk (0x1U << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */
21302 #define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
21303 #define DSI_WPCR3_THSEXIT2_Pos (18U)
21304 #define DSI_WPCR3_THSEXIT2_Msk (0x1U << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */
21305 #define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
21306 #define DSI_WPCR3_THSEXIT3_Pos (19U)
21307 #define DSI_WPCR3_THSEXIT3_Msk (0x1U << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */
21308 #define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
21309 #define DSI_WPCR3_THSEXIT4_Pos (20U)
21310 #define DSI_WPCR3_THSEXIT4_Msk (0x1U << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */
21311 #define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
21312 #define DSI_WPCR3_THSEXIT5_Pos (21U)
21313 #define DSI_WPCR3_THSEXIT5_Msk (0x1U << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */
21314 #define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
21315 #define DSI_WPCR3_THSEXIT6_Pos (22U)
21316 #define DSI_WPCR3_THSEXIT6_Msk (0x1U << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */
21317 #define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
21318 #define DSI_WPCR3_THSEXIT7_Pos (23U)
21319 #define DSI_WPCR3_THSEXIT7_Msk (0x1U << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */
21320 #define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
21321
21322 #define DSI_WPCR3_TLPXC_Pos (24U)
21323 #define DSI_WPCR3_TLPXC_Msk (0xFFU << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */
21324 #define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
21325 #define DSI_WPCR3_TLPXC0_Pos (24U)
21326 #define DSI_WPCR3_TLPXC0_Msk (0x1U << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */
21327 #define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
21328 #define DSI_WPCR3_TLPXC1_Pos (25U)
21329 #define DSI_WPCR3_TLPXC1_Msk (0x1U << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */
21330 #define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
21331 #define DSI_WPCR3_TLPXC2_Pos (26U)
21332 #define DSI_WPCR3_TLPXC2_Msk (0x1U << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */
21333 #define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
21334 #define DSI_WPCR3_TLPXC3_Pos (27U)
21335 #define DSI_WPCR3_TLPXC3_Msk (0x1U << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */
21336 #define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
21337 #define DSI_WPCR3_TLPXC4_Pos (28U)
21338 #define DSI_WPCR3_TLPXC4_Msk (0x1U << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */
21339 #define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
21340 #define DSI_WPCR3_TLPXC5_Pos (29U)
21341 #define DSI_WPCR3_TLPXC5_Msk (0x1U << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */
21342 #define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
21343 #define DSI_WPCR3_TLPXC6_Pos (30U)
21344 #define DSI_WPCR3_TLPXC6_Msk (0x1U << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */
21345 #define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
21346 #define DSI_WPCR3_TLPXC7_Pos (31U)
21347 #define DSI_WPCR3_TLPXC7_Msk (0x1U << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */
21348 #define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
21349
21350 /******************* Bit definition for DSI_WPCR4 register ***************/
21351 #define DSI_WPCR4_TCLKPOST_Pos (0U)
21352 #define DSI_WPCR4_TCLKPOST_Msk (0xFFU << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */
21353 #define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
21354 #define DSI_WPCR4_TCLKPOST0_Pos (0U)
21355 #define DSI_WPCR4_TCLKPOST0_Msk (0x1U << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */
21356 #define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
21357 #define DSI_WPCR4_TCLKPOST1_Pos (1U)
21358 #define DSI_WPCR4_TCLKPOST1_Msk (0x1U << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */
21359 #define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
21360 #define DSI_WPCR4_TCLKPOST2_Pos (2U)
21361 #define DSI_WPCR4_TCLKPOST2_Msk (0x1U << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */
21362 #define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
21363 #define DSI_WPCR4_TCLKPOST3_Pos (3U)
21364 #define DSI_WPCR4_TCLKPOST3_Msk (0x1U << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */
21365 #define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
21366 #define DSI_WPCR4_TCLKPOST4_Pos (4U)
21367 #define DSI_WPCR4_TCLKPOST4_Msk (0x1U << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */
21368 #define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
21369 #define DSI_WPCR4_TCLKPOST5_Pos (5U)
21370 #define DSI_WPCR4_TCLKPOST5_Msk (0x1U << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */
21371 #define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
21372 #define DSI_WPCR4_TCLKPOST6_Pos (6U)
21373 #define DSI_WPCR4_TCLKPOST6_Msk (0x1U << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */
21374 #define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
21375 #define DSI_WPCR4_TCLKPOST7_Pos (7U)
21376 #define DSI_WPCR4_TCLKPOST7_Msk (0x1U << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */
21377 #define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
21378
21379 /******************* Bit definition for DSI_WRPCR register ***************/
21380 #define DSI_WRPCR_PLLEN_Pos (0U)
21381 #define DSI_WRPCR_PLLEN_Msk (0x1U << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */
21382 #define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */
21383 #define DSI_WRPCR_PLL_NDIV_Pos (2U)
21384 #define DSI_WRPCR_PLL_NDIV_Msk (0x7FU << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */
21385 #define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */
21386 #define DSI_WRPCR_PLL_NDIV0_Pos (2U)
21387 #define DSI_WRPCR_PLL_NDIV0_Msk (0x1U << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */
21388 #define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
21389 #define DSI_WRPCR_PLL_NDIV1_Pos (3U)
21390 #define DSI_WRPCR_PLL_NDIV1_Msk (0x1U << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */
21391 #define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
21392 #define DSI_WRPCR_PLL_NDIV2_Pos (4U)
21393 #define DSI_WRPCR_PLL_NDIV2_Msk (0x1U << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */
21394 #define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
21395 #define DSI_WRPCR_PLL_NDIV3_Pos (5U)
21396 #define DSI_WRPCR_PLL_NDIV3_Msk (0x1U << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */
21397 #define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
21398 #define DSI_WRPCR_PLL_NDIV4_Pos (6U)
21399 #define DSI_WRPCR_PLL_NDIV4_Msk (0x1U << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */
21400 #define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
21401 #define DSI_WRPCR_PLL_NDIV5_Pos (7U)
21402 #define DSI_WRPCR_PLL_NDIV5_Msk (0x1U << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */
21403 #define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
21404 #define DSI_WRPCR_PLL_NDIV6_Pos (8U)
21405 #define DSI_WRPCR_PLL_NDIV6_Msk (0x1U << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */
21406 #define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
21407
21408 #define DSI_WRPCR_PLL_IDF_Pos (11U)
21409 #define DSI_WRPCR_PLL_IDF_Msk (0xFU << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */
21410 #define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */
21411 #define DSI_WRPCR_PLL_IDF0_Pos (11U)
21412 #define DSI_WRPCR_PLL_IDF0_Msk (0x1U << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */
21413 #define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
21414 #define DSI_WRPCR_PLL_IDF1_Pos (12U)
21415 #define DSI_WRPCR_PLL_IDF1_Msk (0x1U << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */
21416 #define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
21417 #define DSI_WRPCR_PLL_IDF2_Pos (13U)
21418 #define DSI_WRPCR_PLL_IDF2_Msk (0x1U << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */
21419 #define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
21420 #define DSI_WRPCR_PLL_IDF3_Pos (14U)
21421 #define DSI_WRPCR_PLL_IDF3_Msk (0x1U << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */
21422 #define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
21423
21424 #define DSI_WRPCR_PLL_ODF_Pos (16U)
21425 #define DSI_WRPCR_PLL_ODF_Msk (0x3U << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */
21426 #define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */
21427 #define DSI_WRPCR_PLL_ODF0_Pos (16U)
21428 #define DSI_WRPCR_PLL_ODF0_Msk (0x1U << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */
21429 #define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
21430 #define DSI_WRPCR_PLL_ODF1_Pos (17U)
21431 #define DSI_WRPCR_PLL_ODF1_Msk (0x1U << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */
21432 #define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
21433
21434 #define DSI_WRPCR_REGEN_Pos (24U)
21435 #define DSI_WRPCR_REGEN_Msk (0x1U << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */
21436 #define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */
21437
21438 /**
21439 * @}
21440 */
21441
21442 /**
21443 * @}
21444 */
21445
21446 /** @addtogroup Exported_macros
21447 * @{
21448 */
21449
21450 /******************************* ADC Instances ********************************/
21451 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
21452 ((__INSTANCE__) == ADC2) || \
21453 ((__INSTANCE__) == ADC3))
21454 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
21455
21456 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
21457
21458 /******************************* CAN Instances ********************************/
21459 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
21460 ((__INSTANCE__) == CAN2) || \
21461 ((__INSTANCE__) == CAN3))
21462 /******************************* CRC Instances ********************************/
21463 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
21464
21465 /******************************* DAC Instances ********************************/
21466 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
21467
21468 /******************************* DCMI Instances *******************************/
21469 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
21470
21471 /****************************** DFSDM Instances *******************************/
21472 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
21473 ((INSTANCE) == DFSDM1_Filter1) || \
21474 ((INSTANCE) == DFSDM1_Filter2) || \
21475 ((INSTANCE) == DFSDM1_Filter3))
21476
21477 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
21478 ((INSTANCE) == DFSDM1_Channel1) || \
21479 ((INSTANCE) == DFSDM1_Channel2) || \
21480 ((INSTANCE) == DFSDM1_Channel3) || \
21481 ((INSTANCE) == DFSDM1_Channel4) || \
21482 ((INSTANCE) == DFSDM1_Channel5) || \
21483 ((INSTANCE) == DFSDM1_Channel6) || \
21484 ((INSTANCE) == DFSDM1_Channel7))
21485
21486 /******************************* DMA2D Instances *******************************/
21487 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
21488
21489 /******************************** DMA Instances *******************************/
21490 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
21491 ((__INSTANCE__) == DMA1_Stream1) || \
21492 ((__INSTANCE__) == DMA1_Stream2) || \
21493 ((__INSTANCE__) == DMA1_Stream3) || \
21494 ((__INSTANCE__) == DMA1_Stream4) || \
21495 ((__INSTANCE__) == DMA1_Stream5) || \
21496 ((__INSTANCE__) == DMA1_Stream6) || \
21497 ((__INSTANCE__) == DMA1_Stream7) || \
21498 ((__INSTANCE__) == DMA2_Stream0) || \
21499 ((__INSTANCE__) == DMA2_Stream1) || \
21500 ((__INSTANCE__) == DMA2_Stream2) || \
21501 ((__INSTANCE__) == DMA2_Stream3) || \
21502 ((__INSTANCE__) == DMA2_Stream4) || \
21503 ((__INSTANCE__) == DMA2_Stream5) || \
21504 ((__INSTANCE__) == DMA2_Stream6) || \
21505 ((__INSTANCE__) == DMA2_Stream7))
21506
21507 /******************************* GPIO Instances *******************************/
21508 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
21509 ((__INSTANCE__) == GPIOB) || \
21510 ((__INSTANCE__) == GPIOC) || \
21511 ((__INSTANCE__) == GPIOD) || \
21512 ((__INSTANCE__) == GPIOE) || \
21513 ((__INSTANCE__) == GPIOF) || \
21514 ((__INSTANCE__) == GPIOG) || \
21515 ((__INSTANCE__) == GPIOH) || \
21516 ((__INSTANCE__) == GPIOI) || \
21517 ((__INSTANCE__) == GPIOJ) || \
21518 ((__INSTANCE__) == GPIOK))
21519
21520 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
21521 ((__INSTANCE__) == GPIOB) || \
21522 ((__INSTANCE__) == GPIOC) || \
21523 ((__INSTANCE__) == GPIOD) || \
21524 ((__INSTANCE__) == GPIOE) || \
21525 ((__INSTANCE__) == GPIOF) || \
21526 ((__INSTANCE__) == GPIOG) || \
21527 ((__INSTANCE__) == GPIOH) || \
21528 ((__INSTANCE__) == GPIOI) || \
21529 ((__INSTANCE__) == GPIOJ) || \
21530 ((__INSTANCE__) == GPIOK))
21531
21532 /****************************** CEC Instances *********************************/
21533 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
21534
21535 /****************************** QSPI Instances *********************************/
21536 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
21537
21538
21539 /******************************** I2C Instances *******************************/
21540 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
21541 ((__INSTANCE__) == I2C2) || \
21542 ((__INSTANCE__) == I2C3) || \
21543 ((__INSTANCE__) == I2C4))
21544
21545 /****************************** SMBUS Instances *******************************/
21546 #define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
21547 ((__INSTANCE__) == I2C2) || \
21548 ((__INSTANCE__) == I2C3) || \
21549 ((__INSTANCE__) == I2C4))
21550
21551
21552 /******************************** I2S Instances *******************************/
21553 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
21554 ((__INSTANCE__) == SPI2) || \
21555 ((__INSTANCE__) == SPI3))
21556
21557 /******************************* LPTIM Instances ********************************/
21558 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
21559
21560 /****************************** LTDC Instances ********************************/
21561 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
21562
21563 /****************************** MDIOS Instances ********************************/
21564 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
21565
21566 /****************************** MDIOS Instances ********************************/
21567 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
21568
21569
21570 /******************************* RNG Instances ********************************/
21571 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
21572
21573 /****************************** RTC Instances *********************************/
21574 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
21575
21576 /******************************* SAI Instances ********************************/
21577 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
21578 ((__PERIPH__) == SAI1_Block_B) || \
21579 ((__PERIPH__) == SAI2_Block_A) || \
21580 ((__PERIPH__) == SAI2_Block_B))
21581 /* Legacy define */
21582 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
21583
21584 /******************************** SDMMC Instances *******************************/
21585 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
21586 ((__INSTANCE__) == SDMMC2))
21587
21588 /****************************** SPDIFRX Instances *********************************/
21589 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
21590
21591 /******************************** SPI Instances *******************************/
21592 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
21593 ((__INSTANCE__) == SPI2) || \
21594 ((__INSTANCE__) == SPI3) || \
21595 ((__INSTANCE__) == SPI4) || \
21596 ((__INSTANCE__) == SPI5) || \
21597 ((__INSTANCE__) == SPI6))
21598
21599 /****************** TIM Instances : All supported instances *******************/
21600 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21601 ((__INSTANCE__) == TIM2) || \
21602 ((__INSTANCE__) == TIM3) || \
21603 ((__INSTANCE__) == TIM4) || \
21604 ((__INSTANCE__) == TIM5) || \
21605 ((__INSTANCE__) == TIM6) || \
21606 ((__INSTANCE__) == TIM7) || \
21607 ((__INSTANCE__) == TIM8) || \
21608 ((__INSTANCE__) == TIM9) || \
21609 ((__INSTANCE__) == TIM10) || \
21610 ((__INSTANCE__) == TIM11) || \
21611 ((__INSTANCE__) == TIM12) || \
21612 ((__INSTANCE__) == TIM13) || \
21613 ((__INSTANCE__) == TIM14))
21614
21615 /****************** TIM Instances : supporting 32 bits counter ****************/
21616 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
21617 ((__INSTANCE__) == TIM5))
21618
21619 /****************** TIM Instances : supporting the break function *************/
21620 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21621 ((INSTANCE) == TIM8))
21622
21623 /************** TIM Instances : supporting Break source selection *************/
21624 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21625 ((INSTANCE) == TIM8))
21626
21627 /****************** TIM Instances : supporting 2 break inputs *****************/
21628 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21629 ((INSTANCE) == TIM8))
21630
21631 /************* TIM Instances : at least 1 capture/compare channel *************/
21632 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21633 ((__INSTANCE__) == TIM2) || \
21634 ((__INSTANCE__) == TIM3) || \
21635 ((__INSTANCE__) == TIM4) || \
21636 ((__INSTANCE__) == TIM5) || \
21637 ((__INSTANCE__) == TIM8) || \
21638 ((__INSTANCE__) == TIM9) || \
21639 ((__INSTANCE__) == TIM10) || \
21640 ((__INSTANCE__) == TIM11) || \
21641 ((__INSTANCE__) == TIM12) || \
21642 ((__INSTANCE__) == TIM13) || \
21643 ((__INSTANCE__) == TIM14))
21644
21645 /************ TIM Instances : at least 2 capture/compare channels *************/
21646 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21647 ((__INSTANCE__) == TIM2) || \
21648 ((__INSTANCE__) == TIM3) || \
21649 ((__INSTANCE__) == TIM4) || \
21650 ((__INSTANCE__) == TIM5) || \
21651 ((__INSTANCE__) == TIM8) || \
21652 ((__INSTANCE__) == TIM9) || \
21653 ((__INSTANCE__) == TIM12))
21654
21655 /************ TIM Instances : at least 3 capture/compare channels *************/
21656 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21657 ((__INSTANCE__) == TIM2) || \
21658 ((__INSTANCE__) == TIM3) || \
21659 ((__INSTANCE__) == TIM4) || \
21660 ((__INSTANCE__) == TIM5) || \
21661 ((__INSTANCE__) == TIM8))
21662
21663 /************ TIM Instances : at least 4 capture/compare channels *************/
21664 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21665 ((__INSTANCE__) == TIM2) || \
21666 ((__INSTANCE__) == TIM3) || \
21667 ((__INSTANCE__) == TIM4) || \
21668 ((__INSTANCE__) == TIM5) || \
21669 ((__INSTANCE__) == TIM8))
21670
21671 /****************** TIM Instances : at least 5 capture/compare channels *******/
21672 #define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21673 ((__INSTANCE__) == TIM8))
21674
21675 /****************** TIM Instances : at least 6 capture/compare channels *******/
21676 #define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21677 ((__INSTANCE__) == TIM8))
21678
21679 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
21680 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21681 ((__INSTANCE__) == TIM8))
21682
21683 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
21684 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21685 ((__INSTANCE__) == TIM8) || \
21686 ((__INSTANCE__) == TIM2) || \
21687 ((__INSTANCE__) == TIM3) || \
21688 ((__INSTANCE__) == TIM4) || \
21689 ((__INSTANCE__) == TIM5) || \
21690 ((__INSTANCE__) == TIM6) || \
21691 ((__INSTANCE__) == TIM7))
21692
21693 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
21694 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21695 ((__INSTANCE__) == TIM2) || \
21696 ((__INSTANCE__) == TIM3) || \
21697 ((__INSTANCE__) == TIM4) || \
21698 ((__INSTANCE__) == TIM5) || \
21699 ((__INSTANCE__) == TIM8))
21700
21701 /******************** TIM Instances : DMA burst feature ***********************/
21702 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21703 ((__INSTANCE__) == TIM2) || \
21704 ((__INSTANCE__) == TIM3) || \
21705 ((__INSTANCE__) == TIM4) || \
21706 ((__INSTANCE__) == TIM5) || \
21707 ((__INSTANCE__) == TIM8))
21708
21709 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
21710 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
21711 (((__INSTANCE__) == TIM1) || \
21712 ((__INSTANCE__) == TIM8))
21713
21714 /****************** TIM Instances : supporting counting mode selection ********/
21715 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21716 ((__INSTANCE__) == TIM2) || \
21717 ((__INSTANCE__) == TIM3) || \
21718 ((__INSTANCE__) == TIM4) || \
21719 ((__INSTANCE__) == TIM5) || \
21720 ((__INSTANCE__) == TIM8))
21721
21722 /****************** TIM Instances : supporting encoder interface **************/
21723 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21724 ((__INSTANCE__) == TIM2) || \
21725 ((__INSTANCE__) == TIM3) || \
21726 ((__INSTANCE__) == TIM4) || \
21727 ((__INSTANCE__) == TIM5) || \
21728 ((__INSTANCE__) == TIM8))
21729
21730 /****************** TIM Instances : supporting OCxREF clear *******************/
21731 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
21732 (((__INSTANCE__) == TIM2) || \
21733 ((__INSTANCE__) == TIM3) || \
21734 ((__INSTANCE__) == TIM4) || \
21735 ((__INSTANCE__) == TIM5))
21736
21737 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
21738 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
21739 (((__INSTANCE__) == TIM1) || \
21740 ((__INSTANCE__) == TIM2) || \
21741 ((__INSTANCE__) == TIM3) || \
21742 ((__INSTANCE__) == TIM4) || \
21743 ((__INSTANCE__) == TIM5) || \
21744 ((__INSTANCE__) == TIM8))
21745
21746 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
21747 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
21748 (((__INSTANCE__) == TIM1) || \
21749 ((__INSTANCE__) == TIM2) || \
21750 ((__INSTANCE__) == TIM3) || \
21751 ((__INSTANCE__) == TIM4) || \
21752 ((__INSTANCE__) == TIM5) || \
21753 ((__INSTANCE__) == TIM8))
21754
21755 /******************** TIM Instances : Advanced-control timers *****************/
21756 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21757 ((__INSTANCE__) == TIM8))
21758
21759 /******************* TIM Instances : Timer input XOR function *****************/
21760 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21761 ((__INSTANCE__) == TIM2) || \
21762 ((__INSTANCE__) == TIM3) || \
21763 ((__INSTANCE__) == TIM4) || \
21764 ((__INSTANCE__) == TIM5) || \
21765 ((__INSTANCE__) == TIM8))
21766
21767 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
21768 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21769 ((__INSTANCE__) == TIM2) || \
21770 ((__INSTANCE__) == TIM3) || \
21771 ((__INSTANCE__) == TIM4) || \
21772 ((__INSTANCE__) == TIM5) || \
21773 ((__INSTANCE__) == TIM6) || \
21774 ((__INSTANCE__) == TIM7) || \
21775 ((__INSTANCE__) == TIM8))
21776
21777 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
21778 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21779 ((__INSTANCE__) == TIM2) || \
21780 ((__INSTANCE__) == TIM3) || \
21781 ((__INSTANCE__) == TIM4) || \
21782 ((__INSTANCE__) == TIM5) || \
21783 ((__INSTANCE__) == TIM8) || \
21784 ((__INSTANCE__) == TIM9) || \
21785 ((__INSTANCE__) == TIM12))
21786
21787 /***************** TIM Instances : external trigger input available ************/
21788 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21789 ((__INSTANCE__) == TIM2) || \
21790 ((__INSTANCE__) == TIM3) || \
21791 ((__INSTANCE__) == TIM4) || \
21792 ((__INSTANCE__) == TIM5) || \
21793 ((__INSTANCE__) == TIM8))
21794
21795 /****************** TIM Instances : remapping capability **********************/
21796 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
21797 ((__INSTANCE__) == TIM5) || \
21798 ((__INSTANCE__) == TIM11))
21799
21800 /******************* TIM Instances : output(s) available **********************/
21801 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
21802 ((((__INSTANCE__) == TIM1) && \
21803 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21804 ((__CHANNEL__) == TIM_CHANNEL_2) || \
21805 ((__CHANNEL__) == TIM_CHANNEL_3) || \
21806 ((__CHANNEL__) == TIM_CHANNEL_4) || \
21807 ((__CHANNEL__) == TIM_CHANNEL_5) || \
21808 ((__CHANNEL__) == TIM_CHANNEL_6))) \
21809 || \
21810 (((__INSTANCE__) == TIM2) && \
21811 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21812 ((__CHANNEL__) == TIM_CHANNEL_2) || \
21813 ((__CHANNEL__) == TIM_CHANNEL_3) || \
21814 ((__CHANNEL__) == TIM_CHANNEL_4))) \
21815 || \
21816 (((__INSTANCE__) == TIM3) && \
21817 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21818 ((__CHANNEL__) == TIM_CHANNEL_2) || \
21819 ((__CHANNEL__) == TIM_CHANNEL_3) || \
21820 ((__CHANNEL__) == TIM_CHANNEL_4))) \
21821 || \
21822 (((__INSTANCE__) == TIM4) && \
21823 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21824 ((__CHANNEL__) == TIM_CHANNEL_2) || \
21825 ((__CHANNEL__) == TIM_CHANNEL_3) || \
21826 ((__CHANNEL__) == TIM_CHANNEL_4))) \
21827 || \
21828 (((__INSTANCE__) == TIM5) && \
21829 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21830 ((__CHANNEL__) == TIM_CHANNEL_2) || \
21831 ((__CHANNEL__) == TIM_CHANNEL_3) || \
21832 ((__CHANNEL__) == TIM_CHANNEL_4))) \
21833 || \
21834 (((__INSTANCE__) == TIM8) && \
21835 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21836 ((__CHANNEL__) == TIM_CHANNEL_2) || \
21837 ((__CHANNEL__) == TIM_CHANNEL_3) || \
21838 ((__CHANNEL__) == TIM_CHANNEL_4) || \
21839 ((__CHANNEL__) == TIM_CHANNEL_5) || \
21840 ((__CHANNEL__) == TIM_CHANNEL_6))) \
21841 || \
21842 (((__INSTANCE__) == TIM9) && \
21843 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21844 ((__CHANNEL__) == TIM_CHANNEL_2))) \
21845 || \
21846 (((__INSTANCE__) == TIM10) && \
21847 (((__CHANNEL__) == TIM_CHANNEL_1))) \
21848 || \
21849 (((__INSTANCE__) == TIM11) && \
21850 (((__CHANNEL__) == TIM_CHANNEL_1))) \
21851 || \
21852 (((__INSTANCE__) == TIM12) && \
21853 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21854 ((__CHANNEL__) == TIM_CHANNEL_2))) \
21855 || \
21856 (((__INSTANCE__) == TIM13) && \
21857 (((__CHANNEL__) == TIM_CHANNEL_1))) \
21858 || \
21859 (((__INSTANCE__) == TIM14) && \
21860 (((__CHANNEL__) == TIM_CHANNEL_1))))
21861
21862 /************ TIM Instances : complementary output(s) available ***************/
21863 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
21864 ((((__INSTANCE__) == TIM1) && \
21865 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21866 ((__CHANNEL__) == TIM_CHANNEL_2) || \
21867 ((__CHANNEL__) == TIM_CHANNEL_3))) \
21868 || \
21869 (((__INSTANCE__) == TIM8) && \
21870 (((__CHANNEL__) == TIM_CHANNEL_1) || \
21871 ((__CHANNEL__) == TIM_CHANNEL_2) || \
21872 ((__CHANNEL__) == TIM_CHANNEL_3))))
21873
21874 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
21875 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
21876 (((__INSTANCE__) == TIM1) || \
21877 ((__INSTANCE__) == TIM8) )
21878
21879 /****************** TIM Instances : supporting synchronization ****************/
21880 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
21881 (((__INSTANCE__) == TIM1) || \
21882 ((__INSTANCE__) == TIM2) || \
21883 ((__INSTANCE__) == TIM3) || \
21884 ((__INSTANCE__) == TIM4) || \
21885 ((__INSTANCE__) == TIM5) || \
21886 ((__INSTANCE__) == TIM6) || \
21887 ((__INSTANCE__) == TIM7) || \
21888 ((__INSTANCE__) == TIM8))
21889
21890 /****************** TIM Instances : supporting clock division *****************/
21891 #define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21892 ((__INSTANCE__) == TIM2) || \
21893 ((__INSTANCE__) == TIM3) || \
21894 ((__INSTANCE__) == TIM4) || \
21895 ((__INSTANCE__) == TIM5) || \
21896 ((__INSTANCE__) == TIM8) || \
21897 ((__INSTANCE__) == TIM9) || \
21898 ((__INSTANCE__) == TIM10) || \
21899 ((__INSTANCE__) == TIM11) || \
21900 ((__INSTANCE__) == TIM12) || \
21901 ((__INSTANCE__) == TIM13) || \
21902 ((__INSTANCE__) == TIM14))
21903
21904 /****************** TIM Instances : supporting repetition counter *************/
21905 #define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21906 ((__INSTANCE__) == TIM8))
21907
21908 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
21909 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21910 ((__INSTANCE__) == TIM2) || \
21911 ((__INSTANCE__) == TIM3) || \
21912 ((__INSTANCE__) == TIM4) || \
21913 ((__INSTANCE__) == TIM5) || \
21914 ((__INSTANCE__) == TIM8) || \
21915 ((__INSTANCE__) == TIM9) || \
21916 ((__INSTANCE__) == TIM12))
21917
21918 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
21919 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21920 ((__INSTANCE__) == TIM2) || \
21921 ((__INSTANCE__) == TIM3) || \
21922 ((__INSTANCE__) == TIM4) || \
21923 ((__INSTANCE__) == TIM5) || \
21924 ((__INSTANCE__) == TIM8))
21925
21926 /****************** TIM Instances : supporting Hall sensor interface **********/
21927 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21928 ((__INSTANCE__) == TIM2) || \
21929 ((__INSTANCE__) == TIM3) || \
21930 ((__INSTANCE__) == TIM4) || \
21931 ((__INSTANCE__) == TIM5) || \
21932 ((__INSTANCE__) == TIM8))
21933
21934 /****************** TIM Instances : supporting commutation event generation ***/
21935 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21936 ((__INSTANCE__) == TIM8))
21937
21938 /******************** USART Instances : Synchronous mode **********************/
21939 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
21940 ((__INSTANCE__) == USART2) || \
21941 ((__INSTANCE__) == USART3) || \
21942 ((__INSTANCE__) == USART6))
21943
21944 /******************** UART Instances : Asynchronous mode **********************/
21945 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
21946 ((__INSTANCE__) == USART2) || \
21947 ((__INSTANCE__) == USART3) || \
21948 ((__INSTANCE__) == UART4) || \
21949 ((__INSTANCE__) == UART5) || \
21950 ((__INSTANCE__) == USART6) || \
21951 ((__INSTANCE__) == UART7) || \
21952 ((__INSTANCE__) == UART8))
21953
21954 /****************** UART Instances : Auto Baud Rate detection ****************/
21955 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
21956 ((__INSTANCE__) == USART2) || \
21957 ((__INSTANCE__) == USART3) || \
21958 ((__INSTANCE__) == USART6))
21959
21960 /****************** UART Instances : Driver Enable *****************/
21961 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
21962 ((__INSTANCE__) == USART2) || \
21963 ((__INSTANCE__) == USART3) || \
21964 ((__INSTANCE__) == UART4) || \
21965 ((__INSTANCE__) == UART5) || \
21966 ((__INSTANCE__) == USART6) || \
21967 ((__INSTANCE__) == UART7) || \
21968 ((__INSTANCE__) == UART8))
21969
21970 /******************** UART Instances : Half-Duplex mode **********************/
21971 #define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
21972 ((__INSTANCE__) == USART2) || \
21973 ((__INSTANCE__) == USART3) || \
21974 ((__INSTANCE__) == UART4) || \
21975 ((__INSTANCE__) == UART5) || \
21976 ((__INSTANCE__) == USART6) || \
21977 ((__INSTANCE__) == UART7) || \
21978 ((__INSTANCE__) == UART8))
21979
21980 /****************** UART Instances : Hardware Flow control ********************/
21981 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
21982 ((__INSTANCE__) == USART2) || \
21983 ((__INSTANCE__) == USART3) || \
21984 ((__INSTANCE__) == UART4) || \
21985 ((__INSTANCE__) == UART5) || \
21986 ((__INSTANCE__) == USART6) || \
21987 ((__INSTANCE__) == UART7) || \
21988 ((__INSTANCE__) == UART8))
21989
21990 /******************** UART Instances : LIN mode **********************/
21991 #define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
21992 ((__INSTANCE__) == USART2) || \
21993 ((__INSTANCE__) == USART3) || \
21994 ((__INSTANCE__) == UART4) || \
21995 ((__INSTANCE__) == UART5) || \
21996 ((__INSTANCE__) == USART6) || \
21997 ((__INSTANCE__) == UART7) || \
21998 ((__INSTANCE__) == UART8))
21999
22000 /********************* UART Instances : Smart card mode ***********************/
22001 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22002 ((__INSTANCE__) == USART2) || \
22003 ((__INSTANCE__) == USART3) || \
22004 ((__INSTANCE__) == USART6))
22005
22006 /*********************** UART Instances : IRDA mode ***************************/
22007 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22008 ((__INSTANCE__) == USART2) || \
22009 ((__INSTANCE__) == USART3) || \
22010 ((__INSTANCE__) == UART4) || \
22011 ((__INSTANCE__) == UART5) || \
22012 ((__INSTANCE__) == USART6) || \
22013 ((__INSTANCE__) == UART7) || \
22014 ((__INSTANCE__) == UART8))
22015
22016 /****************************** IWDG Instances ********************************/
22017 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
22018
22019 /****************************** WWDG Instances ********************************/
22020 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
22021
22022
22023 /******************************************************************************/
22024 /* For a painless codes migration between the STM32F7xx device product */
22025 /* lines, the aliases defined below are put in place to overcome the */
22026 /* differences in the interrupt handlers and IRQn definitions. */
22027 /* No need to update developed interrupt code when moving across */
22028 /* product lines within the same STM32F7 Family */
22029 /******************************************************************************/
22030
22031 /* Aliases for __IRQn */
22032 #define RNG_IRQn HASH_RNG_IRQn
22033
22034 /* Aliases for __IRQHandler */
22035 #define RNG_IRQHandler HASH_RNG_IRQHandler
22036
22037 /**
22038 * @}
22039 */
22040
22041 /**
22042 * @}
22043 */
22044
22045 /**
22046 * @}
22047 */
22048
22049 #ifdef __cplusplus
22050 }
22051 #endif /* __cplusplus */
22052
22053 #endif /* __STM32F779xx_H */
22054
22055
22056 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software