lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_hal_pwr.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of PWR HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef STM32H7xx_HAL_PWR_H
  22 #define STM32H7xx_HAL_PWR_H
  23
  24 #ifdef __cplusplus
  25  extern "C" {
  26 #endif /* __cplusplus */
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32h7xx_hal_def.h"
  30
  31 /** @addtogroup STM32H7xx_HAL_Driver
  32   * @{
  33   */
  34
  35 /** @addtogroup PWR
  36   * @{
  37   */
  38
  39 /* Exported types ------------------------------------------------------------*/
  40
  41 /** @defgroup PWR_Exported_Types PWR Exported Types
  42   * @{
  43   */
  44
  45 /**
  46   * @brief  PWR PVD configuration structure definition
  47   */
  48 typedef struct
  49 {
  50   uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
  51                                     parameter can be a value of @ref
  52                                     PWR_PVD_detection_level.
  53                      */
  54
  55   uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD
  56                                 event. This parameter can be a value of @ref
  57                                 PWR_PVD_Mode.
  58                      */
  59 }PWR_PVDTypeDef;
  60
  61 /**
  62   * @}
  63   */
  64
  65 /* Exported constants --------------------------------------------------------*/
  66 /** @defgroup PWR_Exported_Constants PWR Exported Constants
  67   * @{
  68   */
  69
  70 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
  71   * @{
  72   */
  73 #define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector
  74                                                level 0 selection : 1V95       */
  75 #define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector
  76                                                level 1 selection : 2V1        */
  77 #define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector
  78                                                level 2 selection : 2V25       */
  79 #define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector
  80                                                level 3 selection : 2V4        */
  81 #define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector
  82                                                level 4 selection : 2V55       */
  83 #define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector
  84                                                level 5 selection : 2V7        */
  85 #define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector
  86                                                level 6 selection : 2V85       */
  87 #define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage
  88                                                (Compare internally to VREF)   */
  89 /**
  90   * @}
  91   */
  92
  93 /** @defgroup PWR_PVD_Mode PWR PVD Mode
  94   * @{
  95   */
  96 #define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */
  97 #define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */
  98 #define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */
  99 #define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
 100 #define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */
 101 #define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */
 102 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */
 103 /**
 104   * @}
 105   */
 106
 107 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
 108   * @{
 109   */
 110 #define PWR_MAINREGULATOR_ON      (0U)
 111 #define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
 112 /**
 113   * @}
 114   */
 115
 116 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
 117   * @{
 118   */
 119 #define PWR_SLEEPENTRY_WFI  (0x01U)
 120 #define PWR_SLEEPENTRY_WFE  (0x02U)
 121 /**
 122   * @}
 123   */
 124
 125 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
 126   * @{
 127   */
 128 #define PWR_STOPENTRY_WFI  (0x01U)
 129 #define PWR_STOPENTRY_WFE  (0x02U)
 130 /**
 131   * @}
 132   */
 133
 134 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
 135   * @{
 136   */
 137 #if defined(PWR_SRDCR_VOS)
 138 #define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
 139 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)
 140 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)
 141 #define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)
 142 #else
 143 #define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)
 144 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
 145 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
 146 #define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
 147 #endif /* PWR_SRDCR_VOS */
 148 /**
 149   * @}
 150   */
 151
 152 /** @defgroup PWR_Flag PWR Flag
 153   * @{
 154   */
 155 /* PWR CPU flag */
 156 #define PWR_FLAG_STOP       (0x01U)
 157 #if defined (PWR_CPUCR_SBF_D2)
 158 #define PWR_FLAG_SB_D1      (0x02U)
 159 #define PWR_FLAG_SB_D2      (0x03U)
 160 #endif /* defined (PWR_CPUCR_SBF_D2) */
 161 #define PWR_FLAG_SB         (0x04U)
 162 #if defined (DUAL_CORE)
 163 #define PWR_FLAG_CPU_HOLD   (0x05U)
 164 #define PWR_FLAG_CPU2_HOLD  (0x06U)
 165 #define PWR_FLAG2_STOP      (0x07U)
 166 #define PWR_FLAG2_SB_D1     (0x08U)
 167 #define PWR_FLAG2_SB_D2     (0x09U)
 168 #define PWR_FLAG2_SB        (0x0AU)
 169 #endif /* defined (DUAL_CORE) */
 170 #define PWR_FLAG_PVDO       (0x0BU)
 171 #define PWR_FLAG_AVDO       (0x0CU)
 172 #define PWR_FLAG_ACTVOSRDY  (0x0DU)
 173 #define PWR_FLAG_ACTVOS     (0x0EU)
 174 #define PWR_FLAG_BRR        (0x0FU)
 175 #define PWR_FLAG_VOSRDY     (0x10U)
 176 #if defined (SMPS)
 177 #define PWR_FLAG_SMPSEXTRDY (0x11U)
 178 #else
 179 #define PWR_FLAG_SCUEN      (0x11U)
 180 #endif /* defined (SMPS) */
 181 #if defined (PWR_CSR1_MMCVDO)
 182 #define PWR_FLAG_MMCVDO     (0x12U)
 183 #endif /* defined (PWR_CSR1_MMCVDO) */
 184 #define PWR_FLAG_USB33RDY   (0x13U)
 185 #define PWR_FLAG_TEMPH      (0x14U)
 186 #define PWR_FLAG_TEMPL      (0x15U)
 187 #define PWR_FLAG_VBATH      (0x16U)
 188 #define PWR_FLAG_VBATL      (0x17U)
 189
 190 /* PWR Wake up flag */
 191 #define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
 192 #define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
 193 #define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
 194 #define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
 195 #define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
 196 #define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
 197 /**
 198   * @}
 199   */
 200
 201 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
 202   * @{
 203   */
 204 #define  PWR_EWUP_MASK  (0x0FFF3F3FU)
 205 /**
 206   * @}
 207   */
 208
 209 /**
 210   * @}
 211   */
 212 /* Exported macro ------------------------------------------------------------*/
 213 /** @defgroup PWR_Exported_Macro PWR Exported Macro
 214   * @{
 215   */
 216
 217 /** @brief  Configure the main internal regulator output voltage.
 218   * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a
 219   *                         trade-off between performance and power consumption
 220   *                         when the device does not operate at the maximum
 221   *                         frequency (refer to the datasheet for more details).
 222   *          This parameter can be one of the following values:
 223   *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
 224   *                                                Scale 0 mode.
 225   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
 226   *                                                Scale 1 mode.
 227   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
 228   *                                                Scale 2 mode.
 229   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
 230   *                                                Scale 3 mode.
 231   * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines,
 232   *         configuring Voltage Scale 0 is only possible when Vcore is supplied
 233   *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
 234   *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale
 235   *         0 using __HAL_PWR_VOLTAGESCALING_CONFIG().
 236   *         Transition to Voltage Scale 0 is only possible when the system is
 237   *         already in Voltage Scale 1.
 238   *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1
 239   *         then once in Voltage Scale 1 it is possible to switch to another
 240   *         voltage scale.
 241   *         After each regulator voltage setting, wait on VOSRDY flag to be set
 242   *         using macro __HAL_PWR_GET_FLAG().
 243   *         To enter low power mode , and if current regulator voltage is
 244   *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
 245   *         low power mode.
 246   * @retval None.
 247   */
 248 #if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
 249 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
 250 do {                                                                           \
 251       __IO uint32_t tmpreg = 0x00;                                             \
 252       MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
 253       /* Delay after setting the voltage scaling */                            \
 254       tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
 255       UNUSED(tmpreg);                                                          \
 256 } while(0)
 257 #else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */
 258 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
 259 do {                                                                           \
 260       __IO uint32_t tmpreg = 0x00;                                             \
 261       /* Check the voltage scaling to be configured */                         \
 262       if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \
 263       {                                                                        \
 264         /* Configure the Voltage Scaling 1 */                                  \
 265         MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \
 266         /* Delay after setting the voltage scaling */                          \
 267         tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
 268         /* Enable the PWR overdrive */                                         \
 269         SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \
 270         /* Delay after setting the syscfg boost setting */                     \
 271         tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
 272       }                                                                        \
 273       else                                                                     \
 274       {                                                                        \
 275         /* Disable the PWR overdrive */                                        \
 276         CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \
 277         /* Delay after setting the syscfg boost setting */                     \
 278         tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
 279         /* Configure the Voltage Scaling x */                                  \
 280         MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \
 281         /* Delay after setting the voltage scaling */                          \
 282         tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
 283       }                                                                        \
 284       UNUSED(tmpreg);                                                          \
 285 } while(0)
 286 #endif /* PWR_SRDCR_VOS */
 287
 288 /** @brief  Check PWR flags are set or not.
 289   * @param  __FLAG__ : Specifies the flag to check.
 290   *           This parameter can be one of the following values:
 291   *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
 292   *                                 is enabled by the HAL_PWR_EnablePVD()
 293   *                                 function.
 294   *                                 The PVD is stopped by STANDBY mode. For this
 295   *                                 reason, this bit is equal to 0 after STANDBY
 296   *                                 or reset until the PVDE bit is set.
 297   *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
 298   *                                 is enabled by the HAL_PWREx_EnableAVD()
 299   *                                 function. The AVD is stopped by STANDBY mode.
 300   *                                 For this reason, this bit is equal to 0
 301   *                                 after STANDBY or reset until the AVDE bit
 302   *                                 is set.
 303   *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
 304   *                                      voltage scaling output selection is
 305   *                                      ready.
 306   *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
 307   *                                reset when the device wakes up from STANDBY
 308   *                                mode or by a system reset or power-on reset.
 309   *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
 310   *                                   voltage scaling output selection is ready.
 311   *                                mode or by a system reset or power-on reset.
 312   *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
 313   *                                     from regulator is ready.
 314   *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
 315   *                                  equal or above high threshold level.
 316   *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
 317   *                                  equal or below low threshold level.
 318   *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
 319   *                                  or above high threshold level.
 320   *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
 321   *                                  or below low threshold level.
 322   *            @arg PWR_FLAG_STOP : This flag indicates that the system entered
 323   *                                 in STOP mode.
 324   *            @arg PWR_FLAG_SB : This flag indicates that the system entered in
 325   *                               STANDBY mode.
 326   *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
 327   *                                  entered in STANDBY mode.
 328   *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
 329   *                                  entered in STANDBY mode.
 330   *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered
 331   *                                 in STOP mode.
 332   *            @arg PWR_FLAG2_SB : This flag indicates that the system entered
 333   *                                in STANDBY mode.
 334   *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
 335   *                                   entered in STANDBY mode.
 336   *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
 337   *                                   entered in STANDBY mode.
 338   *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
 339   *                                     up with hold.
 340   *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
 341   *                                      up with hold.
 342   *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
 343   *                                       External supply is sready.
 344   *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply
 345   *                                  configuration update is enabled.
 346   *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
 347   *                                   above or equal to 1.2 V.
 348   * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
 349   *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
 350   *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
 351   *         are used for all H7 family lines.
 352   *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
 353   *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
 354   *         dual core lines.
 355   *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
 356   *         family except STM32H7Axxx and STM32H7Bxxx lines.
 357   *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
 358   *         STM32H7Bxxx lines.
 359   *         The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742,
 360   *         STM32H750, STM32H7Axx and STM32H7Bxx lines.
 361   *         The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ,
 362   *         STM32H7BxxQ lines.
 363   * @retval The (__FLAG__) state (TRUE or FALSE).
 364   */
 365 #if defined (DUAL_CORE) /* Dual core lines */
 366 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
 367 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\
 368  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\
 369  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\
 370  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\
 371  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\
 372  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\
 373  ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\
 374  ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\
 375  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\
 376  ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\
 377  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\
 378  ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\
 379  ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\
 380  ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\
 381  ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\
 382  ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\
 383  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\
 384  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\
 385  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\
 386  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\
 387  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
 388 #else /* Single core lines */
 389 #if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */
 390 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
 391 (((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
 392  ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
 393  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
 394  ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\
 395  ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
 396  ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
 397  ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
 398  ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
 399  ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\
 400  ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\
 401  ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
 402  ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
 403  ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
 404  ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
 405  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
 406 #else /* STM32H7Axxx and STM32H7Bxxx lines */
 407 #if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */
 408 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
 409 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
 410  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
 411  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
 412  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
 413  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
 414  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
 415  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
 416  ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
 417  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
 418  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
 419  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
 420  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
 421  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
 422  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
 423 #else /* STM32H7Axx and STM32H7Bxx LDO lines */
 424 #define __HAL_PWR_GET_FLAG(__FLAG__)                                    \
 425 (((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
 426  ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
 427  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
 428  ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
 429  ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
 430  ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
 431  ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
 432  ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
 433  ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
 434  ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
 435  ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
 436  ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
 437  ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
 438  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
 439 #endif /* SMPS */
 440 #endif /* PWR_CPUCR_SBF_D2 */
 441 #endif /* DUAL_CORE */
 442
 443 /** @brief  Check PWR wake up flags are set or not.
 444   * @param  __FLAG__: specifies the wake up flag to check.
 445   *           This parameter can be one of the following values:
 446   *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
 447   *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
 448   *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
 449   *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
 450   *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
 451   *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
 452   * @retval The (__FLAG__) state (TRUE or FALSE).
 453   */
 454 #define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
 455
 456 #if defined (DUAL_CORE)
 457 /** @brief  Clear CPU PWR flags.
 458   * @param  __FLAG__ : Specifies the flag to clear.
 459   * @note   This parameter is not used for the STM32H7 family and is kept as
 460   *         parameter just to maintain compatibility with other families.
 461   * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
 462   *           This parameter can be one of the following values :
 463   *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
 464   *                                 CPU flags.
 465   * @retval None.
 466   */
 467 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \
 468 do {                                        \
 469      SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);   \
 470      SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
 471 } while(0)
 472 #else
 473 /** @brief  Clear CPU PWR flags.
 474   * @param  __FLAG__ : Specifies the flag to clear.
 475   * @note   This parameter is not used for the STM32H7 family and is kept as
 476   *         parameter just to maintain compatibility with other families.
 477   * @note   This macro clear all CPU flags.
 478   *         For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF.
 479   *         For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.
 480   * @retval None.
 481   */
 482 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
 483 #endif /* defined (DUAL_CORE) */
 484
 485 /** @brief  Clear PWR wake up flags.
 486   * @param  __FLAG__ : Specifies the wake up flag to be cleared.
 487   *           This parameter can be one of the following values :
 488   *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
 489   *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
 490   *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
 491   *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
 492   *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
 493   *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
 494   * @retval None.
 495   */
 496 #define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
 497
 498 /**
 499   * @brief Enable the PVD EXTI Line 16.
 500   * @retval None.
 501   */
 502 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
 503
 504 #if defined (DUAL_CORE)
 505 /**
 506   * @brief Enable the PVD EXTI D2 Line 16.
 507   * @retval None.
 508   */
 509 #define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
 510 #endif /* defined (DUAL_CORE) */
 511
 512 /**
 513   * @brief Disable the PVD EXTI Line 16.
 514   * @retval None.
 515   */
 516 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
 517
 518 #if defined (DUAL_CORE)
 519 /**
 520   * @brief Disable the PVD EXTI D2 Line 16.
 521   * @retval None.
 522   */
 523 #define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
 524 #endif /* defined (DUAL_CORE) */
 525
 526 /**
 527   * @brief   Enable event on PVD EXTI Line 16.
 528   * @retval None.
 529   */
 530 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
 531
 532 #if defined (DUAL_CORE)
 533 /**
 534   * @brief Enable event on PVD EXTI D2 Line.
 535   * @retval None.
 536   */
 537 #define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
 538 #endif /* defined (DUAL_CORE) */
 539
 540 /**
 541   * @brief   Disable event on PVD EXTI Line 16.
 542   * @retval None.
 543   */
 544 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
 545
 546 #if defined (DUAL_CORE)
 547 /**
 548   * @brief Disable event on PVD EXTI D2 Line.
 549   * @retval None.
 550   */
 551 #define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
 552 #endif /* defined (DUAL_CORE) */
 553
 554 /**
 555   * @brief Enable the PVD Rising Interrupt Trigger.
 556   * @retval None.
 557   */
 558 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
 559
 560 /**
 561   * @brief Disable the PVD Rising Interrupt Trigger.
 562   * @retval None.
 563   */
 564 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
 565
 566 /**
 567   * @brief Enable the PVD Falling Interrupt Trigger.
 568   * @retval None.
 569   */
 570 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
 571
 572 /**
 573   * @brief Disable the PVD Falling Interrupt Trigger.
 574   * @retval None.
 575   */
 576 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
 577
 578 /**
 579   * @brief Enable the PVD Rising & Falling Interrupt Trigger.
 580   * @retval None.
 581   */
 582 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
 583 do {                                                    \
 584       __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
 585       __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
 586 } while(0);
 587
 588 /**
 589   * @brief Disable the PVD Rising & Falling Interrupt Trigger.
 590   * @retval None.
 591   */
 592 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
 593 do {                                                     \
 594       __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
 595       __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
 596 } while(0);
 597
 598 /**
 599   * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
 600   * @retval EXTI PVD Line Status.
 601   */
 602 #define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
 603
 604 #if defined (DUAL_CORE)
 605 /**
 606   * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
 607   * @retval EXTI D2 PVD Line Status.
 608   */
 609 #define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
 610 #endif /* defined (DUAL_CORE) */
 611
 612 /**
 613   * @brief Clear the PVD EXTI flag.
 614   * @retval None.
 615   */
 616 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
 617
 618 #if defined (DUAL_CORE)
 619 /**
 620   * @brief Clear the PVD EXTI D2 flag.
 621   * @retval None.
 622   */
 623 #define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
 624 #endif /* defined (DUAL_CORE) */
 625
 626 /**
 627   * @brief  Generates a Software interrupt on PVD EXTI line.
 628   * @retval None.
 629   */
 630 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
 631 /**
 632   * @}
 633   */
 634
 635 /* Include PWR HAL Extension module */
 636 #include "stm32h7xx_hal_pwr_ex.h"
 637
 638 /* Exported functions --------------------------------------------------------*/
 639 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
 640   * @{
 641   */
 642
 643 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
 644   * @{
 645   */
 646 /* Initialization and de-initialization functions *****************************/
 647 void HAL_PWR_DeInit(void);
 648 void HAL_PWR_EnableBkUpAccess(void);
 649 void HAL_PWR_DisableBkUpAccess(void);
 650 /**
 651   * @}
 652   */
 653
 654 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
 655   * @{
 656   */
 657 /* Peripheral Control functions  **********************************************/
 658 /* PVD configuration */
 659 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
 660 void HAL_PWR_EnablePVD(void);
 661 void HAL_PWR_DisablePVD(void);
 662
 663 /* WakeUp pins configuration */
 664 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
 665 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
 666
 667 /* Low Power modes entry */
 668 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
 669 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
 670 void HAL_PWR_EnterSTANDBYMode(void);
 671
 672 /* Power PVD IRQ Handler */
 673 void HAL_PWR_PVD_IRQHandler(void);
 674 void HAL_PWR_PVDCallback(void);
 675
 676 /* Cortex System Control functions  *******************************************/
 677 void HAL_PWR_EnableSleepOnExit(void);
 678 void HAL_PWR_DisableSleepOnExit(void);
 679 void HAL_PWR_EnableSEVOnPend(void);
 680 void HAL_PWR_DisableSEVOnPend(void);
 681 /**
 682   * @}
 683   */
 684
 685 /**
 686   * @}
 687   */
 688
 689 /* Private types -------------------------------------------------------------*/
 690 /* Private variables ---------------------------------------------------------*/
 691 /* Private constants ---------------------------------------------------------*/
 692 /** @defgroup PWR_Private_Constants PWR Private Constants
 693   * @{
 694   */
 695
 696 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
 697   * @{
 698   */
 699 #define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16
 700                                                Connected to the PVD EXTI Line */
 701 /**
 702   * @}
 703   */
 704
 705 /**
 706   * @}
 707   */
 708 /* Private macros ------------------------------------------------------------*/
 709 /** @defgroup PWR_Private_Macros PWR Private Macros
 710   * @{
 711   */
 712
 713 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
 714   * @{
 715   */
 716 /* Check PVD level parameter */
 717 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
 718                                  ((LEVEL) == PWR_PVDLEVEL_1) ||\
 719                                  ((LEVEL) == PWR_PVDLEVEL_2) ||\
 720                                  ((LEVEL) == PWR_PVDLEVEL_3) ||\
 721                                  ((LEVEL) == PWR_PVDLEVEL_4) ||\
 722                                  ((LEVEL) == PWR_PVDLEVEL_5) ||\
 723                                  ((LEVEL) == PWR_PVDLEVEL_6) ||\
 724                                  ((LEVEL) == PWR_PVDLEVEL_7))
 725
 726 /* Check PVD mode parameter */
 727 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
 728                                ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
 729                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
 730                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
 731                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
 732                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
 733                                ((MODE) == PWR_PVD_MODE_NORMAL))
 734
 735 /* Check low power regulator parameter */
 736 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
 737                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
 738
 739 /* Check low power mode entry parameter */
 740 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
 741                                    ((ENTRY) == PWR_SLEEPENTRY_WFE))
 742
 743 /* Check low power mode entry parameter */
 744 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
 745                                   ((ENTRY) == PWR_STOPENTRY_WFE))
 746
 747 /* Check voltage scale level parameter */
 748 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
 749                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
 750                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
 751                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
 752 /**
 753   * @}
 754   */
 755
 756 /**
 757   * @}
 758   */
 759
 760 /**
 761   * @}
 762   */
 763
 764 /**
 765   * @}
 766   */
 767
 768 #ifdef __cplusplus
 769 }
 770 #endif /* __cplusplus */
 771
 772 #endif /* STM32H7xx_HAL_PWR_H */
 773
 774 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/