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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_bus.h
bloba7b739e6325dce73941d9b138a850ddc74f7126c
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_bus.h
4 * @author MCD Application Team
5 * @version $VERSION$
6 * @date $DATE$
7 * @brief Header file of BUS LL module.
8
9 @verbatim
10 ##### RCC Limitations #####
11 ==============================================================================
12 [..]
13 A delay between an RCC peripheral clock enable and the effective peripheral
14 enabling should be taken into account in order to manage the peripheral read/write
15 from/to registers.
16 (+) This delay depends on the peripheral mapping.
17 (++) AHB & APB peripherals, 1 dummy read is necessary
18
19 [..]
20 Workarounds:
21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
23
24 @endverbatim
25 ******************************************************************************
26 * @attention
27 *
28 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
29 * All rights reserved.</center></h2>
30 *
31 * This software component is licensed by ST under BSD 3-Clause license,
32 * the "License"; You may not use this file except in compliance with the
33 * License. You may obtain a copy of the License at:
34 * opensource.org/licenses/BSD-3-Clause
35 *
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef STM32H7xx_LL_BUS_H
41 #define STM32H7xx_LL_BUS_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32h7xx.h"
49
50 /** @addtogroup STM32H7xx_LL_Driver
51 * @{
52 */
53
54 #if defined(RCC)
55
56 /** @defgroup BUS_LL BUS
57 * @{
58 */
59
60 /* Private variables ---------------------------------------------------------*/
61
62 /* Private constants ---------------------------------------------------------*/
63
64 /* Private macros ------------------------------------------------------------*/
65
66 /* Exported types ------------------------------------------------------------*/
67
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
70 * @{
71 */
72
73 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
74 * @{
75 */
76 #define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN
77 #define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN
78
79 #if defined(JPEG)
80 #define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN
81 #endif /* JPEG */
82
83 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
84 #if defined(QUADSPI)
85 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
86 #endif /* QUADSPI */
87 #if defined(OCTOSPI1) || defined(OCTOSPI2)
88 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
89 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
90 #endif /*(OCTOSPI1) || (OCTOSPI2)*/
91 #if defined(OCTOSPIM)
92 #define LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN
93 #endif /* OCTOSPIM */
94 #if defined(OTFDEC1) || defined(OTFDEC2)
95 #define LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN
96 #define LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN
97 #endif /* (OTFDEC1) || (OTFDEC2) */
98 #if defined(GFXMMU)
99 #define LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN
100 #endif /* GFXMMU */
101 #define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN
102 #define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN
103 #define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN
104 #define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN
105 #define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN
106 #if defined(RCC_AHB3LPENR_AXISRAMLPEN)
107 #define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN
108 #else
109 #define LL_AHB3_GRP1_PERIPH_AXISRAM1 RCC_AHB3LPENR_AXISRAM1LPEN
110 #define LL_AHB3_GRP1_PERIPH_AXISRAM LL_AHB3_GRP1_PERIPH_AXISRAM1 /* for backward compatibility*/
111 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */
112 #if defined(CD_AXISRAM2_BASE)
113 #define LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN
114 #endif /* CD_AXISRAM2_BASE */
115 #if defined(CD_AXISRAM3_BASE)
116 #define LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN
117 #endif /* CD_AXISRAM3_BASE */
118 /**
119 * @}
120 */
121
122
123 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
124 * @{
125 */
126 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
127 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
128 #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN
129 #if defined(DUAL_CORE)
130 #define LL_AHB1_GRP1_PERIPH_ART RCC_AHB1ENR_ARTEN
131 #endif /* DUAL_CORE */
132 #if defined(RCC_AHB1ENR_CRCEN)
133 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
134 #endif /* RCC_AHB1ENR_CRCEN */
135 #if defined(ETH)
136 #define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN
137 #define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN
138 #define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN
139 #endif /* ETH */
140 #define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN
141 #define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN
142 #if defined(USB2_OTG_FS)
143 #define LL_AHB1_GRP1_PERIPH_USB2OTGHS RCC_AHB1ENR_USB2OTGHSEN
144 #define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI RCC_AHB1ENR_USB2OTGHSULPIEN
145 #endif /* USB2_OTG_FS */
146 /**
147 * @}
148 */
149
150
151 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
152 * @{
153 */
154 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
155 #if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN)
156 #define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN
157 #endif /* HSEM && RCC_AHB2ENR_HSEMEN */
158 #if defined(CRYP)
159 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
160 #endif /* CRYP */
161 #if defined(HASH)
162 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
163 #endif /* HASH */
164 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
165 #define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN
166 #if defined(BDMA1)
167 #define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN
168 #endif /* BDMA1 */
169 #if defined(RCC_AHB2ENR_D2SRAM1EN)
170 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN
171 #else
172 #define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN
173 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/
174 #endif /* RCC_AHB2ENR_D2SRAM1EN */
175 #if defined(RCC_AHB2ENR_D2SRAM2EN)
176 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN
177 #else
178 #define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN
179 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/
180 #endif /* RCC_AHB2ENR_D2SRAM2EN */
181 #if defined(RCC_AHB2ENR_D2SRAM3EN)
182 #define LL_AHB2_GRP1_PERIPH_D2SRAM3 RCC_AHB2ENR_D2SRAM3EN
183 #endif /* RCC_AHB2ENR_D2SRAM3EN */
184 /**
185 * @}
186 */
187
188
189 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
190 * @{
191 */
192 #define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN
193 #define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN
194 #define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN
195 #define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN
196 #define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN
197 #define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
198 #define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
199 #define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
200 #define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN
201 #define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN
202 #define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN
203 #if defined(RCC_AHB4ENR_CRCEN)
204 #define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN
205 #endif /* RCC_AHB4ENR_CRCEN */
206 #if defined(BDMA2)
207 #define LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN
208 #define LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/
209 #else
210 #define LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN
211 #endif /* BDMA2 */
212 #if defined(ADC3)
213 #define LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN
214 #endif /* ADC3 */
215 #if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN)
216 #define LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN
217 #endif /* HSEM && RCC_AHB4ENR_HSEMEN*/
218 #define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN
219 #if defined(RCC_AHB4LPENR_SRAM4LPEN)
220 #define LL_AHB4_GRP1_PERIPH_SRAM4 RCC_AHB4LPENR_SRAM4LPEN
221 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRAM4
222 #else
223 #define LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN
224 #define LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/
225 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/
226 #endif /* RCC_AHB4ENR_D3SRAM1EN */
227 /**
228 * @}
229 */
230
231
232 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
233 * @{
234 */
235 #define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN
236 #if defined(DSI)
237 #define LL_APB3_GRP1_PERIPH_DSI RCC_APB3ENR_DSIEN
238 #endif /* DSI */
239 #define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN
240 #if defined(RCC_APB3ENR_WWDGEN)
241 #define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/
242 #endif
243 /**
244 * @}
245 */
246
247
248 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
249 * @{
250 */
251 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN
252 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN
253 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN
254 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN
255 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN
256 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN
257 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN
258 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN
259 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN
260 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN
261 #if defined(DUAL_CORE)
262 #define LL_APB1_GRP1_PERIPH_WWDG2 RCC_APB1LENR_WWDG2EN
263 #endif /*DUAL_CORE*/
264 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN
265 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN
266 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN
267 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN
268 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN
269 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN
270 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN
271 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
272 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
273 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN
274 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
275 #define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN
276 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
277 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN
278 /**
279 * @}
280 */
281
282
283 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
284 * @{
285 */
286 #define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN
287 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN
288 #define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN
289 #define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN
290 #define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN
291 /**
292 * @}
293 */
294
295
296 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
297 * @{
298 */
299 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
300 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
301 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
302 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
303 #if defined(UART9)
304 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
305 #endif /* UART9 */
306 #if defined(USART10)
307 #define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN
308 #endif /* USART10 */
309 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
310 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
311 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
312 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
313 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
314 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
315 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
316 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
317 #if defined(SAI3)
318 #define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN
319 #endif /* SAI3 */
320 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
321 #if defined(HRTIM1)
322 #define LL_APB2_GRP1_PERIPH_HRTIM RCC_APB2ENR_HRTIMEN
323 #endif /* HRTIM1 */
324 /**
325 * @}
326 */
327
328
329 /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH
330 * @{
331 */
332 #define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN
333 #define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN
334 #define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN
335 #define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN
336 #define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN
337 #define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN
338 #if defined(LPTIM4)
339 #define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN
340 #endif /* LPTIM4 */
341 #if defined(LPTIM5)
342 #define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN
343 #endif /* LPTIM5 */
344 #if defined(DAC2)
345 #define LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN
346 #endif /* DAC2 */
347 #define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN
348 #define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN
349 #define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN
350 #if defined(SAI4)
351 #define LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN
352 #endif /* SAI4 */
353 #if defined(DTS)
354 #define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN
355 #endif /*DTS*/
356 #if defined(DFSDM2_BASE)
357 #define LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN
358 #endif /* DFSDM2_BASE */
359 /**
360 * @}
361 */
362
363 /** @defgroup BUS_LL_EC_CLKAM_PERIPH CLKAM PERIPH
364 * @{
365 */
366 #if defined(RCC_D3AMR_BDMAAMEN)
367 #define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN
368 #else
369 #define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN
370 #define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
371 #endif /* RCC_D3AMR_BDMAAMEN */
372 #if defined(RCC_SRDAMR_GPIOAMEN)
373 #define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN
374 #endif /* RCC_SRDAMR_GPIOAMEN */
375 #if defined(RCC_D3AMR_LPUART1AMEN)
376 #define LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN
377 #else
378 #define LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN
379 #endif /* RCC_D3AMR_LPUART1AMEN */
380 #if defined(RCC_D3AMR_SPI6AMEN)
381 #define LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN
382 #else
383 #define LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN
384 #endif /* RCC_D3AMR_SPI6AMEN */
385 #if defined(RCC_D3AMR_I2C4AMEN)
386 #define LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN
387 #else
388 #define LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN
389 #endif /* RCC_D3AMR_I2C4AMEN */
390 #if defined(RCC_D3AMR_LPTIM2AMEN)
391 #define LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN
392 #else
393 #define LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN
394 #endif /* RCC_D3AMR_LPTIM2AMEN */
395 #if defined(RCC_D3AMR_LPTIM3AMEN)
396 #define LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN
397 #else
398 #define LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN
399 #endif /* RCC_D3AMR_LPTIM3AMEN */
400 #if defined(RCC_D3AMR_LPTIM4AMEN)
401 #define LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN
402 #endif /* RCC_D3AMR_LPTIM4AMEN */
403 #if defined(RCC_D3AMR_LPTIM5AMEN)
404 #define LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN
405 #endif /* RCC_D3AMR_LPTIM5AMEN */
406 #if defined(DAC2)
407 #define LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN
408 #endif /* DAC2 */
409 #if defined(RCC_D3AMR_COMP12AMEN)
410 #define LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN
411 #else
412 #define LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN
413 #endif /* RCC_D3AMR_COMP12AMEN */
414 #if defined(RCC_D3AMR_VREFAMEN)
415 #define LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN
416 #else
417 #define LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN
418 #endif /* RCC_D3AMR_VREFAMEN */
419 #if defined(RCC_D3AMR_RTCAMEN)
420 #define LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN
421 #else
422 #define LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN
423 #endif /* RCC_D3AMR_RTCAMEN */
424 #if defined(RCC_D3AMR_CRCAMEN)
425 #define LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN
426 #endif /* RCC_D3AMR_CRCAMEN */
427 #if defined(SAI4)
428 #define LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN
429 #endif /* SAI4 */
430 #if defined(ADC3)
431 #define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN
432 #endif /* ADC3 */
433 #if defined(DTS)
434 #define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN
435 #endif /* DTS */
436 #if defined(DFSDM2_BASE)
437 #define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN
438 #endif /* DFSDM2_BASE */
439 #if defined(RCC_D3AMR_BKPRAMAMEN)
440 #define LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN
441 #else
442 #define LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN
443 #endif /* RCC_D3AMR_BKPRAMAMEN */
444 #if defined(RCC_D3AMR_SRAM4AMEN)
445 #define LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN
446 #else
447 #define LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN
448 #define LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM
449 #endif /* RCC_D3AMR_SRAM4AMEN */
450 /**
451 * @}
452 */
453
454 #if defined(RCC_CKGAENR_AXICKG)
455 /** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH
456 * @{
457 */
458 #define LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG
459 #define LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG
460 #define LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG
461 #define LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG
462 #define LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG
463 #define LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG
464 #define LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG
465 #define LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG
466 #define LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG
467 #define LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG
468 #define LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG
469 #define LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG
470 #define LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG
471 #define LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG
472 #define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG
473 #define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG
474 #define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG
475 #define LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG
476 #define LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG
477 #define LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG
478 #define LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG
479 /**
480 * @}
481 */
482 #endif /* RCC_CKGAENR_AXICKG */
483
484 /* Exported macro ------------------------------------------------------------*/
485
486 /* Exported functions --------------------------------------------------------*/
487
488 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
489 * @{
490 */
491
492 /** @defgroup BUS_LL_EF_AHB3 AHB3
493 * @{
494 */
495
496 /**
497 * @brief Enable AHB3 peripherals clock.
498 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock\n
499 * AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock\n
500 * AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock\n
501 * AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
502 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n (*)
503 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n (*)
504 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock\n (*)
505 * AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock\n (*)
506 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock\n (*)
507 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock\n (*)
508 * AHB3ENR GFXMMU LL_AHB3_GRP1_EnableClock\n (*)
509 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n
510 * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n (*)
511 * AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n (*)
512 * AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock\n (*)
513 * AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock\n (*)
514 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock (*)
515 * @param Periphs This parameter can be a combination of the following values:
516 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
517 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
518 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
519 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
520 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
521 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
522 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
523 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
524 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
525 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
526 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
527 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
528 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
529 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
530 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
531 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
532 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
533 *
534 * (*) value not defined in all devices.
535 * @retval None
536 */
537 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
538 {
539 __IO uint32_t tmpreg;
540 SET_BIT(RCC->AHB3ENR, Periphs);
541 /* Delay after an RCC peripheral clock enabling */
542 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
543 (void)tmpreg;
544 }
545
546 /**
547 * @brief Check if AHB3 peripheral clock is enabled or not
548 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock\n
549 * AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock\n
550 * AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock\n
551 * AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
552 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n (*)
553 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n (*)
554 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock\n (*)
555 * AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock\n (*)
556 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock\n (*)
557 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock\n (*)
558 * AHB3ENR GFXMMU LL_AHB3_GRP1_IsEnabledClock\n (*)
559 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n
560 * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n (*)
561 * AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n (*)
562 * AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock\n (*)
563 * AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock\n (*)
564 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock (*)
565 * @param Periphs This parameter can be a combination of the following values:
566 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
567 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
568 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
569 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
570 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
571 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
572 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
573 * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
574 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
575 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
576 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
577 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
578 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
579 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
580 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
581 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
582 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
583 *
584 * (*) value not defined in all devices.
585 * @retval uint32_t
586 */
587 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
588 {
589 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);
590 }
591
592 /**
593 * @brief Disable AHB3 peripherals clock.
594 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock\n
595 * AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock\n
596 * AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock\n
597 * AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
598 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n (*)
599 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n (*)
600 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock\n (*)
601 * AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock\n (*)
602 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock\n (*)
603 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock\n (*)
604 * AHB3ENR GFXMMU LL_AHB3_GRP1_DisableClock\n (*)
605 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n (*)
606 * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n (*)
607 * AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n (*)
608 * AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock\n (*)
609 * AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock\n (*)
610 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock
611 * @param Periphs This parameter can be a combination of the following values:
612 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
613 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
614 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
615 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
616 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
617 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
618 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
619 * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
620 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
621 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
622 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
623 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
624 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
625 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
626 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
627 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
628 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
629 *
630 * (*) value not defined in all devices.
631 * @retval None
632 */
633 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
634 {
635 CLEAR_BIT(RCC->AHB3ENR, Periphs);
636 }
637
638 /**
639 * @brief Force AHB3 peripherals reset.
640 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n
641 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n
642 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n
643 * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
644 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n (*)
645 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n (*)
646 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset\n (*)
647 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ForceReset\n (*)
648 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ForceReset\n (*)
649 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ForceReset\n (*)
650 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ForceReset\n (*)
651 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset
652 * @param Periphs This parameter can be a combination of the following values:
653 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
654 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
655 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
656 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
657 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
658 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
659 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
660 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
661 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
662 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
663 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
664 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
665 *
666 * (*) value not defined in all devices.
667 * @retval None
668 */
669 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
670 {
671 SET_BIT(RCC->AHB3RSTR, Periphs);
672 }
673
674 /**
675 * @brief Release AHB3 peripherals reset.
676 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset\n
677 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset\n
678 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset\n
679 * AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
680 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
681 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n (*)
682 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset\n (*)
683 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ReleaseReset\n (*)
684 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ReleaseReset\n (*)
685 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ReleaseReset\n (*)
686 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ReleaseReset\n (*)
687 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset
688 * @param Periphs This parameter can be a combination of the following values:
689 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
690 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
691 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
692 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
693 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
694 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
695 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
696 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
697 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
698 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
699 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
700 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
701 *
702 * (*) value not defined in all devices.
703 * @retval None
704 */
705 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
706 {
707 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
708 }
709
710 /**
711 * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode.
712 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep\n
713 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep\n
714 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep\n
715 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep\n
716 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
717 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
718 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
719 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
720 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
721 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
722 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_EnableClockSleep\n (*)
723 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep\n
724 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep\n
725 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep\n
726 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep\n
727 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep\n
728 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep
729 * @param Periphs This parameter can be a combination of the following values:
730 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
731 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
732 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
733 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
734 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
735 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
736 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
737 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
738 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
739 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
740 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
741 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
742 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
743 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
744 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
745 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
746 *
747 * (*) value not defined in all devices.
748 * @retval None
749 */
750 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
751 {
752 __IO uint32_t tmpreg;
753 SET_BIT(RCC->AHB3LPENR, Periphs);
754 /* Delay after an RCC peripheral clock enabling */
755 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
756 (void)tmpreg;
757 }
758
759 /**
760 * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode.
761 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep\n
762 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep\n
763 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep\n
764 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep\n
765 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep\n
766 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
767 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
768 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
769 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
770 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
771 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_DisableClockSleep\n (*)
772 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep\n
773 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep\n
774 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep\n
775 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep\n
776 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep\n
777 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep
778 * @param Periphs This parameter can be a combination of the following values:
779 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
780 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
781 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
782 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
783 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
784 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
785 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
786 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
787 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
788 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
789 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
790 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
791 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
792 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
793 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
794 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
795 *
796 * (*) value not defined in all devices.
797 * @retval None
798 */
799 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
800 {
801 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
802 }
803
804 /**
805 * @}
806 */
807
808 /** @defgroup BUS_LL_EF_AHB1 AHB1
809 * @{
810 */
811
812 /**
813 * @brief Enable AHB1 peripherals clock.
814 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
815 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
816 * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n
817 * AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n
818 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*)
819 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*)
820 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*)
821 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock\n
822 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock\n
823 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock\n (*)
824 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock (*)
825 * @param Periphs This parameter can be a combination of the following values:
826 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
827 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
828 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
829 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
830 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
831 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
832 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
833 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
834 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
835 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
836 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
837 *
838 * (*) value not defined in all devices.
839 * @retval None
840 */
841 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
842 {
843 __IO uint32_t tmpreg;
844 SET_BIT(RCC->AHB1ENR, Periphs);
845 /* Delay after an RCC peripheral clock enabling */
846 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
847 (void)tmpreg;
848 }
849
850 /**
851 * @brief Check if AHB1 peripheral clock is enabled or not
852 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
853 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
854 * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
855 * AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock\n (*)
856 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n (*)
857 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n (*)
858 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n (*)
859 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n (*)
860 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
861 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock\n
862 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n (*)
863 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock (*)
864 * @param Periphs This parameter can be a combination of the following values:
865 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
866 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
867 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
868 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
869 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
870 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
871 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
872 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
873 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
874 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
875 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
876 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
877 *
878 * (*) value not defined in all devices.
879 * @retval uint32_t
880 */
881 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
882 {
883 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);
884 }
885
886 /**
887 * @brief Disable AHB1 peripherals clock.
888 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
889 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
890 * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n
891 * AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*)
892 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*)
893 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*)
894 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*)
895 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock\n
896 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock\n
897 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock\n (*)
898 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock (*)
899 * @param Periphs This parameter can be a combination of the following values:
900 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
901 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
902 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
903 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
904 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
905 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
906 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
907 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
908 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
909 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
910 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
911 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
912 *
913 * (*) value not defined in all devices.
914 * @retval None
915 */
916 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
917 {
918 CLEAR_BIT(RCC->AHB1ENR, Periphs);
919 }
920
921 /**
922 * @brief Force AHB1 peripherals reset.
923 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
924 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
925 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
926 * AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset\n (*)
927 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n (*)
928 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset\n (*)
929 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset\n
930 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset (*)
931 * @param Periphs This parameter can be a combination of the following values:
932 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
933 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
934 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
935 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
936 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
937 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
938 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
939 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
940 *
941 * (*) value not defined in all devices.
942 * @retval None
943 */
944 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
945 {
946 SET_BIT(RCC->AHB1RSTR, Periphs);
947 }
948
949 /**
950 * @brief Release AHB1 peripherals reset.
951 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
952 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
953 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
954 * AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset\n (*)
955 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n (*)
956 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset\n (*)
957 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset\n
958 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset (*)
959 * @param Periphs This parameter can be a combination of the following values:
960 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
961 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
962 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
963 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
964 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
965 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
966 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
967 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
968 *
969 * (*) value not defined in all devices.
970 * @retval None
971 */
972 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
973 {
974 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
975 }
976
977 /**
978 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
979 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
980 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
981 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n
982 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
983 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
984 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
985 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
986 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n
987 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n
988 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep\n
989 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n (*)
990 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep (*)
991 * @param Periphs This parameter can be a combination of the following values:
992 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
993 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
994 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
995 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
996 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
997 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
998 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
999 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
1000 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
1001 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
1002 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
1003 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
1004 *
1005 * (*) value not defined in all devices.
1006 * @retval None
1007 */
1008 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
1009 {
1010 __IO uint32_t tmpreg;
1011 SET_BIT(RCC->AHB1LPENR, Periphs);
1012 /* Delay after an RCC peripheral clock enabling */
1013 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
1014 (void)tmpreg;
1015 }
1016
1017 /**
1018 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
1019 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
1020 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
1021 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n
1022 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1023 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1024 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1025 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1026 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1027 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n
1028 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep\n
1029 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n (*)
1030 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep (*)
1031 * @param Periphs This parameter can be a combination of the following values:
1032 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
1033 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
1034 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
1035 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
1036 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
1037 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
1038 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
1039 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
1040 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
1041 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
1042 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
1043 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
1044 *
1045 * (*) value not defined in all devices.
1046 * @retval None
1047 */
1048 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
1049 {
1050 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
1051 }
1052
1053 /**
1054 * @}
1055 */
1056
1057 /** @defgroup BUS_LL_EF_AHB2 AHB2
1058 * @{
1059 */
1060
1061 /**
1062 * @brief Enable AHB2 peripherals clock.
1063 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
1064 * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n (*)
1065 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n (*)
1066 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n (*)
1067 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
1068 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n
1069 * AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock\n (*)
1070 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n
1071 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n
1072 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*)
1073 * @param Periphs This parameter can be a combination of the following values:
1074 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1075 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1076 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1077 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1078 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1079 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1080 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1081 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1082 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1083 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1084 *
1085 * (*) value not defined in all devices.
1086 * @retval None
1087 */
1088 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
1089 {
1090 __IO uint32_t tmpreg;
1091 SET_BIT(RCC->AHB2ENR, Periphs);
1092 /* Delay after an RCC peripheral clock enabling */
1093 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
1094 (void)tmpreg;
1095 }
1096
1097 /**
1098 * @brief Check if AHB2 peripheral clock is enabled or not
1099 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
1100 * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n (*)
1101 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n (*)
1102 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n (*)
1103 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
1104 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n
1105 * AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock\n (*)
1106 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n
1107 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n
1108 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*)
1109 * @param Periphs This parameter can be a combination of the following values:
1110 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1111 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
1112 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1113 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1114 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1115 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1116 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1117 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1118 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1119 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1120 *
1121 * (*) value not defined in all devices.
1122 * @retval uint32_t
1123 */
1124 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
1125 {
1126 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);
1127 }
1128
1129 /**
1130 * @brief Disable AHB2 peripherals clock.
1131 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
1132 * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n (*)
1133 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n (*)
1134 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n (*)
1135 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
1136 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n
1137 * AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock\n (*)
1138 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n
1139 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n
1140 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*)
1141 * @param Periphs This parameter can be a combination of the following values:
1142 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1143 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
1144 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1145 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1146 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1147 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1148 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1149 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1150 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1151 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1152 *
1153 * (*) value not defined in all devices.
1154 * @retval None
1155 */
1156 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
1157 {
1158 CLEAR_BIT(RCC->AHB2ENR, Periphs);
1159 }
1160
1161 /**
1162 * @brief Force AHB2 peripherals reset.
1163 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
1164 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n (*)
1165 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n (*)
1166 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n (*)
1167 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
1168 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n
1169 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset (*)
1170 * @param Periphs This parameter can be a combination of the following values:
1171 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1172 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1173 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1174 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1175 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1176 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1177 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1178 *
1179 * (*) value not defined in all devices.
1180 * @retval None
1181 */
1182 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
1183 {
1184 SET_BIT(RCC->AHB2RSTR, Periphs);
1185 }
1186
1187 /**
1188 * @brief Release AHB2 peripherals reset.
1189 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
1190 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n (*)
1191 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n (*)
1192 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n (*)
1193 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
1194 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n
1195 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset (*)
1196 * @param Periphs This parameter can be a combination of the following values:
1197 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
1198 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1199 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1200 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1201 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1202 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1203 *
1204 * (*) value not defined in all devices.
1205 * @retval None
1206 */
1207 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
1208 {
1209 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
1210 }
1211
1212 /**
1213 * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode.
1214 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n
1215 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
1216 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
1217 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n
1218 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n
1219 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep\n (*)
1220 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n
1221 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n
1222 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*)
1223 * @param Periphs This parameter can be a combination of the following values:
1224 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1225 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1226 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1227 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1228 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1229 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1230 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1231 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1232 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1233 *
1234 * (*) value not defined in all devices.
1235 * @retval None
1236 */
1237 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
1238 {
1239 __IO uint32_t tmpreg;
1240 SET_BIT(RCC->AHB2LPENR, Periphs);
1241 /* Delay after an RCC peripheral clock enabling */
1242 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
1243 (void)tmpreg;
1244 }
1245
1246 /**
1247 * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode.
1248 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep\n
1249 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep\n (*)
1250 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n (*)
1251 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n
1252 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n
1253 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep\n (*)
1254 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n
1255 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n
1256 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*)
1257 * @param Periphs This parameter can be a combination of the following values:
1258 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
1259 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
1260 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
1261 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
1262 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
1263 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
1264 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
1265 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
1266 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
1267 *
1268 * (*) value not defined in all devices.
1269 * @retval None
1270 */
1271 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
1272 {
1273 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
1274 }
1275
1276 /**
1277 * @}
1278 */
1279
1280 /** @defgroup BUS_LL_EF_AHB4 AHB4
1281 * @{
1282 */
1283
1284 /**
1285 * @brief Enable AHB4 peripherals clock.
1286 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n
1287 * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n
1288 * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n
1289 * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n
1290 * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n
1291 * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n
1292 * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n
1293 * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n
1294 * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n
1295 * AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n
1296 * AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n
1297 * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n (*)
1298 * AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock\n
1299 * AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock\n (*)
1300 * AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock\n (*)
1301 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock\n
1302 * AHB4ENR SRAM4EN LL_AHB4_GRP1_EnableClock
1303 * @param Periphs This parameter can be a combination of the following values:
1304 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1305 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1306 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1307 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1308 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1309 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1310 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1311 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1312 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
1313 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1314 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1315 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1316 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1317 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1318 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1319 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1320 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1321 *
1322 * (*) value not defined in all devices.
1323 * @retval None
1324 */
1325 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
1326 {
1327 __IO uint32_t tmpreg;
1328 SET_BIT(RCC->AHB4ENR, Periphs);
1329 /* Delay after an RCC peripheral clock enabling */
1330 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
1331 (void)tmpreg;
1332 }
1333
1334 /**
1335 * @brief Check if AHB4 peripheral clock is enabled or not
1336 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n
1337 * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n
1338 * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n
1339 * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n
1340 * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n
1341 * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n
1342 * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n
1343 * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n
1344 * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n
1345 * AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n
1346 * AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n
1347 * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n (*)
1348 * AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock\n
1349 * AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock\n (*)
1350 * AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock\n (*)
1351 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock\n
1352 * AHB4ENR SRAM4EN LL_AHB4_GRP1_IsEnabledClock
1353 * @param Periphs This parameter can be a combination of the following values:
1354 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1355 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1356 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1357 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1358 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1359 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1360 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1361 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1362 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
1363 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1364 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1365 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1366 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1367 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1368 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1369 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1370 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1371 *
1372 * (*) value not defined in all devices.
1373 * @retval uint32_t
1374 */
1375 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
1376 {
1377 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);
1378 }
1379
1380 /**
1381 * @brief Disable AHB4 peripherals clock.
1382 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n
1383 * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n
1384 * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n
1385 * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n
1386 * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n
1387 * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n
1388 * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n
1389 * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n
1390 * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n
1391 * AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n
1392 * AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n
1393 * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n (*)
1394 * AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock\n
1395 * AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock\n (*)
1396 * AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock\n (*)
1397 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock\n
1398 * AHB4ENR SRAM4EN LL_AHB4_GRP1_DisableClock
1399 * @param Periphs This parameter can be a combination of the following values:
1400 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1401 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1402 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1403 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1404 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1405 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1406 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1407 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1408 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
1409 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1410 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1411 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1412 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1413 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1414 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1415 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1416 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1417 *
1418 * (*) value not defined in all devices.
1419 * @retval None
1420 */
1421 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
1422 {
1423 CLEAR_BIT(RCC->AHB4ENR, Periphs);
1424 }
1425
1426 /**
1427 * @brief Force AHB4 peripherals reset.
1428 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n
1429 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n
1430 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n
1431 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n
1432 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n
1433 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n
1434 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n
1435 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n
1436 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n
1437 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n
1438 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n
1439 * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n (*)
1440 * AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset\n
1441 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset\n (*)
1442 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset (*)
1443 * @param Periphs This parameter can be a combination of the following values:
1444 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1445 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1446 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1447 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1448 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1449 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1450 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1451 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1452 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
1453 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1454 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1455 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1456 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1457 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1458 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1459 *
1460 * (*) value not defined in all devices.
1461 * @retval None
1462 */
1463 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
1464 {
1465 SET_BIT(RCC->AHB4RSTR, Periphs);
1466 }
1467
1468 /**
1469 * @brief Release AHB4 peripherals reset.
1470 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n
1471 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n
1472 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n
1473 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n
1474 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n
1475 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n
1476 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n
1477 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n
1478 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n
1479 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n
1480 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n
1481 * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n (*)
1482 * AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset\n
1483 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset\n (*)
1484 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset (*)
1485 * @param Periphs This parameter can be a combination of the following values:
1486 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1487 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1488 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1489 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1490 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1491 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1492 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1493 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1494 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
1495 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1496 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1497 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1498 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1499 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1500 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
1501 *
1502 * (*) value not defined in all devices.
1503 * @retval None
1504 */
1505 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
1506 {
1507 CLEAR_BIT(RCC->AHB4RSTR, Periphs);
1508 }
1509
1510 /**
1511 * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode.
1512 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n
1513 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n
1514 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n
1515 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n
1516 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n
1517 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n
1518 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n
1519 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n
1520 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n
1521 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n
1522 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n
1523 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
1524 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep\n
1525 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep\n (*)
1526 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep\n
1527 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_EnableClockSleep
1528 * @param Periphs This parameter can be a combination of the following values:
1529 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1530 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1531 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1532 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1533 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1534 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1535 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1536 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1537 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
1538 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1539 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1540 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1541 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1542 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1543 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1544 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1545 * @retval None
1546 */
1547 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
1548 {
1549 __IO uint32_t tmpreg;
1550 SET_BIT(RCC->AHB4LPENR, Periphs);
1551 /* Delay after an RCC peripheral clock enabling */
1552 tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
1553 (void)tmpreg;
1554 }
1555
1556 /**
1557 * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode.
1558 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n
1559 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n
1560 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n
1561 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n
1562 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n
1563 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n
1564 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n
1565 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n
1566 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n
1567 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n
1568 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n
1569 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
1570 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep\n
1571 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep\n (*)
1572 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep\n
1573 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_DisableClockSleep
1574 * @param Periphs This parameter can be a combination of the following values:
1575 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
1576 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
1577 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
1578 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
1579 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
1580 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
1581 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
1582 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
1583 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
1584 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
1585 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
1586 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
1587 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
1588 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
1589 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
1590 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
1591 * @retval None
1592 */
1593 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
1594 {
1595 CLEAR_BIT(RCC->AHB4LPENR, Periphs);
1596 }
1597
1598 /**
1599 * @}
1600 */
1601
1602 /** @defgroup BUS_LL_EF_APB3 APB3
1603 * @{
1604 */
1605
1606 /**
1607 * @brief Enable APB3 peripherals clock.
1608 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_EnableClock\n (*)
1609 * APB3ENR DSIEN LL_APB3_GRP1_EnableClock\n (*)
1610 * APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock
1611 * @param Periphs This parameter can be a combination of the following values:
1612 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1613 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1614 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1615 *
1616 * (*) value not defined in all devices.
1617 * @retval None
1618 */
1619 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
1620 {
1621 __IO uint32_t tmpreg;
1622 SET_BIT(RCC->APB3ENR, Periphs);
1623 /* Delay after an RCC peripheral clock enabling */
1624 tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
1625 (void)tmpreg;
1626 }
1627
1628 /**
1629 * @brief Check if APB3 peripheral clock is enabled or not
1630 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock\n (*)
1631 * APB3ENR DSIEN LL_APB3_GRP1_IsEnabledClock\n (*)
1632 * APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock
1633 * @param Periphs This parameter can be a combination of the following values:
1634 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1635 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1636 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1637 *
1638 * (*) value not defined in all devices.
1639 * @retval uint32_t
1640 */
1641 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
1642 {
1643 return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);
1644 }
1645
1646 /**
1647 * @brief Disable APB3 peripherals clock.
1648 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_DisableClock\n
1649 * APB3ENR DSIEN LL_APB3_GRP1_DisableClock\n
1650 * APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock
1651 * @param Periphs This parameter can be a combination of the following values:
1652 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1653 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1654 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1655 *
1656 * (*) value not defined in all devices.
1657 * @retval None
1658 */
1659 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
1660 {
1661 CLEAR_BIT(RCC->APB3ENR, Periphs);
1662 }
1663
1664 /**
1665 * @brief Force APB3 peripherals reset.
1666 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset\n (*)
1667 * APB3RSTR DSIRST LL_APB3_GRP1_ForceReset (*)
1668 * @param Periphs This parameter can be a combination of the following values:
1669 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1670 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1671 *
1672 * (*) value not defined in all devices.
1673 * @retval None
1674 */
1675 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
1676 {
1677 SET_BIT(RCC->APB3RSTR, Periphs);
1678 }
1679
1680 /**
1681 * @brief Release APB3 peripherals reset.
1682 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset\n
1683 * APB3RSTR DSIRST LL_APB3_GRP1_ReleaseReset
1684 * @param Periphs This parameter can be a combination of the following values:
1685 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1686 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1687 *
1688 * (*) value not defined in all devices.
1689 * @retval None
1690 */
1691 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
1692 {
1693 CLEAR_BIT(RCC->APB3RSTR, Periphs);
1694 }
1695
1696 /**
1697 * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode.
1698 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep\n (*)
1699 * APB3LPENR DSILPEN LL_APB3_GRP1_EnableClockSleep\n (*)
1700 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep
1701 * @param Periphs This parameter can be a combination of the following values:
1702 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1703 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1704 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1705 *
1706 * (*) value not defined in all devices.
1707 * @retval None
1708 */
1709 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
1710 {
1711 __IO uint32_t tmpreg;
1712 SET_BIT(RCC->APB3LPENR, Periphs);
1713 /* Delay after an RCC peripheral clock enabling */
1714 tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
1715 (void)tmpreg;
1716 }
1717
1718 /**
1719 * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode.
1720 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep\n (*)
1721 * APB3LPENR DSILPEN LL_APB3_GRP1_DisableClockSleep\n (*)
1722 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep
1723 * @param Periphs This parameter can be a combination of the following values:
1724 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
1725 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
1726 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
1727 *
1728 * (*) value not defined in all devices.
1729 * @retval None
1730 */
1731 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
1732 {
1733 CLEAR_BIT(RCC->APB3LPENR, Periphs);
1734 }
1735
1736 /**
1737 * @}
1738 */
1739
1740 /** @defgroup BUS_LL_EF_APB1 APB1
1741 * @{
1742 */
1743
1744 /**
1745 * @brief Enable APB1 peripherals clock.
1746 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n
1747 * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n
1748 * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n
1749 * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n
1750 * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n
1751 * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n
1752 * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n
1753 * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n
1754 * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n
1755 * APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1756 * APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock\n (*)
1757 * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n
1758 * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n
1759 * APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1760 * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n
1761 * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n
1762 * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n
1763 * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n
1764 * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n
1765 * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n
1766 * APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n
1767 * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n
1768 * APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n
1769 * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n
1770 * APB1LENR UART8EN LL_APB1_GRP1_EnableClock
1771 * @param Periphs This parameter can be a combination of the following values:
1772 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1773 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1774 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1775 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1776 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1777 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1778 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1779 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1780 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1781 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1782 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
1783 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1784 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1785 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1786 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1787 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1788 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1789 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1790 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1791 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1792 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1793 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1794 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1795 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1796 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1797 *
1798 * (*) value not defined in all devices.
1799 * @retval None
1800 */
1801 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1802 {
1803 __IO uint32_t tmpreg;
1804 SET_BIT(RCC->APB1LENR, Periphs);
1805 /* Delay after an RCC peripheral clock enabling */
1806 tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
1807 (void)tmpreg;
1808 }
1809
1810 /**
1811 * @brief Check if APB1 peripheral clock is enabled or not
1812 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1813 * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1814 * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1815 * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1816 * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1817 * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1818 * APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1819 * APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1820 * APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1821 * APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1822 * APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock\n (*)
1823 * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1824 * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1825 * APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1826 * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1827 * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1828 * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1829 * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1830 * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1831 * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1832 * APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1833 * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1834 * APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n
1835 * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1836 * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock
1837 * @param Periphs This parameter can be a combination of the following values:
1838 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1839 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1840 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1841 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1842 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1843 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1844 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1845 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1846 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1847 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1848 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
1849 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1850 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1851 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1852 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1853 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1854 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1855 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1856 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1857 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1858 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1859 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1860 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1861 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1862 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1863 *
1864 * (*) value not defined in all devices.
1865 * @retval uint32_t
1866 */
1867 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1868 {
1869 return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);
1870 }
1871
1872 /**
1873 * @brief Disable APB1 peripherals clock.
1874 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n
1875 * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n
1876 * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n
1877 * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n
1878 * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n
1879 * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n
1880 * APB1LENR TIM12EN LL_APB1_GRP1_DisableClock\n
1881 * APB1LENR TIM13EN LL_APB1_GRP1_DisableClock\n
1882 * APB1LENR TIM14EN LL_APB1_GRP1_DisableClock\n
1883 * APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1884 * APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock\n (*)
1885 * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n
1886 * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n
1887 * APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1888 * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n
1889 * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n
1890 * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n
1891 * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n
1892 * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n
1893 * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n
1894 * APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n
1895 * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n
1896 * APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n
1897 * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n
1898 * APB1LENR UART8EN LL_APB1_GRP1_DisableClock
1899 * @param Periphs This parameter can be a combination of the following values:
1900 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1901 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1902 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1903 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1904 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1905 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1906 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1907 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1908 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1909 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1910 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
1911 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1912 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1913 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1914 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1915 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1916 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1917 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1918 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1919 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1920 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1921 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1922 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1923 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1924 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1925 *
1926 * (*) value not defined in all devices.
1927 * @retval None
1928 */
1929 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1930 {
1931 CLEAR_BIT(RCC->APB1LENR, Periphs);
1932 }
1933
1934 /**
1935 * @brief Force APB1 peripherals reset.
1936 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1937 * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1938 * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1939 * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1940 * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1941 * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1942 * APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset\n
1943 * APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset\n
1944 * APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset\n
1945 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
1946 * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1947 * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1948 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
1949 * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n
1950 * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n
1951 * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n
1952 * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n
1953 * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1954 * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1955 * APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n
1956 * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n
1957 * APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n
1958 * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n
1959 * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset
1960 * @param Periphs This parameter can be a combination of the following values:
1961 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1962 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1963 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1964 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1965 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1966 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1967 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1968 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1969 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1970 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1971 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1972 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1973 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
1974 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1975 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1976 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1977 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1978 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1979 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1980 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1981 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
1982 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
1983 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1984 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1985 * @retval None
1986 */
1987 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1988 {
1989 SET_BIT(RCC->APB1LRSTR, Periphs);
1990 }
1991
1992 /**
1993 * @brief Release APB1 peripherals reset.
1994 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1995 * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1996 * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1997 * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1998 * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1999 * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
2000 * APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
2001 * APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
2002 * APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
2003 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
2004 * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
2005 * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
2006 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
2007 * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
2008 * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
2009 * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
2010 * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
2011 * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
2012 * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
2013 * APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
2014 * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n
2015 * APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n
2016 * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
2017 * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset
2018 * @param Periphs This parameter can be a combination of the following values:
2019 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2020 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2021 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2022 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2023 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2024 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2025 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2026 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2027 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2028 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2029 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2030 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2031 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2032 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2033 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2034 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2035 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2036 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2037 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2038 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2039 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2040 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2041 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2042 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2043 * @retval None
2044 */
2045 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
2046 {
2047 CLEAR_BIT(RCC->APB1LRSTR, Periphs);
2048 }
2049
2050 /**
2051 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
2052 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
2053 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
2054 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
2055 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
2056 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
2057 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
2058 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n
2059 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n
2060 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n
2061 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n
2062 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep\n (*)
2063 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
2064 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
2065 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n
2066 * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
2067 * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
2068 * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
2069 * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
2070 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
2071 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
2072 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n
2073 * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n
2074 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n
2075 * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n
2076 * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep
2077 * @param Periphs This parameter can be a combination of the following values:
2078 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2079 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2080 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2081 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2082 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2083 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2084 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2085 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2086 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2087 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2088 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
2089 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2090 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2091 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2092 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2093 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2094 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2095 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2096 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2097 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2098 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2099 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2100 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2101 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2102 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2103 *
2104 * (*) value not defined in all devices.
2105 * @retval None
2106 */
2107 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
2108 {
2109 __IO uint32_t tmpreg;
2110 SET_BIT(RCC->APB1LLPENR, Periphs);
2111 /* Delay after an RCC peripheral clock enabling */
2112 tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
2113 (void)tmpreg;
2114 }
2115
2116 /**
2117 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
2118 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
2119 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
2120 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
2121 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
2122 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
2123 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
2124 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n
2125 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n
2126 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n
2127 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n
2128 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep\n (*)
2129 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
2130 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
2131 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n
2132 * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
2133 * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
2134 * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
2135 * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
2136 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
2137 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
2138 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n
2139 * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n
2140 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n
2141 * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n
2142 * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep
2143 * @param Periphs This parameter can be a combination of the following values:
2144 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
2145 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
2146 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
2147 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
2148 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
2149 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
2150 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
2151 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
2152 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
2153 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
2154 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
2155 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
2156 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
2157 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
2158 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
2159 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
2160 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
2161 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
2162 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
2163 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
2164 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
2165 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
2166 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
2167 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
2168 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
2169 *
2170 * (*) value not defined in all devices.
2171 * @retval None
2172 */
2173 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
2174 {
2175 CLEAR_BIT(RCC->APB1LLPENR, Periphs);
2176 }
2177
2178 /**
2179 * @brief Enable APB1 peripherals clock.
2180 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_EnableClock\n
2181 * APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock\n
2182 * APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock\n
2183 * APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock\n
2184 * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock
2185 * @param Periphs This parameter can be a combination of the following values:
2186 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2187 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2188 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2189 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2190 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2191 * @retval None
2192 */
2193 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
2194 {
2195 __IO uint32_t tmpreg;
2196 SET_BIT(RCC->APB1HENR, Periphs);
2197 /* Delay after an RCC peripheral clock enabling */
2198 tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
2199 (void)tmpreg;
2200 }
2201
2202 /**
2203 * @brief Check if APB1 peripheral clock is enabled or not
2204 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock\n
2205 * APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock\n
2206 * APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock\n
2207 * APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock\n
2208 * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock
2209 * @param Periphs This parameter can be a combination of the following values:
2210 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2211 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2212 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2213 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2214 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2215 * @retval uint32_t
2216 */
2217 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
2218 {
2219 return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);
2220 }
2221
2222 /**
2223 * @brief Disable APB1 peripherals clock.
2224 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_DisableClock\n
2225 * APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock\n
2226 * APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock\n
2227 * APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock\n
2228 * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock
2229 * @param Periphs This parameter can be a combination of the following values:
2230 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2231 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2232 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2233 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2234 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2235 * @retval None
2236 */
2237 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
2238 {
2239 CLEAR_BIT(RCC->APB1HENR, Periphs);
2240 }
2241
2242 /**
2243 * @brief Force APB1 peripherals reset.
2244 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset\n
2245 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset\n
2246 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset\n
2247 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset\n
2248 * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset
2249 * @param Periphs This parameter can be a combination of the following values:
2250 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2251 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2252 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2253 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2254 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2255 * @retval None
2256 */
2257 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
2258 {
2259 SET_BIT(RCC->APB1HRSTR, Periphs);
2260 }
2261
2262 /**
2263 * @brief Release APB1 peripherals reset.
2264 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset\n
2265 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset\n
2266 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset\n
2267 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset\n
2268 * APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset
2269 * @param Periphs This parameter can be a combination of the following values:
2270 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2271 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2272 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2273 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2274 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2275 * @retval None
2276 */
2277 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
2278 {
2279 CLEAR_BIT(RCC->APB1HRSTR, Periphs);
2280 }
2281
2282 /**
2283 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
2284 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep\n
2285 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep\n
2286 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep\n
2287 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n
2288 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep
2289 * @param Periphs This parameter can be a combination of the following values:
2290 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2291 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2292 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2293 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2294 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2295 * @retval None
2296 */
2297 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
2298 {
2299 __IO uint32_t tmpreg;
2300 SET_BIT(RCC->APB1HLPENR, Periphs);
2301 /* Delay after an RCC peripheral clock enabling */
2302 tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
2303 (void)tmpreg;
2304 }
2305
2306 /**
2307 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
2308 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep\n
2309 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep\n
2310 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep\n
2311 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n
2312 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep
2313 * @param Periphs This parameter can be a combination of the following values:
2314 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
2315 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
2316 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
2317 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
2318 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
2319 * @retval None
2320 */
2321 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
2322 {
2323 CLEAR_BIT(RCC->APB1HLPENR, Periphs);
2324 }
2325
2326 /**
2327 * @}
2328 */
2329
2330 /** @defgroup BUS_LL_EF_APB2 APB2
2331 * @{
2332 */
2333
2334 /**
2335 * @brief Enable APB2 peripherals clock.
2336 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
2337 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
2338 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
2339 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
2340 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n (*)
2341 * APB2ENR USART10EN LL_APB2_GRP1_EnableClock\n (*)
2342 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
2343 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
2344 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
2345 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
2346 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
2347 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
2348 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
2349 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
2350 * APB2ENR SAI3EN LL_APB2_GRP1_EnableClock\n (*)
2351 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
2352 * APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock (*)
2353 * @param Periphs This parameter can be a combination of the following values:
2354 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2355 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2356 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2357 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2358 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2359 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2360 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2361 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2362 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2363 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2364 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2365 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2366 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2367 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2368 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2369 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2370 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2371 *
2372 * (*) value not defined in all devices.
2373 * @retval None
2374 */
2375 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
2376 {
2377 __IO uint32_t tmpreg;
2378 SET_BIT(RCC->APB2ENR, Periphs);
2379 /* Delay after an RCC peripheral clock enabling */
2380 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
2381 (void)tmpreg;
2382 }
2383
2384 /**
2385 * @brief Check if APB2 peripheral clock is enabled or not
2386 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
2387 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
2388 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
2389 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
2390 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n (*)
2391 * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n (*)
2392 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
2393 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
2394 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
2395 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
2396 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
2397 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
2398 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
2399 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
2400 * APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock\n
2401 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
2402 * APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock
2403 * @param Periphs This parameter can be a combination of the following values:
2404 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2405 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2406 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2407 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2408 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2409 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2410 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2411 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2412 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2413 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2414 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2415 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2416 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2417 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2418 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2419 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2420 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2421 *
2422 * (*) value not defined in all devices.
2423 * @retval uint32_t
2424 */
2425 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2426 {
2427 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);
2428 }
2429
2430 /**
2431 * @brief Disable APB2 peripherals clock.
2432 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
2433 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
2434 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
2435 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
2436 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n (*)
2437 * APB2ENR USART10EN LL_APB2_GRP1_DisableClock\n (*)
2438 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
2439 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
2440 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
2441 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
2442 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
2443 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
2444 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
2445 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
2446 * APB2ENR SAI3EN LL_APB2_GRP1_DisableClock\n (*)
2447 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
2448 * APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock (*)
2449 * @param Periphs This parameter can be a combination of the following values:
2450 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2451 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2452 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2453 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2454 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2455 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2456 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2457 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2458 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2459 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2460 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2461 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2462 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2463 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2464 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2465 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2466 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2467 *
2468 * (*) value not defined in all devices.
2469 * @retval None
2470 */
2471 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
2472 {
2473 CLEAR_BIT(RCC->APB2ENR, Periphs);
2474 }
2475
2476 /**
2477 * @brief Force APB2 peripherals reset.
2478 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
2479 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
2480 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
2481 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
2482 * APB2ENR UART9RST LL_APB2_GRP1_ForceReset\n (*)
2483 * APB2ENR USART10RST LL_APB2_GRP1_ForceReset\n (*)
2484 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
2485 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
2486 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
2487 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
2488 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
2489 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
2490 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
2491 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
2492 * APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset\n (*)
2493 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
2494 * APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset (*)
2495 * @param Periphs This parameter can be a combination of the following values:
2496 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2497 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2498 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2499 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2500 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2501 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2502 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2503 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2504 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2505 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2506 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2507 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2508 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2509 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2510 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2511 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2512 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2513 *
2514 * (*) value not defined in all devices.
2515 * @retval None
2516 */
2517 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
2518 {
2519 SET_BIT(RCC->APB2RSTR, Periphs);
2520 }
2521
2522 /**
2523 * @brief Release APB2 peripherals reset.
2524 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
2525 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
2526 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
2527 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
2528 * APB2ENR UART9RST LL_APB2_GRP1_ReleaseReset\n (*)
2529 * APB2ENR USART10RST LL_APB2_GRP1_ReleaseReset\n (*)
2530 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
2531 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
2532 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
2533 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
2534 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
2535 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
2536 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
2537 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
2538 * APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset\n (*)
2539 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
2540 * APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset (*)
2541 * @param Periphs This parameter can be a combination of the following values:
2542 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2543 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2544 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2545 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2546 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2547 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2548 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2549 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2550 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2551 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2552 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2553 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2554 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2555 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2556 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2557 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2558 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2559 *
2560 * (*) value not defined in all devices.
2561 * @retval None
2562 */
2563 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
2564 {
2565 CLEAR_BIT(RCC->APB2RSTR, Periphs);
2566 }
2567
2568 /**
2569 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
2570 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n
2571 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n
2572 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n
2573 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep\n
2574 * APB2ENR UART9LPEN LL_APB2_GRP1_EnableClockSleep\n (*)
2575 * APB2ENR USART10LPEN LL_APB2_GRP1_EnableClockSleep\n (*)
2576 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2577 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n
2578 * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n
2579 * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n
2580 * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n
2581 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n
2582 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n
2583 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n
2584 * APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep\n (*)
2585 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep\n
2586 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep (*)
2587 * @param Periphs This parameter can be a combination of the following values:
2588 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2589 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2590 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2591 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2592 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2593 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2594 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2595 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2596 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2597 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2598 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2599 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2600 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2601 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2602 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2603 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2604 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2605 * @retval None
2606 */
2607 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2608 {
2609 __IO uint32_t tmpreg;
2610 SET_BIT(RCC->APB2LPENR, Periphs);
2611 /* Delay after an RCC peripheral clock enabling */
2612 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2613 (void)tmpreg;
2614 }
2615
2616 /**
2617 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
2618 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n
2619 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n
2620 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n
2621 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep\n
2622 * APB2ENR UART9LPEN LL_APB2_GRP1_DisableClockSleep\n (*)
2623 * APB2ENR USART10LPEN LL_APB2_GRP1_DisableClockSleep\n (*)
2624 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2625 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n
2626 * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n
2627 * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n
2628 * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n
2629 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n
2630 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n
2631 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n
2632 * APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep\n (*)
2633 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep\n
2634 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep (*)
2635 * @param Periphs This parameter can be a combination of the following values:
2636 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2637 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
2638 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2639 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
2640 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2641 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
2642 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2643 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
2644 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
2645 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
2646 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
2647 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
2648 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
2649 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
2650 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
2651 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
2652 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
2653 * @retval None
2654 */
2655 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2656 {
2657 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2658 }
2659
2660 /**
2661 * @}
2662 */
2663
2664 /** @defgroup BUS_LL_EF_APB4 APB4
2665 * @{
2666 */
2667
2668 /**
2669 * @brief Enable APB4 peripherals clock.
2670 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock\n
2671 * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n
2672 * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n
2673 * APB4ENR I2C4EN LL_APB4_GRP1_EnableClock\n
2674 * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n
2675 * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n
2676 * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n (*)
2677 * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n (*)
2678 * APB4ENR DAC2EN LL_APB4_GRP1_EnableClock\n (*)
2679 * APB4ENR COMP12EN LL_APB4_GRP1_EnableClock\n
2680 * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n
2681 * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n
2682 * APB4ENR SAI4EN LL_APB4_GRP1_EnableClock\n (*)
2683 * APB4ENR DTSEN LL_APB4_GRP1_EnableClock\n (*)
2684 * APB4ENR DFSDM2EN LL_APB4_GRP1_EnableClock (*)
2685 * @param Periphs This parameter can be a combination of the following values:
2686 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2687 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2688 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2689 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2690 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2691 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2692 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2693 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2694 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2695 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2696 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2697 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2698 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2699 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2700 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2701 *
2702 * (*) value not defined in all devices.
2703 * @retval None
2704 */
2705 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
2706 {
2707 __IO uint32_t tmpreg;
2708 SET_BIT(RCC->APB4ENR, Periphs);
2709 /* Delay after an RCC peripheral clock enabling */
2710 tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
2711 (void)tmpreg;
2712 }
2713
2714 /**
2715 * @brief Check if APB4 peripheral clock is enabled or not
2716 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock\n
2717 * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n
2718 * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n
2719 * APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock\n
2720 * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n
2721 * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n
2722 * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n (*)
2723 * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n (*)
2724 * APB4ENR DAC2EN LL_APB4_GRP1_IsEnabledClock\n (*)
2725 * APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock\n
2726 * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n
2727 * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n
2728 * APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock\n (*)
2729 * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock\n (*)
2730 * APB4ENR DFSDM2EN LL_APB4_GRP1_IsEnabledClock (*)
2731 * @param Periphs This parameter can be a combination of the following values:
2732 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2733 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2734 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2735 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2736 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2737 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2738 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2739 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2740 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2741 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2742 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2743 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2744 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2745 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2746 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2747 *
2748 * (*) value not defined in all devices.
2749 * @retval uint32_t
2750 */
2751 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
2752 {
2753 return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);
2754 }
2755
2756 /**
2757 * @brief Disable APB4 peripherals clock.
2758 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock\n
2759 * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n
2760 * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n
2761 * APB4ENR I2C4EN LL_APB4_GRP1_DisableClock\n
2762 * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n
2763 * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n
2764 * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n (*)
2765 * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n (*)
2766 * APB4ENR DAC2EN LL_APB4_GRP1_DisableClock\n (*)
2767 * APB4ENR COMP12EN LL_APB4_GRP1_DisableClock\n
2768 * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n
2769 * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n
2770 * APB4ENR SAI4EN LL_APB4_GRP1_DisableClock\n (*)
2771 * APB4ENR DTSEN LL_APB4_GRP1_DisableClock\n (*)
2772 * APB4ENR DFSDM2EN LL_APB4_GRP1_DisableClock (*)
2773 * @param Periphs This parameter can be a combination of the following values:
2774 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2775 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2776 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2777 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2778 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2779 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2780 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2781 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2782 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2783 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2784 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2785 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2786 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2787 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2788 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2789 *
2790 * (*) value not defined in all devices.
2791 * @retval None
2792 */
2793 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
2794 {
2795 CLEAR_BIT(RCC->APB4ENR, Periphs);
2796 }
2797
2798 /**
2799 * @brief Force APB4 peripherals reset.
2800 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset\n
2801 * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n
2802 * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n
2803 * APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset\n
2804 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n
2805 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n
2806 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n (*)
2807 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n (*)
2808 * APB4RSTR DAC2EN LL_APB4_GRP1_ForceReset\n (*)
2809 * APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset\n
2810 * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n
2811 * APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset\n (*)
2812 * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset\n (*)
2813 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*)
2814 * @param Periphs This parameter can be a combination of the following values:
2815 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2816 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2817 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2818 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2819 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2820 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2821 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2822 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2823 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2824 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2825 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2826 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2827 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2828 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2829 *
2830 * (*) value not defined in all devices.
2831 * @retval None
2832 */
2833 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
2834 {
2835 SET_BIT(RCC->APB4RSTR, Periphs);
2836 }
2837
2838 /**
2839 * @brief Release APB4 peripherals reset.
2840 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset\n
2841 * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n
2842 * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n
2843 * APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset\n
2844 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n
2845 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n
2846 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n (*)
2847 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n (*)
2848 * APB4RSTR DAC2RST LL_APB4_GRP1_ReleaseReset\n (*)
2849 * APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset\n
2850 * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n
2851 * APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset\n
2852 * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset\n (*)
2853 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ReleaseReset (*)
2854 * @param Periphs This parameter can be a combination of the following values:
2855 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2856 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2857 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2858 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2859 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2860 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2861 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2862 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2863 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2864 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2865 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2866 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2867 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2868 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2869 *
2870 * (*) value not defined in all devices.
2871 * @retval None
2872 */
2873 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
2874 {
2875 CLEAR_BIT(RCC->APB4RSTR, Periphs);
2876 }
2877
2878 /**
2879 * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode.
2880 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep\n
2881 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n
2882 * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n
2883 * APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep\n
2884 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n
2885 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n
2886 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2887 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2888 * APB4LPENR DAC2LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2889 * APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep\n
2890 * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n
2891 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n
2892 * APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2893 * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep\n (*)
2894 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_EnableClockSleep (*)
2895 * @param Periphs This parameter can be a combination of the following values:
2896 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2897 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2898 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2899 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2900 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2901 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2902 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2903 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2904 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2905 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2906 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2907 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2908 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2909 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2910 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2911 *
2912 * (*) value not defined in all devices.
2913 * @retval None
2914 */
2915 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
2916 {
2917 __IO uint32_t tmpreg;
2918 SET_BIT(RCC->APB4LPENR, Periphs);
2919 /* Delay after an RCC peripheral clock enabling */
2920 tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
2921 (void)tmpreg;
2922 }
2923
2924 /**
2925 * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode.
2926 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep\n
2927 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n
2928 * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n
2929 * APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep\n
2930 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n
2931 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n
2932 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
2933 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
2934 * APB4LPENR DAC2LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
2935 * APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep\n
2936 * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n
2937 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n
2938 * APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep\n (*)
2939 * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep\n (*)
2940 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_DisableClockSleep (*)
2941 * @param Periphs This parameter can be a combination of the following values:
2942 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
2943 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
2944 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
2945 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
2946 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
2947 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
2948 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
2949 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
2950 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*)
2951 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
2952 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
2953 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
2954 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
2955 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
2956 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
2957 *
2958 * (*) value not defined in all devices.
2959 * @retval None
2960 */
2961 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
2962 {
2963 CLEAR_BIT(RCC->APB4LPENR, Periphs);
2964 }
2965
2966 /**
2967 * @}
2968 */
2969
2970 /** @defgroup BUS_LL_EF_CLKAM
2971 * @{
2972 */
2973
2974 /**
2975 * @brief Enable peripherals clock for CLKAM Mode.
2976 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Enable\n
2977 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Enable\n
2978 * D3AMR / SRDAMR SPI6 LL_CLKAM_Enable\n
2979 * D3AMR / SRDAMR I2C4 LL_CLKAM_Enable\n
2980 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Enable\n
2981 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Enable\n
2982 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Enable\n (*)
2983 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Enable\n (*)
2984 * D3AMR / SRDAMR DAC2 LL_CLKAM_Enable\n (*)
2985 * D3AMR / SRDAMR COMP12 LL_CLKAM_Enable\n
2986 * D3AMR / SRDAMR VREF LL_CLKAM_Enable\n
2987 * D3AMR / SRDAMR RTC LL_CLKAM_Enable\n
2988 * D3AMR / SRDAMR CRC LL_CLKAM_Enable\n
2989 * D3AMR / SRDAMR SAI4 LL_CLKAM_Enable\n (*)
2990 * D3AMR / SRDAMR ADC3 LL_CLKAM_Enable\n (*)
2991 * D3AMR / SRDAMR DTS LL_CLKAM_Enable\n (*)
2992 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Enable\n (*)
2993 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Enable\n
2994 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable
2995 * @param Periphs This parameter can be a combination of the following values:
2996 * @arg @ref LL_CLKAM_PERIPH_BDMA
2997 * @arg @ref LL_CLKAM_PERIPH_LPUART1
2998 * @arg @ref LL_CLKAM_PERIPH_SPI6
2999 * @arg @ref LL_CLKAM_PERIPH_I2C4
3000 * @arg @ref LL_CLKAM_PERIPH_LPTIM2
3001 * @arg @ref LL_CLKAM_PERIPH_LPTIM3
3002 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
3003 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
3004 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*)
3005 * @arg @ref LL_CLKAM_PERIPH_COMP12
3006 * @arg @ref LL_CLKAM_PERIPH_VREF
3007 * @arg @ref LL_CLKAM_PERIPH_RTC
3008 * @arg @ref LL_CLKAM_PERIPH_CRC
3009 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
3010 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
3011 * @arg @ref LL_CLKAM_PERIPH_DTS (*)
3012 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
3013 * @arg @ref LL_CLKAM_PERIPH_BKPRAM
3014 * @arg @ref LL_CLKAM_PERIPH_SRAM4
3015 *
3016 * (*) value not defined in all devices.
3017 * @retval None
3018 */
3019 __STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
3020 {
3021 __IO uint32_t tmpreg;
3022
3023 #if defined(RCC_D3AMR_BDMAAMEN)
3024 SET_BIT(RCC->D3AMR, Periphs);
3025 /* Delay after an RCC peripheral clock enabling */
3026 tmpreg = READ_BIT(RCC->D3AMR, Periphs);
3027 #else
3028 SET_BIT(RCC->SRDAMR, Periphs);
3029 /* Delay after an RCC peripheral clock enabling */
3030 tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
3031 #endif /* RCC_D3AMR_BDMAAMEN */
3032 (void)tmpreg;
3033 }
3034
3035 /**
3036 * @brief Disable peripherals clock for CLKAM Mode.
3037 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Disable\n
3038 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Disable\n
3039 * D3AMR / SRDAMR SPI6 LL_CLKAM_Disable\n
3040 * D3AMR / SRDAMR I2C4 LL_CLKAM_Disable\n
3041 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Disable\n
3042 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Disable\n
3043 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Disable\n (*)
3044 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Disable\n (*)
3045 * D3AMR / SRDAMR DAC2 LL_CLKAM_Disable\n (*)
3046 * D3AMR / SRDAMR COMP12 LL_CLKAM_Disable\n
3047 * D3AMR / SRDAMR VREF LL_CLKAM_Disable\n
3048 * D3AMR / SRDAMR RTC LL_CLKAM_Disable\n
3049 * D3AMR / SRDAMR CRC LL_CLKAM_Disable\n
3050 * D3AMR / SRDAMR SAI4 LL_CLKAM_Disable\n (*)
3051 * D3AMR / SRDAMR ADC3 LL_CLKAM_Disable\n (*)
3052 * D3AMR / SRDAMR DTS LL_CLKAM_Disable\n (*)
3053 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Disable\n (*)
3054 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Disable\n
3055 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable
3056 * @param Periphs This parameter can be a combination of the following values:
3057 * @arg @ref LL_CLKAM_PERIPH_BDMA
3058 * @arg @ref LL_CLKAM_PERIPH_LPUART1
3059 * @arg @ref LL_CLKAM_PERIPH_SPI6
3060 * @arg @ref LL_CLKAM_PERIPH_I2C4
3061 * @arg @ref LL_CLKAM_PERIPH_LPTIM2
3062 * @arg @ref LL_CLKAM_PERIPH_LPTIM3
3063 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
3064 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
3065 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*)
3066 * @arg @ref LL_CLKAM_PERIPH_COMP12
3067 * @arg @ref LL_CLKAM_PERIPH_VREF
3068 * @arg @ref LL_CLKAM_PERIPH_RTC
3069 * @arg @ref LL_CLKAM_PERIPH_CRC
3070 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
3071 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
3072 * @arg @ref LL_CLKAM_PERIPH_DTS (*)
3073 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
3074 * @arg @ref LL_CLKAM_PERIPH_BKPRAM
3075 * @arg @ref LL_CLKAM_PERIPH_SRAM4
3076 *
3077 * (*) value not defined in all devices.
3078 * @retval None
3079 */
3080 __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
3081 {
3082 #if defined(RCC_D3AMR_BDMAAMEN)
3083 CLEAR_BIT(RCC->D3AMR, Periphs);
3084 #else
3085 CLEAR_BIT(RCC->SRDAMR, Periphs);
3086 #endif /* RCC_D3AMR_BDMAAMEN */
3087 }
3088
3089 #if defined(RCC_CKGAENR_AXICKG)
3090 /**
3091 * @}
3092 */
3093
3094 /**
3095 * @brief Enable clock gating for AXI bus peripherals.
3096 * @rmtoll
3097 * @param :
3098 * @retval None
3099 */
3100 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
3101 {
3102 __IO uint32_t tmpreg;
3103 SET_BIT(RCC->CKGAENR, Periphs);
3104 /* Delay after an RCC peripheral clock enabling */
3105 tmpreg = READ_BIT(RCC->CKGAENR, Periphs);
3106 (void)tmpreg;
3107 }
3108 /**
3109 * @}
3110 */
3111 #endif /* RCC_CKGAENR_AXICKG */
3112
3113 #if defined(RCC_CKGAENR_AXICKG)
3114 /**
3115 * @}
3116 */
3117
3118 /**
3119 * @brief Disable clock gating for AXI bus peripherals.
3120 * @rmtoll
3121 * @param :
3122 * @retval None
3123 */
3124 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
3125 {
3126 CLEAR_BIT(RCC->CKGAENR, Periphs);
3127 }
3128 /**
3129 * @}
3130 */
3131 #endif /* RCC_CKGAENR_AXICKG */
3132
3133
3134 #if defined(DUAL_CORE)
3135 /** @defgroup BUS_LL_EF_AHB3 AHB3
3136 * @{
3137 */
3138
3139 /**
3140 * @brief Enable C1 AHB3 peripherals clock.
3141 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_EnableClock\n
3142 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_EnableClock\n
3143 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_EnableClock\n
3144 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_EnableClock\n
3145 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_EnableClock\n (*)
3146 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3147 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3148 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_EnableClock\n (*)
3149 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3150 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_EnableClock\n (*)
3151 * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_EnableClock\n (*)
3152 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_EnableClock
3153 * @param Periphs This parameter can be a combination of the following values:
3154 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
3155 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3156 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
3157 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3158 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3159 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3160 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3161 * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
3162 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3163 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3164 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3165 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3166 *
3167 * (*) value not defined in all devices.
3168 * @retval None
3169 */
3170 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
3171 {
3172 __IO uint32_t tmpreg;
3173 SET_BIT(RCC_C1->AHB3ENR, Periphs);
3174 /* Delay after an RCC peripheral clock enabling */
3175 tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);
3176 (void)tmpreg;
3177 }
3178
3179 /**
3180 * @brief Check if C1 AHB3 peripheral clock is enabled or not
3181 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3182 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3183 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3184 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_IsEnabledClock\n
3185 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3186 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3187 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3188 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3189 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3190 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3191 * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
3192 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_IsEnabledClock
3193 * @param Periphs This parameter can be a combination of the following values:
3194 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
3195 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3196 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
3197 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3198 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3199 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3200 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3201 * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
3202 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3203 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3204 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3205 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3206 *
3207 * (*) value not defined in all devices.
3208 * @retval uint32_t
3209 */
3210 __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
3211 {
3212 return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);
3213 }
3214
3215 /**
3216 * @brief Disable C1 AHB3 peripherals clock.
3217 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_DisableClock\n
3218 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_DisableClock\n
3219 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_DisableClock\n
3220 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_DisableClock\n
3221 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_DisableClock\n (*)
3222 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3223 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3224 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_DisableClock\n (*)
3225 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3226 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_DisableClock\n (*)
3227 * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_DisableClock\n (*)
3228 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_DisableClock
3229 * @param Periphs This parameter can be a combination of the following values:
3230 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
3231 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3232 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
3233 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3234 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3235 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3236 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3237 * @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR (*)
3238 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3239 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3240 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3241 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3242 *
3243 * (*) value not defined in all devices.
3244 * @retval None
3245 */
3246 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)
3247 {
3248 CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);
3249 }
3250
3251 /**
3252 * @brief Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
3253 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3254 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3255 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3256 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3257 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3258 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3259 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3260 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3261 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3262 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3263 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*)
3264 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3265 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3266 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3267 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3268 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n
3269 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_EnableClockSleep
3270 * @param Periphs This parameter can be a combination of the following values:
3271 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3272 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
3273 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3274 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3275 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3276 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3277 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3278 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3279 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3280 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3281 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3282 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
3283 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
3284 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
3285 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
3286 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
3287 *
3288 * (*) value not defined in all devices.
3289 * @retval None
3290 */
3291 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
3292 {
3293 __IO uint32_t tmpreg;
3294 SET_BIT(RCC_C1->AHB3LPENR, Periphs);
3295 /* Delay after an RCC peripheral clock enabling */
3296 tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);
3297 (void)tmpreg;
3298 }
3299
3300 /**
3301 * @brief Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
3302 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3303 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3304 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3305 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3306 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3307 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3308 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3309 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3310 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3311 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3312 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*)
3313 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3314 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3315 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3316 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3317 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n
3318 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_DisableClockSleep
3319 * @param Periphs This parameter can be a combination of the following values:
3320 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
3321 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
3322 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
3323 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
3324 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
3325 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
3326 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
3327 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
3328 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
3329 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
3330 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
3331 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
3332 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
3333 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
3334 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
3335 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
3336 *
3337 * (*) value not defined in all devices.
3338 * @retval None
3339 */
3340 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
3341 {
3342 CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);
3343 }
3344
3345 /**
3346 * @}
3347 */
3348
3349 /** @defgroup BUS_LL_EF_AHB1 AHB1
3350 * @{
3351 */
3352
3353 /**
3354 * @brief Enable C1 AHB1 peripherals clock.
3355 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_EnableClock\n
3356 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_EnableClock\n
3357 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_EnableClock\n
3358 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3359 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3360 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3361 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3362 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3363 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n
3364 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock\n
3365 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n (*)
3366 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock (*)
3367 * @param Periphs This parameter can be a combination of the following values:
3368 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3369 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3370 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3371 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3372 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3373 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3374 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3375 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3376 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3377 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3378 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3379 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3380 *
3381 * (*) value not defined in all devices.
3382 * @retval None
3383 */
3384 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)
3385 {
3386 __IO uint32_t tmpreg;
3387 SET_BIT(RCC_C1->AHB1ENR, Periphs);
3388 /* Delay after an RCC peripheral clock enabling */
3389 tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);
3390 (void)tmpreg;
3391 }
3392
3393 /**
3394 * @brief Check if C1 AHB1 peripheral clock is enabled or not
3395 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_IsEnabledClock\n
3396 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_IsEnabledClock\n
3397 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_IsEnabledClock\n
3398 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3399 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3400 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3401 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3402 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3403 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n
3404 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock\n
3405 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*)
3406 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock (*)
3407 * @param Periphs This parameter can be a combination of the following values:
3408 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3409 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3410 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3411 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3412 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3413 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3414 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3415 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3416 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3417 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3418 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3419 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3420 *
3421 * (*) value not defined in all devices.
3422 * @retval uint32_t
3423 */
3424 __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
3425 {
3426 return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);
3427 }
3428
3429 /**
3430 * @brief Disable C1 AHB1 peripherals clock.
3431 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_DisableClock\n
3432 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_DisableClock\n
3433 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_DisableClock\n
3434 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3435 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3436 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3437 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3438 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3439 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n
3440 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock\n
3441 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n (*)
3442 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock (*)
3443 * @param Periphs This parameter can be a combination of the following values:
3444 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3445 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3446 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3447 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3448 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3449 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3450 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3451 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3452 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3453 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3454 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3455 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3456 *
3457 * (*) value not defined in all devices.
3458 * @retval None
3459 */
3460 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)
3461 {
3462 CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);
3463 }
3464
3465 /**
3466 * @brief Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
3467 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3468 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3469 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3470 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3471 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3472 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3473 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3474 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3475 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3476 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep\n
3477 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
3478 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep (*)
3479 * @param Periphs This parameter can be a combination of the following values:
3480 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3481 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3482 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3483 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3484 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3485 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3486 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3487 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3488 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3489 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3490 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3491 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3492 *
3493 * (*) value not defined in all devices.
3494 * @retval None
3495 */
3496 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
3497 {
3498 __IO uint32_t tmpreg;
3499 SET_BIT(RCC_C1->AHB1LPENR, Periphs);
3500 /* Delay after an RCC peripheral clock enabling */
3501 tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);
3502 (void)tmpreg;
3503 }
3504
3505 /**
3506 * @brief Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
3507 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3508 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3509 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3510 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3511 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3512 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3513 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3514 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3515 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3516 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep\n
3517 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
3518 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep (*)
3519 * @param Periphs This parameter can be a combination of the following values:
3520 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
3521 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
3522 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
3523 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
3524 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
3525 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
3526 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
3527 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
3528 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
3529 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
3530 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
3531 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
3532 *
3533 * (*) value not defined in all devices.
3534 * @retval None
3535 */
3536 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
3537 {
3538 CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);
3539 }
3540
3541 /**
3542 * @}
3543 */
3544
3545 /** @defgroup BUS_LL_EF_AHB2 AHB2
3546 * @{
3547 */
3548
3549 /**
3550 * @brief Enable C1 AHB2 peripherals clock.
3551 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_EnableClock\n
3552 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_EnableClock\n (*)
3553 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_EnableClock\n (*)
3554 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_EnableClock\n (*)
3555 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_EnableClock\n
3556 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_EnableClock\n
3557 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_EnableClock\n (*)
3558 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_EnableClock\n
3559 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_EnableClock\n
3560 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_EnableClock (*)
3561 * @param Periphs This parameter can be a combination of the following values:
3562 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3563 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
3564 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3565 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3566 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3567 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3568 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3569 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3570 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3571 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3572 *
3573 * (*) value not defined in all devices.
3574 * @retval None
3575 */
3576 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)
3577 {
3578 __IO uint32_t tmpreg;
3579 SET_BIT(RCC_C1->AHB2ENR, Periphs);
3580 /* Delay after an RCC peripheral clock enabling */
3581 tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);
3582 (void)tmpreg;
3583 }
3584
3585 /**
3586 * @brief Check if C1 AHB2 peripheral clock is enabled or not
3587 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_IsEnabledClock\n
3588 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3589 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3590 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3591 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_IsEnabledClock\n
3592 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_IsEnabledClock\n
3593 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
3594 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_IsEnabledClock\n
3595 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_IsEnabledClock\n
3596 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_IsEnabledClock (*)
3597 * @param Periphs This parameter can be a combination of the following values:
3598 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3599 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
3600 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3601 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3602 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3603 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3604 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3605 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3606 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3607 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3608 *
3609 * (*) value not defined in all devices.
3610 * @retval uint32_t
3611 */
3612 __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
3613 {
3614 return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);
3615 }
3616
3617 /**
3618 * @brief Disable C1 AHB2 peripherals clock.
3619 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_DisableClock\n
3620 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_DisableClock\n (*)
3621 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_DisableClock\n (*)
3622 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_DisableClock\n (*)
3623 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_DisableClock\n
3624 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_DisableClock\n
3625 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_DisableClock\n (*)
3626 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_DisableClock\n
3627 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_DisableClock\n
3628 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_DisableClock (*)
3629 * @param Periphs This parameter can be a combination of the following values:
3630 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3631 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
3632 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3633 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3634 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3635 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
3636 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3637 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3638 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3639 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3640 *
3641 * (*) value not defined in all devices.
3642 * @retval None
3643 */
3644 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)
3645 {
3646 CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);
3647 }
3648
3649 /**
3650 * @brief Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
3651 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3652 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
3653 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
3654 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3655 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3656 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3657 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
3658 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n
3659 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_EnableClockSleep (*)
3660 * @param Periphs This parameter can be a combination of the following values:
3661 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3662 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3663 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3664 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3665 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3666 * @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
3667 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3668 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3669 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3670 *
3671 * (*) value not defined in all devices.
3672 * @retval None
3673 */
3674 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
3675 {
3676 __IO uint32_t tmpreg;
3677 SET_BIT(RCC_C1->AHB2LPENR, Periphs);
3678 /* Delay after an RCC peripheral clock enabling */
3679 tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);
3680 (void)tmpreg;
3681 }
3682
3683 /**
3684 * @brief Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
3685 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3686 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
3687 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
3688 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3689 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3690 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
3691 * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3692 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n
3693 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_DisableClockSleep
3694 * @param Periphs This parameter can be a combination of the following values:
3695 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
3696 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
3697 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
3698 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
3699 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
3700 * @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
3701 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
3702 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
3703 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
3704 *
3705 * (*) value not defined in all devices.
3706 * @retval None
3707 */
3708 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
3709 {
3710 CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);
3711 }
3712
3713 /**
3714 * @}
3715 */
3716
3717 /** @defgroup BUS_LL_EF_AHB4 AHB4
3718 * @{
3719 */
3720
3721 /**
3722 * @brief Enable C1 AHB4 peripherals clock.
3723 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_EnableClock\n
3724 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_EnableClock\n
3725 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_EnableClock\n
3726 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_EnableClock\n
3727 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_EnableClock\n
3728 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_EnableClock\n
3729 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_EnableClock\n
3730 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_EnableClock\n
3731 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_EnableClock\n
3732 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_EnableClock\n
3733 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_EnableClock\n
3734 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_EnableClock\n (*)
3735 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_EnableClock\n
3736 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_EnableClock\n (*)
3737 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_EnableClock\n (*)
3738 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_EnableClock\n
3739 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_EnableClock
3740 * @param Periphs This parameter can be a combination of the following values:
3741 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3742 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3743 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3744 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3745 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3746 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3747 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3748 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3749 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
3750 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3751 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3752 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3753 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3754 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
3755 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
3756 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
3757 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
3758 *
3759 * (*) value not defined in all devices.
3760 * @retval None
3761 */
3762 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)
3763 {
3764 __IO uint32_t tmpreg;
3765 SET_BIT(RCC_C1->AHB4ENR, Periphs);
3766 /* Delay after an RCC peripheral clock enabling */
3767 tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);
3768 (void)tmpreg;
3769 }
3770
3771 /**
3772 * @brief Check if C1 AHB4 peripheral clock is enabled or not
3773 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3774 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3775 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3776 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3777 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3778 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3779 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3780 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3781 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3782 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3783 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3784 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
3785 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3786 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
3787 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
3788 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_IsEnabledClock\n
3789 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_IsEnabledClock
3790 * @param Periphs This parameter can be a combination of the following values:
3791 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3792 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3793 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3794 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3795 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3796 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3797 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3798 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3799 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
3800 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3801 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3802 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3803 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3804 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
3805 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
3806 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
3807 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
3808 *
3809 * (*) value not defined in all devices.
3810 * @retval uint32_t
3811 */
3812 __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
3813 {
3814 return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);
3815 }
3816
3817 /**
3818 * @brief Disable C1 AHB4 peripherals clock.
3819 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_DisableClock\n
3820 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_DisableClock\n
3821 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_DisableClock\n
3822 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_DisableClock\n
3823 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_DisableClock\n
3824 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_DisableClock\n
3825 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_DisableClock\n
3826 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_DisableClock\n
3827 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_DisableClock\n
3828 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_DisableClock\n
3829 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_DisableClock\n
3830 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_DisableClock\n (*)
3831 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_DisableClock\n
3832 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_DisableClock\n (*)
3833 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_DisableClock\n (*)
3834 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_DisableClock\n
3835 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_DisableClock
3836 * @param Periphs This parameter can be a combination of the following values:
3837 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3838 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3839 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3840 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3841 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3842 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3843 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3844 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3845 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
3846 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3847 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3848 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3849 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3850 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
3851 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
3852 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
3853 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
3854 *
3855 * (*) value not defined in all devices.
3856 * @retval None
3857 */
3858 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)
3859 {
3860 CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);
3861 }
3862
3863 /**
3864 * @brief Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
3865 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3866 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3867 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3868 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3869 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3870 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3871 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3872 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3873 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3874 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3875 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3876 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
3877 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3878 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
3879 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n
3880 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_EnableClockSleep
3881 * @param Periphs This parameter can be a combination of the following values:
3882 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3883 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3884 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3885 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3886 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3887 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3888 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3889 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3890 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
3891 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3892 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3893 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3894 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3895 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
3896 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
3897 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
3898 * @retval None
3899 */
3900 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
3901 {
3902 __IO uint32_t tmpreg;
3903 SET_BIT(RCC_C1->AHB4LPENR, Periphs);
3904 /* Delay after an RCC peripheral clock enabling */
3905 tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);
3906 (void)tmpreg;
3907 }
3908
3909 /**
3910 * @brief Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
3911 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3912 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3913 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3914 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3915 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3916 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3917 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3918 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3919 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3920 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3921 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3922 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
3923 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3924 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
3925 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n
3926 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_DisableClockSleep
3927 * @param Periphs This parameter can be a combination of the following values:
3928 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
3929 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
3930 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
3931 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
3932 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
3933 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
3934 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
3935 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
3936 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
3937 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
3938 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
3939 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*)
3940 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
3941 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
3942 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
3943 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
3944 * @retval None
3945 */
3946 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
3947 {
3948 CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);
3949 }
3950
3951 /**
3952 * @}
3953 */
3954
3955 /** @defgroup BUS_LL_EF_APB3 APB3
3956 * @{
3957 */
3958
3959 /**
3960 * @brief Enable C1 APB3 peripherals clock.
3961 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_EnableClock\n (*)
3962 * APB3ENR DSIEN LL_C1_APB3_GRP1_EnableClock\n (*)
3963 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_EnableClock
3964 * @param Periphs This parameter can be a combination of the following values:
3965 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
3966 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
3967 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
3968 *
3969 * (*) value not defined in all devices.
3970 * @retval None
3971 */
3972 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)
3973 {
3974 __IO uint32_t tmpreg;
3975 SET_BIT(RCC_C1->APB3ENR, Periphs);
3976 /* Delay after an RCC peripheral clock enabling */
3977 tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);
3978 (void)tmpreg;
3979 }
3980
3981 /**
3982 * @brief Check if C1 APB3 peripheral clock is enabled or not
3983 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_IsEnabledClock\n (*)
3984 * APB3ENR DSIEN LL_C1_APB3_GRP1_IsEnabledClock\n (*)
3985 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_IsEnabledClock
3986 * @param Periphs This parameter can be a combination of the following values:
3987 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
3988 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
3989 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
3990 *
3991 * (*) value not defined in all devices.
3992 * @retval uint32_t
3993 */
3994 __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
3995 {
3996 return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);
3997 }
3998
3999 /**
4000 * @brief Disable C1 APB3 peripherals clock.
4001 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_DisableClock\n (*)
4002 * APB3ENR DSIEN LL_C1_APB3_GRP1_DisableClock\n (*)
4003 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_DisableClock
4004 * @param Periphs This parameter can be a combination of the following values:
4005 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4006 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4007 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4008 *
4009 * (*) value not defined in all devices.
4010 * @retval None
4011 */
4012 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)
4013 {
4014 CLEAR_BIT(RCC_C1->APB3ENR, Periphs);
4015 }
4016
4017 /**
4018 * @brief Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.
4019 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*)
4020 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*)
4021 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_EnableClockSleep
4022 * @param Periphs This parameter can be a combination of the following values:
4023 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4024 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4025 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4026 *
4027 * (*) value not defined in all devices.
4028 * @retval None
4029 */
4030 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
4031 {
4032 __IO uint32_t tmpreg;
4033 SET_BIT(RCC_C1->APB3LPENR, Periphs);
4034 /* Delay after an RCC peripheral clock enabling */
4035 tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);
4036 (void)tmpreg;
4037 }
4038
4039 /**
4040 * @brief Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.
4041 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*)
4042 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*)
4043 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_DisableClockSleep
4044 * @param Periphs This parameter can be a combination of the following values:
4045 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
4046 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
4047 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
4048 *
4049 * (*) value not defined in all devices.
4050 * @retval None
4051 */
4052 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
4053 {
4054 CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);
4055 }
4056
4057 /**
4058 * @}
4059 */
4060
4061 /** @defgroup BUS_LL_EF_APB1 APB1
4062 * @{
4063 */
4064
4065 /**
4066 * @brief Enable C1 APB1 peripherals clock.
4067 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_EnableClock\n
4068 * APB1LENR TIM3EN LL_C1_APB1_GRP1_EnableClock\n
4069 * APB1LENR TIM4EN LL_C1_APB1_GRP1_EnableClock\n
4070 * APB1LENR TIM5EN LL_C1_APB1_GRP1_EnableClock\n
4071 * APB1LENR TIM6EN LL_C1_APB1_GRP1_EnableClock\n
4072 * APB1LENR TIM7EN LL_C1_APB1_GRP1_EnableClock\n
4073 * APB1LENR TIM12EN LL_C1_APB1_GRP1_EnableClock\n
4074 * APB1LENR TIM13EN LL_C1_APB1_GRP1_EnableClock\n
4075 * APB1LENR TIM14EN LL_C1_APB1_GRP1_EnableClock\n
4076 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_EnableClock\n
4077 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_EnableClock\n (*)
4078 * APB1LENR SPI2EN LL_C1_APB1_GRP1_EnableClock\n
4079 * APB1LENR SPI3EN LL_C1_APB1_GRP1_EnableClock\n
4080 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_EnableClock\n
4081 * APB1LENR USART2EN LL_C1_APB1_GRP1_EnableClock\n
4082 * APB1LENR USART3EN LL_C1_APB1_GRP1_EnableClock\n
4083 * APB1LENR UART4EN LL_C1_APB1_GRP1_EnableClock\n
4084 * APB1LENR UART5EN LL_C1_APB1_GRP1_EnableClock\n
4085 * APB1LENR I2C1EN LL_C1_APB1_GRP1_EnableClock\n
4086 * APB1LENR I2C2EN LL_C1_APB1_GRP1_EnableClock\n
4087 * APB1LENR I2C3EN LL_C1_APB1_GRP1_EnableClock\n
4088 * APB1LENR CECEN LL_C1_APB1_GRP1_EnableClock\n
4089 * APB1LENR DAC12EN LL_C1_APB1_GRP1_EnableClock\n
4090 * APB1LENR UART7EN LL_C1_APB1_GRP1_EnableClock\n
4091 * APB1LENR UART8EN LL_C1_APB1_GRP1_EnableClock
4092 * @param Periphs This parameter can be a combination of the following values:
4093 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4094 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4095 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4096 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4097 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4098 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4099 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4100 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4101 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4102 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4103 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4104 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4105 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4106 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4107 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4108 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4109 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4110 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4111 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4112 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4113 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4114 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4115 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4116 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4117 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4118 *
4119 * (*) value not defined in all devices.
4120 * @retval None
4121 */
4122 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)
4123 {
4124 __IO uint32_t tmpreg;
4125 SET_BIT(RCC_C1->APB1LENR, Periphs);
4126 /* Delay after an RCC peripheral clock enabling */
4127 tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);
4128 (void)tmpreg;
4129 }
4130
4131 /**
4132 * @brief Check if C1 APB1 peripheral clock is enabled or not
4133 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4134 * APB1LENR TIM3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4135 * APB1LENR TIM4EN LL_C1_APB1_GRP1_IsEnabledClock\n
4136 * APB1LENR TIM5EN LL_C1_APB1_GRP1_IsEnabledClock\n
4137 * APB1LENR TIM6EN LL_C1_APB1_GRP1_IsEnabledClock\n
4138 * APB1LENR TIM7EN LL_C1_APB1_GRP1_IsEnabledClock\n
4139 * APB1LENR TIM12EN LL_C1_APB1_GRP1_IsEnabledClock\n
4140 * APB1LENR TIM13EN LL_C1_APB1_GRP1_IsEnabledClock\n
4141 * APB1LENR TIM14EN LL_C1_APB1_GRP1_IsEnabledClock\n
4142 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_IsEnabledClock\n
4143 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_IsEnabledClock\n (*)
4144 * APB1LENR SPI2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4145 * APB1LENR SPI3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4146 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_IsEnabledClock\n
4147 * APB1LENR USART2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4148 * APB1LENR USART3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4149 * APB1LENR UART4EN LL_C1_APB1_GRP1_IsEnabledClock\n
4150 * APB1LENR UART5EN LL_C1_APB1_GRP1_IsEnabledClock\n
4151 * APB1LENR I2C1EN LL_C1_APB1_GRP1_IsEnabledClock\n
4152 * APB1LENR I2C2EN LL_C1_APB1_GRP1_IsEnabledClock\n
4153 * APB1LENR I2C3EN LL_C1_APB1_GRP1_IsEnabledClock\n
4154 * APB1LENR CECEN LL_C1_APB1_GRP1_IsEnabledClock\n
4155 * APB1LENR DAC12EN LL_C1_APB1_GRP1_IsEnabledClock\n
4156 * APB1LENR UART7EN LL_C1_APB1_GRP1_IsEnabledClock\n
4157 * APB1LENR UART8EN LL_C1_APB1_GRP1_IsEnabledClock
4158 * @param Periphs This parameter can be a combination of the following values:
4159 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4160 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4161 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4162 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4163 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4164 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4165 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4166 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4167 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4168 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4169 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4170 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4171 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4172 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4173 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4174 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4175 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4176 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4177 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4178 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4179 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4180 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4181 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4182 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4183 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4184 *
4185 * (*) value not defined in all devices.
4186 * @retval uint32_t
4187 */
4188 __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
4189 {
4190 return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);
4191 }
4192
4193 /**
4194 * @brief Disable C1 APB1 peripherals clock.
4195 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_DisableClock\n
4196 * APB1LENR TIM3EN LL_C1_APB1_GRP1_DisableClock\n
4197 * APB1LENR TIM4EN LL_C1_APB1_GRP1_DisableClock\n
4198 * APB1LENR TIM5EN LL_C1_APB1_GRP1_DisableClock\n
4199 * APB1LENR TIM6EN LL_C1_APB1_GRP1_DisableClock\n
4200 * APB1LENR TIM7EN LL_C1_APB1_GRP1_DisableClock\n
4201 * APB1LENR TIM12EN LL_C1_APB1_GRP1_DisableClock\n
4202 * APB1LENR TIM13EN LL_C1_APB1_GRP1_DisableClock\n
4203 * APB1LENR TIM14EN LL_C1_APB1_GRP1_DisableClock\n
4204 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_DisableClock\n
4205 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_DisableClock\n (*)
4206 * APB1LENR SPI2EN LL_C1_APB1_GRP1_DisableClock\n
4207 * APB1LENR SPI3EN LL_C1_APB1_GRP1_DisableClock\n
4208 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_DisableClock\n
4209 * APB1LENR USART2EN LL_C1_APB1_GRP1_DisableClock\n
4210 * APB1LENR USART3EN LL_C1_APB1_GRP1_DisableClock\n
4211 * APB1LENR UART4EN LL_C1_APB1_GRP1_DisableClock\n
4212 * APB1LENR UART5EN LL_C1_APB1_GRP1_DisableClock\n
4213 * APB1LENR I2C1EN LL_C1_APB1_GRP1_DisableClock\n
4214 * APB1LENR I2C2EN LL_C1_APB1_GRP1_DisableClock\n
4215 * APB1LENR I2C3EN LL_C1_APB1_GRP1_DisableClock\n
4216 * APB1LENR CECEN LL_C1_APB1_GRP1_DisableClock\n
4217 * APB1LENR DAC12EN LL_C1_APB1_GRP1_DisableClock\n
4218 * APB1LENR UART7EN LL_C1_APB1_GRP1_DisableClock\n
4219 * APB1LENR UART8EN LL_C1_APB1_GRP1_DisableClock
4220 * @param Periphs This parameter can be a combination of the following values:
4221 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4222 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4223 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4224 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4225 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4226 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4227 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4228 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4229 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4230 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4231 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4232 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4233 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4234 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4235 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4236 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4237 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4238 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4239 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4240 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4241 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4242 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4243 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4244 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4245 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4246 *
4247 * (*) value not defined in all devices.
4248 * @retval uint32_t
4249 */
4250 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)
4251 {
4252 CLEAR_BIT(RCC_C1->APB1LENR, Periphs);
4253 }
4254
4255 /**
4256 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4257 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4258 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4259 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4260 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4261 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4262 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4263 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4264 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4265 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4266 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4267 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n (*)
4268 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4269 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4270 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4271 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4272 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4273 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4274 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4275 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4276 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4277 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4278 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4279 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4280 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n
4281 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_EnableClockSleep
4282 * @param Periphs This parameter can be a combination of the following values:
4283 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4284 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4285 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4286 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4287 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4288 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4289 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4290 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4291 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4292 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4293 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4294 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4295 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4296 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4297 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4298 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4299 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4300 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4301 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4302 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4303 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4304 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4305 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4306 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4307 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4308 *
4309 * (*) value not defined in all devices.
4310 * @retval None
4311 */
4312 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
4313 {
4314 __IO uint32_t tmpreg;
4315 SET_BIT(RCC_C1->APB1LLPENR, Periphs);
4316 /* Delay after an RCC peripheral clock enabling */
4317 tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);
4318 (void)tmpreg;
4319 }
4320
4321 /**
4322 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4323 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4324 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4325 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4326 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4327 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4328 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4329 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4330 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4331 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4332 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4333 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n (*)
4334 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4335 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4336 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4337 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4338 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4339 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4340 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4341 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4342 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4343 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4344 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4345 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4346 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n
4347 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_DisableClockSleep
4348 * @param Periphs This parameter can be a combination of the following values:
4349 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
4350 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
4351 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
4352 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
4353 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
4354 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
4355 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
4356 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
4357 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
4358 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
4359 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
4360 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
4361 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
4362 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
4363 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
4364 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
4365 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
4366 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
4367 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
4368 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
4369 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
4370 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
4371 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
4372 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
4373 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
4374 *
4375 * (*) value not defined in all devices.
4376 * @retval None
4377 */
4378 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
4379 {
4380 CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);
4381 }
4382
4383 /**
4384 * @brief Enable C1 APB1 peripherals clock.
4385 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_EnableClock\n
4386 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_EnableClock\n
4387 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_EnableClock\n
4388 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_EnableClock\n
4389 * APB1HENR FDCANEN LL_C1_APB1_GRP2_EnableClock
4390 * @param Periphs This parameter can be a combination of the following values:
4391 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4392 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4393 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4394 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4395 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4396 * @retval None
4397 */
4398 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
4399 {
4400 __IO uint32_t tmpreg;
4401 SET_BIT(RCC_C1->APB1HENR, Periphs);
4402 /* Delay after an RCC peripheral clock enabling */
4403 tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);
4404 (void)tmpreg;
4405 }
4406
4407 /**
4408 * @brief Check if C1 APB1 peripheral clock is enabled or not
4409 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_IsEnabledClock\n
4410 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_IsEnabledClock\n
4411 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_IsEnabledClock\n
4412 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_IsEnabledClock\n
4413 * APB1HENR FDCANEN LL_C1_APB1_GRP2_IsEnabledClock
4414 * @param Periphs This parameter can be a combination of the following values:
4415 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4416 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4417 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4418 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4419 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4420 * @retval uint32_t
4421 */
4422 __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
4423 {
4424 return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);
4425 }
4426
4427 /**
4428 * @brief Disable C1 APB1 peripherals clock.
4429 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_DisableClock\n
4430 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_DisableClock\n
4431 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_DisableClock\n
4432 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_DisableClock\n
4433 * APB1HENR FDCANEN LL_C1_APB1_GRP2_DisableClock
4434 * @param Periphs This parameter can be a combination of the following values:
4435 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4436 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4437 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4438 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4439 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4440 * @retval None
4441 */
4442 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)
4443 {
4444 CLEAR_BIT(RCC_C1->APB1HENR, Periphs);
4445 }
4446
4447 /**
4448 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4449 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4450 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4451 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4452 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n
4453 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_EnableClockSleep
4454 * @param Periphs This parameter can be a combination of the following values:
4455 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4456 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4457 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4458 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4459 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4460 * @retval None
4461 */
4462 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
4463 {
4464 __IO uint32_t tmpreg;
4465 SET_BIT(RCC_C1->APB1HLPENR, Periphs);
4466 /* Delay after an RCC peripheral clock enabling */
4467 tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);
4468 (void)tmpreg;
4469 }
4470
4471 /**
4472 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
4473 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4474 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4475 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4476 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n
4477 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_DisableClockSleep
4478 * @param Periphs This parameter can be a combination of the following values:
4479 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
4480 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
4481 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
4482 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
4483 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
4484 * @retval None
4485 */
4486 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
4487 {
4488 CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);
4489 }
4490
4491 /**
4492 * @}
4493 */
4494
4495 /** @defgroup BUS_LL_EF_APB2 APB2
4496 * @{
4497 */
4498
4499 /**
4500 * @brief Enable C1 APB2 peripherals clock.
4501 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_EnableClock\n
4502 * APB2ENR TIM8EN LL_C1_APB2_GRP1_EnableClock\n
4503 * APB2ENR USART1EN LL_C1_APB2_GRP1_EnableClock\n
4504 * APB2ENR USART6EN LL_C1_APB2_GRP1_EnableClock\n
4505 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClock\n (*)
4506 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClock\n (*)
4507 * APB2ENR SPI1EN LL_C1_APB2_GRP1_EnableClock\n
4508 * APB2ENR SPI4EN LL_C1_APB2_GRP1_EnableClock\n
4509 * APB2ENR TIM15EN LL_C1_APB2_GRP1_EnableClock\n
4510 * APB2ENR TIM16EN LL_C1_APB2_GRP1_EnableClock\n
4511 * APB2ENR TIM17EN LL_C1_APB2_GRP1_EnableClock\n
4512 * APB2ENR SPI5EN LL_C1_APB2_GRP1_EnableClock\n
4513 * APB2ENR SAI1EN LL_C1_APB2_GRP1_EnableClock\n
4514 * APB2ENR SAI2EN LL_C1_APB2_GRP1_EnableClock\n
4515 * APB2ENR SAI3EN LL_C1_APB2_GRP1_EnableClock\n (*)
4516 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_EnableClock\n
4517 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_EnableClock (*)
4518 * @param Periphs This parameter can be a combination of the following values:
4519 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4520 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4521 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4522 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4523 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4524 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4525 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4526 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4527 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4528 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4529 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4530 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4531 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4532 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
4533 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4534 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4535 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4536 *
4537 * (*) value not defined in all devices.
4538 * @retval None
4539 */
4540 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)
4541 {
4542 __IO uint32_t tmpreg;
4543 SET_BIT(RCC_C1->APB2ENR, Periphs);
4544 /* Delay after an RCC peripheral clock enabling */
4545 tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);
4546 (void)tmpreg;
4547 }
4548
4549 /**
4550 * @brief Check if C1 APB2 peripheral clock is enabled or not
4551 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4552 * APB2ENR TIM8EN LL_C1_APB2_GRP1_IsEnabledClock\n
4553 * APB2ENR USART1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4554 * APB2ENR USART6EN LL_C1_APB2_GRP1_IsEnabledClock\n
4555 * APB2ENR UART9EN LL_C1_APB2_GRP1_IsEnabledClock\n (*)
4556 * APB2ENR USART10EN LL_C1_APB2_GRP1_IsEnabledClock\n (*)
4557 * APB2ENR SPI1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4558 * APB2ENR SPI4EN LL_C1_APB2_GRP1_IsEnabledClock\n
4559 * APB2ENR TIM15EN LL_C1_APB2_GRP1_IsEnabledClock\n
4560 * APB2ENR TIM16EN LL_C1_APB2_GRP1_IsEnabledClock\n
4561 * APB2ENR TIM17EN LL_C1_APB2_GRP1_IsEnabledClock\n
4562 * APB2ENR SPI5EN LL_C1_APB2_GRP1_IsEnabledClock\n
4563 * APB2ENR SAI1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4564 * APB2ENR SAI2EN LL_C1_APB2_GRP1_IsEnabledClock\n
4565 * APB2ENR SAI3EN LL_C1_APB2_GRP1_IsEnabledClock\n (*)
4566 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_IsEnabledClock\n
4567 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_IsEnabledClock (*)
4568 * @param Periphs This parameter can be a combination of the following values:
4569 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4570 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4571 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4572 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
4573 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4574 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4575 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4576 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4577 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4578 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4579 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4580 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4581 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4582 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
4583 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4584 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4585 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4586 *
4587 * (*) value not defined in all devices.
4588 * @retval None
4589 */
4590 __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
4591 {
4592 return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);
4593 }
4594
4595 /**
4596 * @brief Disable C1 APB2 peripherals clock.
4597 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_DisableClock\n
4598 * APB2ENR TIM8EN LL_C1_APB2_GRP1_DisableClock\n
4599 * APB2ENR USART1EN LL_C1_APB2_GRP1_DisableClock\n
4600 * APB2ENR USART6EN LL_C1_APB2_GRP1_DisableClock\n
4601 * APB2ENR UART9EN LL_C1_APB2_GRP1_DisableClock\n (*)
4602 * APB2ENR USART10EN LL_C1_APB2_GRP1_DisableClock\n (*)
4603 * APB2ENR SPI1EN LL_C1_APB2_GRP1_DisableClock\n
4604 * APB2ENR SPI4EN LL_C1_APB2_GRP1_DisableClock\n
4605 * APB2ENR TIM15EN LL_C1_APB2_GRP1_DisableClock\n
4606 * APB2ENR TIM16EN LL_C1_APB2_GRP1_DisableClock\n
4607 * APB2ENR TIM17EN LL_C1_APB2_GRP1_DisableClock\n
4608 * APB2ENR SPI5EN LL_C1_APB2_GRP1_DisableClock\n
4609 * APB2ENR SAI1EN LL_C1_APB2_GRP1_DisableClock\n
4610 * APB2ENR SAI2EN LL_C1_APB2_GRP1_DisableClock\n
4611 * APB2ENR SAI3EN LL_C1_APB2_GRP1_DisableClock\n (*)
4612 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_DisableClock\n
4613 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_DisableClock (*)
4614 * @param Periphs This parameter can be a combination of the following values:
4615 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4616 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4617 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4618 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4619 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4620 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4621 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4622 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4623 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4624 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4625 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4626 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4627 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
4628 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4629 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4630 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4631 *
4632 * (*) value not defined in all devices.
4633 * @retval None
4634 */
4635 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)
4636 {
4637 CLEAR_BIT(RCC_C1->APB2ENR, Periphs);
4638 }
4639
4640 /**
4641 * @brief Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.
4642 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4643 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4644 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4645 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4646 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClockSleep\n (*)
4647 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClockSleep\n (*)
4648 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4649 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4650 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4651 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4652 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4653 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4654 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4655 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4656 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_EnableClockSleep\n (*)
4657 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n
4658 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_EnableClockSleep (*)
4659 * @param Periphs This parameter can be a combination of the following values:
4660 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4661 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4662 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4663 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4664 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4665 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4666 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4667 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4668 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4669 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4670 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4671 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4672 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
4673 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4674 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4675 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4676 *
4677 * (*) value not defined in all devices.
4678 * @retval None
4679 */
4680 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
4681 {
4682 __IO uint32_t tmpreg;
4683 SET_BIT(RCC_C1->APB2LPENR, Periphs);
4684 /* Delay after an RCC peripheral clock enabling */
4685 tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);
4686 (void)tmpreg;
4687 }
4688
4689 /**
4690 * @brief Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.
4691 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4692 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4693 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4694 * APB2LPENR UART9LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*)
4695 * APB2LPENR USART10LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*)
4696 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4697 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4698 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4699 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4700 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4701 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4702 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4703 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4704 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4705 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*)
4706 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n
4707 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_DisableClockSleep (*)
4708 * @param Periphs This parameter can be a combination of the following values:
4709 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
4710 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
4711 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
4712 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
4713 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
4714 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
4715 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
4716 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
4717 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
4718 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
4719 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
4720 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
4721 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
4722 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
4723 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
4724 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
4725 *
4726 * (*) value not defined in all devices.
4727 * @retval None
4728 */
4729 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
4730 {
4731 CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);
4732 }
4733
4734 /**
4735 * @}
4736 */
4737
4738 /** @defgroup BUS_LL_EF_APB4 APB4
4739 * @{
4740 */
4741
4742 /**
4743 * @brief Enable C1 APB4 peripherals clock.
4744 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_EnableClock\n
4745 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_EnableClock\n
4746 * APB4ENR SPI6EN LL_C1_APB4_GRP1_EnableClock\n
4747 * APB4ENR I2C4EN LL_C1_APB4_GRP1_EnableClock\n
4748 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_EnableClock\n
4749 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_EnableClock\n
4750 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_EnableClock\n (*)
4751 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_EnableClock\n (*)
4752 * APB4ENR DAC2EN LL_C1_APB4_GRP1_EnableClock\n (*)
4753 * APB4ENR COMP12EN LL_C1_APB4_GRP1_EnableClock\n
4754 * APB4ENR VREFEN LL_C1_APB4_GRP1_EnableClock\n
4755 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_EnableClock\n
4756 * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClock\n (*)
4757 * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClock\n (*)
4758 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClock (*)
4759 * @param Periphs This parameter can be a combination of the following values:
4760 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
4761 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
4762 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
4763 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
4764 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
4765 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
4766 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
4767 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
4768 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
4769 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
4770 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
4771 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
4772 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
4773 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
4774 *
4775 * (*) value not defined in all devices.
4776 * @retval None
4777 */
4778 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)
4779 {
4780 __IO uint32_t tmpreg;
4781 SET_BIT(RCC_C1->APB4ENR, Periphs);
4782 /* Delay after an RCC peripheral clock enabling */
4783 tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);
4784 (void)tmpreg;
4785 }
4786
4787 /**
4788 * @brief Check if C1 APB4 peripheral clock is enabled or not
4789 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_IsEnabledClock\n
4790 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_IsEnabledClock\n
4791 * APB4ENR SPI6EN LL_C1_APB4_GRP1_IsEnabledClock\n
4792 * APB4ENR I2C4EN LL_C1_APB4_GRP1_IsEnabledClock\n
4793 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_IsEnabledClock\n
4794 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_IsEnabledClock\n
4795 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
4796 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
4797 * APB4ENR COMP12EN LL_C1_APB4_GRP1_IsEnabledClock\n
4798 * APB4ENR VREFEN LL_C1_APB4_GRP1_IsEnabledClock\n
4799 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_IsEnabledClock\n
4800 * APB4ENR SAI4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
4801 * APB4ENR DTSEN LL_C1_APB4_GRP1_IsEnabledClock\n (*)
4802 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_IsEnabledClock (*)
4803 * @param Periphs This parameter can be a combination of the following values:
4804 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
4805 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
4806 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
4807 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
4808 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
4809 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
4810 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
4811 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
4812 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
4813 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
4814 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
4815 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
4816 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
4817 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
4818 *
4819 * (*) value not defined in all devices.
4820 * @retval uint32_t
4821 */
4822 __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
4823 {
4824 return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);
4825 }
4826
4827 /**
4828 * @brief Disable C1 APB4 peripherals clock.
4829 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_DisableClock\n
4830 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_DisableClock\n
4831 * APB4ENR SPI6EN LL_C1_APB4_GRP1_DisableClock\n
4832 * APB4ENR I2C4EN LL_C1_APB4_GRP1_DisableClock\n
4833 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_DisableClock\n
4834 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_DisableClock\n
4835 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_DisableClock\n (*)
4836 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_DisableClock\n (*)
4837 * APB4ENR COMP12EN LL_C1_APB4_GRP1_DisableClock\n
4838 * APB4ENR VREFEN LL_C1_APB4_GRP1_DisableClock\n
4839 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_DisableClock\n
4840 * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClock\n (*)
4841 * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClock\n (*)
4842 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClock (*)
4843 * @param Periphs This parameter can be a combination of the following values:
4844 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
4845 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
4846 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
4847 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
4848 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
4849 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
4850 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
4851 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
4852 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
4853 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
4854 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
4855 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
4856 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
4857 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
4858 *
4859 * (*) value not defined in all devices.
4860 * @retval None
4861 */
4862 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)
4863 {
4864 CLEAR_BIT(RCC_C1->APB4ENR, Periphs);
4865 }
4866
4867 /**
4868 * @brief Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.
4869 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
4870 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
4871 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
4872 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
4873 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
4874 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
4875 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
4876 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
4877 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_EnableClockSleep\n
4878 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
4879 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_EnableClockSleep\n
4880 * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
4881 * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClockSleep\n (*)
4882 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClockSleep (*)
4883 * @param Periphs This parameter can be a combination of the following values:
4884 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
4885 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
4886 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
4887 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
4888 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
4889 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
4890 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
4891 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
4892 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
4893 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
4894 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
4895 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
4896 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
4897 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
4898 *
4899 * (*) value not defined in all devices.
4900 * @retval None
4901 */
4902 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
4903 {
4904 __IO uint32_t tmpreg;
4905 SET_BIT(RCC_C1->APB4LPENR, Periphs);
4906 /* Delay after an RCC peripheral clock enabling */
4907 tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);
4908 (void)tmpreg;
4909 }
4910
4911 /**
4912 * @brief Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.
4913 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4914 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4915 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4916 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4917 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4918 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4919 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4920 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4921 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4922 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4923 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_DisableClockSleep\n
4924 * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
4925 * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClockSleep\n (*)
4926 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClockSleep (*)
4927 * @param Periphs This parameter can be a combination of the following values:
4928 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
4929 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
4930 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
4931 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
4932 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
4933 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
4934 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
4935 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
4936 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
4937 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
4938 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
4939 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*)
4940 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*)
4941 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
4942 *
4943 * (*) value not defined in all devices.
4944 * @retval None
4945 */
4946 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
4947 {
4948 CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);
4949 }
4950
4951 /**
4952 * @}
4953 */
4954
4955 /** @defgroup BUS_LL_EF_AHB3 AHB3
4956 * @{
4957 */
4958
4959 /**
4960 * @brief Enable C2 AHB3 peripherals clock.
4961 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_EnableClock\n
4962 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_EnableClock\n
4963 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_EnableClock\n
4964 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_EnableClock\n
4965 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_EnableClock\n
4966 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_EnableClock\n
4967 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock\n
4968 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_EnableClock\n
4969 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_EnableClock\n
4970 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_EnableClock\n
4971 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_EnableClock
4972 * @param Periphs This parameter can be a combination of the following values:
4973 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
4974 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
4975 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
4976 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
4977 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
4978 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
4979 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
4980 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
4981 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
4982 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
4983 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
4984 * @retval None
4985 */
4986 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
4987 {
4988 __IO uint32_t tmpreg;
4989 SET_BIT(RCC_C2->AHB3ENR, Periphs);
4990 /* Delay after an RCC peripheral clock enabling */
4991 tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);
4992 (void)tmpreg;
4993 }
4994
4995 /**
4996 * @brief Check if C2 AHB3 peripheral clock is enabled or not
4997 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_IsEnabledClock\n
4998 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_IsEnabledClock\n
4999 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5000 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5001 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5002 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_IsEnabledClock\n
5003 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5004 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_IsEnabledClock\n
5005 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_IsEnabledClock\n
5006 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_IsEnabledClock\n
5007 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_IsEnabledClock
5008 * @param Periphs This parameter can be a combination of the following values:
5009 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
5010 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5011 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
5012 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5013 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
5014 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5015 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5016 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5017 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5018 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5019 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5020 * @retval uint32_t
5021 */
5022 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
5023 {
5024 return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);
5025 }
5026
5027 /**
5028 * @brief Disable C2 AHB3 peripherals clock.
5029 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_DisableClock\n
5030 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_DisableClock\n
5031 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_DisableClock\n
5032 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_DisableClock\n
5033 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_DisableClock\n
5034 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_DisableClock\n
5035 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock\n
5036 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_DisableClock\n
5037 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_DisableClock\n
5038 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_DisableClock\n
5039 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_DisableClock
5040 * @param Periphs This parameter can be a combination of the following values:
5041 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
5042 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5043 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
5044 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5045 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
5046 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5047 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5048 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5049 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5050 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5051 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5052 * @retval None
5053 */
5054 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
5055 {
5056 CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);
5057 }
5058
5059 /**
5060 * @brief Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
5061 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5062 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5063 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5064 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5065 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5066 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5067 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5068 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5069 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5070 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n
5071 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_EnableClockSleep
5072 * @param Periphs This parameter can be a combination of the following values:
5073 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5074 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
5075 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5076 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
5077 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5078 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5079 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5080 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5081 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5082 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5083 * @retval None
5084 */
5085 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
5086 {
5087 __IO uint32_t tmpreg;
5088 SET_BIT(RCC_C2->AHB3LPENR, Periphs);
5089 /* Delay after an RCC peripheral clock enabling */
5090 tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);
5091 (void)tmpreg;
5092 }
5093
5094 /**
5095 * @brief Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
5096 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5097 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5098 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5099 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5100 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5101 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5102 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5103 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5104 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5105 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n
5106 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_DisableClockSleep
5107 * @param Periphs This parameter can be a combination of the following values:
5108 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
5109 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
5110 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC
5111 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
5112 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
5113 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
5114 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
5115 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
5116 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
5117 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
5118 * @retval None
5119 */
5120 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
5121 {
5122 CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);
5123 }
5124
5125 /**
5126 * @}
5127 */
5128
5129 /** @defgroup BUS_LL_EF_AHB1 AHB1
5130 * @{
5131 */
5132
5133 /**
5134 * @brief Enable C2 AHB1 peripherals clock.
5135 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n
5136 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n
5137 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_EnableClock\n
5138 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_EnableClock\n
5139 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_EnableClock\n
5140 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_EnableClock\n
5141 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_EnableClock\n
5142 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n
5143 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock\n
5144 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n
5145 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock
5146 * @param Periphs This parameter can be a combination of the following values:
5147 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5148 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5149 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5150 * @arg @ref LL_AHB1_GRP1_PERIPH_ART
5151 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
5152 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
5153 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
5154 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5155 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5156 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
5157 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
5158 * @retval None
5159 */
5160 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
5161 {
5162 __IO uint32_t tmpreg;
5163 SET_BIT(RCC_C2->AHB1ENR, Periphs);
5164 /* Delay after an RCC peripheral clock enabling */
5165 tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);
5166 (void)tmpreg;
5167 }
5168
5169 /**
5170 * @brief Check if C2 AHB1 peripheral clock is enabled or not
5171 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
5172 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n
5173 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_IsEnabledClock\n
5174 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5175 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5176 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5177 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5178 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5179 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5180 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n
5181 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock
5182 * @param Periphs This parameter can be a combination of the following values:
5183 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5184 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5185 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5186 * @arg @ref LL_AHB1_GRP1_PERIPH_ART
5187 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
5188 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
5189 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
5190 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5191 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5192 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
5193 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
5194 * @retval uint32_t
5195 */
5196 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
5197 {
5198 return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);
5199 }
5200
5201 /**
5202 * @brief Disable C2 AHB1 peripherals clock.
5203 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n
5204 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n
5205 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_DisableClock\n
5206 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_DisableClock\n
5207 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_DisableClock\n
5208 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_DisableClock\n
5209 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_DisableClock\n
5210 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n
5211 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock\n
5212 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n
5213 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock
5214 * @param Periphs This parameter can be a combination of the following values:
5215 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5216 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5217 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5218 * @arg @ref LL_AHB1_GRP1_PERIPH_ART
5219 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
5220 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
5221 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
5222 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5223 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5224 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
5225 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
5226 * @retval None
5227 */
5228 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
5229 {
5230 CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);
5231 }
5232
5233 /**
5234 * @brief Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
5235 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5236 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5237 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5238 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5239 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5240 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5241 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5242 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5243 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5244 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n
5245 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep
5246 * @param Periphs This parameter can be a combination of the following values:
5247 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5248 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5249 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5250 * @arg @ref LL_AHB1_GRP1_PERIPH_ART
5251 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
5252 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
5253 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
5254 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5255 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5256 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
5257 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
5258 * @retval None
5259 */
5260 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
5261 {
5262 __IO uint32_t tmpreg;
5263 SET_BIT(RCC_C2->AHB1LPENR, Periphs);
5264 /* Delay after an RCC peripheral clock enabling */
5265 tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);
5266 (void)tmpreg;
5267 }
5268
5269 /**
5270 * @brief Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
5271 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5272 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5273 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5274 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5275 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5276 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5277 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5278 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5279 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5280 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n
5281 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep
5282 * @param Periphs This parameter can be a combination of the following values:
5283 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
5284 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
5285 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
5286 * @arg @ref LL_AHB1_GRP1_PERIPH_ART
5287 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
5288 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
5289 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
5290 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
5291 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
5292 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
5293 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
5294 * @retval None
5295 */
5296 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
5297 {
5298 CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);
5299 }
5300
5301 /**
5302 * @}
5303 */
5304
5305 /** @defgroup BUS_LL_EF_AHB2 AHB2
5306 * @{
5307 */
5308
5309 /**
5310 * @brief Enable C2 AHB2 peripherals clock.
5311 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_EnableClock\n
5312 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_EnableClock\n
5313 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_EnableClock\n
5314 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_EnableClock\n
5315 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_EnableClock
5316 * @param Periphs This parameter can be a combination of the following values:
5317 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5318 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5319 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5320 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5321 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5322 *
5323 * (*) value not defined in all devices.
5324 * @retval None
5325 */
5326 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
5327 {
5328 __IO uint32_t tmpreg;
5329 SET_BIT(RCC_C2->AHB2ENR, Periphs);
5330 /* Delay after an RCC peripheral clock enabling */
5331 tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);
5332 (void)tmpreg;
5333 }
5334
5335 /**
5336 * @brief Check if C2 AHB2 peripheral clock is enabled or not
5337 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5338 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5339 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5340 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_IsEnabledClock\n
5341 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_IsEnabledClock
5342 * @param Periphs This parameter can be a combination of the following values:
5343 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5344 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5345 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5346 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5347 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5348 *
5349 * (*) value not defined in all devices.
5350 * @retval uint32_t
5351 */
5352 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
5353 {
5354 return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);
5355 }
5356
5357 /**
5358 * @brief Disable C2 AHB2 peripherals clock.
5359 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_DisableClock\n
5360 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_DisableClock\n
5361 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_DisableClock\n
5362 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_DisableClock\n
5363 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_DisableClock
5364 * @param Periphs This parameter can be a combination of the following values:
5365 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5366 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5367 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5368 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5369 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5370 *
5371 * (*) value not defined in all devices.
5372 * @retval None
5373 */
5374 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
5375 {
5376 CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);
5377 }
5378
5379 /**
5380 * @brief Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
5381 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5382 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5383 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5384 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5385 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5386 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5387 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n
5388 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_EnableClockSleep
5389 * @param Periphs This parameter can be a combination of the following values:
5390 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5391 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5392 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5393 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5394 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5395 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
5396 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
5397 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
5398 *
5399 * (*) value not defined in all devices.
5400 * @retval None
5401 */
5402 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
5403 {
5404 __IO uint32_t tmpreg;
5405 SET_BIT(RCC_C2->AHB2LPENR, Periphs);
5406 /* Delay after an RCC peripheral clock enabling */
5407 tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);
5408 (void)tmpreg;
5409 }
5410
5411 /**
5412 * @brief Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
5413 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5414 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5415 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5416 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5417 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5418 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5419 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n
5420 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_DisableClockSleep
5421 * @param Periphs This parameter can be a combination of the following values:
5422 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
5423 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
5424 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
5425 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
5426 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
5427 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
5428 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
5429 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
5430 *
5431 * (*) value not defined in all devices.
5432 * @retval None
5433 */
5434 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
5435 {
5436 CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);
5437 }
5438
5439 /**
5440 * @}
5441 */
5442
5443 /** @defgroup BUS_LL_EF_AHB4 AHB4
5444 * @{
5445 */
5446
5447 /**
5448 * @brief Enable C2 AHB4 peripherals clock.
5449 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_EnableClock\n
5450 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_EnableClock\n
5451 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_EnableClock\n
5452 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_EnableClock\n
5453 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_EnableClock\n
5454 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_EnableClock\n
5455 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_EnableClock\n
5456 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_EnableClock\n
5457 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_EnableClock\n
5458 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_EnableClock\n
5459 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_EnableClock\n
5460 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_EnableClock\n
5461 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_EnableClock\n
5462 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_EnableClock\n
5463 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_EnableClock\n
5464 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_EnableClock\n
5465 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_EnableClock
5466 * @param Periphs This parameter can be a combination of the following values:
5467 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5468 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5469 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5470 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5471 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5472 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5473 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5474 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5475 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
5476 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5477 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5478 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
5479 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5480 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
5481 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
5482 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5483 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5484 *
5485 * (*) value not defined in all devices.
5486 * @retval None
5487 */
5488 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)
5489 {
5490 __IO uint32_t tmpreg;
5491 SET_BIT(RCC_C2->AHB4ENR, Periphs);
5492 /* Delay after an RCC peripheral clock enabling */
5493 tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);
5494 (void)tmpreg;
5495 }
5496
5497 /**
5498 * @brief Check if C2 AHB4 peripheral clock is enabled or not
5499 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5500 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5501 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5502 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5503 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5504 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5505 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5506 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5507 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5508 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5509 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5510 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5511 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5512 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_IsEnabledClock\n
5513 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5514 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_IsEnabledClock\n
5515 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_IsEnabledClock
5516 * @param Periphs This parameter can be a combination of the following values:
5517 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5518 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5519 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5520 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5521 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5522 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5523 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5524 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5525 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
5526 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5527 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5528 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
5529 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5530 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
5531 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
5532 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5533 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5534 *
5535 * (*) value not defined in all devices.
5536 * @retval uint32_t
5537 */
5538 __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
5539 {
5540 return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);
5541 }
5542
5543 /**
5544 * @brief Disable C2 AHB4 peripherals clock.
5545 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_DisableClock\n
5546 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_DisableClock\n
5547 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_DisableClock\n
5548 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_DisableClock\n
5549 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_DisableClock\n
5550 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_DisableClock\n
5551 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_DisableClock\n
5552 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_DisableClock\n
5553 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_DisableClock\n
5554 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_DisableClock\n
5555 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_DisableClock\n
5556 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_DisableClock\n
5557 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_DisableClock\n
5558 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_DisableClock\n
5559 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_DisableClock\n
5560 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_DisableClock\n
5561 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_DisableClock
5562 * @param Periphs This parameter can be a combination of the following values:
5563 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5564 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5565 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5566 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5567 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5568 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5569 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5570 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5571 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
5572 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5573 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5574 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
5575 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5576 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
5577 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
5578 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5579 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5580 *
5581 * (*) value not defined in all devices.
5582 * @retval None
5583 */
5584 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)
5585 {
5586 CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);
5587 }
5588
5589 /**
5590 * @brief Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
5591 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5592 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5593 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5594 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5595 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5596 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5597 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5598 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5599 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5600 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5601 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5602 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5603 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5604 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5605 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n
5606 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_EnableClockSleep
5607 * @param Periphs This parameter can be a combination of the following values:
5608 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5609 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5610 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5611 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5612 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5613 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5614 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5615 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5616 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
5617 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5618 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5619 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
5620 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5621 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
5622 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5623 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5624 * @retval None
5625 */
5626 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
5627 {
5628 __IO uint32_t tmpreg;
5629 SET_BIT(RCC_C2->AHB4LPENR, Periphs);
5630 /* Delay after an RCC peripheral clock enabling */
5631 tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);
5632 (void)tmpreg;
5633 }
5634
5635 /**
5636 * @brief Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
5637 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5638 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5639 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5640 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5641 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5642 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5643 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5644 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5645 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5646 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5647 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5648 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5649 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5650 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5651 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n
5652 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_DisableClockSleep
5653 * @param Periphs This parameter can be a combination of the following values:
5654 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
5655 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
5656 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
5657 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
5658 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
5659 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
5660 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
5661 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
5662 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
5663 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
5664 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
5665 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC
5666 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
5667 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
5668 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
5669 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
5670 * @retval None
5671 */
5672 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
5673 {
5674 CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);
5675 }
5676
5677 /**
5678 * @}
5679 */
5680
5681 /** @defgroup BUS_LL_EF_APB3 APB3
5682 * @{
5683 */
5684
5685 /**
5686 * @brief Enable C2 APB3 peripherals clock.
5687 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_EnableClock\n
5688 * APB3ENR DSIEN LL_C2_APB3_GRP1_EnableClock\n
5689 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_EnableClock
5690 * @param Periphs This parameter can be a combination of the following values:
5691 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
5692 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5693 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5694 *
5695 * (*) value not defined in all devices.
5696 * @retval None
5697 */
5698 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
5699 {
5700 __IO uint32_t tmpreg;
5701 SET_BIT(RCC_C2->APB3ENR, Periphs);
5702 /* Delay after an RCC peripheral clock enabling */
5703 tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);
5704 (void)tmpreg;
5705 }
5706
5707 /**
5708 * @brief Check if C2 APB3 peripheral clock is enabled or not
5709 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_IsEnabledClock\n
5710 * APB3ENR DSIEN LL_C2_APB3_GRP1_IsEnabledClock\n
5711 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_IsEnabledClock
5712 * @param Periphs This parameter can be a combination of the following values:
5713 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
5714 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5715 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5716 *
5717 * (*) value not defined in all devices.
5718 * @retval uint32_t
5719 */
5720 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
5721 {
5722 return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);
5723 }
5724
5725 /**
5726 * @brief Disable C2 APB3 peripherals clock.
5727 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_DisableClock\n
5728 * APB3ENR DSIEN LL_C2_APB3_GRP1_DisableClock\n
5729 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_DisableClock
5730 * @param Periphs This parameter can be a combination of the following values:
5731 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
5732 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5733 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5734 *
5735 * (*) value not defined in all devices.
5736 * @retval None
5737 */
5738 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
5739 {
5740 CLEAR_BIT(RCC_C2->APB3ENR, Periphs);
5741 }
5742
5743 /**
5744 * @brief Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.
5745 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_EnableClockSleep\n
5746 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_EnableClockSleep\n
5747 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_EnableClockSleep
5748 * @param Periphs This parameter can be a combination of the following values:
5749 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
5750 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5751 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5752 *
5753 * (*) value not defined in all devices.
5754 * @retval None
5755 */
5756 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
5757 {
5758 __IO uint32_t tmpreg;
5759 SET_BIT(RCC_C2->APB3LPENR, Periphs);
5760 /* Delay after an RCC peripheral clock enabling */
5761 tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);
5762 (void)tmpreg;
5763 }
5764
5765 /**
5766 * @brief Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.
5767 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_DisableClockSleep\n
5768 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_DisableClockSleep\n
5769 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_DisableClockSleep
5770 * @param Periphs This parameter can be a combination of the following values:
5771 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC
5772 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
5773 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
5774 *
5775 * (*) value not defined in all devices.
5776 * @retval None
5777 */
5778 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
5779 {
5780 CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);
5781 }
5782
5783 /**
5784 * @}
5785 */
5786
5787 /** @defgroup BUS_LL_EF_APB1 APB1
5788 * @{
5789 */
5790
5791 /**
5792 * @brief Enable C2 APB1 peripherals clock.
5793 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_EnableClock\n
5794 * APB1LENR TIM3EN LL_C2_APB1_GRP1_EnableClock\n
5795 * APB1LENR TIM4EN LL_C2_APB1_GRP1_EnableClock\n
5796 * APB1LENR TIM5EN LL_C2_APB1_GRP1_EnableClock\n
5797 * APB1LENR TIM6EN LL_C2_APB1_GRP1_EnableClock\n
5798 * APB1LENR TIM7EN LL_C2_APB1_GRP1_EnableClock\n
5799 * APB1LENR TIM12EN LL_C2_APB1_GRP1_EnableClock\n
5800 * APB1LENR TIM13EN LL_C2_APB1_GRP1_EnableClock\n
5801 * APB1LENR TIM14EN LL_C2_APB1_GRP1_EnableClock\n
5802 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_EnableClock\n
5803 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_EnableClock\n
5804 * APB1LENR SPI2EN LL_C2_APB1_GRP1_EnableClock\n
5805 * APB1LENR SPI3EN LL_C2_APB1_GRP1_EnableClock\n
5806 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_EnableClock\n
5807 * APB1LENR USART2EN LL_C2_APB1_GRP1_EnableClock\n
5808 * APB1LENR USART3EN LL_C2_APB1_GRP1_EnableClock\n
5809 * APB1LENR UART4EN LL_C2_APB1_GRP1_EnableClock\n
5810 * APB1LENR UART5EN LL_C2_APB1_GRP1_EnableClock\n
5811 * APB1LENR I2C1EN LL_C2_APB1_GRP1_EnableClock\n
5812 * APB1LENR I2C2EN LL_C2_APB1_GRP1_EnableClock\n
5813 * APB1LENR I2C3EN LL_C2_APB1_GRP1_EnableClock\n
5814 * APB1LENR CECEN LL_C2_APB1_GRP1_EnableClock\n
5815 * APB1LENR DAC12EN LL_C2_APB1_GRP1_EnableClock\n
5816 * APB1LENR UART7EN LL_C2_APB1_GRP1_EnableClock\n
5817 * APB1LENR UART8EN LL_C2_APB1_GRP1_EnableClock
5818 * @param Periphs This parameter can be a combination of the following values:
5819 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
5820 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
5821 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
5822 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
5823 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
5824 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
5825 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
5826 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
5827 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
5828 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
5829 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
5830 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
5831 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
5832 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
5833 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
5834 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
5835 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
5836 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
5837 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
5838 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
5839 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
5840 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
5841 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
5842 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
5843 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
5844 * @retval None
5845 */
5846 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
5847 {
5848 __IO uint32_t tmpreg;
5849 SET_BIT(RCC_C2->APB1LENR, Periphs);
5850 /* Delay after an RCC peripheral clock enabling */
5851 tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);
5852 (void)tmpreg;
5853 }
5854
5855 /**
5856 * @brief Check if C2 APB1 peripheral clock is enabled or not
5857 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n
5858 * APB1LENR TIM3EN LL_C2_APB1_GRP1_IsEnabledClock\n
5859 * APB1LENR TIM4EN LL_C2_APB1_GRP1_IsEnabledClock\n
5860 * APB1LENR TIM5EN LL_C2_APB1_GRP1_IsEnabledClock\n
5861 * APB1LENR TIM6EN LL_C2_APB1_GRP1_IsEnabledClock\n
5862 * APB1LENR TIM7EN LL_C2_APB1_GRP1_IsEnabledClock\n
5863 * APB1LENR TIM12EN LL_C2_APB1_GRP1_IsEnabledClock\n
5864 * APB1LENR TIM13EN LL_C2_APB1_GRP1_IsEnabledClock\n
5865 * APB1LENR TIM14EN LL_C2_APB1_GRP1_IsEnabledClock\n
5866 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock\n
5867 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_IsEnabledClock\n
5868 * APB1LENR SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n
5869 * APB1LENR SPI3EN LL_C2_APB1_GRP1_IsEnabledClock\n
5870 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_IsEnabledClock\n
5871 * APB1LENR USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n
5872 * APB1LENR USART3EN LL_C2_APB1_GRP1_IsEnabledClock\n
5873 * APB1LENR UART4EN LL_C2_APB1_GRP1_IsEnabledClock\n
5874 * APB1LENR UART5EN LL_C2_APB1_GRP1_IsEnabledClock\n
5875 * APB1LENR I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n
5876 * APB1LENR I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n
5877 * APB1LENR I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n
5878 * APB1LENR CECEN LL_C2_APB1_GRP1_IsEnabledClock\n
5879 * APB1LENR DAC12EN LL_C2_APB1_GRP1_IsEnabledClock\n
5880 * APB1LENR UART7EN LL_C2_APB1_GRP1_IsEnabledClock\n
5881 * APB1LENR UART8EN LL_C2_APB1_GRP1_IsEnabledClock
5882 * @param Periphs This parameter can be a combination of the following values:
5883 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
5884 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
5885 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
5886 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
5887 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
5888 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
5889 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
5890 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
5891 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
5892 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
5893 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
5894 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
5895 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
5896 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
5897 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
5898 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
5899 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
5900 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
5901 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
5902 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
5903 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
5904 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
5905 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
5906 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
5907 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
5908 * @retval uint32_t
5909 */
5910 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
5911 {
5912 return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);
5913 }
5914
5915 /**
5916 * @brief Disable C2 APB1 peripherals clock.
5917 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_DisableClock\n
5918 * APB1LENR TIM3EN LL_C2_APB1_GRP1_DisableClock\n
5919 * APB1LENR TIM4EN LL_C2_APB1_GRP1_DisableClock\n
5920 * APB1LENR TIM5EN LL_C2_APB1_GRP1_DisableClock\n
5921 * APB1LENR TIM6EN LL_C2_APB1_GRP1_DisableClock\n
5922 * APB1LENR TIM7EN LL_C2_APB1_GRP1_DisableClock\n
5923 * APB1LENR TIM12EN LL_C2_APB1_GRP1_DisableClock\n
5924 * APB1LENR TIM13EN LL_C2_APB1_GRP1_DisableClock\n
5925 * APB1LENR TIM14EN LL_C2_APB1_GRP1_DisableClock\n
5926 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_DisableClock\n
5927 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_DisableClock\n
5928 * APB1LENR SPI2EN LL_C2_APB1_GRP1_DisableClock\n
5929 * APB1LENR SPI3EN LL_C2_APB1_GRP1_DisableClock\n
5930 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_DisableClock\n
5931 * APB1LENR USART2EN LL_C2_APB1_GRP1_DisableClock\n
5932 * APB1LENR USART3EN LL_C2_APB1_GRP1_DisableClock\n
5933 * APB1LENR UART4EN LL_C2_APB1_GRP1_DisableClock\n
5934 * APB1LENR UART5EN LL_C2_APB1_GRP1_DisableClock\n
5935 * APB1LENR I2C1EN LL_C2_APB1_GRP1_DisableClock\n
5936 * APB1LENR I2C2EN LL_C2_APB1_GRP1_DisableClock\n
5937 * APB1LENR I2C3EN LL_C2_APB1_GRP1_DisableClock\n
5938 * APB1LENR CECEN LL_C2_APB1_GRP1_DisableClock\n
5939 * APB1LENR DAC12EN LL_C2_APB1_GRP1_DisableClock\n
5940 * APB1LENR UART7EN LL_C2_APB1_GRP1_DisableClock\n
5941 * APB1LENR UART8EN LL_C2_APB1_GRP1_DisableClock
5942 * @param Periphs This parameter can be a combination of the following values:
5943 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
5944 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
5945 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
5946 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
5947 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
5948 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
5949 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
5950 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
5951 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
5952 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
5953 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
5954 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
5955 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
5956 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
5957 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
5958 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
5959 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
5960 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
5961 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
5962 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
5963 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
5964 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
5965 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
5966 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
5967 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
5968 * @retval None
5969 */
5970 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
5971 {
5972 CLEAR_BIT(RCC_C2->APB1LENR, Periphs);
5973 }
5974
5975 /**
5976 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
5977 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5978 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5979 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5980 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5981 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5982 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5983 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5984 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5985 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5986 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5987 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5988 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5989 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5990 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5991 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5992 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5993 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5994 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5995 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5996 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5997 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5998 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_EnableClockSleep\n
5999 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6000 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n
6001 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_EnableClockSleep
6002 * @param Periphs This parameter can be a combination of the following values:
6003 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6004 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6005 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6006 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6007 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6008 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6009 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6010 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6011 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6012 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6013 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
6014 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6015 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6016 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6017 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6018 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6019 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6020 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6021 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6022 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6023 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6024 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6025 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6026 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6027 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6028 * @retval None
6029 */
6030 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
6031 {
6032 __IO uint32_t tmpreg;
6033 SET_BIT(RCC_C2->APB1LLPENR, Periphs);
6034 /* Delay after an RCC peripheral clock enabling */
6035 tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);
6036 (void)tmpreg;
6037 }
6038
6039 /**
6040 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6041 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6042 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6043 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6044 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6045 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6046 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6047 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6048 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6049 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6050 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6051 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6052 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6053 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6054 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6055 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6056 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6057 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6058 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6059 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6060 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6061 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6062 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6063 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6064 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n
6065 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_DisableClockSleep
6066 * @param Periphs This parameter can be a combination of the following values:
6067 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
6068 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
6069 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
6070 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
6071 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
6072 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
6073 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
6074 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
6075 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
6076 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
6077 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
6078 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
6079 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
6080 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
6081 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
6082 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
6083 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
6084 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
6085 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
6086 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
6087 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
6088 * @arg @ref LL_APB1_GRP1_PERIPH_CEC
6089 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12
6090 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
6091 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
6092 * @retval None
6093 */
6094 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
6095 {
6096 CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);
6097 }
6098
6099 /**
6100 * @brief Enable C2 APB1 peripherals clock.
6101 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_EnableClock\n
6102 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_EnableClock\n
6103 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_EnableClock\n
6104 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_EnableClock\n
6105 * APB1HENR FDCANEN LL_C2_APB1_GRP2_EnableClock
6106 * @param Periphs This parameter can be a combination of the following values:
6107 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6108 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6109 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6110 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6111 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6112 * @retval None
6113 */
6114 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
6115 {
6116 __IO uint32_t tmpreg;
6117 SET_BIT(RCC_C2->APB1HENR, Periphs);
6118 /* Delay after an RCC peripheral clock enabling */
6119 tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);
6120 (void)tmpreg;
6121 }
6122
6123 /**
6124 * @brief Check if C2 APB1 peripheral clock is enabled or not
6125 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_IsEnabledClock\n
6126 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_IsEnabledClock\n
6127 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_IsEnabledClock\n
6128 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_IsEnabledClock\n
6129 * APB1HENR FDCANEN LL_C2_APB1_GRP2_IsEnabledClock
6130 * @param Periphs This parameter can be a combination of the following values:
6131 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6132 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6133 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6134 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6135 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6136 * @retval uint32_t
6137 */
6138 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
6139 {
6140 return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);
6141 }
6142
6143 /**
6144 * @brief Disable C2 APB1 peripherals clock.
6145 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_DisableClock\n
6146 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_DisableClock\n
6147 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_DisableClock\n
6148 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_DisableClock\n
6149 * APB1HENR FDCANEN LL_C2_APB1_GRP2_DisableClock
6150 * @param Periphs This parameter can be a combination of the following values:
6151 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6152 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6153 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6154 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6155 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6156 * @retval None
6157 */
6158 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
6159 {
6160 CLEAR_BIT(RCC_C2->APB1HENR, Periphs);
6161 }
6162
6163 /**
6164 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6165 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6166 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6167 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6168 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n
6169 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_EnableClockSleep
6170 * @param Periphs This parameter can be a combination of the following values:
6171 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6172 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6173 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6174 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6175 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6176 * @retval None
6177 */
6178 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
6179 {
6180 __IO uint32_t tmpreg;
6181 SET_BIT(RCC_C2->APB1HLPENR, Periphs);
6182 /* Delay after an RCC peripheral clock enabling */
6183 tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);
6184 (void)tmpreg;
6185 }
6186
6187 /**
6188 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
6189 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6190 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6191 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6192 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n
6193 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_DisableClockSleep
6194 * @param Periphs This parameter can be a combination of the following values:
6195 * @arg @ref LL_APB1_GRP2_PERIPH_CRS
6196 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
6197 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
6198 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
6199 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
6200 * @retval None
6201 */
6202 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
6203 {
6204 CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);
6205 }
6206
6207 /**
6208 * @}
6209 */
6210
6211 /** @defgroup BUS_LL_EF_APB2 APB2
6212 * @{
6213 */
6214
6215 /**
6216 * @brief Enable C2 APB2 peripherals clock.
6217 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n
6218 * APB2ENR TIM8EN LL_C2_APB2_GRP1_EnableClock\n
6219 * APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n
6220 * APB2ENR USART6EN LL_C2_APB2_GRP1_EnableClock\n
6221 * APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n
6222 * APB2ENR SPI4EN LL_C2_APB2_GRP1_EnableClock\n
6223 * APB2ENR TIM15EN LL_C2_APB2_GRP1_EnableClock\n
6224 * APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n
6225 * APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n
6226 * APB2ENR SPI5EN LL_C2_APB2_GRP1_EnableClock\n
6227 * APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock\n
6228 * APB2ENR SAI2EN LL_C2_APB2_GRP1_EnableClock\n
6229 * APB2ENR SAI3EN LL_C2_APB2_GRP1_EnableClock\n
6230 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_EnableClock\n
6231 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_EnableClock
6232 * @param Periphs This parameter can be a combination of the following values:
6233 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6234 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6235 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6236 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6237 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6238 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6239 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6240 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6241 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6242 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6243 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6244 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
6245 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
6246 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6247 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
6248 * @retval None
6249 */
6250 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
6251 {
6252 __IO uint32_t tmpreg;
6253 SET_BIT(RCC_C2->APB2ENR, Periphs);
6254 /* Delay after an RCC peripheral clock enabling */
6255 tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);
6256 (void)tmpreg;
6257 }
6258
6259 /**
6260 * @brief Check if C2 APB2 peripheral clock is enabled or not
6261 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6262 * APB2ENR TIM8EN LL_C2_APB2_GRP1_IsEnabledClock\n
6263 * APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6264 * APB2ENR USART6EN LL_C2_APB2_GRP1_IsEnabledClock\n
6265 * APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6266 * APB2ENR SPI4EN LL_C2_APB2_GRP1_IsEnabledClock\n
6267 * APB2ENR TIM15EN LL_C2_APB2_GRP1_IsEnabledClock\n
6268 * APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n
6269 * APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n
6270 * APB2ENR SPI5EN LL_C2_APB2_GRP1_IsEnabledClock\n
6271 * APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6272 * APB2ENR SAI2EN LL_C2_APB2_GRP1_IsEnabledClock\n
6273 * APB2ENR SAI3EN LL_C2_APB2_GRP1_IsEnabledClock\n
6274 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
6275 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_IsEnabledClock
6276 * @param Periphs This parameter can be a combination of the following values:
6277 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6278 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6279 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6280 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6281 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6282 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6283 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6284 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6285 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6286 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6287 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6288 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
6289 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
6290 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6291 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
6292 * @retval uint32_t
6293 */
6294 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
6295 {
6296 return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);
6297 }
6298
6299 /**
6300 * @brief Disable C2 APB2 peripherals clock.
6301 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n
6302 * APB2ENR TIM8EN LL_C2_APB2_GRP1_DisableClock\n
6303 * APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n
6304 * APB2ENR USART6EN LL_C2_APB2_GRP1_DisableClock\n
6305 * APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n
6306 * APB2ENR SPI4EN LL_C2_APB2_GRP1_DisableClock\n
6307 * APB2ENR TIM15EN LL_C2_APB2_GRP1_DisableClock\n
6308 * APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n
6309 * APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n
6310 * APB2ENR SPI5EN LL_C2_APB2_GRP1_DisableClock\n
6311 * APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock\n
6312 * APB2ENR SAI2EN LL_C2_APB2_GRP1_DisableClock\n
6313 * APB2ENR SAI3EN LL_C2_APB2_GRP1_DisableClock\n
6314 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_DisableClock\n
6315 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_DisableClock
6316 * @param Periphs This parameter can be a combination of the following values:
6317 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6318 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6319 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6320 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6321 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6322 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6323 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6324 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6325 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6326 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6327 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6328 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
6329 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
6330 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6331 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
6332 * @retval None
6333 */
6334 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
6335 {
6336 CLEAR_BIT(RCC_C2->APB2ENR, Periphs);
6337 }
6338
6339 /**
6340 * @brief Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.
6341 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6342 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6343 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6344 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6345 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6346 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6347 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6348 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6349 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6350 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6351 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6352 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6353 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6354 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n
6355 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_EnableClockSleep
6356 * @param Periphs This parameter can be a combination of the following values:
6357 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6358 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6359 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6360 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6361 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6362 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6363 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6364 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6365 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6366 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6367 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6368 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
6369 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
6370 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6371 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
6372 * @retval None
6373 */
6374 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
6375 {
6376 __IO uint32_t tmpreg;
6377 SET_BIT(RCC_C2->APB2LPENR, Periphs);
6378 /* Delay after an RCC peripheral clock enabling */
6379 tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);
6380 (void)tmpreg;
6381 }
6382
6383 /**
6384 * @brief Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.
6385 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6386 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6387 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6388 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6389 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6390 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6391 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6392 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6393 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6394 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6395 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6396 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6397 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6398 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n
6399 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_DisableClockSleep
6400 * @param Periphs This parameter can be a combination of the following values:
6401 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
6402 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
6403 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
6404 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
6405 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
6406 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
6407 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
6408 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
6409 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
6410 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
6411 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
6412 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
6413 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3
6414 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
6415 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
6416 * @retval None
6417 */
6418 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
6419 {
6420 CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);
6421 }
6422
6423 /**
6424 * @}
6425 */
6426
6427 /** @defgroup BUS_LL_EF_APB4 APB4
6428 * @{
6429 */
6430
6431 /**
6432 * @brief Enable C2 APB4 peripherals clock.
6433 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_EnableClock\n
6434 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_EnableClock\n
6435 * APB4ENR SPI6EN LL_C2_APB4_GRP1_EnableClock\n
6436 * APB4ENR I2C4EN LL_C2_APB4_GRP1_EnableClock\n
6437 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_EnableClock\n
6438 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_EnableClock\n
6439 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_EnableClock\n
6440 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_EnableClock\n
6441 * APB4ENR COMP12EN LL_C2_APB4_GRP1_EnableClock\n
6442 * APB4ENR VREFEN LL_C2_APB4_GRP1_EnableClock\n
6443 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_EnableClock\n
6444 * APB4ENR SAI4EN LL_C2_APB4_GRP1_EnableClock
6445 * @param Periphs This parameter can be a combination of the following values:
6446 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6447 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6448 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6449 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6450 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6451 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6452 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
6453 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
6454 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6455 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6456 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6457 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
6458 * @retval None
6459 */
6460 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
6461 {
6462 __IO uint32_t tmpreg;
6463 SET_BIT(RCC_C2->APB4ENR, Periphs);
6464 /* Delay after an RCC peripheral clock enabling */
6465 tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);
6466 (void)tmpreg;
6467 }
6468
6469 /**
6470 * @brief Check if C2 APB4 peripheral clock is enabled or not
6471 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_IsEnabledClock\n
6472 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_IsEnabledClock\n
6473 * APB4ENR SPI6EN LL_C2_APB4_GRP1_IsEnabledClock\n
6474 * APB4ENR I2C4EN LL_C2_APB4_GRP1_IsEnabledClock\n
6475 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_IsEnabledClock\n
6476 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_IsEnabledClock\n
6477 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_IsEnabledClock\n
6478 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_IsEnabledClock\n
6479 * APB4ENR COMP12EN LL_C2_APB4_GRP1_IsEnabledClock\n
6480 * APB4ENR VREFEN LL_C2_APB4_GRP1_IsEnabledClock\n
6481 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_IsEnabledClock\n
6482 * APB4ENR SAI4EN LL_C2_APB4_GRP1_IsEnabledClock
6483 * @param Periphs This parameter can be a combination of the following values:
6484 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6485 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6486 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6487 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6488 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6489 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6490 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
6491 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
6492 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6493 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6494 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6495 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
6496 * @retval uint32_t
6497 */
6498 __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
6499 {
6500 return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);
6501 }
6502
6503 /**
6504 * @brief Disable C2 APB4 peripherals clock.
6505 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_DisableClock\n
6506 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_DisableClock\n
6507 * APB4ENR SPI6EN LL_C2_APB4_GRP1_DisableClock\n
6508 * APB4ENR I2C4EN LL_C2_APB4_GRP1_DisableClock\n
6509 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_DisableClock\n
6510 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_DisableClock\n
6511 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_DisableClock\n
6512 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_DisableClock\n
6513 * APB4ENR COMP12EN LL_C2_APB4_GRP1_DisableClock\n
6514 * APB4ENR VREFEN LL_C2_APB4_GRP1_DisableClock\n
6515 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_DisableClock\n
6516 * APB4ENR SAI4EN LL_C2_APB4_GRP1_DisableClock
6517 * @param Periphs This parameter can be a combination of the following values:
6518 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6519 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6520 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6521 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6522 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6523 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6524 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
6525 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
6526 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6527 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6528 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6529 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
6530 * @retval None
6531 */
6532 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)
6533 {
6534 CLEAR_BIT(RCC_C2->APB4ENR, Periphs);
6535 }
6536
6537 /**
6538 * @brief Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.
6539 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6540 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6541 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6542 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6543 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6544 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6545 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6546 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6547 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6548 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6549 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_EnableClockSleep\n
6550 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_EnableClockSleep
6551 * @param Periphs This parameter can be a combination of the following values:
6552 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6553 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6554 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6555 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6556 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6557 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6558 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
6559 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
6560 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6561 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6562 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6563 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
6564 * @retval None
6565 */
6566 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
6567 {
6568 __IO uint32_t tmpreg;
6569 SET_BIT(RCC_C2->APB4LPENR, Periphs);
6570 /* Delay after an RCC peripheral clock enabling */
6571 tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);
6572 (void)tmpreg;
6573 }
6574
6575 /**
6576 * @brief Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.
6577 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6578 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6579 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6580 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6581 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6582 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6583 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6584 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6585 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6586 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6587 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_DisableClockSleep\n
6588 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_DisableClockSleep
6589 * @param Periphs This parameter can be a combination of the following values:
6590 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
6591 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
6592 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6
6593 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4
6594 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
6595 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
6596 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
6597 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
6598 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12
6599 * @arg @ref LL_APB4_GRP1_PERIPH_VREF
6600 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
6601 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4
6602 * @retval None
6603 */
6604 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
6605 {
6606 CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);
6607 }
6608
6609 /**
6610 * @}
6611 */
6612
6613 #endif /*DUAL_CORE*/
6614
6615 /**
6616 * @}
6617 */
6618
6619 /**
6620 * @}
6621 */
6622
6623 #endif /* defined(RCC) */
6624
6625 /**
6626 * @}
6627 */
6628
6629 #ifdef __cplusplus
6630 }
6631 #endif
6632
6633 #endif /* STM32H7xx_LL_BUS_H */
6634
6635 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software