| blob | c24b53c5688a52e0157816331b9162b0ae73ca87 |
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_hrtim.h
4 * @author MCD Application Team
5 * @brief Header file of HRTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_HRTIM_H
22 #define STM32H7xx_LL_HRTIM_H
24 #ifdef __cplusplus
26 #endif
28 /* Includes ------------------------------------------------------------------*/
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
35 #if defined (HRTIM1)
37 /** @defgroup HRTIM_LL HRTIM
38 * @{
39 */
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
44 * @{
45 */
47 {
54 };
57 {
62 };
65 {
76 };
79 {
90 };
93 {
104 };
107 {
113 };
116 {
123 };
126 {
133 };
136 {
147 };
150 {
156 HRTIM_TIMCR_UPDGAT /* 5: TIMER E */
157 };
160 {
167 };
170 {
181 };
184 {
195 };
198 {
204 };
206 /**
207 * @}
208 */
211 /* Private constants ---------------------------------------------------------*/
212 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
213 * @{
214 */
215 #define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
216 HRTIM_CR1_TAUDIS |\
217 HRTIM_CR1_TBUDIS |\
218 HRTIM_CR1_TCUDIS |\
219 HRTIM_CR1_TDUDIS |\
220 HRTIM_CR1_TEUDIS))
222 #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
223 HRTIM_CR2_TASWU |\
224 HRTIM_CR2_TBSWU |\
225 HRTIM_CR2_TCSWU |\
226 HRTIM_CR2_TDSWU |\
227 HRTIM_CR2_TESWU))
229 #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
230 HRTIM_CR2_TARST |\
231 HRTIM_CR2_TBRST |\
232 HRTIM_CR2_TCRST |\
233 HRTIM_CR2_TDRST |\
234 HRTIM_CR2_TERST))
236 #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
237 HRTIM_OENR_TA2OEN |\
238 HRTIM_OENR_TB1OEN |\
239 HRTIM_OENR_TB2OEN |\
240 HRTIM_OENR_TC1OEN |\
241 HRTIM_OENR_TC2OEN |\
242 HRTIM_OENR_TD1OEN |\
243 HRTIM_OENR_TD2OEN |\
244 HRTIM_OENR_TE1OEN |\
245 HRTIM_OENR_TE2OEN))
247 #define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
248 HRTIM_ODISR_TA2ODIS |\
249 HRTIM_ODISR_TB1ODIS |\
250 HRTIM_ODISR_TB2ODIS |\
251 HRTIM_ODISR_TC1ODIS |\
252 HRTIM_ODISR_TC2ODIS |\
253 HRTIM_ODISR_TD1ODIS |\
254 HRTIM_ODISR_TD2ODIS |\
255 HRTIM_ODISR_TE1ODIS |\
256 HRTIM_ODISR_TE2ODIS))
258 #define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
259 HRTIM_OUTR_IDLM1 |\
260 HRTIM_OUTR_IDLES1 |\
261 HRTIM_OUTR_FAULT1 |\
262 HRTIM_OUTR_CHP1 |\
263 HRTIM_OUTR_DIDL1))
265 #define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
266 HRTIM_EECR1_EE1POL |\
267 HRTIM_EECR1_EE1SNS |\
268 HRTIM_EECR1_EE1FAST))
270 #define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
271 HRTIM_FLTINR1_FLT1SRC))
273 #define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
274 HRTIM_BMCR_BMCLK |\
275 HRTIM_BMCR_BMOM))
277 /**
278 * @}
279 */
282 /* Private macros ------------------------------------------------------------*/
283 /* Exported types ------------------------------------------------------------*/
284 /* Exported constants --------------------------------------------------------*/
285 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
286 * @{
287 */
289 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
290 * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
291 * @{
292 */
293 #define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
294 #define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
295 #define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
296 #define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
297 #define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
298 #define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
299 #define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
301 #define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
302 #define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
303 #define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
304 #define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
305 #define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
306 #define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
307 #define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
309 #define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
310 #define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
311 #define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
312 #define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
313 #define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
314 #define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
315 #define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
316 #define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
317 #define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
318 #define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
319 #define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
320 #define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
321 #define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
322 #define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
323 /**
324 * @}
325 */
327 /** @defgroup HRTIM_LL_EC_IT IT Defines
328 * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
329 * @{
330 */
331 #define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
332 #define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
333 #define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
334 #define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
335 #define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
336 #define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
337 #define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
339 #define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
340 #define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
341 #define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
342 #define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
343 #define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
344 #define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
345 #define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
347 #define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
348 #define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
349 #define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
350 #define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
351 #define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
352 #define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
353 #define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
354 #define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
355 #define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
356 #define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
357 #define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
358 #define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
359 #define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
360 #define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
361 /**
362 * @}
363 */
365 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
366 * @{
367 * @brief Constants defining defining the synchronization input source.
368 */
369 #define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */
370 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
371 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
372 /**
373 * @}
374 */
376 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
377 * @{
378 * @brief Constants defining the source and event to be sent on the synchronization output.
379 */
380 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
381 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
382 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
383 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
384 /**
385 * @}
386 */
388 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
389 * @{
390 * @brief Constants defining the routing and conditioning of the synchronization output event.
391 */
393 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
394 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
395 /**
396 * @}
397 */
399 /** @defgroup HRTIM_LL_EC_TIMER TIMER ID
400 * @{
401 * @brief Constants identifying a timing unit.
402 */
410 #define LL_HRTIM_TIMER_X (HRTIM_MCR_TACEN |\
411 HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
412 HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
413 #define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
415 /**
416 * @}
417 */
419 /** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID
420 * @{
421 * @brief Constants identifying an HRTIM output.
422 */
433 /**
434 * @}
435 */
437 /** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID
438 * @{
439 * @brief Constants identifying a compare unit.
440 */
443 /**
444 * @}
445 */
447 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID
448 * @{
449 * @brief Constants identifying a capture unit.
450 */
453 /**
454 * @}
455 */
457 /** @defgroup HRTIM_LL_EC_FAULT FAULT ID
458 * @{
459 * @brief Constants identifying a fault channel.
460 */
466 /**
467 * @}
468 */
470 /** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID
471 * @{
472 * @brief Constants identifying an external event channel.
473 */
484 /**
485 * @}
486 */
488 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE
489 * @{
490 * @brief Constants defining the state of an HRTIM output.
491 */
492 #define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
493 #define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
494 #define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
495 /**
496 * @}
497 */
499 /** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER
500 * @{
501 * @brief Constants identifying an ADC trigger.
502 */
507 /**
508 * @}
509 */
511 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
512 * @{
513 * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
514 */
515 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */
516 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer A */
517 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< HRTIM_ADCxR register update is triggered by the Timer B */
518 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */
519 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< HRTIM_ADCxR register update is triggered by the Timer D */
520 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */
521 /**
522 * @}
523 */
525 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
526 * @{
527 * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
528 */
540 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 HRTIM_ADC1R_AD1TAC2 /*!< ADC Trigger on Timer A compare 2 */
541 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
542 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
543 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
544 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
545 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 HRTIM_ADC1R_AD1TBC2 /*!< ADC Trigger on Timer B compare 2 */
546 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
547 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
548 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
549 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
550 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 HRTIM_ADC1R_AD1TCC2 /*!< ADC Trigger on Timer C compare 2 */
551 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
552 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
553 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
554 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 HRTIM_ADC1R_AD1TDC2 /*!< ADC Trigger on Timer D compare 2 */
555 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
556 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
557 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
558 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 HRTIM_ADC1R_AD1TEC2 /*!< ADC Trigger on Timer E compare 2 */
559 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
560 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
561 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
562 /**
563 * @}
564 */
566 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
567 * @{
568 * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
569 */
580 #define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
581 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
582 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 HRTIM_ADC2R_AD2TAC3 /*!< ADC Trigger on Timer A compare 3 */
583 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
584 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
585 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
586 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 HRTIM_ADC2R_AD2TBC3 /*!< ADC Trigger on Timer B compare 3 */
587 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
588 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
589 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
590 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 HRTIM_ADC2R_AD2TCC3 /*!< ADC Trigger on Timer C compare 3 */
591 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
592 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
593 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
594 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
595 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 HRTIM_ADC2R_AD2TDC3 /*!< ADC Trigger on Timer D compare 3 */
596 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
597 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
598 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
599 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
600 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
601 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
602 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
603 /**
604 * @}
605 */
607 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO
608 * @{
609 * @brief Constants defining timer high-resolution clock prescaler ratio.
610 */
611 #define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
612 #define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
613 #define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
614 #define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
615 #define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
616 #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
617 #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
618 #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
619 /**
620 * @}
621 */
623 /** @defgroup HRTIM_LL_EC_MODE COUNTER MODE
624 * @{
625 * @brief Constants defining timer counter operating mode.
626 */
627 #define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
628 #define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */
629 #define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
630 /**
631 * @}
632 */
634 /** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER
635 * @{
636 * @brief Constants defining on which output the DAC synchronization event is sent.
637 */
639 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
640 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
641 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
642 /**
643 * @}
644 */
646 /** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER
647 * @{
648 * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
649 */
651 #define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
652 #define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
653 #define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
654 #define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
655 #define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
656 #define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
657 #define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
658 #define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
659 /**
660 * @}
661 */
663 /** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING
664 * @{
665 * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
666 */
667 #define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
668 #define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
669 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
670 #define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
671 #define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
672 #define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
673 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
674 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
675 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
676 /**
677 * @}
678 */
680 /** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE
681 * @{
682 * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
683 */
685 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
686 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
687 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
688 /**
689 * @}
690 */
692 /** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER
693 * @{
694 * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
695 */
697 #define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
698 #define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
699 #define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
700 #define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
701 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
702 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
703 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
704 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
705 #define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
706 #define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
707 #define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
708 #define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
709 #define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
710 #define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
711 #define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
712 #define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
713 #define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
714 #define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
715 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
716 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
717 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
718 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
719 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
720 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
721 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
722 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
723 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
724 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
725 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
726 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
727 /**
728 * @}
729 */
731 /** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER
732 * @{
733 * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
734 */
736 #define LL_HRTIM_CAPTURETRIG_UPDATE HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
737 #define LL_HRTIM_CAPTURETRIG_EEV_1 HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
738 #define LL_HRTIM_CAPTURETRIG_EEV_2 HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
739 #define LL_HRTIM_CAPTURETRIG_EEV_3 HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
740 #define LL_HRTIM_CAPTURETRIG_EEV_4 HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
741 #define LL_HRTIM_CAPTURETRIG_EEV_5 HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
742 #define LL_HRTIM_CAPTURETRIG_EEV_6 HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
743 #define LL_HRTIM_CAPTURETRIG_EEV_7 HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
744 #define LL_HRTIM_CAPTURETRIG_EEV_8 HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
745 #define LL_HRTIM_CAPTURETRIG_EEV_9 HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
746 #define LL_HRTIM_CAPTURETRIG_EEV_10 HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
747 #define LL_HRTIM_CAPTURETRIG_TA1_SET HRTIM_CPT1CR_TA1SET /*!< Capture is triggered by TA1 output inactive to active transition */
748 #define LL_HRTIM_CAPTURETRIG_TA1_RESET HRTIM_CPT1CR_TA1RST /*!< Capture is triggered by TA1 output active to inactive transition */
749 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 HRTIM_CPT1CR_TIMACMP1 /*!< Timer A Compare 1 triggers Capture */
750 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 HRTIM_CPT1CR_TIMACMP2 /*!< Timer A Compare 2 triggers Capture */
751 #define LL_HRTIM_CAPTURETRIG_TB1_SET HRTIM_CPT1CR_TB1SET /*!< Capture is triggered by TB1 output inactive to active transition */
752 #define LL_HRTIM_CAPTURETRIG_TB1_RESET HRTIM_CPT1CR_TB1RST /*!< Capture is triggered by TB1 output active to inactive transition */
753 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 HRTIM_CPT1CR_TIMBCMP1 /*!< Timer B Compare 1 triggers Capture */
754 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 HRTIM_CPT1CR_TIMBCMP2 /*!< Timer B Compare 2 triggers Capture */
755 #define LL_HRTIM_CAPTURETRIG_TC1_SET HRTIM_CPT1CR_TC1SET /*!< Capture is triggered by TC1 output inactive to active transition */
756 #define LL_HRTIM_CAPTURETRIG_TC1_RESET HRTIM_CPT1CR_TC1RST /*!< Capture is triggered by TC1 output active to inactive transition */
757 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 HRTIM_CPT1CR_TIMCCMP1 /*!< Timer C Compare 1 triggers Capture */
758 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 HRTIM_CPT1CR_TIMCCMP2 /*!< Timer C Compare 2 triggers Capture */
759 #define LL_HRTIM_CAPTURETRIG_TD1_SET HRTIM_CPT1CR_TD1SET /*!< Capture is triggered by TD1 output inactive to active transition */
760 #define LL_HRTIM_CAPTURETRIG_TD1_RESET HRTIM_CPT1CR_TD1RST /*!< Capture is triggered by TD1 output active to inactive transition */
761 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 HRTIM_CPT1CR_TIMDCMP1 /*!< Timer D Compare 1 triggers Capture */
762 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 HRTIM_CPT1CR_TIMDCMP2 /*!< Timer D Compare 2 triggers Capture */
763 #define LL_HRTIM_CAPTURETRIG_TE1_SET HRTIM_CPT1CR_TE1SET /*!< Capture is triggered by TE1 output inactive to active transition */
764 #define LL_HRTIM_CAPTURETRIG_TE1_RESET HRTIM_CPT1CR_TE1RST /*!< Capture is triggered by TE1 output active to inactive transition */
765 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1 HRTIM_CPT1CR_TIMECMP1 /*!< Timer E Compare 1 triggers Capture */
766 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2 HRTIM_CPT1CR_TIMECMP2 /*!< Timer E Compare 2 triggers Capture */
767 /**
768 * @}
769 */
771 /** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
772 * @{
773 * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
774 */
775 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
776 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
777 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
778 #define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
779 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
780 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
781 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
782 #define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
784 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
785 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
786 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
787 #define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
788 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
789 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
790 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
791 #define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
792 /**
793 * @}
794 */
796 /** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE
797 * @{
798 * @brief Constants defining how the timer behaves during a burst mode operation.
799 */
800 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
801 #define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
802 /**
803 * @}
804 */
806 /** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA
807 * @{
808 * @brief Constants defining the registers that can be written during a burst DMA operation.
809 */
811 #define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
812 #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
813 #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
814 #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
815 #define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
816 #define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
817 #define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
818 #define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
819 #define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
820 #define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
821 #define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
822 #define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
823 #define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
824 #define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
825 #define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
826 #define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
827 #define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
828 #define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
829 #define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
830 #define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
831 #define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
832 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
833 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
834 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
835 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
836 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
837 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
838 #define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
839 #define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
840 #define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
841 #define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
842 /**
843 * @}
844 */
846 /** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS
847 * @{
848 * @brief Constants defining on which output the signal is currently applied in push-pull mode.
849 */
850 #define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
851 #define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
852 /**
853 * @}
854 */
856 /** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS
857 * @{
858 * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
859 */
860 #define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
861 #define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
862 /**
863 * @}
864 */
866 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
867 * @{
868 * @brief Constants defining the event filtering applied to external events by a timer.
869 */
870 #define LL_HRTIM_EEFLTR_NONE (0x00000000U)
871 #define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
872 #define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
873 #define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
874 #define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
875 #define LL_HRTIM_EEFLTR_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
876 #define LL_HRTIM_EEFLTR_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
877 #define LL_HRTIM_EEFLTR_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
878 #define LL_HRTIM_EEFLTR_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
879 #define LL_HRTIM_EEFLTR_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
880 #define LL_HRTIM_EEFLTR_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
881 #define LL_HRTIM_EEFLTR_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
882 #define LL_HRTIM_EEFLTR_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
883 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
884 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
885 #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
886 /**
887 * @}
888 */
890 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
891 * @{
892 * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
893 */
894 #define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */
895 #define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
896 /**
897 * @}
898 */
900 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
901 * @{
902 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
903 */
907 #define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
909 #define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
910 #define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
911 #define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
912 /**
913 * @}
914 */
916 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
917 * @{
918 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
919 */
922 /**
923 * @}
924 */
926 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
927 * @{
928 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
929 */
932 /**
933 * @}
934 */
936 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
937 * @{
938 * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
939 */
943 #define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
945 #define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
946 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
947 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
949 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
950 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
951 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
952 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
953 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
954 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
955 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
956 /**
957 * @}
958 */
960 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
961 * @{
962 * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
963 */
965 #define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
966 #define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
967 #define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
968 #define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
969 #define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
970 #define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
971 #define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
972 /**
973 * @}
974 */
976 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
977 * @{
978 * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
979 */
983 #define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
985 #define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
986 #define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
987 #define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
989 #define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
990 #define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
991 #define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
992 #define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
993 #define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
994 #define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
995 #define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
996 /**
997 * @}
998 */
1000 /** @defgroup HRTIM_LL_EC_CROSSBAR_INPUT CROSSBAR INPUT
1001 * @{
1002 * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
1003 */
1005 #define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
1006 #define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */
1007 #define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */
1008 #define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */
1009 #define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */
1010 #define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */
1011 #define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */
1012 #define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */
1013 #define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
1014 #define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
1015 #define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
1016 #define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transision */
1017 #define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transision */
1018 #define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transision */
1019 #define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transision */
1020 #define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transision */
1021 #define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transision */
1022 #define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transision */
1023 #define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transision */
1024 #define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transision */
1025 #define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */
1026 #define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */
1027 #define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */
1028 #define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */
1029 #define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */
1030 #define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */
1031 #define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */
1032 #define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */
1033 #define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */
1034 #define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */
1035 #define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */
1036 /**
1037 * @}
1038 */
1040 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
1041 * @{
1042 * @brief Constants defining the polarity of a timer output.
1043 */
1046 /**
1047 * @}
1048 */
1050 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
1051 * @{
1052 * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
1053 */
1054 #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */
1055 #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1056 /**
1057 * @}
1058 */
1060 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
1061 * @{
1062 * @brief Constants defining the half mode of an HRTIM Timer instance.
1063 */
1066 /**
1067 * @}
1068 */
1070 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
1071 * @{
1072 * @brief Constants defining the output level when output is in IDLE state
1073 */
1074 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
1075 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1076 /**
1077 * @}
1078 */
1080 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
1081 * @{
1082 * @brief Constants defining the output level when output is in FAULT state.
1083 */
1084 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */
1085 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1086 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1087 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1088 /**
1089 * @}
1090 */
1092 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
1093 * @{
1094 * @brief Constants defining whether or not chopper mode is enabled for a timer output.
1095 */
1097 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
1098 /**
1099 * @}
1100 */
1102 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
1103 * @{
1104 * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
1105 during a programmable period before the output takes its idle state.
1106 */
1107 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
1108 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1109 /**
1110 * @}
1111 */
1112 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
1113 * @{
1114 * @brief Constants defining the level of a timer output.
1115 */
1116 #define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
1117 #define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
1118 /**
1119 * @}
1120 */
1122 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
1123 * @{
1124 * @brief Constants defining available sources associated to external events.
1125 */
1129 #define LL_HRTIM_EE_SRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 (EExSrc4) */
1130 /**
1131 * @}
1132 */
1133 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
1134 * @{
1135 * @brief Constants defining the polarity of an external event.
1136 */
1139 /**
1140 * @}
1141 */
1143 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
1144 * @{
1145 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
1146 */
1148 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1149 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1150 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1151 /**
1152 * @}
1153 */
1155 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
1156 * @{
1157 * @brief Constants defining whether or not an external event is programmed in fast mode.
1158 */
1159 #define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1160 #define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1161 /**
1162 * @}
1163 */
1165 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
1166 * @{
1167 * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
1168 */
1172 #define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
1174 #define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
1175 #define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
1176 #define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
1178 #define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
1179 #define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
1180 #define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
1181 #define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
1182 #define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
1183 #define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
1184 #define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
1185 /**
1186 * @}
1187 */
1189 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
1190 * @{
1191 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
1192 */
1196 #define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
1197 /**
1198 * @}
1199 */
1201 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
1202 * @{
1203 * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
1204 */
1206 #define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1207 /**
1208 * @}
1209 */
1211 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
1212 * @{
1213 * @brief Constants defining the polarity of a fault event.
1214 */
1217 /**
1218 * @}
1219 */
1221 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
1222 * @{
1223 * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
1224 */
1228 #define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1230 #define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1231 #define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1232 #define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1234 #define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1235 #define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1236 #define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1237 #define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1238 #define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1239 #define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1240 #define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1241 /**
1242 * @}
1243 */
1245 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
1246 * @{
1247 * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
1248 */
1252 #define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
1253 /**
1254 * @}
1255 */
1257 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
1258 * @{
1259 * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
1260 */
1261 #define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */
1262 #define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1263 /**
1264 * @}
1265 */
1267 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
1268 * @{
1269 * @brief Constants defining the clock source for the burst mode counter.
1270 */
1271 #define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1272 #define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1273 #define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1274 #define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1275 #define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1276 #define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1277 #define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1278 #define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1279 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1280 #define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1281 /**
1282 * @}
1283 */
1285 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
1286 * @{
1287 * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
1288 */
1292 #define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
1294 #define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
1295 #define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
1296 #define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
1298 #define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
1299 #define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
1300 #define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
1301 #define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
1302 #define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
1303 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
1304 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
1305 /**
1306 * @}
1307 */
1309 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
1310 * @{
1311 * @brief Constants defining the events that can be used to trig the burst mode operation.
1312 */
1314 #define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
1315 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
1316 #define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
1317 #define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
1318 #define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
1319 #define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
1320 #define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
1321 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
1322 #define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
1323 #define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
1324 #define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
1325 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
1326 #define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
1327 #define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
1328 #define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
1329 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
1330 #define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
1331 #define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 event is starting the burst mode operation */
1332 #define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
1333 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
1334 #define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 event is starting the burst mode operation */
1335 #define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
1336 #define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset event is starting the burst mode operation */
1337 #define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
1338 #define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
1339 #define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
1340 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */
1341 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */
1342 #define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
1343 #define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
1344 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
1345 /**
1346 * @}
1347 */
1349 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
1350 * @{
1351 * @brief Constants defining the operating state of the burst mode controller.
1352 */
1355 /**
1356 * @}
1357 */
1359 /**
1360 * @}
1361 */
1363 /* Exported macro ------------------------------------------------------------*/
1364 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
1365 * @{
1366 */
1368 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
1369 * @{
1370 */
1372 /**
1373 * @brief Write a value in HRTIM register
1374 * @param __INSTANCE__ HRTIM Instance
1375 * @param __REG__ Register to be written
1376 * @param __VALUE__ Value to be written in the register
1377 * @retval None
1378 */
1379 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1381 /**
1382 * @brief Read a value in HRTIM register
1383 * @param __INSTANCE__ HRTIM Instance
1384 * @param __REG__ Register to be read
1385 * @retval Register value
1386 */
1387 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1388 /**
1389 * @}
1390 */
1392 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
1393 * @{
1394 */
1395 /**
1396 * @brief HELPER macro returning the output state from output enable/disable status
1397 * @param __OUTPUT_STATUS_EN__ output enable status
1398 * @param __OUTPUT_STATUS_DIS__ output Disable status
1399 * @retval Returned value can be one of the following values:
1400 * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
1401 * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
1402 * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
1403 */
1404 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
1405 (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
1406 ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
1407 /**
1408 * @}
1409 */
1411 /**
1412 * @}
1413 */
1415 /* Exported functions --------------------------------------------------------*/
1416 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
1417 * @{
1418 */
1419 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
1420 * @{
1421 */
1423 /**
1424 * @brief Select the HRTIM synchronization input source.
1425 * @note This function must not be called when the concerned timer(s) is (are) enabled .
1426 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
1427 * @param HRTIMx High Resolution Timer instance
1428 * @param SyncInSrc This parameter can be one of the following values:
1429 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
1430 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
1431 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
1432 * @retval None
1433 */
1435 {
1437 }
1439 /**
1440 * @brief Get actual HRTIM synchronization input source.
1441 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
1442 * @param HRTIMx High Resolution Timer instance
1443 * @retval SyncInSrc Returned value can be one of the following values:
1444 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
1445 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
1446 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
1447 */
1449 {
1451 }
1453 /**
1454 * @brief Configure the HRTIM synchronization output.
1455 * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
1456 * MCR SYNCOUT LL_HRTIM_ConfigSyncOut
1457 * @param HRTIMx High Resolution Timer instance
1458 * @param Config This parameter can be one of the following values:
1459 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
1460 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
1461 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
1462 * @param Src This parameter can be one of the following values:
1463 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
1464 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
1465 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
1466 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
1467 * @retval None
1468 */
1469 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
1470 {
1471 MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
1472 }
1474 /**
1475 * @brief Set the routing and conditioning of the synchronization output event.
1476 * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
1477 * @note This function can be called only when the master timer is enabled.
1478 * @param HRTIMx High Resolution Timer instance
1479 * @param SyncOutConfig This parameter can be one of the following values:
1480 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
1481 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
1482 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
1483 * @retval None
1484 */
1486 {
1488 }
1490 /**
1491 * @brief Get actual routing and conditioning of the synchronization output event.
1492 * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
1493 * @param HRTIMx High Resolution Timer instance
1494 * @retval SyncOutConfig Returned value can be one of the following values:
1495 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
1496 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
1497 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
1498 */
1500 {
1502 }
1504 /**
1505 * @brief Set the source and event to be sent on the HRTIM synchronization output.
1506 * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
1507 * @param HRTIMx High Resolution Timer instance
1508 * @param SyncOutSrc This parameter can be one of the following values:
1509 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
1510 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
1511 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
1512 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
1513 * @retval None
1514 */
1516 {
1518 }
1520 /**
1521 * @brief Get actual source and event sent on the HRTIM synchronization output.
1522 * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
1523 * @param HRTIMx High Resolution Timer instance
1524 * @retval SyncOutSrc Returned value can be one of the following values:
1525 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
1526 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
1527 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
1528 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
1529 */
1531 {
1533 }
1535 /**
1536 * @brief Disable (temporarily) update event generation.
1537 * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
1538 * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
1539 * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
1540 * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
1541 * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
1542 * CR1 TEUDIS LL_HRTIM_SuspendUpdate
1543 * @note Allow to temporarily disable the transfer from preload to active
1544 * registers, whatever the selected update event. This allows to modify
1545 * several registers in multiple timers.
1546 * @param HRTIMx High Resolution Timer instance
1547 * @param Timers This parameter can be a combination of the following values:
1548 * @arg @ref LL_HRTIM_TIMER_MASTER
1549 * @arg @ref LL_HRTIM_TIMER_A
1550 * @arg @ref LL_HRTIM_TIMER_B
1551 * @arg @ref LL_HRTIM_TIMER_C
1552 * @arg @ref LL_HRTIM_TIMER_D
1553 * @arg @ref LL_HRTIM_TIMER_E
1554 * @retval None
1555 */
1557 {
1559 }
1561 /**
1562 * @brief Enable update event generation.
1563 * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
1564 * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
1565 * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
1566 * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
1567 * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
1568 * CR1 TEUDIS LL_HRTIM_ResumeUpdate
1569 * @note The regular update event takes place.
1570 * @param HRTIMx High Resolution Timer instance
1571 * @param Timers This parameter can be a combination of the following values:
1572 * @arg @ref LL_HRTIM_TIMER_MASTER
1573 * @arg @ref LL_HRTIM_TIMER_A
1574 * @arg @ref LL_HRTIM_TIMER_B
1575 * @arg @ref LL_HRTIM_TIMER_C
1576 * @arg @ref LL_HRTIM_TIMER_D
1577 * @arg @ref LL_HRTIM_TIMER_E
1578 * @retval None
1579 */
1581 {
1583 }
1585 /**
1586 * @brief Force an immediate transfer from the preload to the active register .
1587 * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
1588 * CR2 TASWU LL_HRTIM_ForceUpdate\n
1589 * CR2 TBSWU LL_HRTIM_ForceUpdate\n
1590 * CR2 TCSWU LL_HRTIM_ForceUpdate\n
1591 * CR2 TDSWU LL_HRTIM_ForceUpdate\n
1592 * CR2 TESWU LL_HRTIM_ForceUpdate
1593 * @note Any pending update request is cancelled.
1594 * @param HRTIMx High Resolution Timer instance
1595 * @param Timers This parameter can be a combination of the following values:
1596 * @arg @ref LL_HRTIM_TIMER_MASTER
1597 * @arg @ref LL_HRTIM_TIMER_A
1598 * @arg @ref LL_HRTIM_TIMER_B
1599 * @arg @ref LL_HRTIM_TIMER_C
1600 * @arg @ref LL_HRTIM_TIMER_D
1601 * @arg @ref LL_HRTIM_TIMER_E
1602 * @retval None
1603 */
1605 {
1607 }
1609 /**
1610 * @brief Reset the HRTIM timer(s) counter.
1611 * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
1612 * CR2 TARST LL_HRTIM_CounterReset\n
1613 * CR2 TBRST LL_HRTIM_CounterReset\n
1614 * CR2 TCRST LL_HRTIM_CounterReset\n
1615 * CR2 TDRST LL_HRTIM_CounterReset\n
1616 * CR2 TERST LL_HRTIM_CounterReset
1617 * @param HRTIMx High Resolution Timer instance
1618 * @param Timers This parameter can be a combination of the following values:
1619 * @arg @ref LL_HRTIM_TIMER_MASTER
1620 * @arg @ref LL_HRTIM_TIMER_A
1621 * @arg @ref LL_HRTIM_TIMER_B
1622 * @arg @ref LL_HRTIM_TIMER_C
1623 * @arg @ref LL_HRTIM_TIMER_D
1624 * @arg @ref LL_HRTIM_TIMER_E
1625 * @retval None
1626 */
1628 {
1629 SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
1630 }
1632 /**
1633 * @brief Enable the HRTIM timer(s) output(s) .
1634 * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
1635 * OENR TA2OEN LL_HRTIM_EnableOutput\n
1636 * OENR TB1OEN LL_HRTIM_EnableOutput\n
1637 * OENR TB2OEN LL_HRTIM_EnableOutput\n
1638 * OENR TC1OEN LL_HRTIM_EnableOutput\n
1639 * OENR TC2OEN LL_HRTIM_EnableOutput\n
1640 * OENR TD1OEN LL_HRTIM_EnableOutput\n
1641 * OENR TD2OEN LL_HRTIM_EnableOutput\n
1642 * OENR TE1OEN LL_HRTIM_EnableOutput\n
1643 * OENR TE2OEN LL_HRTIM_EnableOutput
1644 * @param HRTIMx High Resolution Timer instance
1645 * @param Outputs This parameter can be a combination of the following values:
1646 * @arg @ref LL_HRTIM_OUTPUT_TA1
1647 * @arg @ref LL_HRTIM_OUTPUT_TA2
1648 * @arg @ref LL_HRTIM_OUTPUT_TB1
1649 * @arg @ref LL_HRTIM_OUTPUT_TB2
1650 * @arg @ref LL_HRTIM_OUTPUT_TC1
1651 * @arg @ref LL_HRTIM_OUTPUT_TC2
1652 * @arg @ref LL_HRTIM_OUTPUT_TD1
1653 * @arg @ref LL_HRTIM_OUTPUT_TD2
1654 * @arg @ref LL_HRTIM_OUTPUT_TE1
1655 * @arg @ref LL_HRTIM_OUTPUT_TE2
1656 * @retval None
1657 */
1659 {
1661 }
1663 /**
1664 * @brief Disable the HRTIM timer(s) output(s) .
1665 * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
1666 * OENR TA2OEN LL_HRTIM_DisableOutput\n
1667 * OENR TB1OEN LL_HRTIM_DisableOutput\n
1668 * OENR TB2OEN LL_HRTIM_DisableOutput\n
1669 * OENR TC1OEN LL_HRTIM_DisableOutput\n
1670 * OENR TC2OEN LL_HRTIM_DisableOutput\n
1671 * OENR TD1OEN LL_HRTIM_DisableOutput\n
1672 * OENR TD2OEN LL_HRTIM_DisableOutput\n
1673 * OENR TE1OEN LL_HRTIM_DisableOutput\n
1674 * OENR TE2OEN LL_HRTIM_DisableOutput
1675 * @param HRTIMx High Resolution Timer instance
1676 * @param Outputs This parameter can be a combination of the following values:
1677 * @arg @ref LL_HRTIM_OUTPUT_TA1
1678 * @arg @ref LL_HRTIM_OUTPUT_TA2
1679 * @arg @ref LL_HRTIM_OUTPUT_TB1
1680 * @arg @ref LL_HRTIM_OUTPUT_TB2
1681 * @arg @ref LL_HRTIM_OUTPUT_TC1
1682 * @arg @ref LL_HRTIM_OUTPUT_TC2
1683 * @arg @ref LL_HRTIM_OUTPUT_TD1
1684 * @arg @ref LL_HRTIM_OUTPUT_TD2
1685 * @arg @ref LL_HRTIM_OUTPUT_TE1
1686 * @arg @ref LL_HRTIM_OUTPUT_TE2
1687 * @retval None
1688 */
1690 {
1692 }
1694 /**
1695 * @brief Indicates whether the HRTIM timer output is enabled.
1696 * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
1697 * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
1698 * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
1699 * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
1700 * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
1701 * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
1702 * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
1703 * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
1704 * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
1705 * OENR TE2OEN LL_HRTIM_IsEnabledOutput
1706 * @param HRTIMx High Resolution Timer instance
1707 * @param Output This parameter can be one of the following values:
1708 * @arg @ref LL_HRTIM_OUTPUT_TA1
1709 * @arg @ref LL_HRTIM_OUTPUT_TA2
1710 * @arg @ref LL_HRTIM_OUTPUT_TB1
1711 * @arg @ref LL_HRTIM_OUTPUT_TB2
1712 * @arg @ref LL_HRTIM_OUTPUT_TC1
1713 * @arg @ref LL_HRTIM_OUTPUT_TC2
1714 * @arg @ref LL_HRTIM_OUTPUT_TD1
1715 * @arg @ref LL_HRTIM_OUTPUT_TD2
1716 * @arg @ref LL_HRTIM_OUTPUT_TE1
1717 * @arg @ref LL_HRTIM_OUTPUT_TE2
1718 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
1719 */
1721 {
1723 }
1725 /**
1726 * @brief Indicates whether the HRTIM timer output is disabled.
1727 * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
1728 * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
1729 * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
1730 * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
1731 * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
1732 * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
1733 * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
1734 * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
1735 * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
1736 * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput
1737 * @param HRTIMx High Resolution Timer instance
1738 * @param Output This parameter can be one of the following values:
1739 * @arg @ref LL_HRTIM_OUTPUT_TA1
1740 * @arg @ref LL_HRTIM_OUTPUT_TA2
1741 * @arg @ref LL_HRTIM_OUTPUT_TB1
1742 * @arg @ref LL_HRTIM_OUTPUT_TB2
1743 * @arg @ref LL_HRTIM_OUTPUT_TC1
1744 * @arg @ref LL_HRTIM_OUTPUT_TC2
1745 * @arg @ref LL_HRTIM_OUTPUT_TD1
1746 * @arg @ref LL_HRTIM_OUTPUT_TD2
1747 * @arg @ref LL_HRTIM_OUTPUT_TE1
1748 * @arg @ref LL_HRTIM_OUTPUT_TE2
1749 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
1750 */
1752 {
1754 }
1756 /**
1757 * @brief Configure an ADC trigger.
1758 * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
1759 * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
1760 * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
1761 * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
1762 * ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n
1763 * ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n
1764 * ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n
1765 * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
1766 * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
1767 * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
1768 * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
1769 * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
1770 * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
1771 * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
1772 * ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n
1773 * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
1774 * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
1775 * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
1776 * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
1777 * ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n
1778 * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
1779 * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
1780 * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
1781 * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
1782 * ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n
1783 * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
1784 * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
1785 * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
1786 * ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n
1787 * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
1788 * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
1789 * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
1790 * ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n
1791 * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
1792 * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
1793 * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
1794 * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
1795 * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
1796 * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
1797 * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
1798 * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
1799 * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
1800 * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
1801 * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
1802 * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
1803 * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
1804 * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
1805 * ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n
1806 * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
1807 * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
1808 * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
1809 * ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n
1810 * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
1811 * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
1812 * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
1813 * ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n
1814 * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
1815 * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
1816 * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
1817 * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
1818 * ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n
1819 * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
1820 * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
1821 * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
1822 * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
1823 * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
1824 * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
1825 * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
1826 * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
1827 * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
1828 * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
1829 * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
1830 * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
1831 * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
1832 * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
1833 * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
1834 * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
1835 * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
1836 * ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n
1837 * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
1838 * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
1839 * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
1840 * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
1841 * ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n
1842 * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
1843 * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
1844 * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
1845 * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
1846 * ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n
1847 * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
1848 * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
1849 * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
1850 * ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n
1851 * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
1852 * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
1853 * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
1854 * ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n
1855 * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
1856 * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
1857 * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
1858 * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
1859 * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
1860 * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
1861 * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
1862 * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
1863 * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
1864 * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
1865 * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
1866 * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
1867 * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
1868 * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
1869 * ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n
1870 * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
1871 * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
1872 * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
1873 * ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n
1874 * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
1875 * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
1876 * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
1877 * ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n
1878 * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
1879 * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
1880 * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
1881 * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
1882 * ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n
1883 * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
1884 * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
1885 * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
1886 * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
1887 * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
1888 * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
1889 * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
1890 * @param HRTIMx High Resolution Timer instance
1891 * @param ADCTrig This parameter can be one of the following values:
1892 * @arg @ref LL_HRTIM_ADCTRIG_1
1893 * @arg @ref LL_HRTIM_ADCTRIG_2
1894 * @arg @ref LL_HRTIM_ADCTRIG_3
1895 * @arg @ref LL_HRTIM_ADCTRIG_4
1896 * @param Update This parameter can be one of the following values:
1897 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
1898 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
1899 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
1900 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
1901 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
1902 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
1903 * @param Src This parameter can be a combination of the following values:
1904 *
1905 * For ADC trigger 1 and ADC trigger 3:
1906 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
1907 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
1908 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
1909 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
1910 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
1911 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
1912 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
1913 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
1914 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
1915 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
1916 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
1917 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
1918 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
1919 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
1920 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
1921 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
1922 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
1923 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
1924 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
1925 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
1926 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
1927 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
1928 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
1929 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
1930 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
1931 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
1932 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
1933 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
1934 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
1935 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
1936 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
1937 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
1938 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
1939 *
1940 * For ADC trigger 2 and ADC trigger 4:
1941 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
1942 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
1943 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
1944 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
1945 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
1946 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
1947 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
1948 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
1949 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
1950 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
1951 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
1952 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
1953 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
1954 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
1955 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
1956 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
1957 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
1958 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
1959 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
1960 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
1961 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
1962 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
1963 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
1964 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
1965 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
1966 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
1967 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
1968 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
1969 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
1970 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
1971 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
1972 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
1973 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
1974 *
1975 * @retval None
1976 */
1977 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
1978 {
1980 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
1984 }
1986 /**
1987 * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
1988 * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
1989 * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
1990 * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
1991 * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n
1992 * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
1993 * registers are not preloaded either: a write access will result in an
1994 * immediate update of the trigger source.
1995 * @param HRTIMx High Resolution Timer instance
1996 * @param ADCTrig This parameter can be one of the following values:
1997 * @arg @ref LL_HRTIM_ADCTRIG_1
1998 * @arg @ref LL_HRTIM_ADCTRIG_2
1999 * @arg @ref LL_HRTIM_ADCTRIG_3
2000 * @arg @ref LL_HRTIM_ADCTRIG_4
2001 * @param Update This parameter can be one of the following values:
2002 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2003 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2004 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2005 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2006 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2007 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2008 * @retval None
2009 */
2010 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
2011 {
2014 }
2016 /**
2017 * @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
2018 * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
2019 * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
2020 * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
2021 * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n
2022 * @param HRTIMx High Resolution Timer instance
2023 * @param ADCTrig This parameter can be one of the following values:
2024 * @arg @ref LL_HRTIM_ADCTRIG_1
2025 * @arg @ref LL_HRTIM_ADCTRIG_2
2026 * @arg @ref LL_HRTIM_ADCTRIG_3
2027 * @arg @ref LL_HRTIM_ADCTRIG_4
2028 * @retval Update Returned value can be one of the following values:
2029 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2030 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2031 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2032 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2033 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2034 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2035 */
2037 {
2040 }
2042 /**
2043 * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
2044 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n
2045 * ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n
2046 * ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n
2047 * ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
2048 * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
2049 * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
2050 * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
2051 * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
2052 * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
2053 * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
2054 * ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n
2055 * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
2056 * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
2057 * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
2058 * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
2059 * ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n
2060 * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
2061 * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
2062 * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
2063 * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
2064 * ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n
2065 * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
2066 * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
2067 * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
2068 * ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n
2069 * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
2070 * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
2071 * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
2072 * ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n
2073 * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
2074 * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
2075 * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
2076 * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
2077 * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
2078 * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
2079 * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
2080 * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
2081 * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
2082 * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
2083 * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
2084 * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
2085 * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
2086 * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
2087 * ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n
2088 * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
2089 * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
2090 * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
2091 * ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n
2092 * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
2093 * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
2094 * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
2095 * ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n
2096 * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
2097 * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
2098 * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
2099 * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
2100 * ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n
2101 * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
2102 * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
2103 * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
2104 * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
2105 * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
2106 * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
2107 * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
2108 * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
2109 * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
2110 * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
2111 * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
2112 * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
2113 * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
2114 * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
2115 * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
2116 * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
2117 * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
2118 * ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n
2119 * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
2120 * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
2121 * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
2122 * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
2123 * ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n
2124 * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
2125 * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
2126 * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
2127 * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
2128 * ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n
2129 * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
2130 * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
2131 * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
2132 * ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n
2133 * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
2134 * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
2135 * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
2136 * ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n
2137 * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
2138 * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
2139 * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
2140 * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
2141 * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
2142 * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
2143 * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
2144 * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
2145 * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
2146 * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
2147 * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
2148 * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
2149 * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
2150 * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
2151 * ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n
2152 * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
2153 * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
2154 * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
2155 * ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n
2156 * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
2157 * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
2158 * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
2159 * ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n
2160 * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
2161 * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
2162 * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
2163 * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
2164 * ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n
2165 * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
2166 * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
2167 * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
2168 * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
2169 * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
2170 * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
2171 * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n
2172 * @param HRTIMx High Resolution Timer instance
2173 * @param ADCTrig This parameter can be one of the following values:
2174 * @arg @ref LL_HRTIM_ADCTRIG_1
2175 * @arg @ref LL_HRTIM_ADCTRIG_2
2176 * @arg @ref LL_HRTIM_ADCTRIG_3
2177 * @arg @ref LL_HRTIM_ADCTRIG_4
2178 * @param Src
2179 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
2180 * combination of the following values:
2181 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2182 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2183 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2184 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2185 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2186 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2187 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2188 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2189 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2190 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2191 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2192 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
2193 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2194 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2195 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2196 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2197 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
2198 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2199 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2200 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2201 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2202 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
2203 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2204 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2205 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2206 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
2207 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2208 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2209 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2210 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
2211 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2212 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2213 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2214 *
2215 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
2216 * combination of the following values:
2217 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2218 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2219 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2220 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2221 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2222 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2223 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2224 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2225 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2226 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2227 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2228 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2229 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
2230 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2231 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2232 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2233 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
2234 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2235 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2236 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2237 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
2238 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2239 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2240 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2241 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2242 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
2243 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2244 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2245 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2246 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2247 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2248 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2249 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2250 *
2251 * @retval None
2252 */
2253 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
2254 {
2255 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2258 }
2260 /**
2261 * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
2262 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n
2263 * ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n
2264 * ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n
2265 * ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
2266 * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
2267 * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
2268 * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
2269 * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
2270 * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
2271 * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
2272 * ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n
2273 * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
2274 * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
2275 * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
2276 * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
2277 * ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n
2278 * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
2279 * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
2280 * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
2281 * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
2282 * ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n
2283 * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
2284 * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
2285 * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
2286 * ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n
2287 * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
2288 * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
2289 * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
2290 * ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n
2291 * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
2292 * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
2293 * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
2294 * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
2295 * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
2296 * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
2297 * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
2298 * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
2299 * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
2300 * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
2301 * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
2302 * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
2303 * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
2304 * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
2305 * ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n
2306 * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
2307 * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
2308 * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
2309 * ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n
2310 * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
2311 * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
2312 * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
2313 * ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n
2314 * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
2315 * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
2316 * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
2317 * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
2318 * ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n
2319 * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
2320 * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
2321 * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
2322 * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
2323 * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
2324 * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
2325 * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
2326 * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
2327 * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
2328 * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
2329 * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
2330 * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
2331 * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
2332 * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
2333 * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
2334 * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
2335 * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
2336 * ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n
2337 * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
2338 * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
2339 * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
2340 * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
2341 * ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n
2342 * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
2343 * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
2344 * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
2345 * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
2346 * ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n
2347 * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
2348 * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
2349 * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
2350 * ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n
2351 * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
2352 * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
2353 * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
2354 * ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n
2355 * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
2356 * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
2357 * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
2358 * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
2359 * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
2360 * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
2361 * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
2362 * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
2363 * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
2364 * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
2365 * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
2366 * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
2367 * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
2368 * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
2369 * ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n
2370 * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
2371 * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
2372 * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
2373 * ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n
2374 * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
2375 * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
2376 * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
2377 * ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n
2378 * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
2379 * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
2380 * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
2381 * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
2382 * ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n
2383 * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
2384 * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
2385 * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
2386 * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
2387 * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
2388 * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
2389 * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
2390 * @param HRTIMx High Resolution Timer instance
2391 * @param ADCTrig This parameter can be one of the following values:
2392 * @arg @ref LL_HRTIM_ADCTRIG_1
2393 * @arg @ref LL_HRTIM_ADCTRIG_2
2394 * @arg @ref LL_HRTIM_ADCTRIG_3
2395 * @arg @ref LL_HRTIM_ADCTRIG_4
2396 * @retval Src This parameter can be a combination of the following values:
2397 *
2398 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
2399 * combination of the following values:
2400 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2401 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2402 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2403 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2404 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2405 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2406 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2407 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2408 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2409 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2410 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2411 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
2412 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2413 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2414 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2415 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2416 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
2417 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2418 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2419 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2420 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2421 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
2422 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2423 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2424 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2425 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
2426 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2427 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2428 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2429 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
2430 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2431 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2432 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2433 *
2434 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
2435 * combination of the following values:
2436 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2437 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2438 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2439 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2440 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2441 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2442 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2443 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2444 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2445 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2446 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2447 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2448 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
2449 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2450 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2451 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2452 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
2453 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2454 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2455 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2456 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
2457 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2458 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2459 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2460 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2461 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
2462 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2463 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2464 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2465 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2466 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2467 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2468 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2469 */
2471 {
2472 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2476 }
2479 /**
2480 * @}
2481 */
2483 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
2484 * @{
2485 */
2487 /**
2488 * @brief Enable timer(s) counter.
2489 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
2490 * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
2491 * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
2492 * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
2493 * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
2494 * MDIER MCEN LL_HRTIM_TIM_CounterEnable
2495 * @param HRTIMx High Resolution Timer instance
2496 * @param Timers This parameter can be a combination of the following values:
2497 * @arg @ref LL_HRTIM_TIMER_MASTER
2498 * @arg @ref LL_HRTIM_TIMER_A
2499 * @arg @ref LL_HRTIM_TIMER_B
2500 * @arg @ref LL_HRTIM_TIMER_C
2501 * @arg @ref LL_HRTIM_TIMER_D
2502 * @arg @ref LL_HRTIM_TIMER_E
2503 * @retval None
2504 */
2506 {
2508 }
2510 /**
2511 * @brief Disable timer(s) counter.
2512 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
2513 * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
2514 * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
2515 * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
2516 * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
2517 * MDIER MCEN LL_HRTIM_TIM_CounterDisable
2518 * @param HRTIMx High Resolution Timer instance
2519 * @param Timers This parameter can be a combination of the following values:
2520 * @arg @ref LL_HRTIM_TIMER_MASTER
2521 * @arg @ref LL_HRTIM_TIMER_A
2522 * @arg @ref LL_HRTIM_TIMER_B
2523 * @arg @ref LL_HRTIM_TIMER_C
2524 * @arg @ref LL_HRTIM_TIMER_D
2525 * @arg @ref LL_HRTIM_TIMER_E
2526 * @retval None
2527 */
2529 {
2531 }
2533 /**
2534 * @brief Indicate whether the timer counter is enabled.
2535 * @rmtoll MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
2536 * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
2537 * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
2538 * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
2539 * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
2540 * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
2541 * @param HRTIMx High Resolution Timer instance
2542 * @param Timer This parameter can be one of the following values:
2543 * @arg @ref LL_HRTIM_TIMER_MASTER
2544 * @arg @ref LL_HRTIM_TIMER_A
2545 * @arg @ref LL_HRTIM_TIMER_B
2546 * @arg @ref LL_HRTIM_TIMER_C
2547 * @arg @ref LL_HRTIM_TIMER_D
2548 * @arg @ref LL_HRTIM_TIMER_E
2549 * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
2550 */
2552 {
2554 }
2556 /**
2557 * @brief Set the timer clock prescaler ratio.
2558 * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
2559 * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
2560 * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
2561 * @note The prescaling ratio cannot be modified once the timer counter is enabled.
2562 * @param HRTIMx High Resolution Timer instance
2563 * @param Timer This parameter can be one of the following values:
2564 * @arg @ref LL_HRTIM_TIMER_MASTER
2565 * @arg @ref LL_HRTIM_TIMER_A
2566 * @arg @ref LL_HRTIM_TIMER_B
2567 * @arg @ref LL_HRTIM_TIMER_C
2568 * @arg @ref LL_HRTIM_TIMER_D
2569 * @arg @ref LL_HRTIM_TIMER_E
2570 * @param Prescaler This parameter can be one of the following values:
2571 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
2572 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
2573 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
2574 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
2575 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
2576 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
2577 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
2578 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
2579 * @retval None
2580 */
2581 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
2582 {
2584 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2586 }
2588 /**
2589 * @brief Get the timer clock prescaler ratio
2590 * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
2591 * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
2592 * @param HRTIMx High Resolution Timer instance
2593 * @param Timer This parameter can be one of the following values:
2594 * @arg @ref LL_HRTIM_TIMER_MASTER
2595 * @arg @ref LL_HRTIM_TIMER_A
2596 * @arg @ref LL_HRTIM_TIMER_B
2597 * @arg @ref LL_HRTIM_TIMER_C
2598 * @arg @ref LL_HRTIM_TIMER_D
2599 * @arg @ref LL_HRTIM_TIMER_E
2600 * @retval Prescaler Returned value can be one of the following values:
2601 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
2602 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
2603 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
2604 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
2605 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
2606 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
2607 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
2608 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
2609 */
2611 {
2613 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2615 }
2617 /**
2618 * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
2619 * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
2620 * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
2621 * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
2622 * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
2623 * @param HRTIMx High Resolution Timer instance
2624 * @param Timer This parameter can be one of the following values:
2625 * @arg @ref LL_HRTIM_TIMER_MASTER
2626 * @arg @ref LL_HRTIM_TIMER_A
2627 * @arg @ref LL_HRTIM_TIMER_B
2628 * @arg @ref LL_HRTIM_TIMER_C
2629 * @arg @ref LL_HRTIM_TIMER_D
2630 * @arg @ref LL_HRTIM_TIMER_E
2631 * @param Mode This parameter can be one of the following values:
2632 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
2633 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
2634 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
2635 * @retval None
2636 */
2637 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
2638 {
2640 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2642 }
2644 /**
2645 * @brief Get the counter operating mode mode
2646 * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
2647 * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
2648 * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
2649 * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
2650 * @param HRTIMx High Resolution Timer instance
2651 * @param Timer This parameter can be one of the following values:
2652 * @arg @ref LL_HRTIM_TIMER_MASTER
2653 * @arg @ref LL_HRTIM_TIMER_A
2654 * @arg @ref LL_HRTIM_TIMER_B
2655 * @arg @ref LL_HRTIM_TIMER_C
2656 * @arg @ref LL_HRTIM_TIMER_D
2657 * @arg @ref LL_HRTIM_TIMER_E
2658 * @retval Mode Returned value can be one of the following values:
2659 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
2660 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
2661 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
2662 */
2664 {
2666 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2668 }
2670 /**
2671 * @brief Enable the half duty-cycle mode.
2672 * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
2673 * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
2674 * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
2675 * active register is automatically updated with HRTIM_MPER/2
2676 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
2677 * @param HRTIMx High Resolution Timer instance
2678 * @param Timer This parameter can be one of the following values:
2679 * @arg @ref LL_HRTIM_TIMER_MASTER
2680 * @arg @ref LL_HRTIM_TIMER_A
2681 * @arg @ref LL_HRTIM_TIMER_B
2682 * @arg @ref LL_HRTIM_TIMER_C
2683 * @arg @ref LL_HRTIM_TIMER_D
2684 * @arg @ref LL_HRTIM_TIMER_E
2685 * @retval None
2686 */
2688 {
2690 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2692 }
2694 /**
2695 * @brief Disable the half duty-cycle mode.
2696 * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
2697 * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
2698 * @param HRTIMx High Resolution Timer instance
2699 * @param Timer This parameter can be one of the following values:
2700 * @arg @ref LL_HRTIM_TIMER_MASTER
2701 * @arg @ref LL_HRTIM_TIMER_A
2702 * @arg @ref LL_HRTIM_TIMER_B
2703 * @arg @ref LL_HRTIM_TIMER_C
2704 * @arg @ref LL_HRTIM_TIMER_D
2705 * @arg @ref LL_HRTIM_TIMER_E
2706 * @retval None
2707 */
2709 {
2711 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2713 }
2715 /**
2716 * @brief Indicate whether half duty-cycle mode is enabled for a given timer.
2717 * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
2718 * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
2719 * @param HRTIMx High Resolution Timer instance
2720 * @param Timer This parameter can be one of the following values:
2721 * @arg @ref LL_HRTIM_TIMER_MASTER
2722 * @arg @ref LL_HRTIM_TIMER_A
2723 * @arg @ref LL_HRTIM_TIMER_B
2724 * @arg @ref LL_HRTIM_TIMER_C
2725 * @arg @ref LL_HRTIM_TIMER_D
2726 * @arg @ref LL_HRTIM_TIMER_E
2727 * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
2728 */
2730 {
2732 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2735 }
2736 /**
2737 * @brief Enable the timer start when receiving a synchronization input event.
2738 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
2739 * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
2740 * @param HRTIMx High Resolution Timer instance
2741 * @param Timer This parameter can be one of the following values:
2742 * @arg @ref LL_HRTIM_TIMER_MASTER
2743 * @arg @ref LL_HRTIM_TIMER_A
2744 * @arg @ref LL_HRTIM_TIMER_B
2745 * @arg @ref LL_HRTIM_TIMER_C
2746 * @arg @ref LL_HRTIM_TIMER_D
2747 * @arg @ref LL_HRTIM_TIMER_E
2748 * @retval None
2749 */
2751 {
2753 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2755 }
2757 /**
2758 * @brief Disable the timer start when receiving a synchronization input event.
2759 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
2760 * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
2761 * @param HRTIMx High Resolution Timer instance
2762 * @param Timer This parameter can be one of the following values:
2763 * @arg @ref LL_HRTIM_TIMER_MASTER
2764 * @arg @ref LL_HRTIM_TIMER_A
2765 * @arg @ref LL_HRTIM_TIMER_B
2766 * @arg @ref LL_HRTIM_TIMER_C
2767 * @arg @ref LL_HRTIM_TIMER_D
2768 * @arg @ref LL_HRTIM_TIMER_E
2769 * @retval None
2770 */
2772 {
2774 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2776 }
2778 /**
2779 * @brief Indicate whether the timer start when receiving a synchronization input event.
2780 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
2781 * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
2782 * @param HRTIMx High Resolution Timer instance
2783 * @param Timer This parameter can be one of the following values:
2784 * @arg @ref LL_HRTIM_TIMER_MASTER
2785 * @arg @ref LL_HRTIM_TIMER_A
2786 * @arg @ref LL_HRTIM_TIMER_B
2787 * @arg @ref LL_HRTIM_TIMER_C
2788 * @arg @ref LL_HRTIM_TIMER_D
2789 * @arg @ref LL_HRTIM_TIMER_E
2790 * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
2791 */
2792 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2793 {
2795 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2798 }
2800 /**
2801 * @brief Enable the timer reset when receiving a synchronization input event.
2802 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
2803 * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
2804 * @param HRTIMx High Resolution Timer instance
2805 * @param Timer This parameter can be one of the following values:
2806 * @arg @ref LL_HRTIM_TIMER_MASTER
2807 * @arg @ref LL_HRTIM_TIMER_A
2808 * @arg @ref LL_HRTIM_TIMER_B
2809 * @arg @ref LL_HRTIM_TIMER_C
2810 * @arg @ref LL_HRTIM_TIMER_D
2811 * @arg @ref LL_HRTIM_TIMER_E
2812 * @retval None
2813 */
2815 {
2817 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2819 }
2821 /**
2822 * @brief Disable the timer reset when receiving a synchronization input event.
2823 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
2824 * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
2825 * @param HRTIMx High Resolution Timer instance
2826 * @param Timer This parameter can be one of the following values:
2827 * @arg @ref LL_HRTIM_TIMER_MASTER
2828 * @arg @ref LL_HRTIM_TIMER_A
2829 * @arg @ref LL_HRTIM_TIMER_B
2830 * @arg @ref LL_HRTIM_TIMER_C
2831 * @arg @ref LL_HRTIM_TIMER_D
2832 * @arg @ref LL_HRTIM_TIMER_E
2833 * @retval None
2834 */
2836 {
2838 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2840 }
2842 /**
2843 * @brief Indicate whether the timer reset when receiving a synchronization input event.
2844 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
2845 * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
2846 * @param HRTIMx High Resolution Timer instance
2847 * @param Timer This parameter can be one of the following values:
2848 * @arg @ref LL_HRTIM_TIMER_MASTER
2849 * @arg @ref LL_HRTIM_TIMER_A
2850 * @arg @ref LL_HRTIM_TIMER_B
2851 * @arg @ref LL_HRTIM_TIMER_C
2852 * @arg @ref LL_HRTIM_TIMER_D
2853 * @arg @ref LL_HRTIM_TIMER_E
2854 * @retval None
2855 */
2856 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2857 {
2859 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2862 }
2864 /**
2865 * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
2866 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
2867 * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
2868 * @param HRTIMx High Resolution Timer instance
2869 * @param Timer This parameter can be one of the following values:
2870 * @arg @ref LL_HRTIM_TIMER_MASTER
2871 * @arg @ref LL_HRTIM_TIMER_A
2872 * @arg @ref LL_HRTIM_TIMER_B
2873 * @arg @ref LL_HRTIM_TIMER_C
2874 * @arg @ref LL_HRTIM_TIMER_D
2875 * @arg @ref LL_HRTIM_TIMER_E
2876 * @param DACTrig This parameter can be one of the following values:
2877 * @arg @ref LL_HRTIM_DACTRIG_NONE
2878 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
2879 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
2880 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
2881 * @retval None
2882 */
2883 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
2884 {
2886 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2888 }
2890 /**
2891 * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
2892 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
2893 * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
2894 * @param HRTIMx High Resolution Timer instance
2895 * @param Timer This parameter can be one of the following values:
2896 * @arg @ref LL_HRTIM_TIMER_MASTER
2897 * @arg @ref LL_HRTIM_TIMER_A
2898 * @arg @ref LL_HRTIM_TIMER_B
2899 * @arg @ref LL_HRTIM_TIMER_C
2900 * @arg @ref LL_HRTIM_TIMER_D
2901 * @arg @ref LL_HRTIM_TIMER_E
2902 * @retval DACTrig Returned value can be one of the following values:
2903 * @arg @ref LL_HRTIM_DACTRIG_NONE
2904 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
2905 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
2906 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
2907 */
2909 {
2911 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2913 }
2915 /**
2916 * @brief Enable the timer registers preload mechanism.
2917 * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
2918 * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
2919 * @note When the preload mode is enabled, accessed registers are shadow registers.
2920 * Their content is transferred into the active register after an update request,
2921 * either software or synchronized with an event.
2922 * @param HRTIMx High Resolution Timer instance
2923 * @param Timer This parameter can be one of the following values:
2924 * @arg @ref LL_HRTIM_TIMER_MASTER
2925 * @arg @ref LL_HRTIM_TIMER_A
2926 * @arg @ref LL_HRTIM_TIMER_B
2927 * @arg @ref LL_HRTIM_TIMER_C
2928 * @arg @ref LL_HRTIM_TIMER_D
2929 * @arg @ref LL_HRTIM_TIMER_E
2930 * @retval None
2931 */
2933 {
2935 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2937 }
2939 /**
2940 * @brief Disable the timer registers preload mechanism.
2941 * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
2942 * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
2943 * @param HRTIMx High Resolution Timer instance
2944 * @param Timer This parameter can be one of the following values:
2945 * @arg @ref LL_HRTIM_TIMER_MASTER
2946 * @arg @ref LL_HRTIM_TIMER_A
2947 * @arg @ref LL_HRTIM_TIMER_B
2948 * @arg @ref LL_HRTIM_TIMER_C
2949 * @arg @ref LL_HRTIM_TIMER_D
2950 * @arg @ref LL_HRTIM_TIMER_E
2951 * @retval None
2952 */
2954 {
2956 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2958 }
2960 /**
2961 * @brief Indicate whether the timer registers preload mechanism is enabled.
2962 * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
2963 * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
2964 * @param HRTIMx High Resolution Timer instance
2965 * @param Timer This parameter can be one of the following values:
2966 * @arg @ref LL_HRTIM_TIMER_MASTER
2967 * @arg @ref LL_HRTIM_TIMER_A
2968 * @arg @ref LL_HRTIM_TIMER_B
2969 * @arg @ref LL_HRTIM_TIMER_C
2970 * @arg @ref LL_HRTIM_TIMER_D
2971 * @arg @ref LL_HRTIM_TIMER_E
2972 * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
2973 */
2975 {
2977 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2980 }
2982 /**
2983 * @brief Set the timer register update trigger.
2984 * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
2985 * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
2986 * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
2987 * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
2988 * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
2989 * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
2990 * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
2991 * @param HRTIMx High Resolution Timer instance
2992 * @param Timer This parameter can be one of the following values:
2993 * @arg @ref LL_HRTIM_TIMER_MASTER
2994 * @arg @ref LL_HRTIM_TIMER_A
2995 * @arg @ref LL_HRTIM_TIMER_B
2996 * @arg @ref LL_HRTIM_TIMER_C
2997 * @arg @ref LL_HRTIM_TIMER_D
2998 * @arg @ref LL_HRTIM_TIMER_E
2999 * @param UpdateTrig This parameter can be one of the following values:
3000 *
3001 * For the master timer this parameter can be one of the following values:
3002 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3003 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3004 *
3005 * For timer A..E this parameter can be:
3006 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3007 * or a combination of the following values:
3008 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
3009 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
3010 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
3011 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
3012 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
3013 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
3014 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3015 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
3016 * @retval None
3017 */
3018 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
3019 {
3021 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3022 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
3023 }
3025 /**
3026 * @brief Get the timer register update trigger.
3027 * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
3028 * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
3029 * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
3030 * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
3031 * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
3032 * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
3033 * @param HRTIMx High Resolution Timer instance
3034 * @param Timer This parameter can be one of the following values:
3035 * @arg @ref LL_HRTIM_TIMER_MASTER
3036 * @arg @ref LL_HRTIM_TIMER_A
3037 * @arg @ref LL_HRTIM_TIMER_B
3038 * @arg @ref LL_HRTIM_TIMER_C
3039 * @arg @ref LL_HRTIM_TIMER_D
3040 * @arg @ref LL_HRTIM_TIMER_E
3041 * @retval UpdateTrig Returned value can be one of the following values:
3042 *
3043 * For the master timer this parameter can be one of the following values:
3044 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3045 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3046 *
3047 * For timer A..E this parameter can be:
3048 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3049 * or a combination of the following values:
3050 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
3051 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
3052 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
3053 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
3054 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
3055 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
3056 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3057 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
3058 */
3060 {
3062 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3064 }
3066 /**
3067 * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
3068 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
3069 * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
3070 * @param HRTIMx High Resolution Timer instance
3071 * @param Timer This parameter can be one of the following values:
3072 * @arg @ref LL_HRTIM_TIMER_MASTER
3073 * @arg @ref LL_HRTIM_TIMER_A
3074 * @arg @ref LL_HRTIM_TIMER_B
3075 * @arg @ref LL_HRTIM_TIMER_C
3076 * @arg @ref LL_HRTIM_TIMER_D
3077 * @arg @ref LL_HRTIM_TIMER_E
3078 * @param UpdateGating This parameter can be one of the following values:
3079 *
3080 * For the master timer this parameter can be one of the following values:
3081 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3082 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3083 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3084 *
3085 * For the timer A..E this parameter can be one of the following values:
3086 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3087 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3088 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3089 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
3090 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
3091 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
3092 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
3093 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
3094 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
3095 * @retval None
3096 */
3097 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
3098 {
3100 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3101 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
3102 }
3104 /**
3105 * @brief Get the timer registers update condition.
3106 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
3107 * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
3108 * @param HRTIMx High Resolution Timer instance
3109 * @param Timer This parameter can be one of the following values:
3110 * @arg @ref LL_HRTIM_TIMER_MASTER
3111 * @arg @ref LL_HRTIM_TIMER_A
3112 * @arg @ref LL_HRTIM_TIMER_B
3113 * @arg @ref LL_HRTIM_TIMER_C
3114 * @arg @ref LL_HRTIM_TIMER_D
3115 * @arg @ref LL_HRTIM_TIMER_E
3116 * @retval UpdateGating Returned value can be one of the following values:
3117 *
3118 * For the master timer this parameter can be one of the following values:
3119 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3120 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3121 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3122 *
3123 * For the timer A..E this parameter can be one of the following values:
3124 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3125 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3126 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3127 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
3128 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
3129 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
3130 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
3131 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
3132 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
3133 */
3135 {
3137 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3138 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
3139 }
3141 /**
3142 * @brief Enable the push-pull mode.
3143 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
3144 * @param HRTIMx High Resolution Timer instance
3145 * @param Timer This parameter can be one of the following values:
3146 * @arg @ref LL_HRTIM_TIMER_A
3147 * @arg @ref LL_HRTIM_TIMER_B
3148 * @arg @ref LL_HRTIM_TIMER_C
3149 * @arg @ref LL_HRTIM_TIMER_D
3150 * @arg @ref LL_HRTIM_TIMER_E
3151 * @retval None
3152 */
3154 {
3156 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3159 }
3161 /**
3162 * @brief Disable the push-pull mode.
3163 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
3164 * @param HRTIMx High Resolution Timer instance
3165 * @param Timer This parameter can be one of the following values:
3166 * @arg @ref LL_HRTIM_TIMER_A
3167 * @arg @ref LL_HRTIM_TIMER_B
3168 * @arg @ref LL_HRTIM_TIMER_C
3169 * @arg @ref LL_HRTIM_TIMER_D
3170 * @arg @ref LL_HRTIM_TIMER_E
3171 * @retval None
3172 */
3174 {
3176 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3179 }
3181 /**
3182 * @brief Indicate whether the push-pull mode is enabled.
3183 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
3184 * @param HRTIMx High Resolution Timer instance
3185 * @param Timer This parameter can be one of the following values:
3186 * @arg @ref LL_HRTIM_TIMER_A
3187 * @arg @ref LL_HRTIM_TIMER_B
3188 * @arg @ref LL_HRTIM_TIMER_C
3189 * @arg @ref LL_HRTIM_TIMER_D
3190 * @arg @ref LL_HRTIM_TIMER_E
3191 * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
3192 */
3193 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3194 {
3196 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3199 }
3201 /**
3202 * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
3203 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
3204 * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
3205 * @note In auto-delayed mode the compare match occurs independently from the timer counter value.
3206 * @param HRTIMx High Resolution Timer instance
3207 * @param Timer This parameter can be one of the following values:
3208 * @arg @ref LL_HRTIM_TIMER_A
3209 * @arg @ref LL_HRTIM_TIMER_B
3210 * @arg @ref LL_HRTIM_TIMER_C
3211 * @arg @ref LL_HRTIM_TIMER_D
3212 * @arg @ref LL_HRTIM_TIMER_E
3213 * @param CompareUnit This parameter can be one of the following values:
3214 * @arg @ref LL_HRTIM_COMPAREUNIT_2
3215 * @arg @ref LL_HRTIM_COMPAREUNIT_4
3216 * @param Mode This parameter can be one of the following values:
3217 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
3218 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
3219 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
3220 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
3221 * @retval None
3222 */
3223 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
3225 {
3227 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3229 register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
3231 }
3233 /**
3234 * @brief Get the functioning mode of the compare unit.
3235 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
3236 * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
3237 * @param HRTIMx High Resolution Timer instance
3238 * @param Timer This parameter can be one of the following values:
3239 * @arg @ref LL_HRTIM_TIMER_A
3240 * @arg @ref LL_HRTIM_TIMER_B
3241 * @arg @ref LL_HRTIM_TIMER_C
3242 * @arg @ref LL_HRTIM_TIMER_D
3243 * @arg @ref LL_HRTIM_TIMER_E
3244 * @param CompareUnit This parameter can be one of the following values:
3245 * @arg @ref LL_HRTIM_COMPAREUNIT_2
3246 * @arg @ref LL_HRTIM_COMPAREUNIT_4
3247 * @retval Mode Returned value can be one of the following values:
3248 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
3249 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
3250 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
3251 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
3252 */
3253 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
3254 {
3256 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3258 register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
3260 }
3262 /**
3263 * @brief Set the timer counter value.
3264 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
3265 * CNTxR CNTx LL_HRTIM_TIM_SetCounter
3266 * @note This function can only be called when the timer is stopped.
3267 * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
3268 * significant bits of the counter are not significant. They cannot be
3269 * written and return 0 when read.
3270 * @note The timer behavior is not guaranteed if the counter value is set above
3271 * the period.
3272 * @param HRTIMx High Resolution Timer instance
3273 * @param Timer This parameter can be one of the following values:
3274 * @arg @ref LL_HRTIM_TIMER_MASTER
3275 * @arg @ref LL_HRTIM_TIMER_A
3276 * @arg @ref LL_HRTIM_TIMER_B
3277 * @arg @ref LL_HRTIM_TIMER_C
3278 * @arg @ref LL_HRTIM_TIMER_D
3279 * @arg @ref LL_HRTIM_TIMER_E
3280 * @param Counter Value between 0 and 0xFFFF
3281 * @retval None
3282 */
3283 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
3284 {
3286 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
3289 }
3291 /**
3292 * @brief Get actual timer counter value.
3293 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
3294 * CNTxR CNTx LL_HRTIM_TIM_GetCounter
3295 * @param HRTIMx High Resolution Timer instance
3296 * @param Timer This parameter can be one of the following values:
3297 * @arg @ref LL_HRTIM_TIMER_MASTER
3298 * @arg @ref LL_HRTIM_TIMER_A
3299 * @arg @ref LL_HRTIM_TIMER_B
3300 * @arg @ref LL_HRTIM_TIMER_C
3301 * @arg @ref LL_HRTIM_TIMER_D
3302 * @arg @ref LL_HRTIM_TIMER_E
3303 * @retval Counter Value between 0 and 0xFFFF
3304 */
3306 {
3308 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
3311 }
3313 /**
3314 * @brief Set the timer period value.
3315 * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
3316 * PERxR PERx LL_HRTIM_TIM_SetPeriod
3317 * @param HRTIMx High Resolution Timer instance
3318 * @param Timer This parameter can be one of the following values:
3319 * @arg @ref LL_HRTIM_TIMER_MASTER
3320 * @arg @ref LL_HRTIM_TIMER_A
3321 * @arg @ref LL_HRTIM_TIMER_B
3322 * @arg @ref LL_HRTIM_TIMER_C
3323 * @arg @ref LL_HRTIM_TIMER_D
3324 * @arg @ref LL_HRTIM_TIMER_E
3325 * @param Period Value between 0 and 0xFFFF
3326 * @retval None
3327 */
3328 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
3329 {
3331 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
3334 }
3336 /**
3337 * @brief Get actual timer period value.
3338 * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
3339 * PERxR PERx LL_HRTIM_TIM_GetPeriod
3340 * @param HRTIMx High Resolution Timer instance
3341 * @param Timer This parameter can be one of the following values:
3342 * @arg @ref LL_HRTIM_TIMER_MASTER
3343 * @arg @ref LL_HRTIM_TIMER_A
3344 * @arg @ref LL_HRTIM_TIMER_B
3345 * @arg @ref LL_HRTIM_TIMER_C
3346 * @arg @ref LL_HRTIM_TIMER_D
3347 * @arg @ref LL_HRTIM_TIMER_E
3348 * @retval Period Value between 0 and 0xFFFF
3349 */
3351 {
3353 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
3356 }
3358 /**
3359 * @brief Set the timer repetition period value.
3360 * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
3361 * REPxR REPx LL_HRTIM_TIM_SetRepetition
3362 * @param HRTIMx High Resolution Timer instance
3363 * @param Timer This parameter can be one of the following values:
3364 * @arg @ref LL_HRTIM_TIMER_MASTER
3365 * @arg @ref LL_HRTIM_TIMER_A
3366 * @arg @ref LL_HRTIM_TIMER_B
3367 * @arg @ref LL_HRTIM_TIMER_C
3368 * @arg @ref LL_HRTIM_TIMER_D
3369 * @arg @ref LL_HRTIM_TIMER_E
3370 * @param Repetition Value between 0 and 0xFF
3371 * @retval None
3372 */
3373 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
3374 {
3376 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
3379 }
3381 /**
3382 * @brief Get actual timer repetition period value.
3383 * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
3384 * REPxR REPx LL_HRTIM_TIM_GetRepetition
3385 * @param HRTIMx High Resolution Timer instance
3386 * @param Timer This parameter can be one of the following values:
3387 * @arg @ref LL_HRTIM_TIMER_MASTER
3388 * @arg @ref LL_HRTIM_TIMER_A
3389 * @arg @ref LL_HRTIM_TIMER_B
3390 * @arg @ref LL_HRTIM_TIMER_C
3391 * @arg @ref LL_HRTIM_TIMER_D
3392 * @arg @ref LL_HRTIM_TIMER_E
3393 * @retval Repetition Value between 0 and 0xFF
3394 */
3396 {
3398 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
3401 }
3403 /**
3404 * @brief Set the compare value of the compare unit 1.
3405 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
3406 * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
3407 * @param HRTIMx High Resolution Timer instance
3408 * @param Timer This parameter can be one of the following values:
3409 * @arg @ref LL_HRTIM_TIMER_MASTER
3410 * @arg @ref LL_HRTIM_TIMER_A
3411 * @arg @ref LL_HRTIM_TIMER_B
3412 * @arg @ref LL_HRTIM_TIMER_C
3413 * @arg @ref LL_HRTIM_TIMER_D
3414 * @arg @ref LL_HRTIM_TIMER_E
3415 * @param CompareValue Compare value must be above or equal to 3
3416 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3417 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3418 * @retval None
3419 */
3420 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3421 {
3423 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
3426 }
3428 /**
3429 * @brief Get actual compare value of the compare unit 1.
3430 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
3431 * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
3432 * @param HRTIMx High Resolution Timer instance
3433 * @param Timer This parameter can be one of the following values:
3434 * @arg @ref LL_HRTIM_TIMER_MASTER
3435 * @arg @ref LL_HRTIM_TIMER_A
3436 * @arg @ref LL_HRTIM_TIMER_B
3437 * @arg @ref LL_HRTIM_TIMER_C
3438 * @arg @ref LL_HRTIM_TIMER_D
3439 * @arg @ref LL_HRTIM_TIMER_E
3440 * @retval CompareValue Compare value must be above or equal to 3
3441 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3442 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3443 */
3445 {
3447 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
3450 }
3452 /**
3453 * @brief Set the compare value of the compare unit 2.
3454 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
3455 * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
3456 * @param HRTIMx High Resolution Timer instance
3457 * @param Timer This parameter can be one of the following values:
3458 * @arg @ref LL_HRTIM_TIMER_MASTER
3459 * @arg @ref LL_HRTIM_TIMER_A
3460 * @arg @ref LL_HRTIM_TIMER_B
3461 * @arg @ref LL_HRTIM_TIMER_C
3462 * @arg @ref LL_HRTIM_TIMER_D
3463 * @arg @ref LL_HRTIM_TIMER_E
3464 * @param CompareValue Compare value must be above or equal to 3
3465 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3466 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3467 * @retval None
3468 */
3469 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3470 {
3472 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
3475 }
3477 /**
3478 * @brief Get actual compare value of the compare unit 2.
3479 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
3480 * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
3481 * @param HRTIMx High Resolution Timer instance
3482 * @param Timer This parameter can be one of the following values:
3483 * @arg @ref LL_HRTIM_TIMER_MASTER
3484 * @arg @ref LL_HRTIM_TIMER_A
3485 * @arg @ref LL_HRTIM_TIMER_B
3486 * @arg @ref LL_HRTIM_TIMER_C
3487 * @arg @ref LL_HRTIM_TIMER_D
3488 * @arg @ref LL_HRTIM_TIMER_E
3489 * @retval CompareValue Compare value must be above or equal to 3
3490 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3491 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3492 */
3494 {
3496 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
3499 }
3501 /**
3502 * @brief Set the compare value of the compare unit 3.
3503 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
3504 * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
3505 * @param HRTIMx High Resolution Timer instance
3506 * @param Timer This parameter can be one of the following values:
3507 * @arg @ref LL_HRTIM_TIMER_MASTER
3508 * @arg @ref LL_HRTIM_TIMER_A
3509 * @arg @ref LL_HRTIM_TIMER_B
3510 * @arg @ref LL_HRTIM_TIMER_C
3511 * @arg @ref LL_HRTIM_TIMER_D
3512 * @arg @ref LL_HRTIM_TIMER_E
3513 * @param CompareValue Compare value must be above or equal to 3
3514 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3515 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3516 * @retval None
3517 */
3518 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3519 {
3521 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
3524 }
3526 /**
3527 * @brief Get actual compare value of the compare unit 3.
3528 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
3529 * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
3530 * @param HRTIMx High Resolution Timer instance
3531 * @param Timer This parameter can be one of the following values:
3532 * @arg @ref LL_HRTIM_TIMER_MASTER
3533 * @arg @ref LL_HRTIM_TIMER_A
3534 * @arg @ref LL_HRTIM_TIMER_B
3535 * @arg @ref LL_HRTIM_TIMER_C
3536 * @arg @ref LL_HRTIM_TIMER_D
3537 * @arg @ref LL_HRTIM_TIMER_E
3538 * @retval CompareValue Compare value must be above or equal to 3
3539 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3540 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3541 */
3543 {
3545 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
3548 }
3550 /**
3551 * @brief Set the compare value of the compare unit 4.
3552 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
3553 * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
3554 * @param HRTIMx High Resolution Timer instance
3555 * @param Timer This parameter can be one of the following values:
3556 * @arg @ref LL_HRTIM_TIMER_MASTER
3557 * @arg @ref LL_HRTIM_TIMER_A
3558 * @arg @ref LL_HRTIM_TIMER_B
3559 * @arg @ref LL_HRTIM_TIMER_C
3560 * @arg @ref LL_HRTIM_TIMER_D
3561 * @arg @ref LL_HRTIM_TIMER_E
3562 * @param CompareValue Compare value must be above or equal to 3
3563 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3564 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3565 * @retval None
3566 */
3567 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3568 {
3570 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
3573 }
3575 /**
3576 * @brief Get actual compare value of the compare unit 4.
3577 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
3578 * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
3579 * @param HRTIMx High Resolution Timer instance
3580 * @param Timer This parameter can be one of the following values:
3581 * @arg @ref LL_HRTIM_TIMER_MASTER
3582 * @arg @ref LL_HRTIM_TIMER_A
3583 * @arg @ref LL_HRTIM_TIMER_B
3584 * @arg @ref LL_HRTIM_TIMER_C
3585 * @arg @ref LL_HRTIM_TIMER_D
3586 * @arg @ref LL_HRTIM_TIMER_E
3587 * @retval CompareValue Compare value must be above or equal to 3
3588 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3589 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3590 */
3592 {
3594 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
3597 }
3599 /**
3600 * @brief Set the reset trigger of a timer counter.
3601 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
3602 * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
3603 * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
3604 * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
3605 * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
3606 * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
3607 * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
3608 * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
3609 * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
3610 * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
3611 * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
3612 * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
3613 * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
3614 * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
3615 * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
3616 * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
3617 * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
3618 * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
3619 * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
3620 * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
3621 * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
3622 * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
3623 * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
3624 * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
3625 * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
3626 * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
3627 * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
3628 * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
3629 * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
3630 * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig
3631 * @note The reset of the timer counter can be triggered by up to 30 events
3632 * that can be selected among the following sources:
3633 * @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
3634 * @arg The master timer: Reset and Compare 1..4 (5 events).
3635 * @arg The external events EXTEVNT1..10 (10 events).
3636 * @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events).
3637 * @param HRTIMx High Resolution Timer instance
3638 * @param Timer This parameter can be one of the following values:
3639 * @arg @ref LL_HRTIM_TIMER_A
3640 * @arg @ref LL_HRTIM_TIMER_B
3641 * @arg @ref LL_HRTIM_TIMER_C
3642 * @arg @ref LL_HRTIM_TIMER_D
3643 * @arg @ref LL_HRTIM_TIMER_E
3644 * @param ResetTrig This parameter can be a combination of the following values:
3645 * @arg @ref LL_HRTIM_RESETTRIG_NONE
3646 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
3647 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
3648 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
3649 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
3650 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
3651 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
3652 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
3653 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
3654 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
3655 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
3656 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
3657 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
3658 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
3659 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
3660 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
3661 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
3662 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
3663 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
3664 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
3665 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
3666 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
3667 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
3668 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
3669 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
3670 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
3671 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
3672 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
3673 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
3674 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
3675 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
3676 * @retval None
3677 */
3678 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
3679 {
3681 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
3684 }
3686 /**
3687 * @brief Get actual reset trigger of a timer counter.
3688 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
3689 * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
3690 * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
3691 * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
3692 * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
3693 * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
3694 * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
3695 * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
3696 * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
3697 * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
3698 * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
3699 * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
3700 * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
3701 * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
3702 * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
3703 * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
3704 * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
3705 * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
3706 * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
3707 * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
3708 * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
3709 * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
3710 * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
3711 * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
3712 * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
3713 * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
3714 * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
3715 * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
3716 * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
3717 * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig
3718 * @param HRTIMx High Resolution Timer instance
3719 * @param Timer This parameter can be one of the following values:
3720 * @arg @ref LL_HRTIM_TIMER_A
3721 * @arg @ref LL_HRTIM_TIMER_B
3722 * @arg @ref LL_HRTIM_TIMER_C
3723 * @arg @ref LL_HRTIM_TIMER_D
3724 * @arg @ref LL_HRTIM_TIMER_E
3725 * @retval ResetTrig Returned value can be one of the following values:
3726 * @arg @ref LL_HRTIM_RESETTRIG_NONE
3727 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
3728 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
3729 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
3730 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
3731 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
3732 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
3733 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
3734 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
3735 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
3736 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
3737 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
3738 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
3739 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
3740 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
3741 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
3742 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
3743 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
3744 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
3745 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
3746 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
3747 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
3748 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
3749 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
3750 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
3751 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
3752 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
3753 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
3754 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
3755 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
3756 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
3757 */
3759 {
3761 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
3764 }
3766 /**
3767 * @brief Get captured value for capture unit 1.
3768 * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
3769 * @param HRTIMx High Resolution Timer instance
3770 * @param Timer This parameter can be one of the following values:
3771 * @arg @ref LL_HRTIM_TIMER_A
3772 * @arg @ref LL_HRTIM_TIMER_B
3773 * @arg @ref LL_HRTIM_TIMER_C
3774 * @arg @ref LL_HRTIM_TIMER_D
3775 * @arg @ref LL_HRTIM_TIMER_E
3776 * @retval Captured value
3777 */
3779 {
3781 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
3784 }
3786 /**
3787 * @brief Get captured value for capture unit 2.
3788 * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
3789 * @param HRTIMx High Resolution Timer instance
3790 * @param Timer This parameter can be one of the following values:
3791 * @arg @ref LL_HRTIM_TIMER_A
3792 * @arg @ref LL_HRTIM_TIMER_B
3793 * @arg @ref LL_HRTIM_TIMER_C
3794 * @arg @ref LL_HRTIM_TIMER_D
3795 * @arg @ref LL_HRTIM_TIMER_E
3796 * @retval Captured value
3797 */
3799 {
3801 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
3804 }
3806 /**
3807 * @brief Set the trigger of a capture unit for a given timer.
3808 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
3809 * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
3810 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
3811 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
3812 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
3813 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
3814 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
3815 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
3816 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
3817 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
3818 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
3819 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
3820 * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
3821 * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
3822 * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3823 * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3824 * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
3825 * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
3826 * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3827 * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3828 * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
3829 * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
3830 * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3831 * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3832 * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
3833 * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
3834 * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3835 * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3836 * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
3837 * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
3838 * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3839 * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig
3840 * @param HRTIMx High Resolution Timer instance
3841 * @param Timer This parameter can be one of the following values:
3842 * @arg @ref LL_HRTIM_TIMER_A
3843 * @arg @ref LL_HRTIM_TIMER_B
3844 * @arg @ref LL_HRTIM_TIMER_C
3845 * @arg @ref LL_HRTIM_TIMER_D
3846 * @arg @ref LL_HRTIM_TIMER_E
3847 * @param CaptureUnit This parameter can be one of the following values:
3848 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
3849 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
3850 * @param CaptureTrig This parameter can be a combination of the following values:
3851 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
3852 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
3853 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
3854 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
3855 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
3856 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
3857 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
3858 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
3859 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
3860 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
3861 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
3862 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
3863 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
3864 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
3865 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
3866 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
3867 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
3868 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
3869 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
3870 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
3871 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
3872 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
3873 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
3874 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
3875 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
3876 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
3877 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
3878 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
3879 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
3880 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
3881 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
3882 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
3883 * @retval None
3884 */
3885 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
3887 {
3889 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
3892 }
3894 /**
3895 * @brief Get actual trigger of a capture unit for a given timer.
3896 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
3897 * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
3898 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
3899 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
3900 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
3901 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
3902 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
3903 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
3904 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
3905 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
3906 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
3907 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
3908 * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
3909 * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
3910 * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3911 * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3912 * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
3913 * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
3914 * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3915 * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3916 * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
3917 * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
3918 * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3919 * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3920 * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
3921 * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
3922 * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3923 * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3924 * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
3925 * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
3926 * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3927 * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig
3928 * @param HRTIMx High Resolution Timer instance
3929 * @param Timer This parameter can be one of the following values:
3930 * @arg @ref LL_HRTIM_TIMER_A
3931 * @arg @ref LL_HRTIM_TIMER_B
3932 * @arg @ref LL_HRTIM_TIMER_C
3933 * @arg @ref LL_HRTIM_TIMER_D
3934 * @arg @ref LL_HRTIM_TIMER_E
3935 * @param CaptureUnit This parameter can be one of the following values:
3936 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
3937 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
3938 * @retval CaptureTrig This parameter can be a combination of the following values:
3939 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
3940 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
3941 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
3942 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
3943 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
3944 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
3945 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
3946 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
3947 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
3948 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
3949 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
3950 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
3951 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
3952 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
3953 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
3954 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
3955 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
3956 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
3957 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
3958 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
3959 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
3960 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
3961 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
3962 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
3963 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
3964 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
3965 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
3966 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
3967 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
3968 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
3969 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
3970 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
3971 */
3972 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
3973 {
3975 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
3978 }
3980 /**
3981 * @brief Enable deadtime insertion for a given timer.
3982 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
3983 * @param HRTIMx High Resolution Timer instance
3984 * @param Timer This parameter can be one of the following values:
3985 * @arg @ref LL_HRTIM_TIMER_A
3986 * @arg @ref LL_HRTIM_TIMER_B
3987 * @arg @ref LL_HRTIM_TIMER_C
3988 * @arg @ref LL_HRTIM_TIMER_D
3989 * @arg @ref LL_HRTIM_TIMER_E
3990 * @retval None
3991 */
3993 {
3995 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
3998 }
4000 /**
4001 * @brief Disable deadtime insertion for a given timer.
4002 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
4003 * @param HRTIMx High Resolution Timer instance
4004 * @param Timer This parameter can be one of the following values:
4005 * @arg @ref LL_HRTIM_TIMER_A
4006 * @arg @ref LL_HRTIM_TIMER_B
4007 * @arg @ref LL_HRTIM_TIMER_C
4008 * @arg @ref LL_HRTIM_TIMER_D
4009 * @arg @ref LL_HRTIM_TIMER_E
4010 * @retval None
4011 */
4013 {
4015 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4018 }
4020 /**
4021 * @brief Indicate whether deadtime insertion is enabled for a given timer.
4022 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
4023 * @param HRTIMx High Resolution Timer instance
4024 * @param Timer This parameter can be one of the following values:
4025 * @arg @ref LL_HRTIM_TIMER_A
4026 * @arg @ref LL_HRTIM_TIMER_B
4027 * @arg @ref LL_HRTIM_TIMER_C
4028 * @arg @ref LL_HRTIM_TIMER_D
4029 * @arg @ref LL_HRTIM_TIMER_E
4030 * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
4031 */
4033 {
4035 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4039 }
4041 /**
4042 * @brief Set the delayed protection (DLYPRT) mode.
4043 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
4044 * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
4045 * @note This function must be called prior enabling the delayed protection
4046 * @note Balanced Idle mode is only available in push-pull mode
4047 * @param HRTIMx High Resolution Timer instance
4048 * @param Timer This parameter can be one of the following values:
4049 * @arg @ref LL_HRTIM_TIMER_A
4050 * @arg @ref LL_HRTIM_TIMER_B
4051 * @arg @ref LL_HRTIM_TIMER_C
4052 * @arg @ref LL_HRTIM_TIMER_D
4053 * @arg @ref LL_HRTIM_TIMER_E
4054 * @param DLYPRTMode Delayed protection (DLYPRT) mode
4055 *
4056 * For timers A, B and C this parameter can be one of the following values:
4057 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
4058 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
4059 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
4060 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
4061 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
4062 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
4063 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
4064 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
4065 *
4066 * For timers D and E this parameter can be one of the following values:
4067 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
4068 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
4069 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
4070 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
4071 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
4072 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
4073 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
4074 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
4075 * @retval None
4076 */
4077 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
4078 {
4080 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4083 }
4085 /**
4086 * @brief Get the delayed protection (DLYPRT) mode.
4087 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
4088 * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
4089 * @param HRTIMx High Resolution Timer instance
4090 * @param Timer This parameter can be one of the following values:
4091 * @arg @ref LL_HRTIM_TIMER_A
4092 * @arg @ref LL_HRTIM_TIMER_B
4093 * @arg @ref LL_HRTIM_TIMER_C
4094 * @arg @ref LL_HRTIM_TIMER_D
4095 * @arg @ref LL_HRTIM_TIMER_E
4096 * @retval DLYPRTMode Delayed protection (DLYPRT) mode
4097 *
4098 * For timers A, B and C this parameter can be one of the following values:
4099 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
4100 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
4101 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
4102 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
4103 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
4104 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
4105 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
4106 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
4107 *
4108 * For timers D and E this parameter can be one of the following values:
4109 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
4110 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
4111 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
4112 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
4113 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
4114 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
4115 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
4116 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
4117 */
4119 {
4121 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4124 }
4126 /**
4127 * @brief Enable delayed protection (DLYPRT) for a given timer.
4128 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
4129 * @note This function must not be called once the concerned timer is enabled
4130 * @param HRTIMx High Resolution Timer instance
4131 * @param Timer This parameter can be one of the following values:
4132 * @arg @ref LL_HRTIM_TIMER_A
4133 * @arg @ref LL_HRTIM_TIMER_B
4134 * @arg @ref LL_HRTIM_TIMER_C
4135 * @arg @ref LL_HRTIM_TIMER_D
4136 * @arg @ref LL_HRTIM_TIMER_E
4137 * @retval None
4138 */
4140 {
4142 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4145 }
4147 /**
4148 * @brief Disable delayed protection (DLYPRT) for a given timer.
4149 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
4150 * @note This function must not be called once the concerned timer is enabled
4151 * @param HRTIMx High Resolution Timer instance
4152 * @param Timer This parameter can be one of the following values:
4153 * @arg @ref LL_HRTIM_TIMER_A
4154 * @arg @ref LL_HRTIM_TIMER_B
4155 * @arg @ref LL_HRTIM_TIMER_C
4156 * @arg @ref LL_HRTIM_TIMER_D
4157 * @arg @ref LL_HRTIM_TIMER_E
4158 * @retval None
4159 */
4161 {
4163 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4166 }
4168 /**
4169 * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
4170 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
4171 * @param HRTIMx High Resolution Timer instance
4172 * @param Timer This parameter can be one of the following values:
4173 * @arg @ref LL_HRTIM_TIMER_A
4174 * @arg @ref LL_HRTIM_TIMER_B
4175 * @arg @ref LL_HRTIM_TIMER_C
4176 * @arg @ref LL_HRTIM_TIMER_D
4177 * @arg @ref LL_HRTIM_TIMER_E
4178 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
4179 */
4181 {
4183 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4186 }
4188 /**
4189 * @brief Enable the fault channel(s) for a given timer.
4190 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
4191 * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
4192 * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
4193 * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
4194 * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault
4195 * @param HRTIMx High Resolution Timer instance
4196 * @param Timer This parameter can be one of the following values:
4197 * @arg @ref LL_HRTIM_TIMER_A
4198 * @arg @ref LL_HRTIM_TIMER_B
4199 * @arg @ref LL_HRTIM_TIMER_C
4200 * @arg @ref LL_HRTIM_TIMER_D
4201 * @arg @ref LL_HRTIM_TIMER_E
4202 * @param Faults This parameter can be a combination of the following values:
4203 * @arg @ref LL_HRTIM_FAULT_1
4204 * @arg @ref LL_HRTIM_FAULT_2
4205 * @arg @ref LL_HRTIM_FAULT_3
4206 * @arg @ref LL_HRTIM_FAULT_4
4207 * @arg @ref LL_HRTIM_FAULT_5
4208 * @retval None
4209 */
4210 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
4211 {
4213 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4216 }
4218 /**
4219 * @brief Disable the fault channel(s) for a given timer.
4220 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
4221 * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
4222 * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
4223 * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
4224 * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault
4225 * @param HRTIMx High Resolution Timer instance
4226 * @param Timer This parameter can be one of the following values:
4227 * @arg @ref LL_HRTIM_TIMER_A
4228 * @arg @ref LL_HRTIM_TIMER_B
4229 * @arg @ref LL_HRTIM_TIMER_C
4230 * @arg @ref LL_HRTIM_TIMER_D
4231 * @arg @ref LL_HRTIM_TIMER_E
4232 * @param Faults This parameter can be a combination of the following values:
4233 * @arg @ref LL_HRTIM_FAULT_1
4234 * @arg @ref LL_HRTIM_FAULT_2
4235 * @arg @ref LL_HRTIM_FAULT_3
4236 * @arg @ref LL_HRTIM_FAULT_4
4237 * @arg @ref LL_HRTIM_FAULT_5
4238 * @retval None
4239 */
4240 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
4241 {
4243 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4246 }
4248 /**
4249 * @brief Indicate whether the fault channel is enabled for a given timer.
4250 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
4251 * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
4252 * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
4253 * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
4254 * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault
4255 * @param HRTIMx High Resolution Timer instance
4256 * @param Timer This parameter can be one of the following values:
4257 * @arg @ref LL_HRTIM_TIMER_A
4258 * @arg @ref LL_HRTIM_TIMER_B
4259 * @arg @ref LL_HRTIM_TIMER_C
4260 * @arg @ref LL_HRTIM_TIMER_D
4261 * @arg @ref LL_HRTIM_TIMER_E
4262 * @param Fault This parameter can be one of the following values:
4263 * @arg @ref LL_HRTIM_FAULT_1
4264 * @arg @ref LL_HRTIM_FAULT_2
4265 * @arg @ref LL_HRTIM_FAULT_3
4266 * @arg @ref LL_HRTIM_FAULT_4
4267 * @arg @ref LL_HRTIM_FAULT_5
4268 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
4269 */
4270 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
4271 {
4273 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4277 }
4279 /**
4280 * @brief Lock the fault conditioning set-up for a given timer.
4281 * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
4282 * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
4283 * @param HRTIMx High Resolution Timer instance
4284 * @param Timer This parameter can be one of the following values:
4285 * @arg @ref LL_HRTIM_TIMER_A
4286 * @arg @ref LL_HRTIM_TIMER_B
4287 * @arg @ref LL_HRTIM_TIMER_C
4288 * @arg @ref LL_HRTIM_TIMER_D
4289 * @arg @ref LL_HRTIM_TIMER_E
4290 * @retval None
4291 */
4293 {
4295 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4298 }
4300 /**
4301 * @brief Define how the timer behaves during a burst mode operation.
4302 * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
4303 * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
4304 * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
4305 * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
4306 * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
4307 * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption
4308 * @note This function must not be called when the burst mode is enabled
4309 * @param HRTIMx High Resolution Timer instance
4310 * @param Timer This parameter can be one of the following values:
4311 * @arg @ref LL_HRTIM_TIMER_MASTER
4312 * @arg @ref LL_HRTIM_TIMER_A
4313 * @arg @ref LL_HRTIM_TIMER_B
4314 * @arg @ref LL_HRTIM_TIMER_C
4315 * @arg @ref LL_HRTIM_TIMER_D
4316 * @arg @ref LL_HRTIM_TIMER_E
4317 * @param BurtsModeOption This parameter can be one of the following values:
4318 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
4319 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
4320 * @retval None
4321 */
4322 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
4323 {
4326 }
4328 /**
4329 * @brief Retrieve how the timer behaves during a burst mode operation.
4330 * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
4331 * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
4332 * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
4333 * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
4334 * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
4335 * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption
4336 * @param HRTIMx High Resolution Timer instance
4337 * @param Timer This parameter can be one of the following values:
4338 * @arg @ref LL_HRTIM_TIMER_MASTER
4339 * @arg @ref LL_HRTIM_TIMER_A
4340 * @arg @ref LL_HRTIM_TIMER_B
4341 * @arg @ref LL_HRTIM_TIMER_C
4342 * @arg @ref LL_HRTIM_TIMER_D
4343 * @arg @ref LL_HRTIM_TIMER_E
4344 * @retval BurtsMode This parameter can be one of the following values:
4345 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
4346 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
4347 */
4348 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4349 {
4352 }
4354 /**
4355 * @brief Program which registers are to be written by Burst DMA transfers.
4356 * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
4357 * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
4358 * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
4359 * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
4360 * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
4361 * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
4362 * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
4363 * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
4364 * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
4365 * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
4366 * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
4367 * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
4368 * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
4369 * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
4370 * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
4371 * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
4372 * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
4373 * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
4374 * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
4375 * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
4376 * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
4377 * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
4378 * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
4379 * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
4380 * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
4381 * BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
4382 * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
4383 * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
4384 * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
4385 * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
4386 * @param HRTIMx High Resolution Timer instance
4387 * @param Timer This parameter can be one of the following values:
4388 * @arg @ref LL_HRTIM_TIMER_MASTER
4389 * @arg @ref LL_HRTIM_TIMER_A
4390 * @arg @ref LL_HRTIM_TIMER_B
4391 * @arg @ref LL_HRTIM_TIMER_C
4392 * @arg @ref LL_HRTIM_TIMER_D
4393 * @arg @ref LL_HRTIM_TIMER_E
4394 * @param Registers Registers to be updated by the DMA request
4395 *
4396 * For Master timer this parameter can be can be a combination of the following values:
4397 * @arg @ref LL_HRTIM_BURSTDMA_NONE
4398 * @arg @ref LL_HRTIM_BURSTDMA_MCR
4399 * @arg @ref LL_HRTIM_BURSTDMA_MICR
4400 * @arg @ref LL_HRTIM_BURSTDMA_MDIER
4401 * @arg @ref LL_HRTIM_BURSTDMA_MCNT
4402 * @arg @ref LL_HRTIM_BURSTDMA_MPER
4403 * @arg @ref LL_HRTIM_BURSTDMA_MREP
4404 * @arg @ref LL_HRTIM_BURSTDMA_MCMP1
4405 * @arg @ref LL_HRTIM_BURSTDMA_MCMP2
4406 * @arg @ref LL_HRTIM_BURSTDMA_MCMP3
4407 * @arg @ref LL_HRTIM_BURSTDMA_MCMP4
4408 *
4409 * For Timers A..E this parameter can be can be a combination of the following values:
4410 * @arg @ref LL_HRTIM_BURSTDMA_NONE
4411 * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
4412 * @arg @ref LL_HRTIM_BURSTDMA_TIMICR
4413 * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
4414 * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
4415 * @arg @ref LL_HRTIM_BURSTDMA_TIMPER
4416 * @arg @ref LL_HRTIM_BURSTDMA_TIMREP
4417 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
4418 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
4419 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
4420 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
4421 * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
4422 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
4423 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
4424 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
4425 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
4426 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
4427 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
4428 * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
4429 * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
4430 * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
4431 * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
4432 * @retval None
4433 */
4434 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
4435 {
4438 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer)));
4440 }
4442 /**
4443 * @brief Indicate on which output the signal is currently applied.
4444 * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
4445 * @note Only significant when the timer operates in push-pull mode.
4446 * @param HRTIMx High Resolution Timer instance
4447 * @param Timer This parameter can be one of the following values:
4448 * @arg @ref LL_HRTIM_TIMER_A
4449 * @arg @ref LL_HRTIM_TIMER_B
4450 * @arg @ref LL_HRTIM_TIMER_C
4451 * @arg @ref LL_HRTIM_TIMER_D
4452 * @arg @ref LL_HRTIM_TIMER_E
4453 * @retval CPPSTAT This parameter can be one of the following values:
4454 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
4455 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
4456 */
4457 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4458 {
4460 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
4463 }
4465 /**
4466 * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
4467 * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
4468 * @param HRTIMx High Resolution Timer instance
4469 * @param Timer This parameter can be one of the following values:
4470 * @arg @ref LL_HRTIM_TIMER_A
4471 * @arg @ref LL_HRTIM_TIMER_B
4472 * @arg @ref LL_HRTIM_TIMER_C
4473 * @arg @ref LL_HRTIM_TIMER_D
4474 * @arg @ref LL_HRTIM_TIMER_E
4475 * @retval IPPSTAT This parameter can be one of the following values:
4476 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
4477 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
4478 */
4479 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4480 {
4482 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
4485 }
4487 /**
4488 * @brief Set the event filter for a given timer.
4489 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
4490 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
4491 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
4492 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
4493 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
4494 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
4495 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
4496 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
4497 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
4498 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
4499 * @note This function must not be called when the timer counter is enabled.
4500 * @param HRTIMx High Resolution Timer instance
4501 * @param Timer This parameter can be one of the following values:
4502 * @arg @ref LL_HRTIM_TIMER_A
4503 * @arg @ref LL_HRTIM_TIMER_B
4504 * @arg @ref LL_HRTIM_TIMER_C
4505 * @arg @ref LL_HRTIM_TIMER_D
4506 * @arg @ref LL_HRTIM_TIMER_E
4507 * @param Event This parameter can be one of the following values:
4508 * @arg @ref LL_HRTIM_EVENT_1
4509 * @arg @ref LL_HRTIM_EVENT_2
4510 * @arg @ref LL_HRTIM_EVENT_3
4511 * @arg @ref LL_HRTIM_EVENT_4
4512 * @arg @ref LL_HRTIM_EVENT_5
4513 * @arg @ref LL_HRTIM_EVENT_6
4514 * @arg @ref LL_HRTIM_EVENT_7
4515 * @arg @ref LL_HRTIM_EVENT_8
4516 * @arg @ref LL_HRTIM_EVENT_9
4517 * @arg @ref LL_HRTIM_EVENT_10
4518 * @param Filter This parameter can be one of the following values:
4519 * @arg @ref LL_HRTIM_EEFLTR_NONE
4520 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
4521 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
4522 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
4523 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
4524 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
4525 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
4526 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
4527 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
4528 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
4529 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
4530 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
4531 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
4532 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
4533 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
4534 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
4536 * @retval None
4537 */
4538 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
4539 {
4542 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4544 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
4545 }
4547 /**
4548 * @brief Get actual event filter settings for a given timer.
4549 * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
4550 * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
4551 * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
4552 * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
4553 * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
4554 * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
4555 * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
4556 * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
4557 * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
4558 * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
4559 * @param HRTIMx High Resolution Timer instance
4560 * @param Timer This parameter can be one of the following values:
4561 * @arg @ref LL_HRTIM_TIMER_A
4562 * @arg @ref LL_HRTIM_TIMER_B
4563 * @arg @ref LL_HRTIM_TIMER_C
4564 * @arg @ref LL_HRTIM_TIMER_D
4565 * @arg @ref LL_HRTIM_TIMER_E
4566 * @param Event This parameter can be one of the following values:
4567 * @arg @ref LL_HRTIM_EVENT_1
4568 * @arg @ref LL_HRTIM_EVENT_2
4569 * @arg @ref LL_HRTIM_EVENT_3
4570 * @arg @ref LL_HRTIM_EVENT_4
4571 * @arg @ref LL_HRTIM_EVENT_5
4572 * @arg @ref LL_HRTIM_EVENT_6
4573 * @arg @ref LL_HRTIM_EVENT_7
4574 * @arg @ref LL_HRTIM_EVENT_8
4575 * @arg @ref LL_HRTIM_EVENT_9
4576 * @arg @ref LL_HRTIM_EVENT_10
4577 * @retval Filter This parameter can be one of the following values:
4578 * @arg @ref LL_HRTIM_EEFLTR_NONE
4579 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
4580 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
4581 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
4582 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
4583 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
4584 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
4585 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
4586 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
4587 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
4588 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
4589 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
4590 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
4591 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
4592 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
4593 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
4594 */
4595 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
4596 {
4599 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4601 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
4602 }
4604 /**
4605 * @brief Enable or disable event latch mechanism for a given timer.
4606 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4607 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4608 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4609 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4610 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4611 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4612 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4613 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4614 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4615 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
4616 * @note This function must not be called when the timer counter is enabled.
4617 * @param HRTIMx High Resolution Timer instance
4618 * @param Timer This parameter can be one of the following values:
4619 * @arg @ref LL_HRTIM_TIMER_A
4620 * @arg @ref LL_HRTIM_TIMER_B
4621 * @arg @ref LL_HRTIM_TIMER_C
4622 * @arg @ref LL_HRTIM_TIMER_D
4623 * @arg @ref LL_HRTIM_TIMER_E
4624 * @param Event This parameter can be one of the following values:
4625 * @arg @ref LL_HRTIM_EVENT_1
4626 * @arg @ref LL_HRTIM_EVENT_2
4627 * @arg @ref LL_HRTIM_EVENT_3
4628 * @arg @ref LL_HRTIM_EVENT_4
4629 * @arg @ref LL_HRTIM_EVENT_5
4630 * @arg @ref LL_HRTIM_EVENT_6
4631 * @arg @ref LL_HRTIM_EVENT_7
4632 * @arg @ref LL_HRTIM_EVENT_8
4633 * @arg @ref LL_HRTIM_EVENT_9
4634 * @arg @ref LL_HRTIM_EVENT_10
4635 * @param LatchStatus This parameter can be one of the following values:
4636 * @arg @ref LL_HRTIM_EELATCH_DISABLED
4637 * @arg @ref LL_HRTIM_EELATCH_ENABLED
4638 * @retval None
4639 */
4640 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
4642 {
4645 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4647 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
4648 }
4650 /**
4651 * @brief Get actual event latch status for a given timer.
4652 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4653 * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4654 * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4655 * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4656 * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4657 * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4658 * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4659 * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4660 * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4661 * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
4662 * @param HRTIMx High Resolution Timer instance
4663 * @param Timer This parameter can be one of the following values:
4664 * @arg @ref LL_HRTIM_TIMER_A
4665 * @arg @ref LL_HRTIM_TIMER_B
4666 * @arg @ref LL_HRTIM_TIMER_C
4667 * @arg @ref LL_HRTIM_TIMER_D
4668 * @arg @ref LL_HRTIM_TIMER_E
4669 * @param Event This parameter can be one of the following values:
4670 * @arg @ref LL_HRTIM_EVENT_1
4671 * @arg @ref LL_HRTIM_EVENT_2
4672 * @arg @ref LL_HRTIM_EVENT_3
4673 * @arg @ref LL_HRTIM_EVENT_4
4674 * @arg @ref LL_HRTIM_EVENT_5
4675 * @arg @ref LL_HRTIM_EVENT_6
4676 * @arg @ref LL_HRTIM_EVENT_7
4677 * @arg @ref LL_HRTIM_EVENT_8
4678 * @arg @ref LL_HRTIM_EVENT_9
4679 * @arg @ref LL_HRTIM_EVENT_10
4680 * @retval LatchStatus This parameter can be one of the following values:
4681 * @arg @ref LL_HRTIM_EELATCH_DISABLED
4682 * @arg @ref LL_HRTIM_EELATCH_ENABLED
4683 */
4684 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
4685 {
4688 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4690 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
4691 }
4693 /**
4694 * @}
4695 */
4697 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
4698 * @{
4699 */
4701 /**
4702 * @brief Configure the dead time insertion feature for a given timer.
4703 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
4704 * DTxR SDTF LL_HRTIM_DT_Config\n
4705 * DTxR SDRT LL_HRTIM_DT_Config
4706 * @param HRTIMx High Resolution Timer instance
4707 * @param Timer This parameter can be one of the following values:
4708 * @arg @ref LL_HRTIM_TIMER_A
4709 * @arg @ref LL_HRTIM_TIMER_B
4710 * @arg @ref LL_HRTIM_TIMER_C
4711 * @arg @ref LL_HRTIM_TIMER_D
4712 * @arg @ref LL_HRTIM_TIMER_E
4713 * @param Configuration This parameter must be a combination of all the following values:
4714 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
4715 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
4716 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
4717 * @retval None
4718 */
4719 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
4720 {
4722 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4725 }
4727 /**
4728 * @brief Set the deadtime prescaler value.
4729 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
4730 * @param HRTIMx High Resolution Timer instance
4731 * @param Timer This parameter can be one of the following values:
4732 * @arg @ref LL_HRTIM_TIMER_A
4733 * @arg @ref LL_HRTIM_TIMER_B
4734 * @arg @ref LL_HRTIM_TIMER_C
4735 * @arg @ref LL_HRTIM_TIMER_D
4736 * @arg @ref LL_HRTIM_TIMER_E
4737 * @param Prescaler This parameter can be one of the following values:
4738 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
4739 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
4740 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
4741 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
4742 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
4743 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
4744 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
4745 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
4746 * @retval None
4747 */
4748 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
4749 {
4751 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4754 }
4756 /**
4757 * @brief Get actual deadtime prescaler value.
4758 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
4759 * @param HRTIMx High Resolution Timer instance
4760 * @param Timer This parameter can be one of the following values:
4761 * @arg @ref LL_HRTIM_TIMER_A
4762 * @arg @ref LL_HRTIM_TIMER_B
4763 * @arg @ref LL_HRTIM_TIMER_C
4764 * @arg @ref LL_HRTIM_TIMER_D
4765 * @arg @ref LL_HRTIM_TIMER_E
4766 * @retval Prescaler This parameter can be one of the following values:
4767 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
4768 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
4769 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
4770 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
4771 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
4772 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
4773 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
4774 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
4775 */
4777 {
4779 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4782 }
4784 /**
4785 * @brief Set the deadtime rising value.
4786 * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
4787 * @param HRTIMx High Resolution Timer instance
4788 * @param Timer This parameter can be one of the following values:
4789 * @arg @ref LL_HRTIM_TIMER_A
4790 * @arg @ref LL_HRTIM_TIMER_B
4791 * @arg @ref LL_HRTIM_TIMER_C
4792 * @arg @ref LL_HRTIM_TIMER_D
4793 * @arg @ref LL_HRTIM_TIMER_E
4794 * @param RisingValue Value between 0 and 0x1FF
4795 * @retval None
4796 */
4797 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
4798 {
4800 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4803 }
4805 /**
4806 * @brief Get actual deadtime rising value.
4807 * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
4808 * @param HRTIMx High Resolution Timer instance
4809 * @param Timer This parameter can be one of the following values:
4810 * @arg @ref LL_HRTIM_TIMER_A
4811 * @arg @ref LL_HRTIM_TIMER_B
4812 * @arg @ref LL_HRTIM_TIMER_C
4813 * @arg @ref LL_HRTIM_TIMER_D
4814 * @arg @ref LL_HRTIM_TIMER_E
4815 * @retval RisingValue Value between 0 and 0x1FF
4816 */
4818 {
4820 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4823 }
4825 /**
4826 * @brief Set the deadtime sign on rising edge.
4827 * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
4828 * @param HRTIMx High Resolution Timer instance
4829 * @param Timer This parameter can be one of the following values:
4830 * @arg @ref LL_HRTIM_TIMER_A
4831 * @arg @ref LL_HRTIM_TIMER_B
4832 * @arg @ref LL_HRTIM_TIMER_C
4833 * @arg @ref LL_HRTIM_TIMER_D
4834 * @arg @ref LL_HRTIM_TIMER_E
4835 * @param RisingSign This parameter can be one of the following values:
4836 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
4837 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
4838 * @retval None
4839 */
4840 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
4841 {
4843 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4846 }
4848 /**
4849 * @brief Get actual deadtime sign on rising edge.
4850 * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
4851 * @param HRTIMx High Resolution Timer instance
4852 * @param Timer This parameter can be one of the following values:
4853 * @arg @ref LL_HRTIM_TIMER_A
4854 * @arg @ref LL_HRTIM_TIMER_B
4855 * @arg @ref LL_HRTIM_TIMER_C
4856 * @arg @ref LL_HRTIM_TIMER_D
4857 * @arg @ref LL_HRTIM_TIMER_E
4858 * @retval RisingSign This parameter can be one of the following values:
4859 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
4860 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
4861 */
4863 {
4865 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4868 }
4870 /**
4871 * @brief Set the deadime falling value.
4872 * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
4873 * @param HRTIMx High Resolution Timer instance
4874 * @param Timer This parameter can be one of the following values:
4875 * @arg @ref LL_HRTIM_TIMER_A
4876 * @arg @ref LL_HRTIM_TIMER_B
4877 * @arg @ref LL_HRTIM_TIMER_C
4878 * @arg @ref LL_HRTIM_TIMER_D
4879 * @arg @ref LL_HRTIM_TIMER_E
4880 * @param FallingValue Value between 0 and 0x1FF
4881 * @retval None
4882 */
4883 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
4884 {
4886 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4889 }
4891 /**
4892 * @brief Get actual deadtime falling value
4893 * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
4894 * @param HRTIMx High Resolution Timer instance
4895 * @param Timer This parameter can be one of the following values:
4896 * @arg @ref LL_HRTIM_TIMER_A
4897 * @arg @ref LL_HRTIM_TIMER_B
4898 * @arg @ref LL_HRTIM_TIMER_C
4899 * @arg @ref LL_HRTIM_TIMER_D
4900 * @arg @ref LL_HRTIM_TIMER_E
4901 * @retval FallingValue Value between 0 and 0x1FF
4902 */
4904 {
4906 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4909 }
4911 /**
4912 * @brief Set the deadtime sign on falling edge.
4913 * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
4914 * @param HRTIMx High Resolution Timer instance
4915 * @param Timer This parameter can be one of the following values:
4916 * @arg @ref LL_HRTIM_TIMER_A
4917 * @arg @ref LL_HRTIM_TIMER_B
4918 * @arg @ref LL_HRTIM_TIMER_C
4919 * @arg @ref LL_HRTIM_TIMER_D
4920 * @arg @ref LL_HRTIM_TIMER_E
4921 * @param FallingSign This parameter can be one of the following values:
4922 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
4923 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
4924 * @retval None
4925 */
4926 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
4927 {
4929 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4932 }
4934 /**
4935 * @brief Get actual deadtime sign on falling edge.
4936 * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
4937 * @param HRTIMx High Resolution Timer instance
4938 * @param Timer This parameter can be one of the following values:
4939 * @arg @ref LL_HRTIM_TIMER_A
4940 * @arg @ref LL_HRTIM_TIMER_B
4941 * @arg @ref LL_HRTIM_TIMER_C
4942 * @arg @ref LL_HRTIM_TIMER_D
4943 * @arg @ref LL_HRTIM_TIMER_E
4944 * @retval FallingSign This parameter can be one of the following values:
4945 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
4946 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
4947 */
4949 {
4951 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4954 }
4956 /**
4957 * @brief Lock the deadtime value and sign on rising edge.
4958 * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
4959 * @param HRTIMx High Resolution Timer instance
4960 * @param Timer This parameter can be one of the following values:
4961 * @arg @ref LL_HRTIM_TIMER_A
4962 * @arg @ref LL_HRTIM_TIMER_B
4963 * @arg @ref LL_HRTIM_TIMER_C
4964 * @arg @ref LL_HRTIM_TIMER_D
4965 * @arg @ref LL_HRTIM_TIMER_E
4966 * @retval None
4967 */
4969 {
4971 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4974 }
4976 /**
4977 * @brief Lock the deadtime sign on rising edge.
4978 * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
4979 * @param HRTIMx High Resolution Timer instance
4980 * @param Timer This parameter can be one of the following values:
4981 * @arg @ref LL_HRTIM_TIMER_A
4982 * @arg @ref LL_HRTIM_TIMER_B
4983 * @arg @ref LL_HRTIM_TIMER_C
4984 * @arg @ref LL_HRTIM_TIMER_D
4985 * @arg @ref LL_HRTIM_TIMER_E
4986 * @retval None
4987 */
4989 {
4991 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4994 }
4996 /**
4997 * @brief Lock the deadtime value and sign on falling edge.
4998 * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
4999 * @param HRTIMx High Resolution Timer instance
5000 * @param Timer This parameter can be one of the following values:
5001 * @arg @ref LL_HRTIM_TIMER_A
5002 * @arg @ref LL_HRTIM_TIMER_B
5003 * @arg @ref LL_HRTIM_TIMER_C
5004 * @arg @ref LL_HRTIM_TIMER_D
5005 * @arg @ref LL_HRTIM_TIMER_E
5006 * @retval None
5007 */
5009 {
5011 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
5014 }
5016 /**
5017 * @brief Lock the deadtime sign on falling edge.
5018 * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
5019 * @param HRTIMx High Resolution Timer instance
5020 * @param Timer This parameter can be one of the following values:
5021 * @arg @ref LL_HRTIM_TIMER_A
5022 * @arg @ref LL_HRTIM_TIMER_B
5023 * @arg @ref LL_HRTIM_TIMER_C
5024 * @arg @ref LL_HRTIM_TIMER_D
5025 * @arg @ref LL_HRTIM_TIMER_E
5026 * @retval None
5027 */
5029 {
5031 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
5034 }
5036 /**
5037 * @}
5038 */
5040 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
5041 * @{
5042 */
5044 /**
5045 * @brief Configure the chopper stage for a given timer.
5046 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
5047 * CHPxR CARDTY LL_HRTIM_CHP_Config\n
5048 * CHPxR STRTPW LL_HRTIM_CHP_Config
5049 * @note This function must not be called if the chopper mode is already
5050 * enabled for one of the timer outputs.
5051 * @param HRTIMx High Resolution Timer instance
5052 * @param Timer This parameter can be one of the following values:
5053 * @arg @ref LL_HRTIM_TIMER_A
5054 * @arg @ref LL_HRTIM_TIMER_B
5055 * @arg @ref LL_HRTIM_TIMER_C
5056 * @arg @ref LL_HRTIM_TIMER_D
5057 * @arg @ref LL_HRTIM_TIMER_E
5058 * @param Configuration This parameter must be a combination of all the following values:
5059 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
5060 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
5061 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
5062 * @retval None
5063 */
5064 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
5065 {
5067 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5070 }
5072 /**
5073 * @brief Set prescaler determining the carrier frequency to be added on top
5074 * of the timer output signals when chopper mode is enabled.
5075 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
5076 * @note This function must not be called if the chopper mode is already
5077 * enabled for one of the timer outputs.
5078 * @param HRTIMx High Resolution Timer instance
5079 * @param Timer This parameter can be one of the following values:
5080 * @arg @ref LL_HRTIM_TIMER_A
5081 * @arg @ref LL_HRTIM_TIMER_B
5082 * @arg @ref LL_HRTIM_TIMER_C
5083 * @arg @ref LL_HRTIM_TIMER_D
5084 * @arg @ref LL_HRTIM_TIMER_E
5085 * @param Prescaler This parameter can be one of the following values:
5086 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
5087 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
5088 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
5089 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
5090 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
5091 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
5092 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
5093 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
5094 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
5095 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
5096 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
5097 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
5098 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
5099 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
5100 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
5101 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
5102 * @retval None
5103 */
5104 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
5105 {
5107 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5110 }
5112 /**
5113 * @brief Get actual chopper stage prescaler value.
5114 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
5115 * @param HRTIMx High Resolution Timer instance
5116 * @param Timer This parameter can be one of the following values:
5117 * @arg @ref LL_HRTIM_TIMER_A
5118 * @arg @ref LL_HRTIM_TIMER_B
5119 * @arg @ref LL_HRTIM_TIMER_C
5120 * @arg @ref LL_HRTIM_TIMER_D
5121 * @arg @ref LL_HRTIM_TIMER_E
5122 * @retval Prescaler This parameter can be one of the following values:
5123 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
5124 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
5125 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
5126 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
5127 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
5128 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
5129 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
5130 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
5131 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
5132 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
5133 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
5134 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
5135 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
5136 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
5137 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
5138 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
5139 */
5141 {
5143 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5146 }
5148 /**
5149 * @brief Set the chopper duty cycle.
5150 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
5151 * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
5152 * @note This function must not be called if the chopper mode is already
5153 * enabled for one of the timer outputs.
5154 * @param HRTIMx High Resolution Timer instance
5155 * @param Timer This parameter can be one of the following values:
5156 * @arg @ref LL_HRTIM_TIMER_A
5157 * @arg @ref LL_HRTIM_TIMER_B
5158 * @arg @ref LL_HRTIM_TIMER_C
5159 * @arg @ref LL_HRTIM_TIMER_D
5160 * @arg @ref LL_HRTIM_TIMER_E
5161 * @param DutyCycle This parameter can be one of the following values:
5162 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
5163 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
5164 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
5165 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
5166 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
5167 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
5168 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
5169 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
5170 * @retval None
5171 */
5172 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
5173 {
5175 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5178 }
5180 /**
5181 * @brief Get actual chopper duty cycle.
5182 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
5183 * @param HRTIMx High Resolution Timer instance
5184 * @param Timer This parameter can be one of the following values:
5185 * @arg @ref LL_HRTIM_TIMER_A
5186 * @arg @ref LL_HRTIM_TIMER_B
5187 * @arg @ref LL_HRTIM_TIMER_C
5188 * @arg @ref LL_HRTIM_TIMER_D
5189 * @arg @ref LL_HRTIM_TIMER_E
5190 * @retval DutyCycle This parameter can be one of the following values:
5191 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
5192 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
5193 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
5194 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
5195 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
5196 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
5197 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
5198 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
5199 */
5201 {
5203 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5206 }
5208 /**
5209 * @brief Set the start pulse width.
5210 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
5211 * @note This function must not be called if the chopper mode is already
5212 * enabled for one of the timer outputs.
5213 * @param HRTIMx High Resolution Timer instance
5214 * @param Timer This parameter can be one of the following values:
5215 * @arg @ref LL_HRTIM_TIMER_A
5216 * @arg @ref LL_HRTIM_TIMER_B
5217 * @arg @ref LL_HRTIM_TIMER_C
5218 * @arg @ref LL_HRTIM_TIMER_D
5219 * @arg @ref LL_HRTIM_TIMER_E
5220 * @param PulseWidth This parameter can be one of the following values:
5221 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
5222 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
5223 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
5224 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
5225 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
5226 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
5227 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
5228 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
5229 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
5230 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
5231 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
5232 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
5233 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
5234 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
5235 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
5236 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
5237 * @retval None
5238 */
5239 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
5240 {
5242 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5245 }
5247 /**
5248 * @brief Get actual start pulse width.
5249 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
5250 * @param HRTIMx High Resolution Timer instance
5251 * @param Timer This parameter can be one of the following values:
5252 * @arg @ref LL_HRTIM_TIMER_A
5253 * @arg @ref LL_HRTIM_TIMER_B
5254 * @arg @ref LL_HRTIM_TIMER_C
5255 * @arg @ref LL_HRTIM_TIMER_D
5256 * @arg @ref LL_HRTIM_TIMER_E
5257 * @retval PulseWidth This parameter can be one of the following values:
5258 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
5259 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
5260 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
5261 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
5262 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
5263 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
5264 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
5265 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
5266 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
5267 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
5268 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
5269 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
5270 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
5271 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
5272 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
5273 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
5274 */
5276 {
5278 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5281 }
5283 /**
5284 * @}
5285 */
5287 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management
5288 * @{
5289 */
5291 /**
5292 * @brief Set the timer output set source.
5293 * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
5294 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
5295 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
5296 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5297 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5298 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5299 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5300 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
5301 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5302 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5303 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5304 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5305 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5306 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5307 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5308 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5309 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5310 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5311 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5312 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5313 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5314 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5315 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5316 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5317 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5318 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5319 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5320 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5321 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5322 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5323 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
5324 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
5325 * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
5326 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
5327 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
5328 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5329 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5330 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5331 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5332 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
5333 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5334 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5335 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5336 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5337 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5338 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5339 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5340 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5341 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5342 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5343 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5344 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5345 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5346 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5347 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5348 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5349 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5350 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5351 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5352 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5353 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5354 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5355 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
5356 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
5357 * @param HRTIMx High Resolution Timer instance
5358 * @param Output This parameter can be one of the following values:
5359 * @arg @ref LL_HRTIM_OUTPUT_TA1
5360 * @arg @ref LL_HRTIM_OUTPUT_TA2
5361 * @arg @ref LL_HRTIM_OUTPUT_TB1
5362 * @arg @ref LL_HRTIM_OUTPUT_TB2
5363 * @arg @ref LL_HRTIM_OUTPUT_TC1
5364 * @arg @ref LL_HRTIM_OUTPUT_TC2
5365 * @arg @ref LL_HRTIM_OUTPUT_TD1
5366 * @arg @ref LL_HRTIM_OUTPUT_TD2
5367 * @arg @ref LL_HRTIM_OUTPUT_TE1
5368 * @arg @ref LL_HRTIM_OUTPUT_TE2
5369 * @param SetSrc This parameter can be a combination of the following values:
5370 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5371 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5372 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5373 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5374 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5375 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5376 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5377 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5378 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5379 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5380 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5381 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5382 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5383 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5384 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5385 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5386 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5387 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5388 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5389 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5390 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5391 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5392 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5393 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5394 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5395 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5396 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5397 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5398 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5399 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5400 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5401 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5402 * @retval None
5403 */
5404 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
5405 {
5406 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5407 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
5410 }
5412 /**
5413 * @brief Get the timer output set source.
5414 * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
5415 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
5416 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
5417 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5418 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5419 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5420 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5421 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
5422 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5423 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5424 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5425 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5426 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5427 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5428 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5429 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5430 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5431 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5432 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5433 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5434 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5435 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5436 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5437 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5438 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5439 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5440 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5441 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5442 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5443 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5444 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
5445 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
5446 * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
5447 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
5448 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
5449 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5450 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5451 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5452 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5453 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
5454 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5455 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5456 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5457 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5458 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5459 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5460 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5461 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5462 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5463 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5464 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5465 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5466 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5467 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5468 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5469 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5470 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5471 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5472 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5473 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5474 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5475 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5476 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
5477 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
5478 * @param HRTIMx High Resolution Timer instance
5479 * @param Output This parameter can be one of the following values:
5480 * @arg @ref LL_HRTIM_OUTPUT_TA1
5481 * @arg @ref LL_HRTIM_OUTPUT_TA2
5482 * @arg @ref LL_HRTIM_OUTPUT_TB1
5483 * @arg @ref LL_HRTIM_OUTPUT_TB2
5484 * @arg @ref LL_HRTIM_OUTPUT_TC1
5485 * @arg @ref LL_HRTIM_OUTPUT_TC2
5486 * @arg @ref LL_HRTIM_OUTPUT_TD1
5487 * @arg @ref LL_HRTIM_OUTPUT_TD2
5488 * @arg @ref LL_HRTIM_OUTPUT_TE1
5489 * @arg @ref LL_HRTIM_OUTPUT_TE2
5490 * @retval SetSrc This parameter can be a combination of the following values:
5491 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5492 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5493 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5494 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5495 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5496 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5497 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5498 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5499 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5500 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5501 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5502 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5503 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5504 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5505 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5506 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5507 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5508 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5509 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5510 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5511 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5512 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5513 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5514 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5515 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5516 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5517 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5518 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5519 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5520 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5521 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5522 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5523 */
5525 {
5526 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5527 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
5530 }
5532 /**
5533 * @brief Set the timer output reset source.
5534 * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
5535 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
5536 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
5537 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5538 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5539 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5540 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5541 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
5542 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5543 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5544 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5545 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5546 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5547 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5548 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5549 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5550 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5551 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5552 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5553 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5554 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5555 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5556 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5557 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5558 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5559 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5560 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5561 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5562 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5563 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5564 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
5565 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
5566 * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
5567 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
5568 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
5569 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5570 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5571 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5572 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5573 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
5574 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5575 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5576 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5577 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5578 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5579 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5580 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5581 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5582 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5583 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5584 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5585 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5586 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5587 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5588 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5589 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5590 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5591 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5592 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5593 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5594 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5595 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5596 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
5597 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
5598 * @param HRTIMx High Resolution Timer instance
5599 * @param Output This parameter can be one of the following values:
5600 * @arg @ref LL_HRTIM_OUTPUT_TA1
5601 * @arg @ref LL_HRTIM_OUTPUT_TA2
5602 * @arg @ref LL_HRTIM_OUTPUT_TB1
5603 * @arg @ref LL_HRTIM_OUTPUT_TB2
5604 * @arg @ref LL_HRTIM_OUTPUT_TC1
5605 * @arg @ref LL_HRTIM_OUTPUT_TC2
5606 * @arg @ref LL_HRTIM_OUTPUT_TD1
5607 * @arg @ref LL_HRTIM_OUTPUT_TD2
5608 * @arg @ref LL_HRTIM_OUTPUT_TE1
5609 * @arg @ref LL_HRTIM_OUTPUT_TE2
5610 * @param ResetSrc This parameter can be a combination of the following values:
5611 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5612 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5613 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5614 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5615 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5616 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5617 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5618 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5619 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5620 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5621 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5622 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5623 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5624 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5625 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5626 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5627 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5628 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5629 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5630 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5631 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5632 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5633 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5634 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5635 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5636 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5637 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5638 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5639 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5640 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5641 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5642 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5643 * @retval None
5644 */
5645 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
5646 {
5647 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5648 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
5651 }
5653 /**
5654 * @brief Get the timer output set source.
5655 * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
5656 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
5657 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
5658 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5659 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5660 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5661 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5662 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
5663 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5664 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5665 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5666 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5667 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5668 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5669 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5670 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5671 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5672 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5673 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5674 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5675 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5676 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5677 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5678 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5679 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5680 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5681 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5682 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5683 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5684 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5685 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
5686 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
5687 * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
5688 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
5689 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
5690 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5691 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5692 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5693 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5694 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
5695 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5696 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5697 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5698 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5699 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5700 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5701 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5702 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5703 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5704 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5705 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5706 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5707 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5708 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5709 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5710 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5711 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5712 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5713 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5714 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5715 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5716 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5717 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
5718 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
5719 * @param HRTIMx High Resolution Timer instance
5720 * @param Output This parameter can be one of the following values:
5721 * @arg @ref LL_HRTIM_OUTPUT_TA1
5722 * @arg @ref LL_HRTIM_OUTPUT_TA2
5723 * @arg @ref LL_HRTIM_OUTPUT_TB1
5724 * @arg @ref LL_HRTIM_OUTPUT_TB2
5725 * @arg @ref LL_HRTIM_OUTPUT_TC1
5726 * @arg @ref LL_HRTIM_OUTPUT_TC2
5727 * @arg @ref LL_HRTIM_OUTPUT_TD1
5728 * @arg @ref LL_HRTIM_OUTPUT_TD2
5729 * @arg @ref LL_HRTIM_OUTPUT_TE1
5730 * @arg @ref LL_HRTIM_OUTPUT_TE2
5731 * @retval ResetSrc This parameter can be a combination of the following values:
5732 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5733 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5734 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5735 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5736 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5737 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5738 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5739 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5740 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5741 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5742 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5743 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5744 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5745 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5746 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5747 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5748 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5749 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5750 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5751 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5752 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5753 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5754 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5755 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5756 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5757 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5758 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5759 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5760 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5761 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5762 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5763 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5764 */
5765 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
5766 {
5767 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5768 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
5771 }
5773 /**
5774 * @brief Configure a timer output.
5775 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
5776 * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
5777 * OUTxR IDLES1 LL_HRTIM_OUT_Config\n
5778 * OUTxR FAULT1 LL_HRTIM_OUT_Config\n
5779 * OUTxR CHP1 LL_HRTIM_OUT_Config\n
5780 * OUTxR DIDL1 LL_HRTIM_OUT_Config\n
5781 * OUTxR POL2 LL_HRTIM_OUT_Config\n
5782 * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
5783 * OUTxR IDLES2 LL_HRTIM_OUT_Config\n
5784 * OUTxR FAULT2 LL_HRTIM_OUT_Config\n
5785 * OUTxR CHP2 LL_HRTIM_OUT_Config\n
5786 * OUTxR DIDL2 LL_HRTIM_OUT_Config
5787 * @param HRTIMx High Resolution Timer instance
5788 * @param Output This parameter can be one of the following values:
5789 * @arg @ref LL_HRTIM_OUTPUT_TA1
5790 * @arg @ref LL_HRTIM_OUTPUT_TA2
5791 * @arg @ref LL_HRTIM_OUTPUT_TB1
5792 * @arg @ref LL_HRTIM_OUTPUT_TB2
5793 * @arg @ref LL_HRTIM_OUTPUT_TC1
5794 * @arg @ref LL_HRTIM_OUTPUT_TC2
5795 * @arg @ref LL_HRTIM_OUTPUT_TD1
5796 * @arg @ref LL_HRTIM_OUTPUT_TD2
5797 * @arg @ref LL_HRTIM_OUTPUT_TE1
5798 * @arg @ref LL_HRTIM_OUTPUT_TE2
5799 * @param Configuration This parameter must be a combination of all the following values:
5800 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
5801 * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
5802 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
5803 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
5804 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
5805 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
5806 * @retval None
5807 */
5808 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
5809 {
5810 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5811 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5815 }
5817 /**
5818 * @brief Set the polarity of a timer output.
5819 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
5820 * OUTxR POL2 LL_HRTIM_OUT_SetPolarity
5821 * @param HRTIMx High Resolution Timer instance
5822 * @param Output This parameter can be one of the following values:
5823 * @arg @ref LL_HRTIM_OUTPUT_TA1
5824 * @arg @ref LL_HRTIM_OUTPUT_TA2
5825 * @arg @ref LL_HRTIM_OUTPUT_TB1
5826 * @arg @ref LL_HRTIM_OUTPUT_TB2
5827 * @arg @ref LL_HRTIM_OUTPUT_TC1
5828 * @arg @ref LL_HRTIM_OUTPUT_TC2
5829 * @arg @ref LL_HRTIM_OUTPUT_TD1
5830 * @arg @ref LL_HRTIM_OUTPUT_TD2
5831 * @arg @ref LL_HRTIM_OUTPUT_TE1
5832 * @arg @ref LL_HRTIM_OUTPUT_TE2
5833 * @param Polarity This parameter can be one of the following values:
5834 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
5835 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
5836 * @retval None
5837 */
5838 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
5839 {
5840 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5841 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5843 MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
5844 }
5846 /**
5847 * @brief Get actual polarity of the timer output.
5848 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
5849 * OUTxR POL2 LL_HRTIM_OUT_GetPolarity
5850 * @param HRTIMx High Resolution Timer instance
5851 * @param Output This parameter can be one of the following values:
5852 * @arg @ref LL_HRTIM_OUTPUT_TA1
5853 * @arg @ref LL_HRTIM_OUTPUT_TA2
5854 * @arg @ref LL_HRTIM_OUTPUT_TB1
5855 * @arg @ref LL_HRTIM_OUTPUT_TB2
5856 * @arg @ref LL_HRTIM_OUTPUT_TC1
5857 * @arg @ref LL_HRTIM_OUTPUT_TC2
5858 * @arg @ref LL_HRTIM_OUTPUT_TD1
5859 * @arg @ref LL_HRTIM_OUTPUT_TD2
5860 * @arg @ref LL_HRTIM_OUTPUT_TE1
5861 * @arg @ref LL_HRTIM_OUTPUT_TE2
5862 * @retval Polarity This parameter can be one of the following values:
5863 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
5864 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
5865 */
5867 {
5868 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5869 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5871 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
5872 }
5874 /**
5875 * @brief Set the output IDLE mode.
5876 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
5877 * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
5878 * @note This function must not be called when the burst mode is active
5879 * @param HRTIMx High Resolution Timer instance
5880 * @param Output This parameter can be one of the following values:
5881 * @arg @ref LL_HRTIM_OUTPUT_TA1
5882 * @arg @ref LL_HRTIM_OUTPUT_TA2
5883 * @arg @ref LL_HRTIM_OUTPUT_TB1
5884 * @arg @ref LL_HRTIM_OUTPUT_TB2
5885 * @arg @ref LL_HRTIM_OUTPUT_TC1
5886 * @arg @ref LL_HRTIM_OUTPUT_TC2
5887 * @arg @ref LL_HRTIM_OUTPUT_TD1
5888 * @arg @ref LL_HRTIM_OUTPUT_TD2
5889 * @arg @ref LL_HRTIM_OUTPUT_TE1
5890 * @arg @ref LL_HRTIM_OUTPUT_TE2
5891 * @param IdleMode This parameter can be one of the following values:
5892 * @arg @ref LL_HRTIM_OUT_NO_IDLE
5893 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
5894 * @retval None
5895 */
5896 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
5897 {
5898 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5899 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5901 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
5902 }
5904 /**
5905 * @brief Get actual output IDLE mode.
5906 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
5907 * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
5908 * @param HRTIMx High Resolution Timer instance
5909 * @param Output This parameter can be one of the following values:
5910 * @arg @ref LL_HRTIM_OUTPUT_TA1
5911 * @arg @ref LL_HRTIM_OUTPUT_TA2
5912 * @arg @ref LL_HRTIM_OUTPUT_TB1
5913 * @arg @ref LL_HRTIM_OUTPUT_TB2
5914 * @arg @ref LL_HRTIM_OUTPUT_TC1
5915 * @arg @ref LL_HRTIM_OUTPUT_TC2
5916 * @arg @ref LL_HRTIM_OUTPUT_TD1
5917 * @arg @ref LL_HRTIM_OUTPUT_TD2
5918 * @arg @ref LL_HRTIM_OUTPUT_TE1
5919 * @arg @ref LL_HRTIM_OUTPUT_TE2
5920 * @retval IdleMode This parameter can be one of the following values:
5921 * @arg @ref LL_HRTIM_OUT_NO_IDLE
5922 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
5923 */
5925 {
5926 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5927 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5929 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
5930 }
5932 /**
5933 * @brief Set the output IDLE level.
5934 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
5935 * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
5936 * @note This function must be called prior enabling the timer.
5937 * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
5938 * @param HRTIMx High Resolution Timer instance
5939 * @param Output This parameter can be one of the following values:
5940 * @arg @ref LL_HRTIM_OUTPUT_TA1
5941 * @arg @ref LL_HRTIM_OUTPUT_TA2
5942 * @arg @ref LL_HRTIM_OUTPUT_TB1
5943 * @arg @ref LL_HRTIM_OUTPUT_TB2
5944 * @arg @ref LL_HRTIM_OUTPUT_TC1
5945 * @arg @ref LL_HRTIM_OUTPUT_TC2
5946 * @arg @ref LL_HRTIM_OUTPUT_TD1
5947 * @arg @ref LL_HRTIM_OUTPUT_TD2
5948 * @arg @ref LL_HRTIM_OUTPUT_TE1
5949 * @arg @ref LL_HRTIM_OUTPUT_TE2
5950 * @param IdleLevel This parameter can be one of the following values:
5951 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
5952 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
5953 * @retval None
5954 */
5955 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
5956 {
5957 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5958 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5960 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
5961 }
5963 /**
5964 * @brief Get actual output IDLE level.
5965 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
5966 * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
5967 * @param HRTIMx High Resolution Timer instance
5968 * @param Output This parameter can be one of the following values:
5969 * @arg @ref LL_HRTIM_OUTPUT_TA1
5970 * @arg @ref LL_HRTIM_OUTPUT_TA2
5971 * @arg @ref LL_HRTIM_OUTPUT_TB1
5972 * @arg @ref LL_HRTIM_OUTPUT_TB2
5973 * @arg @ref LL_HRTIM_OUTPUT_TC1
5974 * @arg @ref LL_HRTIM_OUTPUT_TC2
5975 * @arg @ref LL_HRTIM_OUTPUT_TD1
5976 * @arg @ref LL_HRTIM_OUTPUT_TD2
5977 * @arg @ref LL_HRTIM_OUTPUT_TE1
5978 * @arg @ref LL_HRTIM_OUTPUT_TE2
5979 * @retval IdleLevel This parameter can be one of the following values:
5980 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
5981 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
5982 */
5984 {
5985 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5986 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5988 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
5989 }
5991 /**
5992 * @brief Set the output FAULT state.
5993 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
5994 * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
5995 * @note This function must not called when the timer is enabled and a fault
5996 * channel is enabled at timer level.
5997 * @param HRTIMx High Resolution Timer instance
5998 * @param Output This parameter can be one of the following values:
5999 * @arg @ref LL_HRTIM_OUTPUT_TA1
6000 * @arg @ref LL_HRTIM_OUTPUT_TA2
6001 * @arg @ref LL_HRTIM_OUTPUT_TB1
6002 * @arg @ref LL_HRTIM_OUTPUT_TB2
6003 * @arg @ref LL_HRTIM_OUTPUT_TC1
6004 * @arg @ref LL_HRTIM_OUTPUT_TC2
6005 * @arg @ref LL_HRTIM_OUTPUT_TD1
6006 * @arg @ref LL_HRTIM_OUTPUT_TD2
6007 * @arg @ref LL_HRTIM_OUTPUT_TE1
6008 * @arg @ref LL_HRTIM_OUTPUT_TE2
6009 * @param FaultState This parameter can be one of the following values:
6010 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
6011 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
6012 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
6013 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
6014 * @retval None
6015 */
6016 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
6017 {
6018 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6019 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6021 MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
6022 }
6024 /**
6025 * @brief Get actual FAULT state.
6026 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
6027 * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
6028 * @param HRTIMx High Resolution Timer instance
6029 * @param Output This parameter can be one of the following values:
6030 * @arg @ref LL_HRTIM_OUTPUT_TA1
6031 * @arg @ref LL_HRTIM_OUTPUT_TA2
6032 * @arg @ref LL_HRTIM_OUTPUT_TB1
6033 * @arg @ref LL_HRTIM_OUTPUT_TB2
6034 * @arg @ref LL_HRTIM_OUTPUT_TC1
6035 * @arg @ref LL_HRTIM_OUTPUT_TC2
6036 * @arg @ref LL_HRTIM_OUTPUT_TD1
6037 * @arg @ref LL_HRTIM_OUTPUT_TD2
6038 * @arg @ref LL_HRTIM_OUTPUT_TE1
6039 * @arg @ref LL_HRTIM_OUTPUT_TE2
6040 * @retval FaultState This parameter can be one of the following values:
6041 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
6042 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
6043 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
6044 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
6045 */
6047 {
6048 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6049 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6051 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6052 }
6054 /**
6055 * @brief Set the output chopper mode.
6056 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
6057 * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
6058 * @note This function must not called when the timer is enabled.
6059 * @param HRTIMx High Resolution Timer instance
6060 * @param Output This parameter can be one of the following values:
6061 * @arg @ref LL_HRTIM_OUTPUT_TA1
6062 * @arg @ref LL_HRTIM_OUTPUT_TA2
6063 * @arg @ref LL_HRTIM_OUTPUT_TB1
6064 * @arg @ref LL_HRTIM_OUTPUT_TB2
6065 * @arg @ref LL_HRTIM_OUTPUT_TC1
6066 * @arg @ref LL_HRTIM_OUTPUT_TC2
6067 * @arg @ref LL_HRTIM_OUTPUT_TD1
6068 * @arg @ref LL_HRTIM_OUTPUT_TD2
6069 * @arg @ref LL_HRTIM_OUTPUT_TE1
6070 * @arg @ref LL_HRTIM_OUTPUT_TE2
6071 * @param ChopperMode This parameter can be one of the following values:
6072 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
6073 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
6074 * @retval None
6075 */
6076 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
6077 {
6078 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6079 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6081 MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
6082 }
6084 /**
6085 * @brief Get actual output chopper mode
6086 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
6087 * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
6088 * @param HRTIMx High Resolution Timer instance
6089 * @param Output This parameter can be one of the following values:
6090 * @arg @ref LL_HRTIM_OUTPUT_TA1
6091 * @arg @ref LL_HRTIM_OUTPUT_TA2
6092 * @arg @ref LL_HRTIM_OUTPUT_TB1
6093 * @arg @ref LL_HRTIM_OUTPUT_TB2
6094 * @arg @ref LL_HRTIM_OUTPUT_TC1
6095 * @arg @ref LL_HRTIM_OUTPUT_TC2
6096 * @arg @ref LL_HRTIM_OUTPUT_TD1
6097 * @arg @ref LL_HRTIM_OUTPUT_TD2
6098 * @arg @ref LL_HRTIM_OUTPUT_TE1
6099 * @arg @ref LL_HRTIM_OUTPUT_TE2
6100 * @retval ChopperMode This parameter can be one of the following values:
6101 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
6102 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
6103 */
6105 {
6106 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6107 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6109 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6110 }
6112 /**
6113 * @brief Set the output burst mode entry mode.
6114 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
6115 * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
6116 * @note This function must not called when the timer is enabled.
6117 * @param HRTIMx High Resolution Timer instance
6118 * @param Output This parameter can be one of the following values:
6119 * @arg @ref LL_HRTIM_OUTPUT_TA1
6120 * @arg @ref LL_HRTIM_OUTPUT_TA2
6121 * @arg @ref LL_HRTIM_OUTPUT_TB1
6122 * @arg @ref LL_HRTIM_OUTPUT_TB2
6123 * @arg @ref LL_HRTIM_OUTPUT_TC1
6124 * @arg @ref LL_HRTIM_OUTPUT_TC2
6125 * @arg @ref LL_HRTIM_OUTPUT_TD1
6126 * @arg @ref LL_HRTIM_OUTPUT_TD2
6127 * @arg @ref LL_HRTIM_OUTPUT_TE1
6128 * @arg @ref LL_HRTIM_OUTPUT_TE2
6129 * @param BMEntryMode This parameter can be one of the following values:
6130 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
6131 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
6132 * @retval None
6133 */
6134 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
6135 {
6136 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6137 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6139 MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
6140 }
6142 /**
6143 * @brief Get actual output burst mode entry mode.
6144 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
6145 * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
6146 * @param HRTIMx High Resolution Timer instance
6147 * @param Output This parameter can be one of the following values:
6148 * @arg @ref LL_HRTIM_OUTPUT_TA1
6149 * @arg @ref LL_HRTIM_OUTPUT_TA2
6150 * @arg @ref LL_HRTIM_OUTPUT_TB1
6151 * @arg @ref LL_HRTIM_OUTPUT_TB2
6152 * @arg @ref LL_HRTIM_OUTPUT_TC1
6153 * @arg @ref LL_HRTIM_OUTPUT_TC2
6154 * @arg @ref LL_HRTIM_OUTPUT_TD1
6155 * @arg @ref LL_HRTIM_OUTPUT_TD2
6156 * @arg @ref LL_HRTIM_OUTPUT_TE1
6157 * @arg @ref LL_HRTIM_OUTPUT_TE2
6158 * @retval BMEntryMode This parameter can be one of the following values:
6159 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
6160 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
6161 */
6163 {
6164 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6165 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6167 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6168 }
6170 /**
6171 * @brief Get the level (active or inactive) of the designated output when the
6172 * delayed protection was triggered.
6173 * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
6174 * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
6175 * @param HRTIMx High Resolution Timer instance
6176 * @param Output This parameter can be one of the following values:
6177 * @arg @ref LL_HRTIM_OUTPUT_TA1
6178 * @arg @ref LL_HRTIM_OUTPUT_TA2
6179 * @arg @ref LL_HRTIM_OUTPUT_TB1
6180 * @arg @ref LL_HRTIM_OUTPUT_TB2
6181 * @arg @ref LL_HRTIM_OUTPUT_TC1
6182 * @arg @ref LL_HRTIM_OUTPUT_TC2
6183 * @arg @ref LL_HRTIM_OUTPUT_TD1
6184 * @arg @ref LL_HRTIM_OUTPUT_TD2
6185 * @arg @ref LL_HRTIM_OUTPUT_TE1
6186 * @arg @ref LL_HRTIM_OUTPUT_TE2
6187 * @retval OutputLevel This parameter can be one of the following values:
6188 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
6189 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
6190 */
6191 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
6192 {
6193 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6194 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
6196 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
6197 HRTIM_TIMISR_O1STAT_Pos);
6198 }
6200 /**
6201 * @brief Force the timer output to its active or inactive level.
6202 * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
6203 * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
6204 * SETx2R SST LL_HRTIM_OUT_ForceLevel\n
6205 * RSTx2R SRT LL_HRTIM_OUT_ForceLevel
6206 * @param HRTIMx High Resolution Timer instance
6207 * @param Output This parameter can be one of the following values:
6208 * @arg @ref LL_HRTIM_OUTPUT_TA1
6209 * @arg @ref LL_HRTIM_OUTPUT_TA2
6210 * @arg @ref LL_HRTIM_OUTPUT_TB1
6211 * @arg @ref LL_HRTIM_OUTPUT_TB2
6212 * @arg @ref LL_HRTIM_OUTPUT_TC1
6213 * @arg @ref LL_HRTIM_OUTPUT_TC2
6214 * @arg @ref LL_HRTIM_OUTPUT_TD1
6215 * @arg @ref LL_HRTIM_OUTPUT_TD2
6216 * @arg @ref LL_HRTIM_OUTPUT_TE1
6217 * @arg @ref LL_HRTIM_OUTPUT_TE2
6218 * @param OutputLevel This parameter can be one of the following values:
6219 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
6220 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
6221 * @retval None
6222 */
6223 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
6224 {
6226 {
6229 };
6231 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6232 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
6235 }
6237 /**
6238 * @brief Get actual output level, before the output stage (chopper, polarity).
6239 * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
6240 * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
6241 * @param HRTIMx High Resolution Timer instance
6242 * @param Output This parameter can be one of the following values:
6243 * @arg @ref LL_HRTIM_OUTPUT_TA1
6244 * @arg @ref LL_HRTIM_OUTPUT_TA2
6245 * @arg @ref LL_HRTIM_OUTPUT_TB1
6246 * @arg @ref LL_HRTIM_OUTPUT_TB2
6247 * @arg @ref LL_HRTIM_OUTPUT_TC1
6248 * @arg @ref LL_HRTIM_OUTPUT_TC2
6249 * @arg @ref LL_HRTIM_OUTPUT_TD1
6250 * @arg @ref LL_HRTIM_OUTPUT_TD2
6251 * @arg @ref LL_HRTIM_OUTPUT_TE1
6252 * @arg @ref LL_HRTIM_OUTPUT_TE2
6253 * @retval OutputLevel This parameter can be one of the following values:
6254 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
6255 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
6256 */
6258 {
6259 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6260 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
6262 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
6263 HRTIM_TIMISR_O1CPY_Pos);
6264 }
6266 /**
6267 * @}
6268 */
6270 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
6271 * @{
6272 */
6274 /**
6275 * @brief Configure external event conditioning.
6276 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
6277 * EECR1 EE1POL LL_HRTIM_EE_Config\n
6278 * EECR1 EE1SNS LL_HRTIM_EE_Config\n
6279 * EECR1 EE1FAST LL_HRTIM_EE_Config\n
6280 * EECR1 EE2SRC LL_HRTIM_EE_Config\n
6281 * EECR1 EE2POL LL_HRTIM_EE_Config\n
6282 * EECR1 EE2SNS LL_HRTIM_EE_Config\n
6283 * EECR1 EE2FAST LL_HRTIM_EE_Config\n
6284 * EECR1 EE3SRC LL_HRTIM_EE_Config\n
6285 * EECR1 EE3POL LL_HRTIM_EE_Config\n
6286 * EECR1 EE3SNS LL_HRTIM_EE_Config\n
6287 * EECR1 EE3FAST LL_HRTIM_EE_Config\n
6288 * EECR1 EE4SRC LL_HRTIM_EE_Config\n
6289 * EECR1 EE4POL LL_HRTIM_EE_Config\n
6290 * EECR1 EE4SNS LL_HRTIM_EE_Config\n
6291 * EECR1 EE4FAST LL_HRTIM_EE_Config\n
6292 * EECR1 EE5SRC LL_HRTIM_EE_Config\n
6293 * EECR1 EE5POL LL_HRTIM_EE_Config\n
6294 * EECR1 EE5SNS LL_HRTIM_EE_Config\n
6295 * EECR1 EE5FAST LL_HRTIM_EE_Config\n
6296 * EECR2 EE6SRC LL_HRTIM_EE_Config\n
6297 * EECR2 EE6POL LL_HRTIM_EE_Config\n
6298 * EECR2 EE6SNS LL_HRTIM_EE_Config\n
6299 * EECR2 EE6FAST LL_HRTIM_EE_Config\n
6300 * EECR2 EE7SRC LL_HRTIM_EE_Config\n
6301 * EECR2 EE7POL LL_HRTIM_EE_Config\n
6302 * EECR2 EE7SNS LL_HRTIM_EE_Config\n
6303 * EECR2 EE7FAST LL_HRTIM_EE_Config\n
6304 * EECR2 EE8SRC LL_HRTIM_EE_Config\n
6305 * EECR2 EE8POL LL_HRTIM_EE_Config\n
6306 * EECR2 EE8SNS LL_HRTIM_EE_Config\n
6307 * EECR2 EE8FAST LL_HRTIM_EE_Config\n
6308 * EECR2 EE9SRC LL_HRTIM_EE_Config\n
6309 * EECR2 EE9POL LL_HRTIM_EE_Config\n
6310 * EECR2 EE9SNS LL_HRTIM_EE_Config\n
6311 * EECR2 EE9FAST LL_HRTIM_EE_Config\n
6312 * EECR2 EE10SRC LL_HRTIM_EE_Config\n
6313 * EECR2 EE10POL LL_HRTIM_EE_Config\n
6314 * EECR2 EE10SNS LL_HRTIM_EE_Config\n
6315 * EECR2 EE10FAST LL_HRTIM_EE_Config
6316 * @note This function must not be called when the timer counter is enabled.
6317 * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
6318 * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
6319 * @param HRTIMx High Resolution Timer instance
6320 * @param Event This parameter can be one of the following values:
6321 * @arg @ref LL_HRTIM_EVENT_1
6322 * @arg @ref LL_HRTIM_EVENT_2
6323 * @arg @ref LL_HRTIM_EVENT_3
6324 * @arg @ref LL_HRTIM_EVENT_4
6325 * @arg @ref LL_HRTIM_EVENT_5
6326 * @arg @ref LL_HRTIM_EVENT_6
6327 * @arg @ref LL_HRTIM_EVENT_7
6328 * @arg @ref LL_HRTIM_EVENT_8
6329 * @arg @ref LL_HRTIM_EVENT_9
6330 * @arg @ref LL_HRTIM_EVENT_10
6331 * @param Configuration This parameter must be a combination of all the following values:
6332 * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
6333 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
6334 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
6335 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
6336 * @retval None
6337 */
6338 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
6339 {
6341 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6345 }
6347 /**
6348 * @brief Set the external event source.
6349 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
6350 * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
6351 * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
6352 * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
6353 * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
6354 * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
6355 * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
6356 * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
6357 * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
6358 * EECR2 EE10SRC LL_HRTIM_EE_SetSrc
6359 * @param HRTIMx High Resolution Timer instance
6360 * @param Event This parameter can be one of the following values:
6361 * @arg @ref LL_HRTIM_EVENT_1
6362 * @arg @ref LL_HRTIM_EVENT_2
6363 * @arg @ref LL_HRTIM_EVENT_3
6364 * @arg @ref LL_HRTIM_EVENT_4
6365 * @arg @ref LL_HRTIM_EVENT_5
6366 * @arg @ref LL_HRTIM_EVENT_6
6367 * @arg @ref LL_HRTIM_EVENT_7
6368 * @arg @ref LL_HRTIM_EVENT_8
6369 * @arg @ref LL_HRTIM_EVENT_9
6370 * @arg @ref LL_HRTIM_EVENT_10
6371 * @param Src This parameter can be one of the following values:
6372 * @arg External event source 1
6373 * @arg External event source 2
6374 * @arg External event source 3
6375 * @arg External event source 4
6376 * @retval None
6377 */
6379 {
6381 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6383 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
6384 }
6386 /**
6387 * @brief Get actual external event source.
6388 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
6389 * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
6390 * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
6391 * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
6392 * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
6393 * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
6394 * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
6395 * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
6396 * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
6397 * EECR2 EE10SRC LL_HRTIM_EE_GetSrc
6398 * @param HRTIMx High Resolution Timer instance
6399 * @param Event This parameter can be one of the following values:
6400 * @arg @ref LL_HRTIM_EVENT_1
6401 * @arg @ref LL_HRTIM_EVENT_2
6402 * @arg @ref LL_HRTIM_EVENT_3
6403 * @arg @ref LL_HRTIM_EVENT_4
6404 * @arg @ref LL_HRTIM_EVENT_5
6405 * @arg @ref LL_HRTIM_EVENT_6
6406 * @arg @ref LL_HRTIM_EVENT_7
6407 * @arg @ref LL_HRTIM_EVENT_8
6408 * @arg @ref LL_HRTIM_EVENT_9
6409 * @arg @ref LL_HRTIM_EVENT_10
6410 * @retval EventSrc This parameter can be one of the following values:
6411 * @arg External event source 1
6412 * @arg External event source 2
6413 * @arg External event source 3
6414 * @arg External event source 4
6415 */
6417 {
6419 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6421 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6422 }
6424 /**
6425 * @brief Set the polarity of an external event.
6426 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
6427 * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
6428 * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
6429 * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
6430 * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
6431 * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
6432 * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
6433 * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
6434 * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
6435 * EECR2 EE10POL LL_HRTIM_EE_SetPolarity
6436 * @note This function must not be called when the timer counter is enabled.
6437 * @note Event polarity is only significant when event detection is level-sensitive.
6438 * @param HRTIMx High Resolution Timer instance
6439 * @param Event This parameter can be one of the following values:
6440 * @arg @ref LL_HRTIM_EVENT_1
6441 * @arg @ref LL_HRTIM_EVENT_2
6442 * @arg @ref LL_HRTIM_EVENT_3
6443 * @arg @ref LL_HRTIM_EVENT_4
6444 * @arg @ref LL_HRTIM_EVENT_5
6445 * @arg @ref LL_HRTIM_EVENT_6
6446 * @arg @ref LL_HRTIM_EVENT_7
6447 * @arg @ref LL_HRTIM_EVENT_8
6448 * @arg @ref LL_HRTIM_EVENT_9
6449 * @arg @ref LL_HRTIM_EVENT_10
6450 * @param Polarity This parameter can be one of the following values:
6451 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
6452 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
6453 * @retval None
6454 */
6455 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
6456 {
6458 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6460 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
6461 }
6463 /**
6464 * @brief Get actual polarity setting of an external event.
6465 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
6466 * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
6467 * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
6468 * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
6469 * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
6470 * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
6471 * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
6472 * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
6473 * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
6474 * EECR2 EE10POL LL_HRTIM_EE_GetPolarity
6475 * @param HRTIMx High Resolution Timer instance
6476 * @param Event This parameter can be one of the following values:
6477 * @arg @ref LL_HRTIM_EVENT_1
6478 * @arg @ref LL_HRTIM_EVENT_2
6479 * @arg @ref LL_HRTIM_EVENT_3
6480 * @arg @ref LL_HRTIM_EVENT_4
6481 * @arg @ref LL_HRTIM_EVENT_5
6482 * @arg @ref LL_HRTIM_EVENT_6
6483 * @arg @ref LL_HRTIM_EVENT_7
6484 * @arg @ref LL_HRTIM_EVENT_8
6485 * @arg @ref LL_HRTIM_EVENT_9
6486 * @arg @ref LL_HRTIM_EVENT_10
6487 * @retval Polarity This parameter can be one of the following values:
6488 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
6489 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
6490 */
6492 {
6494 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6496 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6497 }
6499 /**
6500 * @brief Set the sensitivity of an external event.
6501 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
6502 * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
6503 * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
6504 * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
6505 * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
6506 * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
6507 * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
6508 * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
6509 * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
6510 * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
6511 * @param HRTIMx High Resolution Timer instance
6512 * @param Event This parameter can be one of the following values:
6513 * @arg @ref LL_HRTIM_EVENT_1
6514 * @arg @ref LL_HRTIM_EVENT_2
6515 * @arg @ref LL_HRTIM_EVENT_3
6516 * @arg @ref LL_HRTIM_EVENT_4
6517 * @arg @ref LL_HRTIM_EVENT_5
6518 * @arg @ref LL_HRTIM_EVENT_6
6519 * @arg @ref LL_HRTIM_EVENT_7
6520 * @arg @ref LL_HRTIM_EVENT_8
6521 * @arg @ref LL_HRTIM_EVENT_9
6522 * @arg @ref LL_HRTIM_EVENT_10
6523 * @param Sensitivity This parameter can be one of the following values:
6524 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
6525 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
6526 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
6527 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
6528 * @retval None
6529 */
6531 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
6532 {
6534 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6536 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
6537 }
6539 /**
6540 * @brief Get actual sensitivity setting of an external event.
6541 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
6542 * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
6543 * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
6544 * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
6545 * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
6546 * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
6547 * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
6548 * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
6549 * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
6550 * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
6551 * @param HRTIMx High Resolution Timer instance
6552 * @param Event This parameter can be one of the following values:
6553 * @arg @ref LL_HRTIM_EVENT_1
6554 * @arg @ref LL_HRTIM_EVENT_2
6555 * @arg @ref LL_HRTIM_EVENT_3
6556 * @arg @ref LL_HRTIM_EVENT_4
6557 * @arg @ref LL_HRTIM_EVENT_5
6558 * @arg @ref LL_HRTIM_EVENT_6
6559 * @arg @ref LL_HRTIM_EVENT_7
6560 * @arg @ref LL_HRTIM_EVENT_8
6561 * @arg @ref LL_HRTIM_EVENT_9
6562 * @arg @ref LL_HRTIM_EVENT_10
6563 * @retval Polarity This parameter can be one of the following values:
6564 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
6565 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
6566 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
6567 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
6568 */
6570 {
6572 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6574 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6575 }
6577 /**
6578 * @brief Set the fast mode of an external event.
6579 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
6580 * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
6581 * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
6582 * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
6583 * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
6584 * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
6585 * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
6586 * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
6587 * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
6588 * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
6589 * @note This function must not be called when the timer counter is enabled.
6590 * @param HRTIMx High Resolution Timer instance
6591 * @param Event This parameter can be one of the following values:
6592 * @arg @ref LL_HRTIM_EVENT_1
6593 * @arg @ref LL_HRTIM_EVENT_2
6594 * @arg @ref LL_HRTIM_EVENT_3
6595 * @arg @ref LL_HRTIM_EVENT_4
6596 * @arg @ref LL_HRTIM_EVENT_5
6597 * @param FastMode This parameter can be one of the following values:
6598 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
6599 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
6600 * @retval None
6601 */
6602 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
6603 {
6605 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6607 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
6608 }
6610 /**
6611 * @brief Get actual fast mode setting of an external event.
6612 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
6613 * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
6614 * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
6615 * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
6616 * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
6617 * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
6618 * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
6619 * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
6620 * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
6621 * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
6622 * @param HRTIMx High Resolution Timer instance
6623 * @param Event This parameter can be one of the following values:
6624 * @arg @ref LL_HRTIM_EVENT_1
6625 * @arg @ref LL_HRTIM_EVENT_2
6626 * @arg @ref LL_HRTIM_EVENT_3
6627 * @arg @ref LL_HRTIM_EVENT_4
6628 * @arg @ref LL_HRTIM_EVENT_5
6629 * @retval FastMode This parameter can be one of the following values:
6630 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
6631 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
6632 */
6634 {
6636 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6638 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6639 }
6641 /**
6642 * @brief Set the digital noise filter of a external event.
6643 * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
6644 * EECR3 EE7F LL_HRTIM_EE_SetFilter\n
6645 * EECR3 EE8F LL_HRTIM_EE_SetFilter\n
6646 * EECR3 EE9F LL_HRTIM_EE_SetFilter\n
6647 * EECR3 EE10F LL_HRTIM_EE_SetFilter
6648 * @param HRTIMx High Resolution Timer instance
6649 * @param Event This parameter can be one of the following values:
6650 * @arg @ref LL_HRTIM_EVENT_6
6651 * @arg @ref LL_HRTIM_EVENT_7
6652 * @arg @ref LL_HRTIM_EVENT_8
6653 * @arg @ref LL_HRTIM_EVENT_9
6654 * @arg @ref LL_HRTIM_EVENT_10
6655 * @param Filter This parameter can be one of the following values:
6656 * @arg @ref LL_HRTIM_EE_FILTER_NONE
6657 * @arg @ref LL_HRTIM_EE_FILTER_1
6658 * @arg @ref LL_HRTIM_EE_FILTER_2
6659 * @arg @ref LL_HRTIM_EE_FILTER_3
6660 * @arg @ref LL_HRTIM_EE_FILTER_4
6661 * @arg @ref LL_HRTIM_EE_FILTER_5
6662 * @arg @ref LL_HRTIM_EE_FILTER_6
6663 * @arg @ref LL_HRTIM_EE_FILTER_7
6664 * @arg @ref LL_HRTIM_EE_FILTER_8
6665 * @arg @ref LL_HRTIM_EE_FILTER_9
6666 * @arg @ref LL_HRTIM_EE_FILTER_10
6667 * @arg @ref LL_HRTIM_EE_FILTER_11
6668 * @arg @ref LL_HRTIM_EE_FILTER_12
6669 * @arg @ref LL_HRTIM_EE_FILTER_13
6670 * @arg @ref LL_HRTIM_EE_FILTER_14
6671 * @arg @ref LL_HRTIM_EE_FILTER_15
6672 * @retval None
6673 */
6674 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
6675 {
6679 }
6681 /**
6682 * @brief Get actual digital noise filter setting of a external event.
6683 * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
6684 * EECR3 EE7F LL_HRTIM_EE_GetFilter\n
6685 * EECR3 EE8F LL_HRTIM_EE_GetFilter\n
6686 * EECR3 EE9F LL_HRTIM_EE_GetFilter\n
6687 * EECR3 EE10F LL_HRTIM_EE_GetFilter
6688 * @param HRTIMx High Resolution Timer instance
6689 * @param Event This parameter can be one of the following values:
6690 * @arg @ref LL_HRTIM_EVENT_6
6691 * @arg @ref LL_HRTIM_EVENT_7
6692 * @arg @ref LL_HRTIM_EVENT_8
6693 * @arg @ref LL_HRTIM_EVENT_9
6694 * @arg @ref LL_HRTIM_EVENT_10
6695 * @retval Filter This parameter can be one of the following values:
6696 * @arg @ref LL_HRTIM_EE_FILTER_NONE
6697 * @arg @ref LL_HRTIM_EE_FILTER_1
6698 * @arg @ref LL_HRTIM_EE_FILTER_2
6699 * @arg @ref LL_HRTIM_EE_FILTER_3
6700 * @arg @ref LL_HRTIM_EE_FILTER_4
6701 * @arg @ref LL_HRTIM_EE_FILTER_5
6702 * @arg @ref LL_HRTIM_EE_FILTER_6
6703 * @arg @ref LL_HRTIM_EE_FILTER_7
6704 * @arg @ref LL_HRTIM_EE_FILTER_8
6705 * @arg @ref LL_HRTIM_EE_FILTER_9
6706 * @arg @ref LL_HRTIM_EE_FILTER_10
6707 * @arg @ref LL_HRTIM_EE_FILTER_11
6708 * @arg @ref LL_HRTIM_EE_FILTER_12
6709 * @arg @ref LL_HRTIM_EE_FILTER_13
6710 * @arg @ref LL_HRTIM_EE_FILTER_14
6711 * @arg @ref LL_HRTIM_EE_FILTER_15
6712 */
6714 {
6717 (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6718 }
6720 /**
6721 * @brief Set the external event prescaler.
6722 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
6723 * @param HRTIMx High Resolution Timer instance
6724 * @param Prescaler This parameter can be one of the following values:
6725 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
6726 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
6727 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
6728 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
6729 * @retval None
6730 */
6733 {
6735 }
6737 /**
6738 * @brief Get actual external event prescaler setting.
6739 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
6740 * @param HRTIMx High Resolution Timer instance
6741 * @retval Prescaler This parameter can be one of the following values:
6742 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
6743 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
6744 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
6745 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
6746 */
6749 {
6751 }
6753 /**
6754 * @}
6755 */
6757 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management
6758 * @{
6759 */
6760 /**
6761 * @brief Configure fault signal conditioning Polarity and Source.
6762 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
6763 * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
6764 * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
6765 * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
6766 * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
6767 * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
6768 * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
6769 * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
6770 * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
6771 * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config
6772 * @note This function must not be called when the fault channel is enabled.
6773 * @param HRTIMx High Resolution Timer instance
6774 * @param Fault This parameter can be one of the following values:
6775 * @arg @ref LL_HRTIM_FAULT_1
6776 * @arg @ref LL_HRTIM_FAULT_2
6777 * @arg @ref LL_HRTIM_FAULT_3
6778 * @arg @ref LL_HRTIM_FAULT_4
6779 * @arg @ref LL_HRTIM_FAULT_5
6780 * @param Configuration This parameter must be a combination of all the following values:
6781 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_INTERNAL
6782 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
6783 * @retval None
6784 */
6785 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
6786 {
6788 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6792 }
6794 /**
6795 * @brief Set the source of a fault signal.
6796 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
6797 * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
6798 * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
6799 * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
6800 * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc
6801 * @note This function must not be called when the fault channel is enabled.
6802 * @param HRTIMx High Resolution Timer instance
6803 * @param Fault This parameter can be one of the following values:
6804 * @arg @ref LL_HRTIM_FAULT_1
6805 * @arg @ref LL_HRTIM_FAULT_2
6806 * @arg @ref LL_HRTIM_FAULT_3
6807 * @arg @ref LL_HRTIM_FAULT_4
6808 * @arg @ref LL_HRTIM_FAULT_5
6809 * @param Src This parameter can be one of the following values:
6810 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
6811 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
6812 * @retval None
6813 */
6815 {
6817 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6819 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));
6820 }
6822 /**
6823 * @brief Get actual source of a fault signal.
6824 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
6825 * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
6826 * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
6827 * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
6828 * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc
6829 * @param HRTIMx High Resolution Timer instance
6830 * @param Fault This parameter can be one of the following values:
6831 * @arg @ref LL_HRTIM_FAULT_1
6832 * @arg @ref LL_HRTIM_FAULT_2
6833 * @arg @ref LL_HRTIM_FAULT_3
6834 * @arg @ref LL_HRTIM_FAULT_4
6835 * @arg @ref LL_HRTIM_FAULT_5
6836 * @retval Source This parameter can be one of the following values:
6837 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
6838 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
6839 */
6841 {
6843 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6845 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
6846 }
6848 /**
6849 * @brief Set the polarity of a fault signal.
6850 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
6851 * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
6852 * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
6853 * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
6854 * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity
6855 * @note This function must not be called when the fault channel is enabled.
6856 * @param HRTIMx High Resolution Timer instance
6857 * @param Fault This parameter can be one of the following values:
6858 * @arg @ref LL_HRTIM_FAULT_1
6859 * @arg @ref LL_HRTIM_FAULT_2
6860 * @arg @ref LL_HRTIM_FAULT_3
6861 * @arg @ref LL_HRTIM_FAULT_4
6862 * @arg @ref LL_HRTIM_FAULT_5
6863 * @param Polarity This parameter can be one of the following values:
6864 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
6865 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
6866 * @retval None
6867 */
6868 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
6869 {
6871 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6873 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));
6874 }
6876 /**
6877 * @brief Get actual polarity of a fault signal.
6878 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
6879 * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
6880 * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
6881 * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
6882 * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity
6883 * @param HRTIMx High Resolution Timer instance
6884 * @param Fault This parameter can be one of the following values:
6885 * @arg @ref LL_HRTIM_FAULT_1
6886 * @arg @ref LL_HRTIM_FAULT_2
6887 * @arg @ref LL_HRTIM_FAULT_3
6888 * @arg @ref LL_HRTIM_FAULT_4
6889 * @arg @ref LL_HRTIM_FAULT_5
6890 * @retval Polarity This parameter can be one of the following values:
6891 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
6892 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
6893 */
6895 {
6897 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6899 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
6900 }
6902 /**
6903 * @brief Set the digital noise filter of a fault signal.
6904 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
6905 * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
6906 * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
6907 * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
6908 * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter
6909 * @note This function must not be called when the fault channel is enabled.
6910 * @param HRTIMx High Resolution Timer instance
6911 * @param Fault This parameter can be one of the following values:
6912 * @arg @ref LL_HRTIM_FAULT_1
6913 * @arg @ref LL_HRTIM_FAULT_2
6914 * @arg @ref LL_HRTIM_FAULT_3
6915 * @arg @ref LL_HRTIM_FAULT_4
6916 * @arg @ref LL_HRTIM_FAULT_5
6917 * @param Filter This parameter can be one of the following values:
6918 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
6919 * @arg @ref LL_HRTIM_FLT_FILTER_1
6920 * @arg @ref LL_HRTIM_FLT_FILTER_2
6921 * @arg @ref LL_HRTIM_FLT_FILTER_3
6922 * @arg @ref LL_HRTIM_FLT_FILTER_4
6923 * @arg @ref LL_HRTIM_FLT_FILTER_5
6924 * @arg @ref LL_HRTIM_FLT_FILTER_6
6925 * @arg @ref LL_HRTIM_FLT_FILTER_7
6926 * @arg @ref LL_HRTIM_FLT_FILTER_8
6927 * @arg @ref LL_HRTIM_FLT_FILTER_9
6928 * @arg @ref LL_HRTIM_FLT_FILTER_10
6929 * @arg @ref LL_HRTIM_FLT_FILTER_11
6930 * @arg @ref LL_HRTIM_FLT_FILTER_12
6931 * @arg @ref LL_HRTIM_FLT_FILTER_13
6932 * @arg @ref LL_HRTIM_FLT_FILTER_14
6933 * @arg @ref LL_HRTIM_FLT_FILTER_15
6934 * @retval None
6935 */
6936 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
6937 {
6939 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6941 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));
6942 }
6944 /**
6945 * @brief Get actual digital noise filter setting of a fault signal.
6946 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
6947 * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
6948 * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
6949 * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
6950 * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter
6951 * @param HRTIMx High Resolution Timer instance
6952 * @param Fault This parameter can be one of the following values:
6953 * @arg @ref LL_HRTIM_FAULT_1
6954 * @arg @ref LL_HRTIM_FAULT_2
6955 * @arg @ref LL_HRTIM_FAULT_3
6956 * @arg @ref LL_HRTIM_FAULT_4
6957 * @arg @ref LL_HRTIM_FAULT_5
6958 * @retval Filter This parameter can be one of the following values:
6959 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
6960 * @arg @ref LL_HRTIM_FLT_FILTER_1
6961 * @arg @ref LL_HRTIM_FLT_FILTER_2
6962 * @arg @ref LL_HRTIM_FLT_FILTER_3
6963 * @arg @ref LL_HRTIM_FLT_FILTER_4
6964 * @arg @ref LL_HRTIM_FLT_FILTER_5
6965 * @arg @ref LL_HRTIM_FLT_FILTER_6
6966 * @arg @ref LL_HRTIM_FLT_FILTER_7
6967 * @arg @ref LL_HRTIM_FLT_FILTER_8
6968 * @arg @ref LL_HRTIM_FLT_FILTER_9
6969 * @arg @ref LL_HRTIM_FLT_FILTER_10
6970 * @arg @ref LL_HRTIM_FLT_FILTER_11
6971 * @arg @ref LL_HRTIM_FLT_FILTER_12
6972 * @arg @ref LL_HRTIM_FLT_FILTER_13
6973 * @arg @ref LL_HRTIM_FLT_FILTER_14
6974 * @arg @ref LL_HRTIM_FLT_FILTER_15
6975 */
6977 {
6979 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6981 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
6983 }
6985 /**
6986 * @brief Set the fault circuitry prescaler.
6987 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
6988 * @param HRTIMx High Resolution Timer instance
6989 * @param Prescaler This parameter can be one of the following values:
6990 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
6991 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
6992 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
6993 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
6994 * @retval None
6995 */
6997 {
6999 }
7001 /**
7002 * @brief Get actual fault circuitry prescaler setting.
7003 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
7004 * @param HRTIMx High Resolution Timer instance
7005 * @retval Prescaler This parameter can be one of the following values:
7006 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
7007 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
7008 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
7009 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
7010 */
7012 {
7014 }
7016 /**
7017 * @brief Lock the fault signal conditioning settings.
7018 * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
7019 * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
7020 * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
7021 * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
7022 * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock
7023 * @param HRTIMx High Resolution Timer instance
7024 * @param Fault This parameter can be one of the following values:
7025 * @arg @ref LL_HRTIM_FAULT_1
7026 * @arg @ref LL_HRTIM_FAULT_2
7027 * @arg @ref LL_HRTIM_FAULT_3
7028 * @arg @ref LL_HRTIM_FAULT_4
7029 * @arg @ref LL_HRTIM_FAULT_5
7030 * @retval None
7031 */
7033 {
7035 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7038 }
7040 /**
7041 * @brief Enable the fault circuitry for the designated fault input.
7042 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
7043 * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
7044 * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
7045 * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
7046 * FLTINR2 FLT5E LL_HRTIM_FLT_Enable
7047 * @param HRTIMx High Resolution Timer instance
7048 * @param Fault This parameter can be one of the following values:
7049 * @arg @ref LL_HRTIM_FAULT_1
7050 * @arg @ref LL_HRTIM_FAULT_2
7051 * @arg @ref LL_HRTIM_FAULT_3
7052 * @arg @ref LL_HRTIM_FAULT_4
7053 * @arg @ref LL_HRTIM_FAULT_5
7054 * @retval None
7055 */
7057 {
7059 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7062 }
7064 /**
7065 * @brief Disable the fault circuitry for for the designated fault input.
7066 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
7067 * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
7068 * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
7069 * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
7070 * FLTINR2 FLT5E LL_HRTIM_FLT_Disable
7071 * @param HRTIMx High Resolution Timer instance
7072 * @param Fault This parameter can be one of the following values:
7073 * @arg @ref LL_HRTIM_FAULT_1
7074 * @arg @ref LL_HRTIM_FAULT_2
7075 * @arg @ref LL_HRTIM_FAULT_3
7076 * @arg @ref LL_HRTIM_FAULT_4
7077 * @arg @ref LL_HRTIM_FAULT_5
7078 * @retval None
7079 */
7081 {
7083 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7086 }
7088 /**
7089 * @brief Indicate whether the fault circuitry is enabled for a given fault input.
7090 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
7091 * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
7092 * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
7093 * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
7094 * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled
7095 * @param HRTIMx High Resolution Timer instance
7096 * @param Fault This parameter can be one of the following values:
7097 * @arg @ref LL_HRTIM_FAULT_1
7098 * @arg @ref LL_HRTIM_FAULT_2
7099 * @arg @ref LL_HRTIM_FAULT_3
7100 * @arg @ref LL_HRTIM_FAULT_4
7101 * @arg @ref LL_HRTIM_FAULT_5
7102 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
7103 */
7105 {
7107 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7109 return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
7111 }
7113 /**
7114 * @}
7115 */
7117 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
7118 * @{
7119 */
7121 /**
7122 * @brief Configure the burst mode controller.
7123 * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
7124 * BMCR BMCLK LL_HRTIM_BM_Config\n
7125 * BMCR BMPRSC LL_HRTIM_BM_Config
7126 * @param HRTIMx High Resolution Timer instance
7127 * @param Configuration This parameter must be a combination of all the following values:
7128 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
7129 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7130 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
7131 * @retval None
7132 */
7134 {
7136 }
7138 /**
7139 * @brief Set the burst mode controller operating mode.
7140 * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
7141 * @param HRTIMx High Resolution Timer instance
7142 * @param Mode This parameter can be one of the following values:
7143 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
7144 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
7145 * @retval None
7146 */
7148 {
7150 }
7152 /**
7153 * @brief Get actual burst mode controller operating mode.
7154 * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
7155 * @param HRTIMx High Resolution Timer instance
7156 * @retval Mode This parameter can be one of the following values:
7157 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
7158 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
7159 */
7161 {
7163 }
7165 /**
7166 * @brief Set the burst mode controller clock source.
7167 * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
7168 * @param HRTIMx High Resolution Timer instance
7169 * @param ClockSrc This parameter can be one of the following values:
7170 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
7171 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
7172 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
7173 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
7174 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
7175 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
7176 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
7177 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
7178 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
7179 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7180 * @retval None
7181 */
7183 {
7185 }
7187 /**
7188 * @brief Get actual burst mode controller clock source.
7189 * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
7190 * @param HRTIMx High Resolution Timer instance
7191 * @retval ClockSrc This parameter can be one of the following values:
7192 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
7193 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
7194 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
7195 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
7196 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
7197 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
7198 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
7199 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
7200 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
7201 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7202 * @retval ClockSrc This parameter can be one of the following values:
7203 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
7204 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
7205 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
7206 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
7207 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
7208 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
7209 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
7210 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
7211 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
7212 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7213 */
7215 {
7217 }
7219 /**
7220 * @brief Set the burst mode controller prescaler.
7221 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
7222 * @param HRTIMx High Resolution Timer instance
7223 * @param Prescaler This parameter can be one of the following values:
7224 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
7225 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
7226 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
7227 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
7228 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
7229 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
7230 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
7231 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
7232 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
7233 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
7234 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
7235 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
7236 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
7237 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
7238 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
7239 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
7240 * @retval None
7241 */
7243 {
7245 }
7247 /**
7248 * @brief Get actual burst mode controller prescaler setting.
7249 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
7250 * @param HRTIMx High Resolution Timer instance
7251 * @retval Prescaler This parameter can be one of the following values:
7252 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
7253 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
7254 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
7255 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
7256 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
7257 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
7258 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
7259 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
7260 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
7261 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
7262 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
7263 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
7264 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
7265 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
7266 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
7267 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
7268 */
7270 {
7272 }
7274 /**
7275 * @brief Enable burst mode compare and period registers preload.
7276 * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
7277 * @param HRTIMx High Resolution Timer instance
7278 * @retval None
7279 */
7281 {
7283 }
7285 /**
7286 * @brief Disable burst mode compare and period registers preload.
7287 * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
7288 * @param HRTIMx High Resolution Timer instance
7289 * @retval None
7290 */
7292 {
7294 }
7296 /**
7297 * @brief Indicate whether burst mode compare and period registers are preloaded.
7298 * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
7299 * @param HRTIMx High Resolution Timer instance
7300 * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
7301 */
7303 {
7308 }
7310 /**
7311 * @brief Set the burst mode controller trigger
7312 * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
7313 * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
7314 * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
7315 * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
7316 * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
7317 * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
7318 * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
7319 * BMTRGR TARST LL_HRTIM_BM_SetTrig\n
7320 * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
7321 * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
7322 * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
7323 * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
7324 * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
7325 * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
7326 * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
7327 * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
7328 * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
7329 * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
7330 * BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n
7331 * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
7332 * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
7333 * BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n
7334 * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
7335 * BMTRGR TERST LL_HRTIM_BM_SetTrig\n
7336 * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
7337 * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
7338 * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
7339 * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
7340 * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
7341 * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
7342 * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
7343 * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
7344 * @param HRTIMx High Resolution Timer instance
7345 * @param Trig This parameter can be a combination of the following values:
7346 * @arg @ref LL_HRTIM_BM_TRIG_NONE
7347 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
7348 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
7349 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
7350 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
7351 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
7352 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
7353 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
7354 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
7355 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
7356 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
7357 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
7358 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
7359 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
7360 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
7361 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
7362 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
7363 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
7364 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
7365 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
7366 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
7367 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
7368 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
7369 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
7370 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
7371 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
7372 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
7373 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
7374 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
7375 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
7376 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
7377 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
7378 * @retval None
7379 */
7381 {
7383 }
7385 /**
7386 * @brief Get actual burst mode controller trigger.
7387 * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
7388 * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
7389 * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
7390 * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
7391 * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
7392 * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
7393 * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
7394 * BMTRGR TARST LL_HRTIM_BM_GetTrig\n
7395 * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
7396 * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
7397 * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
7398 * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
7399 * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
7400 * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
7401 * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
7402 * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
7403 * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
7404 * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
7405 * BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n
7406 * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
7407 * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
7408 * BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n
7409 * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
7410 * BMTRGR TERST LL_HRTIM_BM_GetTrig\n
7411 * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
7412 * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
7413 * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
7414 * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
7415 * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
7416 * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
7417 * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
7418 * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
7419 * @param HRTIMx High Resolution Timer instance
7420 * @retval Trig This parameter can be a combination of the following values:
7421 * @arg @ref LL_HRTIM_BM_TRIG_NONE
7422 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
7423 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
7424 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
7425 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
7426 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
7427 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
7428 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
7429 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
7430 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
7431 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
7432 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
7433 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
7434 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
7435 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
7436 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
7437 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
7438 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
7439 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
7440 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
7441 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
7442 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
7443 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
7444 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
7445 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
7446 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
7447 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
7448 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
7449 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
7450 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
7451 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
7452 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
7453 */
7455 {
7457 }
7459 /**
7460 * @brief Set the burst mode controller compare value.
7461 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
7462 * @param HRTIMx High Resolution Timer instance
7463 * @param CompareValue Compare value must be above or equal to 3
7464 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
7465 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7466 * @retval None
7467 */
7469 {
7471 }
7473 /**
7474 * @brief Get actual burst mode controller compare value.
7475 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
7476 * @param HRTIMx High Resolution Timer instance
7477 * @retval CompareValue Compare value must be above or equal to 3
7478 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
7479 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7480 */
7482 {
7484 }
7486 /**
7487 * @brief Set the burst mode controller period.
7488 * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
7489 * @param HRTIMx High Resolution Timer instance
7490 * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
7491 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7492 * The maximum value is 0x0000 FFDF.
7493 * @retval None
7494 */
7496 {
7498 }
7500 /**
7501 * @brief Get actual burst mode controller period.
7502 * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
7503 * @param HRTIMx High Resolution Timer instance
7504 * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
7505 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7506 * The maximum value is 0x0000 FFDF.
7507 */
7509 {
7511 }
7513 /**
7514 * @brief Enable the burst mode controller
7515 * @rmtoll BMCR BME LL_HRTIM_BM_Enable
7516 * @param HRTIMx High Resolution Timer instance
7517 * @retval None
7518 */
7520 {
7522 }
7524 /**
7525 * @brief Disable the burst mode controller
7526 * @rmtoll BMCR BME LL_HRTIM_BM_Disable
7527 * @param HRTIMx High Resolution Timer instance
7528 * @retval None
7529 */
7531 {
7533 }
7535 /**
7536 * @brief Indicate whether the burst mode controller is enabled.
7537 * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
7538 * @param HRTIMx High Resolution Timer instance
7539 * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
7540 */
7542 {
7544 }
7546 /**
7547 * @brief Trigger the burst operation (software trigger)
7548 * @rmtoll BMTRGR SW LL_HRTIM_BM_Start
7549 * @param HRTIMx High Resolution Timer instance
7550 * @retval None
7551 */
7553 {
7555 }
7557 /**
7558 * @brief Stop the burst mode operation.
7559 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
7560 * @note Causes a burst mode early termination.
7561 * @param HRTIMx High Resolution Timer instance
7562 * @retval None
7563 */
7565 {
7567 }
7569 /**
7570 * @brief Get actual burst mode status
7571 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
7572 * @param HRTIMx High Resolution Timer instance
7573 * @retval Status This parameter can be one of the following values:
7574 * @arg @ref LL_HRTIM_BM_STATUS_NORMAL
7575 * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
7576 */
7578 {
7580 }
7582 /**
7583 * @}
7584 */
7586 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
7587 * @{
7588 */
7590 /**
7591 * @brief Clear the Fault 1 interrupt flag.
7592 * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
7593 * @param HRTIMx High Resolution Timer instance
7594 * @retval None
7595 */
7597 {
7599 }
7601 /**
7602 * @brief Indicate whether Fault 1 interrupt occurred.
7603 * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
7604 * @param HRTIMx High Resolution Timer instance
7605 * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
7606 */
7608 {
7610 }
7612 /**
7613 * @brief Clear the Fault 2 interrupt flag.
7614 * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
7615 * @param HRTIMx High Resolution Timer instance
7616 * @retval None
7617 */
7619 {
7621 }
7623 /**
7624 * @brief Indicate whether Fault 2 interrupt occurred.
7625 * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
7626 * @param HRTIMx High Resolution Timer instance
7627 * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
7628 */
7630 {
7632 }
7634 /**
7635 * @brief Clear the Fault 3 interrupt flag.
7636 * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
7637 * @param HRTIMx High Resolution Timer instance
7638 * @retval None
7639 */
7641 {
7643 }
7645 /**
7646 * @brief Indicate whether Fault 3 interrupt occurred.
7647 * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
7648 * @param HRTIMx High Resolution Timer instance
7649 * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
7650 */
7652 {
7654 }
7656 /**
7657 * @brief Clear the Fault 4 interrupt flag.
7658 * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
7659 * @param HRTIMx High Resolution Timer instance
7660 * @retval None
7661 */
7663 {
7665 }
7667 /**
7668 * @brief Indicate whether Fault 4 interrupt occurred.
7669 * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
7670 * @param HRTIMx High Resolution Timer instance
7671 * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
7672 */
7674 {
7676 }
7678 /**
7679 * @brief Clear the Fault 5 interrupt flag.
7680 * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
7681 * @param HRTIMx High Resolution Timer instance
7682 * @retval None
7683 */
7685 {
7687 }
7689 /**
7690 * @brief Indicate whether Fault 5 interrupt occurred.
7691 * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
7692 * @param HRTIMx High Resolution Timer instance
7693 * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
7694 */
7696 {
7698 }
7700 /**
7701 * @brief Clear the System Fault interrupt flag.
7702 * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
7703 * @param HRTIMx High Resolution Timer instance
7704 * @retval None
7705 */
7707 {
7709 }
7711 /**
7712 * @brief Indicate whether System Fault interrupt occurred.
7713 * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
7714 * @param HRTIMx High Resolution Timer instance
7715 * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
7716 */
7718 {
7719 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
7720 }
7722 /**
7723 * @brief Clear the Burst Mode period interrupt flag.
7724 * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
7725 * @param HRTIMx High Resolution Timer instance
7726 * @retval None
7727 */
7729 {
7731 }
7733 /**
7734 * @brief Indicate whether Burst Mode period interrupt occurred.
7735 * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
7736 * @param HRTIMx High Resolution Timer instance
7737 * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
7738 */
7740 {
7741 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
7742 }
7744 /**
7745 * @brief Clear the Synchronization Input interrupt flag.
7746 * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
7747 * @param HRTIMx High Resolution Timer instance
7748 * @retval None
7749 */
7751 {
7753 }
7755 /**
7756 * @brief Indicate whether the Synchronization Input interrupt occurred.
7757 * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
7758 * @param HRTIMx High Resolution Timer instance
7759 * @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
7760 */
7762 {
7763 return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
7764 }
7766 /**
7767 * @brief Clear the update interrupt flag for a given timer (including the master timer) .
7768 * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
7769 * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
7770 * @param HRTIMx High Resolution Timer instance
7771 * @param Timer This parameter can be one of the following values:
7772 * @arg @ref LL_HRTIM_TIMER_MASTER
7773 * @arg @ref LL_HRTIM_TIMER_A
7774 * @arg @ref LL_HRTIM_TIMER_B
7775 * @arg @ref LL_HRTIM_TIMER_C
7776 * @arg @ref LL_HRTIM_TIMER_D
7777 * @arg @ref LL_HRTIM_TIMER_E
7778 * @retval None
7779 */
7781 {
7783 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7786 }
7788 /**
7789 * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
7790 * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
7791 * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
7792 * @param HRTIMx High Resolution Timer instance
7793 * @param Timer This parameter can be one of the following values:
7794 * @arg @ref LL_HRTIM_TIMER_MASTER
7795 * @arg @ref LL_HRTIM_TIMER_A
7796 * @arg @ref LL_HRTIM_TIMER_B
7797 * @arg @ref LL_HRTIM_TIMER_C
7798 * @arg @ref LL_HRTIM_TIMER_D
7799 * @arg @ref LL_HRTIM_TIMER_E
7800 * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7801 */
7803 {
7805 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7809 }
7811 /**
7812 * @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
7813 * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
7814 * TIMxICR REPC LL_HRTIM_ClearFlag_REP
7815 * @param HRTIMx High Resolution Timer instance
7816 * @param Timer This parameter can be one of the following values:
7817 * @arg @ref LL_HRTIM_TIMER_MASTER
7818 * @arg @ref LL_HRTIM_TIMER_A
7819 * @arg @ref LL_HRTIM_TIMER_B
7820 * @arg @ref LL_HRTIM_TIMER_C
7821 * @arg @ref LL_HRTIM_TIMER_D
7822 * @arg @ref LL_HRTIM_TIMER_E
7823 * @retval None
7824 */
7826 {
7828 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7832 }
7834 /**
7835 * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
7836 * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
7837 * TIMxISR REP LL_HRTIM_IsActiveFlag_REP
7838 * @param HRTIMx High Resolution Timer instance
7839 * @param Timer This parameter can be one of the following values:
7840 * @arg @ref LL_HRTIM_TIMER_MASTER
7841 * @arg @ref LL_HRTIM_TIMER_A
7842 * @arg @ref LL_HRTIM_TIMER_B
7843 * @arg @ref LL_HRTIM_TIMER_C
7844 * @arg @ref LL_HRTIM_TIMER_D
7845 * @arg @ref LL_HRTIM_TIMER_E
7846 * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7847 */
7849 {
7851 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7855 }
7857 /**
7858 * @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
7859 * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
7860 * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
7861 * @param HRTIMx High Resolution Timer instance
7862 * @param Timer This parameter can be one of the following values:
7863 * @arg @ref LL_HRTIM_TIMER_MASTER
7864 * @arg @ref LL_HRTIM_TIMER_A
7865 * @arg @ref LL_HRTIM_TIMER_B
7866 * @arg @ref LL_HRTIM_TIMER_C
7867 * @arg @ref LL_HRTIM_TIMER_D
7868 * @arg @ref LL_HRTIM_TIMER_E
7869 * @retval None
7870 */
7872 {
7874 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7877 }
7879 /**
7880 * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
7881 * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
7882 * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
7883 * @param HRTIMx High Resolution Timer instance
7884 * @param Timer This parameter can be one of the following values:
7885 * @arg @ref LL_HRTIM_TIMER_MASTER
7886 * @arg @ref LL_HRTIM_TIMER_A
7887 * @arg @ref LL_HRTIM_TIMER_B
7888 * @arg @ref LL_HRTIM_TIMER_C
7889 * @arg @ref LL_HRTIM_TIMER_D
7890 * @arg @ref LL_HRTIM_TIMER_E
7891 * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7892 */
7894 {
7896 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7900 }
7902 /**
7903 * @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
7904 * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
7905 * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
7906 * @param HRTIMx High Resolution Timer instance
7907 * @param Timer This parameter can be one of the following values:
7908 * @arg @ref LL_HRTIM_TIMER_MASTER
7909 * @arg @ref LL_HRTIM_TIMER_A
7910 * @arg @ref LL_HRTIM_TIMER_B
7911 * @arg @ref LL_HRTIM_TIMER_C
7912 * @arg @ref LL_HRTIM_TIMER_D
7913 * @arg @ref LL_HRTIM_TIMER_E
7914 * @retval None
7915 */
7917 {
7919 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7922 }
7924 /**
7925 * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
7926 * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
7927 * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
7928 * @param HRTIMx High Resolution Timer instance
7929 * @param Timer This parameter can be one of the following values:
7930 * @arg @ref LL_HRTIM_TIMER_MASTER
7931 * @arg @ref LL_HRTIM_TIMER_A
7932 * @arg @ref LL_HRTIM_TIMER_B
7933 * @arg @ref LL_HRTIM_TIMER_C
7934 * @arg @ref LL_HRTIM_TIMER_D
7935 * @arg @ref LL_HRTIM_TIMER_E
7936 * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7937 */
7939 {
7941 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7945 }
7947 /**
7948 * @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
7949 * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
7950 * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
7951 * @param HRTIMx High Resolution Timer instance
7952 * @param Timer This parameter can be one of the following values:
7953 * @arg @ref LL_HRTIM_TIMER_MASTER
7954 * @arg @ref LL_HRTIM_TIMER_A
7955 * @arg @ref LL_HRTIM_TIMER_B
7956 * @arg @ref LL_HRTIM_TIMER_C
7957 * @arg @ref LL_HRTIM_TIMER_D
7958 * @arg @ref LL_HRTIM_TIMER_E
7959 * @retval None
7960 */
7962 {
7964 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7967 }
7969 /**
7970 * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
7971 * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
7972 * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
7973 * @param HRTIMx High Resolution Timer instance
7974 * @param Timer This parameter can be one of the following values:
7975 * @arg @ref LL_HRTIM_TIMER_MASTER
7976 * @arg @ref LL_HRTIM_TIMER_A
7977 * @arg @ref LL_HRTIM_TIMER_B
7978 * @arg @ref LL_HRTIM_TIMER_C
7979 * @arg @ref LL_HRTIM_TIMER_D
7980 * @arg @ref LL_HRTIM_TIMER_E
7981 * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7982 */
7984 {
7986 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7990 }
7992 /**
7993 * @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
7994 * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
7995 * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
7996 * @param HRTIMx High Resolution Timer instance
7997 * @param Timer This parameter can be one of the following values:
7998 * @arg @ref LL_HRTIM_TIMER_MASTER
7999 * @arg @ref LL_HRTIM_TIMER_A
8000 * @arg @ref LL_HRTIM_TIMER_B
8001 * @arg @ref LL_HRTIM_TIMER_C
8002 * @arg @ref LL_HRTIM_TIMER_D
8003 * @arg @ref LL_HRTIM_TIMER_E
8004 * @retval None
8005 */
8007 {
8009 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8012 }
8014 /**
8015 * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
8016 * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
8017 * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
8018 * @param HRTIMx High Resolution Timer instance
8019 * @param Timer This parameter can be one of the following values:
8020 * @arg @ref LL_HRTIM_TIMER_MASTER
8021 * @arg @ref LL_HRTIM_TIMER_A
8022 * @arg @ref LL_HRTIM_TIMER_B
8023 * @arg @ref LL_HRTIM_TIMER_C
8024 * @arg @ref LL_HRTIM_TIMER_D
8025 * @arg @ref LL_HRTIM_TIMER_E
8026 * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
8027 */
8029 {
8031 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8035 }
8037 /**
8038 * @brief Clear the capture 1 interrupt flag for a given timer.
8039 * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
8040 * @param HRTIMx High Resolution Timer instance
8041 * @param Timer This parameter can be one of the following values:
8042 * @arg @ref LL_HRTIM_TIMER_A
8043 * @arg @ref LL_HRTIM_TIMER_B
8044 * @arg @ref LL_HRTIM_TIMER_C
8045 * @arg @ref LL_HRTIM_TIMER_D
8046 * @arg @ref LL_HRTIM_TIMER_E
8047 * @retval None
8048 */
8050 {
8052 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8055 }
8057 /**
8058 * @brief Indicate whether the capture 1 interrupt occurred for a given timer.
8059 * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
8060 * @param HRTIMx High Resolution Timer instance
8061 * @param Timer This parameter can be one of the following values:
8062 * @arg @ref LL_HRTIM_TIMER_A
8063 * @arg @ref LL_HRTIM_TIMER_B
8064 * @arg @ref LL_HRTIM_TIMER_C
8065 * @arg @ref LL_HRTIM_TIMER_D
8066 * @arg @ref LL_HRTIM_TIMER_E
8067 * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
8068 */
8070 {
8072 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8076 }
8078 /**
8079 * @brief Clear the capture 2 interrupt flag for a given timer.
8080 * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
8081 * @param HRTIMx High Resolution Timer instance
8082 * @param Timer This parameter can be one of the following values:
8083 * @arg @ref LL_HRTIM_TIMER_A
8084 * @arg @ref LL_HRTIM_TIMER_B
8085 * @arg @ref LL_HRTIM_TIMER_C
8086 * @arg @ref LL_HRTIM_TIMER_D
8087 * @arg @ref LL_HRTIM_TIMER_E
8088 * @retval None
8089 */
8091 {
8093 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8096 }
8098 /**
8099 * @brief Indicate whether the capture 2 interrupt occurred for a given timer.
8100 * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
8101 * @param HRTIMx High Resolution Timer instance
8102 * @param Timer This parameter can be one of the following values:
8103 * @arg @ref LL_HRTIM_TIMER_A
8104 * @arg @ref LL_HRTIM_TIMER_B
8105 * @arg @ref LL_HRTIM_TIMER_C
8106 * @arg @ref LL_HRTIM_TIMER_D
8107 * @arg @ref LL_HRTIM_TIMER_E
8108 * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
8109 */
8111 {
8113 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8117 }
8119 /**
8120 * @brief Clear the output 1 set interrupt flag for a given timer.
8121 * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
8122 * @param HRTIMx High Resolution Timer instance
8123 * @param Timer This parameter can be one of the following values:
8124 * @arg @ref LL_HRTIM_TIMER_A
8125 * @arg @ref LL_HRTIM_TIMER_B
8126 * @arg @ref LL_HRTIM_TIMER_C
8127 * @arg @ref LL_HRTIM_TIMER_D
8128 * @arg @ref LL_HRTIM_TIMER_E
8129 * @retval None
8130 */
8132 {
8134 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8137 }
8139 /**
8140 * @brief Indicate whether the output 1 set interrupt occurred for a given timer.
8141 * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
8142 * @param HRTIMx High Resolution Timer instance
8143 * @param Timer This parameter can be one of the following values:
8144 * @arg @ref LL_HRTIM_TIMER_A
8145 * @arg @ref LL_HRTIM_TIMER_B
8146 * @arg @ref LL_HRTIM_TIMER_C
8147 * @arg @ref LL_HRTIM_TIMER_D
8148 * @arg @ref LL_HRTIM_TIMER_E
8149 * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
8150 */
8152 {
8154 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8158 }
8160 /**
8161 * @brief Clear the output 1 reset interrupt flag for a given timer.
8162 * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
8163 * @param HRTIMx High Resolution Timer instance
8164 * @param Timer This parameter can be one of the following values:
8165 * @arg @ref LL_HRTIM_TIMER_A
8166 * @arg @ref LL_HRTIM_TIMER_B
8167 * @arg @ref LL_HRTIM_TIMER_C
8168 * @arg @ref LL_HRTIM_TIMER_D
8169 * @arg @ref LL_HRTIM_TIMER_E
8170 * @retval None
8171 */
8173 {
8175 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8178 }
8180 /**
8181 * @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
8182 * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
8183 * @param HRTIMx High Resolution Timer instance
8184 * @param Timer This parameter can be one of the following values:
8185 * @arg @ref LL_HRTIM_TIMER_A
8186 * @arg @ref LL_HRTIM_TIMER_B
8187 * @arg @ref LL_HRTIM_TIMER_C
8188 * @arg @ref LL_HRTIM_TIMER_D
8189 * @arg @ref LL_HRTIM_TIMER_E
8190 * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
8191 */
8193 {
8195 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8199 }
8201 /**
8202 * @brief Clear the output 2 set interrupt flag for a given timer.
8203 * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
8204 * @param HRTIMx High Resolution Timer instance
8205 * @param Timer This parameter can be one of the following values:
8206 * @arg @ref LL_HRTIM_TIMER_A
8207 * @arg @ref LL_HRTIM_TIMER_B
8208 * @arg @ref LL_HRTIM_TIMER_C
8209 * @arg @ref LL_HRTIM_TIMER_D
8210 * @arg @ref LL_HRTIM_TIMER_E
8211 * @retval None
8212 */
8214 {
8216 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8219 }
8221 /**
8222 * @brief Indicate whether the output 2 set interrupt occurred for a given timer.
8223 * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
8224 * @param HRTIMx High Resolution Timer instance
8225 * @param Timer This parameter can be one of the following values:
8226 * @arg @ref LL_HRTIM_TIMER_A
8227 * @arg @ref LL_HRTIM_TIMER_B
8228 * @arg @ref LL_HRTIM_TIMER_C
8229 * @arg @ref LL_HRTIM_TIMER_D
8230 * @arg @ref LL_HRTIM_TIMER_E
8231 * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
8232 */
8234 {
8236 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8240 }
8242 /**
8243 * @brief Clear the output 2reset interrupt flag for a given timer.
8244 * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
8245 * @param HRTIMx High Resolution Timer instance
8246 * @param Timer This parameter can be one of the following values:
8247 * @arg @ref LL_HRTIM_TIMER_A
8248 * @arg @ref LL_HRTIM_TIMER_B
8249 * @arg @ref LL_HRTIM_TIMER_C
8250 * @arg @ref LL_HRTIM_TIMER_D
8251 * @arg @ref LL_HRTIM_TIMER_E
8252 * @retval None
8253 */
8255 {
8257 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8260 }
8262 /**
8263 * @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
8264 * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
8265 * @param HRTIMx High Resolution Timer instance
8266 * @param Timer This parameter can be one of the following values:
8267 * @arg @ref LL_HRTIM_TIMER_A
8268 * @arg @ref LL_HRTIM_TIMER_B
8269 * @arg @ref LL_HRTIM_TIMER_C
8270 * @arg @ref LL_HRTIM_TIMER_D
8271 * @arg @ref LL_HRTIM_TIMER_E
8272 * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
8273 */
8275 {
8277 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8281 }
8283 /**
8284 * @brief Clear the reset and/or roll-over interrupt flag for a given timer.
8285 * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
8286 * @param HRTIMx High Resolution Timer instance
8287 * @param Timer This parameter can be one of the following values:
8288 * @arg @ref LL_HRTIM_TIMER_A
8289 * @arg @ref LL_HRTIM_TIMER_B
8290 * @arg @ref LL_HRTIM_TIMER_C
8291 * @arg @ref LL_HRTIM_TIMER_D
8292 * @arg @ref LL_HRTIM_TIMER_E
8293 * @retval None
8294 */
8296 {
8298 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8301 }
8303 /**
8304 * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
8305 * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
8306 * @param HRTIMx High Resolution Timer instance
8307 * @param Timer This parameter can be one of the following values:
8308 * @arg @ref LL_HRTIM_TIMER_A
8309 * @arg @ref LL_HRTIM_TIMER_B
8310 * @arg @ref LL_HRTIM_TIMER_C
8311 * @arg @ref LL_HRTIM_TIMER_D
8312 * @arg @ref LL_HRTIM_TIMER_E
8313 * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
8314 */
8316 {
8318 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8322 }
8324 /**
8325 * @brief Clear the delayed protection interrupt flag for a given timer.
8326 * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
8327 * @param HRTIMx High Resolution Timer instance
8328 * @param Timer This parameter can be one of the following values:
8329 * @arg @ref LL_HRTIM_TIMER_A
8330 * @arg @ref LL_HRTIM_TIMER_B
8331 * @arg @ref LL_HRTIM_TIMER_C
8332 * @arg @ref LL_HRTIM_TIMER_D
8333 * @arg @ref LL_HRTIM_TIMER_E
8334 * @retval None
8335 */
8337 {
8339 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8342 }
8344 /**
8345 * @brief Indicate whether the delayed protection interrupt occurred for a given timer.
8346 * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
8347 * @param HRTIMx High Resolution Timer instance
8348 * @param Timer This parameter can be one of the following values:
8349 * @arg @ref LL_HRTIM_TIMER_A
8350 * @arg @ref LL_HRTIM_TIMER_B
8351 * @arg @ref LL_HRTIM_TIMER_C
8352 * @arg @ref LL_HRTIM_TIMER_D
8353 * @arg @ref LL_HRTIM_TIMER_E
8354 * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
8355 */
8357 {
8359 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8363 }
8365 /**
8366 * @}
8367 */
8369 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management
8370 * @{
8371 */
8373 /**
8374 * @brief Enable the fault 1 interrupt.
8375 * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
8376 * @param HRTIMx High Resolution Timer instance
8377 * @retval None
8378 */
8380 {
8382 }
8384 /**
8385 * @brief Disable the fault 1 interrupt.
8386 * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
8387 * @param HRTIMx High Resolution Timer instance
8388 * @retval None
8389 */
8391 {
8393 }
8395 /**
8396 * @brief Indicate whether the fault 1 interrupt is enabled.
8397 * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
8398 * @param HRTIMx High Resolution Timer instance
8399 * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
8400 */
8402 {
8404 }
8406 /**
8407 * @brief Enable the fault 2 interrupt.
8408 * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
8409 * @param HRTIMx High Resolution Timer instance
8410 * @retval None
8411 */
8413 {
8415 }
8417 /**
8418 * @brief Disable the fault 2 interrupt.
8419 * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
8420 * @param HRTIMx High Resolution Timer instance
8421 * @retval None
8422 */
8424 {
8426 }
8428 /**
8429 * @brief Indicate whether the fault 2 interrupt is enabled.
8430 * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
8431 * @param HRTIMx High Resolution Timer instance
8432 * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
8433 */
8435 {
8437 }
8439 /**
8440 * @brief Enable the fault 3 interrupt.
8441 * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
8442 * @param HRTIMx High Resolution Timer instance
8443 * @retval None
8444 */
8446 {
8448 }
8450 /**
8451 * @brief Disable the fault 3 interrupt.
8452 * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
8453 * @param HRTIMx High Resolution Timer instance
8454 * @retval None
8455 */
8457 {
8459 }
8461 /**
8462 * @brief Indicate whether the fault 3 interrupt is enabled.
8463 * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
8464 * @param HRTIMx High Resolution Timer instance
8465 * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
8466 */
8468 {
8470 }
8472 /**
8473 * @brief Enable the fault 4 interrupt.
8474 * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
8475 * @param HRTIMx High Resolution Timer instance
8476 * @retval None
8477 */
8479 {
8481 }
8483 /**
8484 * @brief Disable the fault 4 interrupt.
8485 * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
8486 * @param HRTIMx High Resolution Timer instance
8487 * @retval None
8488 */
8490 {
8492 }
8494 /**
8495 * @brief Indicate whether the fault 4 interrupt is enabled.
8496 * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
8497 * @param HRTIMx High Resolution Timer instance
8498 * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
8499 */
8501 {
8503 }
8505 /**
8506 * @brief Enable the fault 5 interrupt.
8507 * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
8508 * @param HRTIMx High Resolution Timer instance
8509 * @retval None
8510 */
8512 {
8514 }
8516 /**
8517 * @brief Disable the fault 5 interrupt.
8518 * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
8519 * @param HRTIMx High Resolution Timer instance
8520 * @retval None
8521 */
8523 {
8525 }
8527 /**
8528 * @brief Indicate whether the fault 5 interrupt is enabled.
8529 * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
8530 * @param HRTIMx High Resolution Timer instance
8531 * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
8532 */
8534 {
8536 }
8538 /**
8539 * @brief Enable the system fault interrupt.
8540 * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
8541 * @param HRTIMx High Resolution Timer instance
8542 * @retval None
8543 */
8545 {
8547 }
8549 /**
8550 * @brief Disable the system fault interrupt.
8551 * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
8552 * @param HRTIMx High Resolution Timer instance
8553 * @retval None
8554 */
8556 {
8558 }
8560 /**
8561 * @brief Indicate whether the system fault interrupt is enabled.
8562 * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
8563 * @param HRTIMx High Resolution Timer instance
8564 * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
8565 */
8567 {
8568 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
8569 }
8571 /**
8572 * @brief Enable the burst mode period interrupt.
8573 * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
8574 * @param HRTIMx High Resolution Timer instance
8575 * @retval None
8576 */
8578 {
8580 }
8582 /**
8583 * @brief Disable the burst mode period interrupt.
8584 * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
8585 * @param HRTIMx High Resolution Timer instance
8586 * @retval None
8587 */
8589 {
8591 }
8593 /**
8594 * @brief Indicate whether the burst mode period interrupt is enabled.
8595 * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
8596 * @param HRTIMx High Resolution Timer instance
8597 * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
8598 */
8600 {
8601 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
8602 }
8604 /**
8605 * @brief Enable the synchronization input interrupt.
8606 * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
8607 * @param HRTIMx High Resolution Timer instance
8608 * @retval None
8609 */
8611 {
8613 }
8615 /**
8616 * @brief Disable the synchronization input interrupt.
8617 * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
8618 * @param HRTIMx High Resolution Timer instance
8619 * @retval None
8620 */
8622 {
8624 }
8626 /**
8627 * @brief Indicate whether the synchronization input interrupt is enabled.
8628 * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
8629 * @param HRTIMx High Resolution Timer instance
8630 * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
8631 */
8633 {
8634 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
8635 }
8637 /**
8638 * @brief Enable the update interrupt for a given timer.
8639 * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
8640 * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
8641 * @param HRTIMx High Resolution Timer instance
8642 * @param Timer This parameter can be one of the following values:
8643 * @arg @ref LL_HRTIM_TIMER_MASTER
8644 * @arg @ref LL_HRTIM_TIMER_A
8645 * @arg @ref LL_HRTIM_TIMER_B
8646 * @arg @ref LL_HRTIM_TIMER_C
8647 * @arg @ref LL_HRTIM_TIMER_D
8648 * @arg @ref LL_HRTIM_TIMER_E
8649 * @retval None
8650 */
8652 {
8654 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8657 }
8659 /**
8660 * @brief Disable the update interrupt for a given timer.
8661 * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
8662 * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
8663 * @param HRTIMx High Resolution Timer instance
8664 * @param Timer This parameter can be one of the following values:
8665 * @arg @ref LL_HRTIM_TIMER_MASTER
8666 * @arg @ref LL_HRTIM_TIMER_A
8667 * @arg @ref LL_HRTIM_TIMER_B
8668 * @arg @ref LL_HRTIM_TIMER_C
8669 * @arg @ref LL_HRTIM_TIMER_D
8670 * @arg @ref LL_HRTIM_TIMER_E
8671 * @retval None
8672 */
8674 {
8676 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8679 }
8681 /**
8682 * @brief Indicate whether the update interrupt is enabled for a given timer.
8683 * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
8684 * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
8685 * @param HRTIMx High Resolution Timer instance
8686 * @param Timer This parameter can be one of the following values:
8687 * @arg @ref LL_HRTIM_TIMER_MASTER
8688 * @arg @ref LL_HRTIM_TIMER_A
8689 * @arg @ref LL_HRTIM_TIMER_B
8690 * @arg @ref LL_HRTIM_TIMER_C
8691 * @arg @ref LL_HRTIM_TIMER_D
8692 * @arg @ref LL_HRTIM_TIMER_E
8693 * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8694 */
8696 {
8698 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8702 }
8704 /**
8705 * @brief Enable the repetition interrupt for a given timer.
8706 * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
8707 * TIMxDIER REPIE LL_HRTIM_EnableIT_REP
8708 * @param HRTIMx High Resolution Timer instance
8709 * @param Timer This parameter can be one of the following values:
8710 * @arg @ref LL_HRTIM_TIMER_MASTER
8711 * @arg @ref LL_HRTIM_TIMER_A
8712 * @arg @ref LL_HRTIM_TIMER_B
8713 * @arg @ref LL_HRTIM_TIMER_C
8714 * @arg @ref LL_HRTIM_TIMER_D
8715 * @arg @ref LL_HRTIM_TIMER_E
8716 * @retval None
8717 */
8719 {
8721 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8724 }
8726 /**
8727 * @brief Disable the repetition interrupt for a given timer.
8728 * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
8729 * TIMxDIER REPIE LL_HRTIM_DisableIT_REP
8730 * @param HRTIMx High Resolution Timer instance
8731 * @param Timer This parameter can be one of the following values:
8732 * @arg @ref LL_HRTIM_TIMER_MASTER
8733 * @arg @ref LL_HRTIM_TIMER_A
8734 * @arg @ref LL_HRTIM_TIMER_B
8735 * @arg @ref LL_HRTIM_TIMER_C
8736 * @arg @ref LL_HRTIM_TIMER_D
8737 * @arg @ref LL_HRTIM_TIMER_E
8738 * @retval None
8739 */
8741 {
8743 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8746 }
8748 /**
8749 * @brief Indicate whether the repetition interrupt is enabled for a given timer.
8750 * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
8751 * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
8752 * @param HRTIMx High Resolution Timer instance
8753 * @param Timer This parameter can be one of the following values:
8754 * @arg @ref LL_HRTIM_TIMER_MASTER
8755 * @arg @ref LL_HRTIM_TIMER_A
8756 * @arg @ref LL_HRTIM_TIMER_B
8757 * @arg @ref LL_HRTIM_TIMER_C
8758 * @arg @ref LL_HRTIM_TIMER_D
8759 * @arg @ref LL_HRTIM_TIMER_E
8760 * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8761 */
8763 {
8765 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8769 }
8771 /**
8772 * @brief Enable the compare 1 interrupt for a given timer.
8773 * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
8774 * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
8775 * @param HRTIMx High Resolution Timer instance
8776 * @param Timer This parameter can be one of the following values:
8777 * @arg @ref LL_HRTIM_TIMER_MASTER
8778 * @arg @ref LL_HRTIM_TIMER_A
8779 * @arg @ref LL_HRTIM_TIMER_B
8780 * @arg @ref LL_HRTIM_TIMER_C
8781 * @arg @ref LL_HRTIM_TIMER_D
8782 * @arg @ref LL_HRTIM_TIMER_E
8783 * @retval None
8784 */
8786 {
8788 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8791 }
8793 /**
8794 * @brief Disable the compare 1 interrupt for a given timer.
8795 * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
8796 * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
8797 * @param HRTIMx High Resolution Timer instance
8798 * @param Timer This parameter can be one of the following values:
8799 * @arg @ref LL_HRTIM_TIMER_MASTER
8800 * @arg @ref LL_HRTIM_TIMER_A
8801 * @arg @ref LL_HRTIM_TIMER_B
8802 * @arg @ref LL_HRTIM_TIMER_C
8803 * @arg @ref LL_HRTIM_TIMER_D
8804 * @arg @ref LL_HRTIM_TIMER_E
8805 * @retval None
8806 */
8808 {
8810 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8813 }
8815 /**
8816 * @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
8817 * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
8818 * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
8819 * @param HRTIMx High Resolution Timer instance
8820 * @param Timer This parameter can be one of the following values:
8821 * @arg @ref LL_HRTIM_TIMER_MASTER
8822 * @arg @ref LL_HRTIM_TIMER_A
8823 * @arg @ref LL_HRTIM_TIMER_B
8824 * @arg @ref LL_HRTIM_TIMER_C
8825 * @arg @ref LL_HRTIM_TIMER_D
8826 * @arg @ref LL_HRTIM_TIMER_E
8827 * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8828 */
8830 {
8832 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8836 }
8838 /**
8839 * @brief Enable the compare 2 interrupt for a given timer.
8840 * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
8841 * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
8842 * @param HRTIMx High Resolution Timer instance
8843 * @param Timer This parameter can be one of the following values:
8844 * @arg @ref LL_HRTIM_TIMER_MASTER
8845 * @arg @ref LL_HRTIM_TIMER_A
8846 * @arg @ref LL_HRTIM_TIMER_B
8847 * @arg @ref LL_HRTIM_TIMER_C
8848 * @arg @ref LL_HRTIM_TIMER_D
8849 * @arg @ref LL_HRTIM_TIMER_E
8850 * @retval None
8851 */
8853 {
8855 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8858 }
8860 /**
8861 * @brief Disable the compare 2 interrupt for a given timer.
8862 * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
8863 * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
8864 * @param HRTIMx High Resolution Timer instance
8865 * @param Timer This parameter can be one of the following values:
8866 * @arg @ref LL_HRTIM_TIMER_MASTER
8867 * @arg @ref LL_HRTIM_TIMER_A
8868 * @arg @ref LL_HRTIM_TIMER_B
8869 * @arg @ref LL_HRTIM_TIMER_C
8870 * @arg @ref LL_HRTIM_TIMER_D
8871 * @arg @ref LL_HRTIM_TIMER_E
8872 * @retval None
8873 */
8875 {
8877 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8880 }
8882 /**
8883 * @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
8884 * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
8885 * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
8886 * @param HRTIMx High Resolution Timer instance
8887 * @param Timer This parameter can be one of the following values:
8888 * @arg @ref LL_HRTIM_TIMER_MASTER
8889 * @arg @ref LL_HRTIM_TIMER_A
8890 * @arg @ref LL_HRTIM_TIMER_B
8891 * @arg @ref LL_HRTIM_TIMER_C
8892 * @arg @ref LL_HRTIM_TIMER_D
8893 * @arg @ref LL_HRTIM_TIMER_E
8894 * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8895 */
8897 {
8899 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8903 }
8905 /**
8906 * @brief Enable the compare 3 interrupt for a given timer.
8907 * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
8908 * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
8909 * @param HRTIMx High Resolution Timer instance
8910 * @param Timer This parameter can be one of the following values:
8911 * @arg @ref LL_HRTIM_TIMER_MASTER
8912 * @arg @ref LL_HRTIM_TIMER_A
8913 * @arg @ref LL_HRTIM_TIMER_B
8914 * @arg @ref LL_HRTIM_TIMER_C
8915 * @arg @ref LL_HRTIM_TIMER_D
8916 * @arg @ref LL_HRTIM_TIMER_E
8917 * @retval None
8918 */
8920 {
8922 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8925 }
8927 /**
8928 * @brief Disable the compare 3 interrupt for a given timer.
8929 * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
8930 * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
8931 * @param HRTIMx High Resolution Timer instance
8932 * @param Timer This parameter can be one of the following values:
8933 * @arg @ref LL_HRTIM_TIMER_MASTER
8934 * @arg @ref LL_HRTIM_TIMER_A
8935 * @arg @ref LL_HRTIM_TIMER_B
8936 * @arg @ref LL_HRTIM_TIMER_C
8937 * @arg @ref LL_HRTIM_TIMER_D
8938 * @arg @ref LL_HRTIM_TIMER_E
8939 * @retval None
8940 */
8942 {
8944 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8947 }
8949 /**
8950 * @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
8951 * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
8952 * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
8953 * @param HRTIMx High Resolution Timer instance
8954 * @param Timer This parameter can be one of the following values:
8955 * @arg @ref LL_HRTIM_TIMER_MASTER
8956 * @arg @ref LL_HRTIM_TIMER_A
8957 * @arg @ref LL_HRTIM_TIMER_B
8958 * @arg @ref LL_HRTIM_TIMER_C
8959 * @arg @ref LL_HRTIM_TIMER_D
8960 * @arg @ref LL_HRTIM_TIMER_E
8961 * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8962 */
8964 {
8966 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8970 }
8972 /**
8973 * @brief Enable the compare 4 interrupt for a given timer.
8974 * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
8975 * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
8976 * @param HRTIMx High Resolution Timer instance
8977 * @param Timer This parameter can be one of the following values:
8978 * @arg @ref LL_HRTIM_TIMER_MASTER
8979 * @arg @ref LL_HRTIM_TIMER_A
8980 * @arg @ref LL_HRTIM_TIMER_B
8981 * @arg @ref LL_HRTIM_TIMER_C
8982 * @arg @ref LL_HRTIM_TIMER_D
8983 * @arg @ref LL_HRTIM_TIMER_E
8984 * @retval None
8985 */
8987 {
8989 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8992 }
8994 /**
8995 * @brief Disable the compare 4 interrupt for a given timer.
8996 * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
8997 * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
8998 * @param HRTIMx High Resolution Timer instance
8999 * @param Timer This parameter can be one of the following values:
9000 * @arg @ref LL_HRTIM_TIMER_MASTER
9001 * @arg @ref LL_HRTIM_TIMER_A
9002 * @arg @ref LL_HRTIM_TIMER_B
9003 * @arg @ref LL_HRTIM_TIMER_C
9004 * @arg @ref LL_HRTIM_TIMER_D
9005 * @arg @ref LL_HRTIM_TIMER_E
9006 * @retval None
9007 */
9009 {
9011 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9014 }
9016 /**
9017 * @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
9018 * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
9019 * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
9020 * @param HRTIMx High Resolution Timer instance
9021 * @param Timer This parameter can be one of the following values:
9022 * @arg @ref LL_HRTIM_TIMER_MASTER
9023 * @arg @ref LL_HRTIM_TIMER_A
9024 * @arg @ref LL_HRTIM_TIMER_B
9025 * @arg @ref LL_HRTIM_TIMER_C
9026 * @arg @ref LL_HRTIM_TIMER_D
9027 * @arg @ref LL_HRTIM_TIMER_E
9028 * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9029 */
9031 {
9033 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9037 }
9039 /**
9040 * @brief Enable the capture 1 interrupt for a given timer.
9041 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
9042 * @param HRTIMx High Resolution Timer instance
9043 * @param Timer This parameter can be one of the following values:
9044 * @arg @ref LL_HRTIM_TIMER_A
9045 * @arg @ref LL_HRTIM_TIMER_B
9046 * @arg @ref LL_HRTIM_TIMER_C
9047 * @arg @ref LL_HRTIM_TIMER_D
9048 * @arg @ref LL_HRTIM_TIMER_E
9049 * @retval None
9050 */
9052 {
9054 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9057 }
9059 /**
9060 * @brief Enable the capture 1 interrupt for a given timer.
9061 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
9062 * @param HRTIMx High Resolution Timer instance
9063 * @param Timer This parameter can be one of the following values:
9064 * @arg @ref LL_HRTIM_TIMER_A
9065 * @arg @ref LL_HRTIM_TIMER_B
9066 * @arg @ref LL_HRTIM_TIMER_C
9067 * @arg @ref LL_HRTIM_TIMER_D
9068 * @arg @ref LL_HRTIM_TIMER_E
9069 * @retval None
9070 */
9072 {
9074 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9077 }
9079 /**
9080 * @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
9081 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
9082 * @param HRTIMx High Resolution Timer instance
9083 * @param Timer This parameter can be one of the following values:
9084 * @arg @ref LL_HRTIM_TIMER_A
9085 * @arg @ref LL_HRTIM_TIMER_B
9086 * @arg @ref LL_HRTIM_TIMER_C
9087 * @arg @ref LL_HRTIM_TIMER_D
9088 * @arg @ref LL_HRTIM_TIMER_E
9089 * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
9090 */
9092 {
9094 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9098 }
9100 /**
9101 * @brief Enable the capture 2 interrupt for a given timer.
9102 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
9103 * @param HRTIMx High Resolution Timer instance
9104 * @param Timer This parameter can be one of the following values:
9105 * @arg @ref LL_HRTIM_TIMER_A
9106 * @arg @ref LL_HRTIM_TIMER_B
9107 * @arg @ref LL_HRTIM_TIMER_C
9108 * @arg @ref LL_HRTIM_TIMER_D
9109 * @arg @ref LL_HRTIM_TIMER_E
9110 * @retval None
9111 */
9113 {
9115 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9118 }
9120 /**
9121 * @brief Enable the capture 2 interrupt for a given timer.
9122 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
9123 * @param HRTIMx High Resolution Timer instance
9124 * @param Timer This parameter can be one of the following values:
9125 * @arg @ref LL_HRTIM_TIMER_A
9126 * @arg @ref LL_HRTIM_TIMER_B
9127 * @arg @ref LL_HRTIM_TIMER_C
9128 * @arg @ref LL_HRTIM_TIMER_D
9129 * @arg @ref LL_HRTIM_TIMER_E
9130 * @retval None
9131 */
9133 {
9135 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9138 }
9140 /**
9141 * @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
9142 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
9143 * @param HRTIMx High Resolution Timer instance
9144 * @param Timer This parameter can be one of the following values:
9145 * @arg @ref LL_HRTIM_TIMER_A
9146 * @arg @ref LL_HRTIM_TIMER_B
9147 * @arg @ref LL_HRTIM_TIMER_C
9148 * @arg @ref LL_HRTIM_TIMER_D
9149 * @arg @ref LL_HRTIM_TIMER_E
9150 * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
9151 */
9153 {
9155 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9159 }
9161 /**
9162 * @brief Enable the output 1 set interrupt for a given timer.
9163 * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
9164 * @param HRTIMx High Resolution Timer instance
9165 * @param Timer This parameter can be one of the following values:
9166 * @arg @ref LL_HRTIM_TIMER_A
9167 * @arg @ref LL_HRTIM_TIMER_B
9168 * @arg @ref LL_HRTIM_TIMER_C
9169 * @arg @ref LL_HRTIM_TIMER_D
9170 * @arg @ref LL_HRTIM_TIMER_E
9171 * @retval None
9172 */
9174 {
9176 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9179 }
9181 /**
9182 * @brief Disable the output 1 set interrupt for a given timer.
9183 * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
9184 * @param HRTIMx High Resolution Timer instance
9185 * @param Timer This parameter can be one of the following values:
9186 * @arg @ref LL_HRTIM_TIMER_A
9187 * @arg @ref LL_HRTIM_TIMER_B
9188 * @arg @ref LL_HRTIM_TIMER_C
9189 * @arg @ref LL_HRTIM_TIMER_D
9190 * @arg @ref LL_HRTIM_TIMER_E
9191 * @retval None
9192 */
9194 {
9196 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9199 }
9201 /**
9202 * @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
9203 * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
9204 * @param HRTIMx High Resolution Timer instance
9205 * @param Timer This parameter can be one of the following values:
9206 * @arg @ref LL_HRTIM_TIMER_A
9207 * @arg @ref LL_HRTIM_TIMER_B
9208 * @arg @ref LL_HRTIM_TIMER_C
9209 * @arg @ref LL_HRTIM_TIMER_D
9210 * @arg @ref LL_HRTIM_TIMER_E
9211 * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
9212 */
9214 {
9216 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9220 }
9222 /**
9223 * @brief Enable the output 1 reset interrupt for a given timer.
9224 * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
9225 * @param HRTIMx High Resolution Timer instance
9226 * @param Timer This parameter can be one of the following values:
9227 * @arg @ref LL_HRTIM_TIMER_A
9228 * @arg @ref LL_HRTIM_TIMER_B
9229 * @arg @ref LL_HRTIM_TIMER_C
9230 * @arg @ref LL_HRTIM_TIMER_D
9231 * @arg @ref LL_HRTIM_TIMER_E
9232 * @retval None
9233 */
9235 {
9237 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9240 }
9242 /**
9243 * @brief Disable the output 1 reset interrupt for a given timer.
9244 * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
9245 * @param HRTIMx High Resolution Timer instance
9246 * @param Timer This parameter can be one of the following values:
9247 * @arg @ref LL_HRTIM_TIMER_A
9248 * @arg @ref LL_HRTIM_TIMER_B
9249 * @arg @ref LL_HRTIM_TIMER_C
9250 * @arg @ref LL_HRTIM_TIMER_D
9251 * @arg @ref LL_HRTIM_TIMER_E
9252 * @retval None
9253 */
9255 {
9257 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9260 }
9262 /**
9263 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
9264 * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
9265 * @param HRTIMx High Resolution Timer instance
9266 * @param Timer This parameter can be one of the following values:
9267 * @arg @ref LL_HRTIM_TIMER_A
9268 * @arg @ref LL_HRTIM_TIMER_B
9269 * @arg @ref LL_HRTIM_TIMER_C
9270 * @arg @ref LL_HRTIM_TIMER_D
9271 * @arg @ref LL_HRTIM_TIMER_E
9272 * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
9273 */
9275 {
9277 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9281 }
9283 /**
9284 * @brief Enable the output 2 set interrupt for a given timer.
9285 * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
9286 * @param HRTIMx High Resolution Timer instance
9287 * @param Timer This parameter can be one of the following values:
9288 * @arg @ref LL_HRTIM_TIMER_A
9289 * @arg @ref LL_HRTIM_TIMER_B
9290 * @arg @ref LL_HRTIM_TIMER_C
9291 * @arg @ref LL_HRTIM_TIMER_D
9292 * @arg @ref LL_HRTIM_TIMER_E
9293 * @retval None
9294 */
9296 {
9298 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9301 }
9303 /**
9304 * @brief Disable the output 2 set interrupt for a given timer.
9305 * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
9306 * @param HRTIMx High Resolution Timer instance
9307 * @param Timer This parameter can be one of the following values:
9308 * @arg @ref LL_HRTIM_TIMER_A
9309 * @arg @ref LL_HRTIM_TIMER_B
9310 * @arg @ref LL_HRTIM_TIMER_C
9311 * @arg @ref LL_HRTIM_TIMER_D
9312 * @arg @ref LL_HRTIM_TIMER_E
9313 * @retval None
9314 */
9316 {
9318 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9321 }
9323 /**
9324 * @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
9325 * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
9326 * @param HRTIMx High Resolution Timer instance
9327 * @param Timer This parameter can be one of the following values:
9328 * @arg @ref LL_HRTIM_TIMER_A
9329 * @arg @ref LL_HRTIM_TIMER_B
9330 * @arg @ref LL_HRTIM_TIMER_C
9331 * @arg @ref LL_HRTIM_TIMER_D
9332 * @arg @ref LL_HRTIM_TIMER_E
9333 * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
9334 */
9336 {
9338 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9342 }
9344 /**
9345 * @brief Enable the output 2 reset interrupt for a given timer.
9346 * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
9347 * @param HRTIMx High Resolution Timer instance
9348 * @param Timer This parameter can be one of the following values:
9349 * @arg @ref LL_HRTIM_TIMER_A
9350 * @arg @ref LL_HRTIM_TIMER_B
9351 * @arg @ref LL_HRTIM_TIMER_C
9352 * @arg @ref LL_HRTIM_TIMER_D
9353 * @arg @ref LL_HRTIM_TIMER_E
9354 * @retval None
9355 */
9357 {
9359 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9362 }
9364 /**
9365 * @brief Disable the output 2 reset interrupt for a given timer.
9366 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
9367 * @param HRTIMx High Resolution Timer instance
9368 * @param Timer This parameter can be one of the following values:
9369 * @arg @ref LL_HRTIM_TIMER_A
9370 * @arg @ref LL_HRTIM_TIMER_B
9371 * @arg @ref LL_HRTIM_TIMER_C
9372 * @arg @ref LL_HRTIM_TIMER_D
9373 * @arg @ref LL_HRTIM_TIMER_E
9374 * @retval None
9375 */
9377 {
9379 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9382 }
9384 /**
9385 * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
9386 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
9387 * @param HRTIMx High Resolution Timer instance
9388 * @param Timer This parameter can be one of the following values:
9389 * @arg @ref LL_HRTIM_TIMER_A
9390 * @arg @ref LL_HRTIM_TIMER_B
9391 * @arg @ref LL_HRTIM_TIMER_C
9392 * @arg @ref LL_HRTIM_TIMER_D
9393 * @arg @ref LL_HRTIM_TIMER_E
9394 * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
9395 */
9397 {
9399 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9403 }
9405 /**
9406 * @brief Enable the reset/roll-over interrupt for a given timer.
9407 * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
9408 * @param HRTIMx High Resolution Timer instance
9409 * @param Timer This parameter can be one of the following values:
9410 * @arg @ref LL_HRTIM_TIMER_A
9411 * @arg @ref LL_HRTIM_TIMER_B
9412 * @arg @ref LL_HRTIM_TIMER_C
9413 * @arg @ref LL_HRTIM_TIMER_D
9414 * @arg @ref LL_HRTIM_TIMER_E
9415 * @retval None
9416 */
9418 {
9420 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9423 }
9425 /**
9426 * @brief Disable the reset/roll-over interrupt for a given timer.
9427 * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
9428 * @param HRTIMx High Resolution Timer instance
9429 * @param Timer This parameter can be one of the following values:
9430 * @arg @ref LL_HRTIM_TIMER_A
9431 * @arg @ref LL_HRTIM_TIMER_B
9432 * @arg @ref LL_HRTIM_TIMER_C
9433 * @arg @ref LL_HRTIM_TIMER_D
9434 * @arg @ref LL_HRTIM_TIMER_E
9435 * @retval None
9436 */
9438 {
9440 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9443 }
9445 /**
9446 * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
9447 * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
9448 * @param HRTIMx High Resolution Timer instance
9449 * @param Timer This parameter can be one of the following values:
9450 * @arg @ref LL_HRTIM_TIMER_A
9451 * @arg @ref LL_HRTIM_TIMER_B
9452 * @arg @ref LL_HRTIM_TIMER_C
9453 * @arg @ref LL_HRTIM_TIMER_D
9454 * @arg @ref LL_HRTIM_TIMER_E
9455 * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
9456 */
9458 {
9460 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9464 }
9466 /**
9467 * @brief Enable the delayed protection interrupt for a given timer.
9468 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
9469 * @param HRTIMx High Resolution Timer instance
9470 * @param Timer This parameter can be one of the following values:
9471 * @arg @ref LL_HRTIM_TIMER_A
9472 * @arg @ref LL_HRTIM_TIMER_B
9473 * @arg @ref LL_HRTIM_TIMER_C
9474 * @arg @ref LL_HRTIM_TIMER_D
9475 * @arg @ref LL_HRTIM_TIMER_E
9476 * @retval None
9477 */
9479 {
9481 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9484 }
9486 /**
9487 * @brief Disable the delayed protection interrupt for a given timer.
9488 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
9489 * @param HRTIMx High Resolution Timer instance
9490 * @param Timer This parameter can be one of the following values:
9491 * @arg @ref LL_HRTIM_TIMER_A
9492 * @arg @ref LL_HRTIM_TIMER_B
9493 * @arg @ref LL_HRTIM_TIMER_C
9494 * @arg @ref LL_HRTIM_TIMER_D
9495 * @arg @ref LL_HRTIM_TIMER_E
9496 * @retval None
9497 */
9499 {
9501 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9504 }
9506 /**
9507 * @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
9508 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
9509 * @param HRTIMx High Resolution Timer instance
9510 * @param Timer This parameter can be one of the following values:
9511 * @arg @ref LL_HRTIM_TIMER_A
9512 * @arg @ref LL_HRTIM_TIMER_B
9513 * @arg @ref LL_HRTIM_TIMER_C
9514 * @arg @ref LL_HRTIM_TIMER_D
9515 * @arg @ref LL_HRTIM_TIMER_E
9516 * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
9517 */
9519 {
9521 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9525 }
9527 /**
9528 * @}
9529 */
9531 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
9532 * @{
9533 */
9535 /**
9536 * @brief Enable the synchronization input DMA request.
9537 * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
9538 * @param HRTIMx High Resolution Timer instance
9539 * @retval None
9540 */
9542 {
9544 }
9546 /**
9547 * @brief Disable the synchronization input DMA request
9548 * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
9549 * @param HRTIMx High Resolution Timer instance
9550 * @retval None
9551 */
9553 {
9555 }
9557 /**
9558 * @brief Indicate whether the synchronization input DMA request is enabled.
9559 * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
9560 * @param HRTIMx High Resolution Timer instance
9561 * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
9562 */
9564 {
9565 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
9566 }
9568 /**
9569 * @brief Enable the update DMA request for a given timer.
9570 * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
9571 * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
9572 * @param HRTIMx High Resolution Timer instance
9573 * @param Timer This parameter can be one of the following values:
9574 * @arg @ref LL_HRTIM_TIMER_MASTER
9575 * @arg @ref LL_HRTIM_TIMER_A
9576 * @arg @ref LL_HRTIM_TIMER_B
9577 * @arg @ref LL_HRTIM_TIMER_C
9578 * @arg @ref LL_HRTIM_TIMER_D
9579 * @arg @ref LL_HRTIM_TIMER_E
9580 * @retval None
9581 */
9583 {
9585 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9588 }
9590 /**
9591 * @brief Disable the update DMA request for a given timer.
9592 * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
9593 * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
9594 * @param HRTIMx High Resolution Timer instance
9595 * @param Timer This parameter can be one of the following values:
9596 * @arg @ref LL_HRTIM_TIMER_MASTER
9597 * @arg @ref LL_HRTIM_TIMER_A
9598 * @arg @ref LL_HRTIM_TIMER_B
9599 * @arg @ref LL_HRTIM_TIMER_C
9600 * @arg @ref LL_HRTIM_TIMER_D
9601 * @arg @ref LL_HRTIM_TIMER_E
9602 * @retval None
9603 */
9605 {
9607 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9610 }
9612 /**
9613 * @brief Indicate whether the update DMA request is enabled for a given timer.
9614 * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
9615 * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
9616 * @param HRTIMx High Resolution Timer instance
9617 * @param Timer This parameter can be one of the following values:
9618 * @arg @ref LL_HRTIM_TIMER_MASTER
9619 * @arg @ref LL_HRTIM_TIMER_A
9620 * @arg @ref LL_HRTIM_TIMER_B
9621 * @arg @ref LL_HRTIM_TIMER_C
9622 * @arg @ref LL_HRTIM_TIMER_D
9623 * @arg @ref LL_HRTIM_TIMER_E
9624 * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9625 */
9626 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9627 {
9629 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9633 }
9635 /**
9636 * @brief Enable the repetition DMA request for a given timer.
9637 * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
9638 * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
9639 * @param HRTIMx High Resolution Timer instance
9640 * @param Timer This parameter can be one of the following values:
9641 * @arg @ref LL_HRTIM_TIMER_MASTER
9642 * @arg @ref LL_HRTIM_TIMER_A
9643 * @arg @ref LL_HRTIM_TIMER_B
9644 * @arg @ref LL_HRTIM_TIMER_C
9645 * @arg @ref LL_HRTIM_TIMER_D
9646 * @arg @ref LL_HRTIM_TIMER_E
9647 * @retval None
9648 */
9650 {
9652 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9655 }
9657 /**
9658 * @brief Disable the repetition DMA request for a given timer.
9659 * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
9660 * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
9661 * @param HRTIMx High Resolution Timer instance
9662 * @param Timer This parameter can be one of the following values:
9663 * @arg @ref LL_HRTIM_TIMER_MASTER
9664 * @arg @ref LL_HRTIM_TIMER_A
9665 * @arg @ref LL_HRTIM_TIMER_B
9666 * @arg @ref LL_HRTIM_TIMER_C
9667 * @arg @ref LL_HRTIM_TIMER_D
9668 * @arg @ref LL_HRTIM_TIMER_E
9669 * @retval None
9670 */
9672 {
9674 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9677 }
9679 /**
9680 * @brief Indicate whether the repetition DMA request is enabled for a given timer.
9681 * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
9682 * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
9683 * @param HRTIMx High Resolution Timer instance
9684 * @param Timer This parameter can be one of the following values:
9685 * @arg @ref LL_HRTIM_TIMER_MASTER
9686 * @arg @ref LL_HRTIM_TIMER_A
9687 * @arg @ref LL_HRTIM_TIMER_B
9688 * @arg @ref LL_HRTIM_TIMER_C
9689 * @arg @ref LL_HRTIM_TIMER_D
9690 * @arg @ref LL_HRTIM_TIMER_E
9691 * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9692 */
9694 {
9696 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9700 }
9702 /**
9703 * @brief Enable the compare 1 DMA request for a given timer.
9704 * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
9705 * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
9706 * @param HRTIMx High Resolution Timer instance
9707 * @param Timer This parameter can be one of the following values:
9708 * @arg @ref LL_HRTIM_TIMER_MASTER
9709 * @arg @ref LL_HRTIM_TIMER_A
9710 * @arg @ref LL_HRTIM_TIMER_B
9711 * @arg @ref LL_HRTIM_TIMER_C
9712 * @arg @ref LL_HRTIM_TIMER_D
9713 * @arg @ref LL_HRTIM_TIMER_E
9714 * @retval None
9715 */
9717 {
9719 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9722 }
9724 /**
9725 * @brief Disable the compare 1 DMA request for a given timer.
9726 * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
9727 * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
9728 * @param HRTIMx High Resolution Timer instance
9729 * @param Timer This parameter can be one of the following values:
9730 * @arg @ref LL_HRTIM_TIMER_MASTER
9731 * @arg @ref LL_HRTIM_TIMER_A
9732 * @arg @ref LL_HRTIM_TIMER_B
9733 * @arg @ref LL_HRTIM_TIMER_C
9734 * @arg @ref LL_HRTIM_TIMER_D
9735 * @arg @ref LL_HRTIM_TIMER_E
9736 * @retval None
9737 */
9739 {
9741 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9744 }
9746 /**
9747 * @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
9748 * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
9749 * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
9750 * @param HRTIMx High Resolution Timer instance
9751 * @param Timer This parameter can be one of the following values:
9752 * @arg @ref LL_HRTIM_TIMER_MASTER
9753 * @arg @ref LL_HRTIM_TIMER_A
9754 * @arg @ref LL_HRTIM_TIMER_B
9755 * @arg @ref LL_HRTIM_TIMER_C
9756 * @arg @ref LL_HRTIM_TIMER_D
9757 * @arg @ref LL_HRTIM_TIMER_E
9758 * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9759 */
9761 {
9763 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9767 }
9769 /**
9770 * @brief Enable the compare 2 DMA request for a given timer.
9771 * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
9772 * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
9773 * @param HRTIMx High Resolution Timer instance
9774 * @param Timer This parameter can be one of the following values:
9775 * @arg @ref LL_HRTIM_TIMER_MASTER
9776 * @arg @ref LL_HRTIM_TIMER_A
9777 * @arg @ref LL_HRTIM_TIMER_B
9778 * @arg @ref LL_HRTIM_TIMER_C
9779 * @arg @ref LL_HRTIM_TIMER_D
9780 * @arg @ref LL_HRTIM_TIMER_E
9781 * @retval None
9782 */
9784 {
9786 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9789 }
9791 /**
9792 * @brief Disable the compare 2 DMA request for a given timer.
9793 * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
9794 * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
9795 * @param HRTIMx High Resolution Timer instance
9796 * @param Timer This parameter can be one of the following values:
9797 * @arg @ref LL_HRTIM_TIMER_MASTER
9798 * @arg @ref LL_HRTIM_TIMER_A
9799 * @arg @ref LL_HRTIM_TIMER_B
9800 * @arg @ref LL_HRTIM_TIMER_C
9801 * @arg @ref LL_HRTIM_TIMER_D
9802 * @arg @ref LL_HRTIM_TIMER_E
9803 * @retval None
9804 */
9806 {
9808 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9811 }
9813 /**
9814 * @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
9815 * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
9816 * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
9817 * @param HRTIMx High Resolution Timer instance
9818 * @param Timer This parameter can be one of the following values:
9819 * @arg @ref LL_HRTIM_TIMER_MASTER
9820 * @arg @ref LL_HRTIM_TIMER_A
9821 * @arg @ref LL_HRTIM_TIMER_B
9822 * @arg @ref LL_HRTIM_TIMER_C
9823 * @arg @ref LL_HRTIM_TIMER_D
9824 * @arg @ref LL_HRTIM_TIMER_E
9825 * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9826 */
9828 {
9830 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9834 }
9836 /**
9837 * @brief Enable the compare 3 DMA request for a given timer.
9838 * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
9839 * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
9840 * @param HRTIMx High Resolution Timer instance
9841 * @param Timer This parameter can be one of the following values:
9842 * @arg @ref LL_HRTIM_TIMER_MASTER
9843 * @arg @ref LL_HRTIM_TIMER_A
9844 * @arg @ref LL_HRTIM_TIMER_B
9845 * @arg @ref LL_HRTIM_TIMER_C
9846 * @arg @ref LL_HRTIM_TIMER_D
9847 * @arg @ref LL_HRTIM_TIMER_E
9848 * @retval None
9849 */
9851 {
9853 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9856 }
9858 /**
9859 * @brief Disable the compare 3 DMA request for a given timer.
9860 * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
9861 * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
9862 * @param HRTIMx High Resolution Timer instance
9863 * @param Timer This parameter can be one of the following values:
9864 * @arg @ref LL_HRTIM_TIMER_MASTER
9865 * @arg @ref LL_HRTIM_TIMER_A
9866 * @arg @ref LL_HRTIM_TIMER_B
9867 * @arg @ref LL_HRTIM_TIMER_C
9868 * @arg @ref LL_HRTIM_TIMER_D
9869 * @arg @ref LL_HRTIM_TIMER_E
9870 * @retval None
9871 */
9873 {
9875 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9878 }
9880 /**
9881 * @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
9882 * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
9883 * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
9884 * @param HRTIMx High Resolution Timer instance
9885 * @param Timer This parameter can be one of the following values:
9886 * @arg @ref LL_HRTIM_TIMER_MASTER
9887 * @arg @ref LL_HRTIM_TIMER_A
9888 * @arg @ref LL_HRTIM_TIMER_B
9889 * @arg @ref LL_HRTIM_TIMER_C
9890 * @arg @ref LL_HRTIM_TIMER_D
9891 * @arg @ref LL_HRTIM_TIMER_E
9892 * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9893 */
9895 {
9897 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9901 }
9903 /**
9904 * @brief Enable the compare 4 DMA request for a given timer.
9905 * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
9906 * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
9907 * @param HRTIMx High Resolution Timer instance
9908 * @param Timer This parameter can be one of the following values:
9909 * @arg @ref LL_HRTIM_TIMER_MASTER
9910 * @arg @ref LL_HRTIM_TIMER_A
9911 * @arg @ref LL_HRTIM_TIMER_B
9912 * @arg @ref LL_HRTIM_TIMER_C
9913 * @arg @ref LL_HRTIM_TIMER_D
9914 * @arg @ref LL_HRTIM_TIMER_E
9915 * @retval None
9916 */
9918 {
9920 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9923 }
9925 /**
9926 * @brief Disable the compare 4 DMA request for a given timer.
9927 * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
9928 * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
9929 * @param HRTIMx High Resolution Timer instance
9930 * @param Timer This parameter can be one of the following values:
9931 * @arg @ref LL_HRTIM_TIMER_MASTER
9932 * @arg @ref LL_HRTIM_TIMER_A
9933 * @arg @ref LL_HRTIM_TIMER_B
9934 * @arg @ref LL_HRTIM_TIMER_C
9935 * @arg @ref LL_HRTIM_TIMER_D
9936 * @arg @ref LL_HRTIM_TIMER_E
9937 * @retval None
9938 */
9940 {
9942 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9945 }
9947 /**
9948 * @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
9949 * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
9950 * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
9951 * @param HRTIMx High Resolution Timer instance
9952 * @param Timer This parameter can be one of the following values:
9953 * @arg @ref LL_HRTIM_TIMER_MASTER
9954 * @arg @ref LL_HRTIM_TIMER_A
9955 * @arg @ref LL_HRTIM_TIMER_B
9956 * @arg @ref LL_HRTIM_TIMER_C
9957 * @arg @ref LL_HRTIM_TIMER_D
9958 * @arg @ref LL_HRTIM_TIMER_E
9959 * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9960 */
9962 {
9964 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9968 }
9970 /**
9971 * @brief Enable the capture 1 DMA request for a given timer.
9972 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
9973 * @param HRTIMx High Resolution Timer instance
9974 * @param Timer This parameter can be one of the following values:
9975 * @arg @ref LL_HRTIM_TIMER_A
9976 * @arg @ref LL_HRTIM_TIMER_B
9977 * @arg @ref LL_HRTIM_TIMER_C
9978 * @arg @ref LL_HRTIM_TIMER_D
9979 * @arg @ref LL_HRTIM_TIMER_E
9980 * @retval None
9981 */
9983 {
9985 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9988 }
9990 /**
9991 * @brief Disable the capture 1 DMA request for a given timer.
9992 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
9993 * @param HRTIMx High Resolution Timer instance
9994 * @param Timer This parameter can be one of the following values:
9995 * @arg @ref LL_HRTIM_TIMER_A
9996 * @arg @ref LL_HRTIM_TIMER_B
9997 * @arg @ref LL_HRTIM_TIMER_C
9998 * @arg @ref LL_HRTIM_TIMER_D
9999 * @arg @ref LL_HRTIM_TIMER_E
10000 * @retval None
10001 */
10003 {
10005 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10008 }
10010 /**
10011 * @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
10012 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
10013 * @param HRTIMx High Resolution Timer instance
10014 * @param Timer This parameter can be one of the following values:
10015 * @arg @ref LL_HRTIM_TIMER_A
10016 * @arg @ref LL_HRTIM_TIMER_B
10017 * @arg @ref LL_HRTIM_TIMER_C
10018 * @arg @ref LL_HRTIM_TIMER_D
10019 * @arg @ref LL_HRTIM_TIMER_E
10020 * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
10021 */
10023 {
10025 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10029 }
10031 /**
10032 * @brief Enable the capture 2 DMA request for a given timer.
10033 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
10034 * @param HRTIMx High Resolution Timer instance
10035 * @param Timer This parameter can be one of the following values:
10036 * @arg @ref LL_HRTIM_TIMER_A
10037 * @arg @ref LL_HRTIM_TIMER_B
10038 * @arg @ref LL_HRTIM_TIMER_C
10039 * @arg @ref LL_HRTIM_TIMER_D
10040 * @arg @ref LL_HRTIM_TIMER_E
10041 * @retval None
10042 */
10044 {
10046 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10049 }
10051 /**
10052 * @brief Disable the capture 2 DMA request for a given timer.
10053 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
10054 * @param HRTIMx High Resolution Timer instance
10055 * @param Timer This parameter can be one of the following values:
10056 * @arg @ref LL_HRTIM_TIMER_A
10057 * @arg @ref LL_HRTIM_TIMER_B
10058 * @arg @ref LL_HRTIM_TIMER_C
10059 * @arg @ref LL_HRTIM_TIMER_D
10060 * @arg @ref LL_HRTIM_TIMER_E
10061 * @retval None
10062 */
10064 {
10066 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10069 }
10071 /**
10072 * @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
10073 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
10074 * @param HRTIMx High Resolution Timer instance
10075 * @param Timer This parameter can be one of the following values:
10076 * @arg @ref LL_HRTIM_TIMER_A
10077 * @arg @ref LL_HRTIM_TIMER_B
10078 * @arg @ref LL_HRTIM_TIMER_C
10079 * @arg @ref LL_HRTIM_TIMER_D
10080 * @arg @ref LL_HRTIM_TIMER_E
10081 * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
10082 */
10084 {
10086 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10090 }
10092 /**
10093 * @brief Enable the output 1 set DMA request for a given timer.
10094 * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
10095 * @param HRTIMx High Resolution Timer instance
10096 * @param Timer This parameter can be one of the following values:
10097 * @arg @ref LL_HRTIM_TIMER_A
10098 * @arg @ref LL_HRTIM_TIMER_B
10099 * @arg @ref LL_HRTIM_TIMER_C
10100 * @arg @ref LL_HRTIM_TIMER_D
10101 * @arg @ref LL_HRTIM_TIMER_E
10102 * @retval None
10103 */
10105 {
10107 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10110 }
10112 /**
10113 * @brief Disable the output 1 set DMA request for a given timer.
10114 * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
10115 * @param HRTIMx High Resolution Timer instance
10116 * @param Timer This parameter can be one of the following values:
10117 * @arg @ref LL_HRTIM_TIMER_A
10118 * @arg @ref LL_HRTIM_TIMER_B
10119 * @arg @ref LL_HRTIM_TIMER_C
10120 * @arg @ref LL_HRTIM_TIMER_D
10121 * @arg @ref LL_HRTIM_TIMER_E
10122 * @retval None
10123 */
10125 {
10127 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10130 }
10132 /**
10133 * @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
10134 * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
10135 * @param HRTIMx High Resolution Timer instance
10136 * @param Timer This parameter can be one of the following values:
10137 * @arg @ref LL_HRTIM_TIMER_A
10138 * @arg @ref LL_HRTIM_TIMER_B
10139 * @arg @ref LL_HRTIM_TIMER_C
10140 * @arg @ref LL_HRTIM_TIMER_D
10141 * @arg @ref LL_HRTIM_TIMER_E
10142 * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10143 */
10145 {
10147 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10151 }
10153 /**
10154 * @brief Enable the output 1 reset DMA request for a given timer.
10155 * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
10156 * @param HRTIMx High Resolution Timer instance
10157 * @param Timer This parameter can be one of the following values:
10158 * @arg @ref LL_HRTIM_TIMER_A
10159 * @arg @ref LL_HRTIM_TIMER_B
10160 * @arg @ref LL_HRTIM_TIMER_C
10161 * @arg @ref LL_HRTIM_TIMER_D
10162 * @arg @ref LL_HRTIM_TIMER_E
10163 * @retval None
10164 */
10166 {
10168 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10171 }
10173 /**
10174 * @brief Disable the output 1 reset DMA request for a given timer.
10175 * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
10176 * @param HRTIMx High Resolution Timer instance
10177 * @param Timer This parameter can be one of the following values:
10178 * @arg @ref LL_HRTIM_TIMER_A
10179 * @arg @ref LL_HRTIM_TIMER_B
10180 * @arg @ref LL_HRTIM_TIMER_C
10181 * @arg @ref LL_HRTIM_TIMER_D
10182 * @arg @ref LL_HRTIM_TIMER_E
10183 * @retval None
10184 */
10186 {
10188 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10191 }
10193 /**
10194 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
10195 * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
10196 * @param HRTIMx High Resolution Timer instance
10197 * @param Timer This parameter can be one of the following values:
10198 * @arg @ref LL_HRTIM_TIMER_A
10199 * @arg @ref LL_HRTIM_TIMER_B
10200 * @arg @ref LL_HRTIM_TIMER_C
10201 * @arg @ref LL_HRTIM_TIMER_D
10202 * @arg @ref LL_HRTIM_TIMER_E
10203 * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10204 */
10206 {
10208 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10212 }
10214 /**
10215 * @brief Enable the output 2 set DMA request for a given timer.
10216 * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
10217 * @param HRTIMx High Resolution Timer instance
10218 * @param Timer This parameter can be one of the following values:
10219 * @arg @ref LL_HRTIM_TIMER_A
10220 * @arg @ref LL_HRTIM_TIMER_B
10221 * @arg @ref LL_HRTIM_TIMER_C
10222 * @arg @ref LL_HRTIM_TIMER_D
10223 * @arg @ref LL_HRTIM_TIMER_E
10224 * @retval None
10225 */
10227 {
10229 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10232 }
10234 /**
10235 * @brief Disable the output 2 set DMA request for a given timer.
10236 * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
10237 * @param HRTIMx High Resolution Timer instance
10238 * @param Timer This parameter can be one of the following values:
10239 * @arg @ref LL_HRTIM_TIMER_A
10240 * @arg @ref LL_HRTIM_TIMER_B
10241 * @arg @ref LL_HRTIM_TIMER_C
10242 * @arg @ref LL_HRTIM_TIMER_D
10243 * @arg @ref LL_HRTIM_TIMER_E
10244 * @retval None
10245 */
10247 {
10249 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10252 }
10254 /**
10255 * @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
10256 * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
10257 * @param HRTIMx High Resolution Timer instance
10258 * @param Timer This parameter can be one of the following values:
10259 * @arg @ref LL_HRTIM_TIMER_A
10260 * @arg @ref LL_HRTIM_TIMER_B
10261 * @arg @ref LL_HRTIM_TIMER_C
10262 * @arg @ref LL_HRTIM_TIMER_D
10263 * @arg @ref LL_HRTIM_TIMER_E
10264 * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10265 */
10267 {
10269 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10273 }
10275 /**
10276 * @brief Enable the output 2 reset DMA request for a given timer.
10277 * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
10278 * @param HRTIMx High Resolution Timer instance
10279 * @param Timer This parameter can be one of the following values:
10280 * @arg @ref LL_HRTIM_TIMER_A
10281 * @arg @ref LL_HRTIM_TIMER_B
10282 * @arg @ref LL_HRTIM_TIMER_C
10283 * @arg @ref LL_HRTIM_TIMER_D
10284 * @arg @ref LL_HRTIM_TIMER_E
10285 * @retval None
10286 */
10288 {
10290 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10293 }
10295 /**
10296 * @brief Disable the output 2 reset DMA request for a given timer.
10297 * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
10298 * @param HRTIMx High Resolution Timer instance
10299 * @param Timer This parameter can be one of the following values:
10300 * @arg @ref LL_HRTIM_TIMER_A
10301 * @arg @ref LL_HRTIM_TIMER_B
10302 * @arg @ref LL_HRTIM_TIMER_C
10303 * @arg @ref LL_HRTIM_TIMER_D
10304 * @arg @ref LL_HRTIM_TIMER_E
10305 * @retval None
10306 */
10308 {
10310 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10313 }
10315 /**
10316 * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
10317 * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
10318 * @param HRTIMx High Resolution Timer instance
10319 * @param Timer This parameter can be one of the following values:
10320 * @arg @ref LL_HRTIM_TIMER_A
10321 * @arg @ref LL_HRTIM_TIMER_B
10322 * @arg @ref LL_HRTIM_TIMER_C
10323 * @arg @ref LL_HRTIM_TIMER_D
10324 * @arg @ref LL_HRTIM_TIMER_E
10325 * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10326 */
10328 {
10330 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10334 }
10336 /**
10337 * @brief Enable the reset/roll-over DMA request for a given timer.
10338 * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
10339 * @param HRTIMx High Resolution Timer instance
10340 * @param Timer This parameter can be one of the following values:
10341 * @arg @ref LL_HRTIM_TIMER_A
10342 * @arg @ref LL_HRTIM_TIMER_B
10343 * @arg @ref LL_HRTIM_TIMER_C
10344 * @arg @ref LL_HRTIM_TIMER_D
10345 * @arg @ref LL_HRTIM_TIMER_E
10346 * @retval None
10347 */
10349 {
10351 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10354 }
10356 /**
10357 * @brief Disable the reset/roll-over DMA request for a given timer.
10358 * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
10359 * @param HRTIMx High Resolution Timer instance
10360 * @param Timer This parameter can be one of the following values:
10361 * @arg @ref LL_HRTIM_TIMER_A
10362 * @arg @ref LL_HRTIM_TIMER_B
10363 * @arg @ref LL_HRTIM_TIMER_C
10364 * @arg @ref LL_HRTIM_TIMER_D
10365 * @arg @ref LL_HRTIM_TIMER_E
10366 * @retval None
10367 */
10369 {
10371 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10374 }
10376 /**
10377 * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
10378 * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
10379 * @param HRTIMx High Resolution Timer instance
10380 * @param Timer This parameter can be one of the following values:
10381 * @arg @ref LL_HRTIM_TIMER_A
10382 * @arg @ref LL_HRTIM_TIMER_B
10383 * @arg @ref LL_HRTIM_TIMER_C
10384 * @arg @ref LL_HRTIM_TIMER_D
10385 * @arg @ref LL_HRTIM_TIMER_E
10386 * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
10387 */
10389 {
10391 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10395 }
10397 /**
10398 * @brief Enable the delayed protection DMA request for a given timer.
10399 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
10400 * @param HRTIMx High Resolution Timer instance
10401 * @param Timer This parameter can be one of the following values:
10402 * @arg @ref LL_HRTIM_TIMER_A
10403 * @arg @ref LL_HRTIM_TIMER_B
10404 * @arg @ref LL_HRTIM_TIMER_C
10405 * @arg @ref LL_HRTIM_TIMER_D
10406 * @arg @ref LL_HRTIM_TIMER_E
10407 * @retval None
10408 */
10410 {
10412 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10415 }
10417 /**
10418 * @brief Disable the delayed protection DMA request for a given timer.
10419 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
10420 * @param HRTIMx High Resolution Timer instance
10421 * @param Timer This parameter can be one of the following values:
10422 * @arg @ref LL_HRTIM_TIMER_A
10423 * @arg @ref LL_HRTIM_TIMER_B
10424 * @arg @ref LL_HRTIM_TIMER_C
10425 * @arg @ref LL_HRTIM_TIMER_D
10426 * @arg @ref LL_HRTIM_TIMER_E
10427 * @retval None
10428 */
10430 {
10432 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10435 }
10437 /**
10438 * @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
10439 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
10440 * @param HRTIMx High Resolution Timer instance
10441 * @param Timer This parameter can be one of the following values:
10442 * @arg @ref LL_HRTIM_TIMER_A
10443 * @arg @ref LL_HRTIM_TIMER_B
10444 * @arg @ref LL_HRTIM_TIMER_C
10445 * @arg @ref LL_HRTIM_TIMER_D
10446 * @arg @ref LL_HRTIM_TIMER_E
10447 * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
10448 */
10449 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10450 {
10452 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10456 }
10458 /**
10459 * @}
10460 */
10462 #if defined(USE_FULL_LL_DRIVER)
10463 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
10464 * @{
10465 */
10467 /**
10468 * @}
10469 */
10472 /**
10473 * @}
10474 */
10476 /**
10477 * @}
10478 */
10482 /**
10483 * @}
10484 */
10486 #ifdef __cplusplus
10487 }
10488 #endif
10492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/