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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_tim.h
blob0953b661eb9bf877ddff239d2a7c4201e0bb624b
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32H7xx_LL_TIM_H
22 #define __STM32H7xx_LL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
36
37 /** @defgroup TIM_LL TIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
44 * @{
45 */
46 static const uint8_t OFFSET_TAB_CCMRx[] =
47 {
48 0x00U, /* 0: TIMx_CH1 */
49 0x00U, /* 1: TIMx_CH1N */
50 0x00U, /* 2: TIMx_CH2 */
51 0x00U, /* 3: TIMx_CH2N */
52 0x04U, /* 4: TIMx_CH3 */
53 0x04U, /* 5: TIMx_CH3N */
54 0x04U, /* 6: TIMx_CH4 */
55 0x3CU, /* 7: TIMx_CH5 */
56 0x3CU /* 8: TIMx_CH6 */
57 };
58
59 static const uint8_t SHIFT_TAB_OCxx[] =
60 {
61 0U, /* 0: OC1M, OC1FE, OC1PE */
62 0U, /* 1: - NA */
63 8U, /* 2: OC2M, OC2FE, OC2PE */
64 0U, /* 3: - NA */
65 0U, /* 4: OC3M, OC3FE, OC3PE */
66 0U, /* 5: - NA */
67 8U, /* 6: OC4M, OC4FE, OC4PE */
68 0U, /* 7: OC5M, OC5FE, OC5PE */
69 8U /* 8: OC6M, OC6FE, OC6PE */
70 };
71
72 static const uint8_t SHIFT_TAB_ICxx[] =
73 {
74 0U, /* 0: CC1S, IC1PSC, IC1F */
75 0U, /* 1: - NA */
76 8U, /* 2: CC2S, IC2PSC, IC2F */
77 0U, /* 3: - NA */
78 0U, /* 4: CC3S, IC3PSC, IC3F */
79 0U, /* 5: - NA */
80 8U, /* 6: CC4S, IC4PSC, IC4F */
81 0U, /* 7: - NA */
82 0U /* 8: - NA */
83 };
84
85 static const uint8_t SHIFT_TAB_CCxP[] =
86 {
87 0U, /* 0: CC1P */
88 2U, /* 1: CC1NP */
89 4U, /* 2: CC2P */
90 6U, /* 3: CC2NP */
91 8U, /* 4: CC3P */
92 10U, /* 5: CC3NP */
93 12U, /* 6: CC4P */
94 16U, /* 7: CC5P */
95 20U /* 8: CC6P */
96 };
97
98 static const uint8_t SHIFT_TAB_OISx[] =
99 {
100 0U, /* 0: OIS1 */
101 1U, /* 1: OIS1N */
102 2U, /* 2: OIS2 */
103 3U, /* 3: OIS2N */
104 4U, /* 4: OIS3 */
105 5U, /* 5: OIS3N */
106 6U, /* 6: OIS4 */
107 8U, /* 7: OIS5 */
108 10U /* 8: OIS6 */
109 };
110 /**
111 * @}
112 */
113
114 /* Private constants ---------------------------------------------------------*/
115 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
116 * @{
117 */
118
119 #if defined(TIM_BREAK_INPUT_SUPPORT)
120 /* Defines used for the bit position in the register and perform offsets */
121 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
122
123 /* Generic bit definitions for TIMx_AF1 register */
124 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
125 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
126 #endif /* TIM_BREAK_INPUT_SUPPORT */
127
128
129 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
130 #define DT_DELAY_1 ((uint8_t)0x7F)
131 #define DT_DELAY_2 ((uint8_t)0x3F)
132 #define DT_DELAY_3 ((uint8_t)0x1F)
133 #define DT_DELAY_4 ((uint8_t)0x1F)
134
135 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
136 #define DT_RANGE_1 ((uint8_t)0x00)
137 #define DT_RANGE_2 ((uint8_t)0x80)
138 #define DT_RANGE_3 ((uint8_t)0xC0)
139 #define DT_RANGE_4 ((uint8_t)0xE0)
140
141
142 /**
143 * @}
144 */
145
146 /* Private macros ------------------------------------------------------------*/
147 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
148 * @{
149 */
150 /** @brief Convert channel id into channel index.
151 * @param __CHANNEL__ This parameter can be one of the following values:
152 * @arg @ref LL_TIM_CHANNEL_CH1
153 * @arg @ref LL_TIM_CHANNEL_CH1N
154 * @arg @ref LL_TIM_CHANNEL_CH2
155 * @arg @ref LL_TIM_CHANNEL_CH2N
156 * @arg @ref LL_TIM_CHANNEL_CH3
157 * @arg @ref LL_TIM_CHANNEL_CH3N
158 * @arg @ref LL_TIM_CHANNEL_CH4
159 * @arg @ref LL_TIM_CHANNEL_CH5
160 * @arg @ref LL_TIM_CHANNEL_CH6
161 * @retval none
162 */
163 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
164 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
165 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
166 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
167 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
172
173 /** @brief Calculate the deadtime sampling period(in ps).
174 * @param __TIMCLK__ timer input clock frequency (in Hz).
175 * @param __CKD__ This parameter can be one of the following values:
176 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
177 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
178 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
179 * @retval none
180 */
181 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
182 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
183 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
184 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
185 /**
186 * @}
187 */
188
189
190 /* Exported types ------------------------------------------------------------*/
191 #if defined(USE_FULL_LL_DRIVER)
192 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
193 * @{
194 */
195
196 /**
197 * @brief TIM Time Base configuration structure definition.
198 */
199 typedef struct
200 {
201 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
202 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
203
204 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
205
206 uint32_t CounterMode; /*!< Specifies the counter mode.
207 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
208
209 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
210
211 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
212 Auto-Reload Register at the next update event.
213 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
214 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
215
216 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
217
218 uint32_t ClockDivision; /*!< Specifies the clock division.
219 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
220
221 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
222
223 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
224 reaches zero, an update event is generated and counting restarts
225 from the RCR value (N).
226 This means in PWM mode that (N+1) corresponds to:
227 - the number of PWM periods in edge-aligned mode
228 - the number of half PWM period in center-aligned mode
229 This parameter must be a number between 0x00 and 0xFF.
230
231 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
232 } LL_TIM_InitTypeDef;
233
234 /**
235 * @brief TIM Output Compare configuration structure definition.
236 */
237 typedef struct
238 {
239 uint32_t OCMode; /*!< Specifies the output mode.
240 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
241
242 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
243
244 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
245 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
246
247 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
248
249 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
250 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
251
252 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
253
254 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
255 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
256
257 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
258
259 uint32_t OCPolarity; /*!< Specifies the output polarity.
260 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
261
262 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
263
264 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
265 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
266
267 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
268
269
270 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
271 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
272
273 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
274
275 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
276 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
277
278 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
279 } LL_TIM_OC_InitTypeDef;
280
281 /**
282 * @brief TIM Input Capture configuration structure definition.
283 */
284
285 typedef struct
286 {
287
288 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
289 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
290
291 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
292
293 uint32_t ICActiveInput; /*!< Specifies the input.
294 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
295
296 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
297
298 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
299 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
300
301 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
302
303 uint32_t ICFilter; /*!< Specifies the input capture filter.
304 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
305
306 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
307 } LL_TIM_IC_InitTypeDef;
308
309
310 /**
311 * @brief TIM Encoder interface configuration structure definition.
312 */
313 typedef struct
314 {
315 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
316 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
317
318 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
319
320 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
321 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
322
323 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
324
325 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
326 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
327
328 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
329
330 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
331 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
332
333 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
334
335 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
336 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
337
338 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
339
340 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
341 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
342
343 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
344
345 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
346 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
347
348 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
349
350 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
351 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
352
353 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
354
355 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
356 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
357
358 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
359
360 } LL_TIM_ENCODER_InitTypeDef;
361
362 /**
363 * @brief TIM Hall sensor interface configuration structure definition.
364 */
365 typedef struct
366 {
367
368 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
369 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
370
371 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
372
373 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
374 Prescaler must be set to get a maximum counter period longer than the
375 time interval between 2 consecutive changes on the Hall inputs.
376 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
377
378 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
379
380 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
381 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
382
383 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
384
385 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
386 A positive pulse (TRGO event) is generated with a programmable delay every time
387 a change occurs on the Hall inputs.
388 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
389
390 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
391 } LL_TIM_HALLSENSOR_InitTypeDef;
392
393 /**
394 * @brief BDTR (Break and Dead Time) structure definition
395 */
396 typedef struct
397 {
398 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
399 This parameter can be a value of @ref TIM_LL_EC_OSSR
400
401 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
402
403 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
404
405 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
406 This parameter can be a value of @ref TIM_LL_EC_OSSI
407
408 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
409
410 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
411
412 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
413 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
414
415 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
416 has been written, their content is frozen until the next reset.*/
417
418 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
419 switching-on of the outputs.
420 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
421
422 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
423
424 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
425
426 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
427 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
428
429 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
430
431 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
432
433 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
434 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
435
436 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
437
438 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
439
440 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
441 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
442
443 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
444
445 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
446
447 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
448 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
449
450 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
451
452 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
453
454 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
455 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
456
457 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
458
459 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
460
461 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
462 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
463
464 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
465
466 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
467
468 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
469 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
470
471 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
472
473 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
474 } LL_TIM_BDTR_InitTypeDef;
475
476 /**
477 * @}
478 */
479 #endif /* USE_FULL_LL_DRIVER */
480
481 /* Exported constants --------------------------------------------------------*/
482 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
483 * @{
484 */
485
486 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
487 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
488 * @{
489 */
490 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
491 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
492 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
493 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
494 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
495 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
496 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
497 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
498 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
499 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
500 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
501 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
502 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
503 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
504 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
505 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
506 /**
507 * @}
508 */
509
510 #if defined(USE_FULL_LL_DRIVER)
511 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
512 * @{
513 */
514 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
515 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
516 /**
517 * @}
518 */
519
520 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
521 * @{
522 */
523 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
524 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
525 /**
526 * @}
527 */
528
529 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
530 * @{
531 */
532 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
533 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
534 /**
535 * @}
536 */
537 #endif /* USE_FULL_LL_DRIVER */
538
539 /** @defgroup TIM_LL_EC_IT IT Defines
540 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
541 * @{
542 */
543 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
544 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
545 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
546 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
547 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
548 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
549 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
550 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
551 /**
552 * @}
553 */
554
555 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
556 * @{
557 */
558 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
559 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
560 /**
561 * @}
562 */
563
564 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
565 * @{
566 */
567 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
568 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
569 /**
570 * @}
571 */
572
573 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
574 * @{
575 */
576 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
577 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
578 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
579 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
580 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
581 /**
582 * @}
583 */
584
585 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
586 * @{
587 */
588 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
589 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
590 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
591 /**
592 * @}
593 */
594
595 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
596 * @{
597 */
598 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
599 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
600 /**
601 * @}
602 */
603
604 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
605 * @{
606 */
607 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
608 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
609 /**
610 * @}
611 */
612
613 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
614 * @{
615 */
616 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
617 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
618 /**
619 * @}
620 */
621
622 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
623 * @{
624 */
625 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
626 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
627 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
628 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
629 /**
630 * @}
631 */
632
633 /** @defgroup TIM_LL_EC_CHANNEL Channel
634 * @{
635 */
636 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
637 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
638 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
639 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
640 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
641 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
642 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
643 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
644 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
645 /**
646 * @}
647 */
648
649 #if defined(USE_FULL_LL_DRIVER)
650 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
651 * @{
652 */
653 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
654 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
655 /**
656 * @}
657 */
658 #endif /* USE_FULL_LL_DRIVER */
659
660 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
661 * @{
662 */
663 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
664 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
665 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
666 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
667 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
668 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
669 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
670 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
671 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
672 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
673 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
674 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
675 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
676 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
677 /**
678 * @}
679 */
680
681 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
682 * @{
683 */
684 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
685 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
686 /**
687 * @}
688 */
689
690 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
691 * @{
692 */
693 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
694 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
695 /**
696 * @}
697 */
698
699 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
700 * @{
701 */
702 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
703 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
704 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
705 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
706 /**
707 * @}
708 */
709
710 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
711 * @{
712 */
713 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
714 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
715 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
716 /**
717 * @}
718 */
719
720 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
721 * @{
722 */
723 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
724 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
725 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
726 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
732 * @{
733 */
734 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
735 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
736 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
737 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
738 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
739 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
740 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
741 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
742 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
743 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
744 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
745 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
746 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
747 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
748 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
749 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
750 /**
751 * @}
752 */
753
754 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
755 * @{
756 */
757 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
758 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
759 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
760 /**
761 * @}
762 */
763
764 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
765 * @{
766 */
767 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
768 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
769 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
770 /**
771 * @}
772 */
773
774 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
775 * @{
776 */
777 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
778 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
779 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
780 /**
781 * @}
782 */
783
784 /** @defgroup TIM_LL_EC_TRGO Trigger Output
785 * @{
786 */
787 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
788 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
789 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
790 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
791 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
792 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
793 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
794 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
795 /**
796 * @}
797 */
798
799 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
800 * @{
801 */
802 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
803 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
804 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
805 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
806 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
807 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
808 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
809 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
810 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
811 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
812 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
813 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
814 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
815 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
816 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
817 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
823 * @{
824 */
825 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
826 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
827 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
828 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
829 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
830 /**
831 * @}
832 */
833
834 /** @defgroup TIM_LL_EC_TS Trigger Selection
835 * @{
836 */
837 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
838 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
839 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
840 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
841 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
842 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
843 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
844 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
845 #define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */
846 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
847 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
848 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
849 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
850 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
851 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
852 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
853 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
854 #define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) is used as trigger input */
855 /**
856 * @}
857 */
858
859 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
860 * @{
861 */
862 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
863 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
864 /**
865 * @}
866 */
867
868 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
869 * @{
870 */
871 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
872 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
873 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
874 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
875 /**
876 * @}
877 */
878
879 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
880 * @{
881 */
882 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
883 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
884 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
885 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
886 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
887 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
888 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
889 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
890 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
891 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
892 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
893 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
894 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
895 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
896 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
897 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
898 /**
899 * @}
900 */
901
902 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
903 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */
904 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */
905 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
906 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
907 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
908 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
909 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
910 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
911
912 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
913 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */
914 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */
915 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */
916 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */
917 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
918 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
919 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
920 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
921
922 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
923 #define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */
924 #define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */
925 #define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
926 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */
927 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
928
929 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
930 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */
931
932 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
933 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
934 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
935 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */
936 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */
937
938 #define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */
939 #define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */
940 #define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */
941
942 #define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */
943 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */
944 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */
945 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */
946 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */
947
948 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
949 * @{
950 */
951 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
952 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
953 /**
954 * @}
955 */
956
957 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
958 * @{
959 */
960 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
961 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
962 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
963 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
964 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
965 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
966 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
967 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
968 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
969 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
970 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
971 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
972 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
973 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
974 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
975 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
976 /**
977 * @}
978 */
979
980 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
981 * @{
982 */
983 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
984 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
985 /**
986 * @}
987 */
988
989 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
990 * @{
991 */
992 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
993 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
994 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
995 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
996 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
997 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
998 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
999 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1000 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1001 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1002 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1003 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1004 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1005 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1006 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1007 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1008 /**
1009 * @}
1010 */
1011
1012 /** @defgroup TIM_LL_EC_OSSI OSSI
1013 * @{
1014 */
1015 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1016 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1017 /**
1018 * @}
1019 */
1020
1021 /** @defgroup TIM_LL_EC_OSSR OSSR
1022 * @{
1023 */
1024 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1025 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1026 /**
1027 * @}
1028 */
1029
1030 #if defined(TIM_BREAK_INPUT_SUPPORT)
1031 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1032 * @{
1033 */
1034 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1035 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1036 /**
1037 * @}
1038 */
1039
1040 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1041 * @{
1042 */
1043 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1044 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1045 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1046 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1047 /**
1048 * @}
1049 */
1050
1051 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1052 * @{
1053 */
1054 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1055 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1056 /**
1057 * @}
1058 */
1059 #endif /* TIM_BREAK_INPUT_SUPPORT */
1060
1061 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1062 * @{
1063 */
1064 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1065 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1066 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1067 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1068 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1069 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1070 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1071 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1072 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1073 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1074 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1075 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1076 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1077 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1078 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1079 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1080 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1081 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1082 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1083 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1084 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1085 #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
1086 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1087 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1088 #endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */
1089 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1090 /**
1091 * @}
1092 */
1093
1094 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1095 * @{
1096 */
1097 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1098 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1099 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1100 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1101 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1102 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1103 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1104 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1105 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1106 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1107 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1108 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1109 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1110 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1111 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1112 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1113 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1114 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1115 /**
1116 * @}
1117 */
1118
1119 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1120 * @{
1121 */
1122 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /* !< TIM1 input 1 is connected to GPIO */
1123 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1 input 1 is connected to COMP1 OUT */
1124 /**
1125 * @}
1126 */
1127
1128 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
1129 * @{
1130 */
1131 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /* !< TIM8 input 1 is connected to GPIO */
1132 #define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8 input 1 is connected to COMP2 OUT */
1133 /**
1134 * @}
1135 */
1136
1137 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
1138 * @{
1139 */
1140 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /* !< TIM2 input 4 is connected to GPIO */
1141 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2 input 4 is connected to COMP1 OUT */
1142 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2 input 4 is connected to COMP2 OUT */
1143 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
1144 /**
1145 * @}
1146 */
1147
1148 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1149 * @{
1150 */
1151 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /* !< TIM3 input 1 is connected to GPIO */
1152 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3 input 1 is connected to COMP1 OUT */
1153 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3 input 1 is connected to COMP2 OUT */
1154 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
1155 /**
1156 * @}
1157 */
1158
1159 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
1160 * @{
1161 */
1162 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /* !< TIM5 input 1 is connected to GPIO */
1163 #define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5 input 1 is connected to CAN TMP */
1164 #define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5 input 1 is connected to CAN RTP */
1165 /**
1166 * @}
1167 */
1168
1169 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 Timer Input Ch1 Remap
1170 * @{
1171 */
1172 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /* !< TIM12 input 1 is connected to GPIO */
1173 #define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 input 1 is connected to SPDIF FS */
1174 /**
1175 * @}
1176 */
1177
1178 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1179 * @{
1180 */
1181 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /* !< TIM15 input 1 is connected to GPIO */
1182 #define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15 input 1 is connected to TIM2 CH1 */
1183 #define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15 input 1 is connected to TIM3 CH1 */
1184 #define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
1185 #define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15 input 1 is connected to RCC LSE */
1186 #define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI */
1187 #define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */
1188 /**
1189 * @}
1190 */
1191
1192 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1193 * @{
1194 */
1195 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /* !< TIM15 input 2 is connected to GPIO */
1196 #define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15 input 2 is connected to TIM2 CH2 */
1197 #define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM3 CH2 */
1198 #define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */
1199 /**
1200 * @}
1201 */
1202
1203 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1204 * @{
1205 */
1206 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /* !< TIM16 input 1 is connected to GPIO */
1207 #define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 input 1 is connected to RCC LSI */
1208 #define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 input 1 is connected to RCC LSE */
1209 #define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */
1210 /**
1211 * @}
1212 */
1213
1214 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1215 * @{
1216 */
1217 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /* !< TIM17 input 1 is connected to GPIO */
1218 #define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 input 1 is connected to SPDIF FS */
1219 #define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
1220 #define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */
1221 /**
1222 * @}
1223 */
1224
1225 /** @defgroup TIM_LL_EC_TIM23_TI4_RMP TIM23 Timer Input Ch4 Remap
1226 * @{
1227 */
1228 #define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /* !< TIM23 input 4 is connected to GPIO */
1229 #define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23 input 4 is connected to COMP1 OUT */
1230 #define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23 input 4 is connected to COMP2 OUT */
1231 #define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
1232 /**
1233 * @}
1234 */
1235
1236 /** @defgroup TIM_LL_EC_TIM24_TI1_RMP TIM24 Timer Input Ch1 Remap
1237 * @{
1238 */
1239 #define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /* !< TIM24 input 1 is connected to GPIO */
1240 #define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */
1241 #define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */
1242 #define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
1243
1244 #if defined(TIM_BREAK_INPUT_SUPPORT)
1245 /** Legacy definitions for compatibility purpose
1246 @cond 0
1247 */
1248 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1249 /**
1250 @endcond
1251 */
1252 #endif /* TIM_BREAK_INPUT_SUPPORT */
1253 /**
1254 * @}
1255 */
1256
1257 /* Exported macro ------------------------------------------------------------*/
1258 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1259 * @{
1260 */
1261
1262 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1263 * @{
1264 */
1265 /**
1266 * @brief Write a value in TIM register.
1267 * @param __INSTANCE__ TIM Instance
1268 * @param __REG__ Register to be written
1269 * @param __VALUE__ Value to be written in the register
1270 * @retval None
1271 */
1272 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1273
1274 /**
1275 * @brief Read a value in TIM register.
1276 * @param __INSTANCE__ TIM Instance
1277 * @param __REG__ Register to be read
1278 * @retval Register value
1279 */
1280 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1281 /**
1282 * @}
1283 */
1284
1285 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1286 * @{
1287 */
1288
1289 /**
1290 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1291 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1292 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1293 * to TIMx_CNT register bit 31)
1294 * @param __CNT__ Counter value
1295 * @retval UIF status bit
1296 */
1297 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1298 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1299
1300 /**
1301 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1302 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1303 * @param __TIMCLK__ timer input clock frequency (in Hz)
1304 * @param __CKD__ This parameter can be one of the following values:
1305 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1306 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1307 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1308 * @param __DT__ deadtime duration (in ns)
1309 * @retval DTG[0:7]
1310 */
1311 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1312 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1313 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1314 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1315 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1316 0U)
1317
1318 /**
1319 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1320 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1321 * @param __TIMCLK__ timer input clock frequency (in Hz)
1322 * @param __CNTCLK__ counter clock frequency (in Hz)
1323 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1324 */
1325 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1326 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
1327
1328 /**
1329 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1330 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1331 * @param __TIMCLK__ timer input clock frequency (in Hz)
1332 * @param __PSC__ prescaler
1333 * @param __FREQ__ output signal frequency (in Hz)
1334 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1335 */
1336 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1337 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1338
1339 /**
1340 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1341 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1342 * @param __TIMCLK__ timer input clock frequency (in Hz)
1343 * @param __PSC__ prescaler
1344 * @param __DELAY__ timer output compare active/inactive delay (in us)
1345 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1346 */
1347 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1348 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1349 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1350
1351 /**
1352 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1353 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1354 * @param __TIMCLK__ timer input clock frequency (in Hz)
1355 * @param __PSC__ prescaler
1356 * @param __DELAY__ timer output compare active/inactive delay (in us)
1357 * @param __PULSE__ pulse duration (in us)
1358 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1359 */
1360 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1361 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1362 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1363
1364 /**
1365 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1366 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1367 * @param __ICPSC__ This parameter can be one of the following values:
1368 * @arg @ref LL_TIM_ICPSC_DIV1
1369 * @arg @ref LL_TIM_ICPSC_DIV2
1370 * @arg @ref LL_TIM_ICPSC_DIV4
1371 * @arg @ref LL_TIM_ICPSC_DIV8
1372 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1373 */
1374 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1375 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1376
1377
1378 /**
1379 * @}
1380 */
1381
1382
1383 /**
1384 * @}
1385 */
1386
1387 /* Exported functions --------------------------------------------------------*/
1388 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1389 * @{
1390 */
1391
1392 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1393 * @{
1394 */
1395 /**
1396 * @brief Enable timer counter.
1397 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1398 * @param TIMx Timer instance
1399 * @retval None
1400 */
1401 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1402 {
1403 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1404 }
1405
1406 /**
1407 * @brief Disable timer counter.
1408 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1409 * @param TIMx Timer instance
1410 * @retval None
1411 */
1412 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1413 {
1414 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1415 }
1416
1417 /**
1418 * @brief Indicates whether the timer counter is enabled.
1419 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1420 * @param TIMx Timer instance
1421 * @retval State of bit (1 or 0).
1422 */
1423 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1424 {
1425 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1426 }
1427
1428 /**
1429 * @brief Enable update event generation.
1430 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1431 * @param TIMx Timer instance
1432 * @retval None
1433 */
1434 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1435 {
1436 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1437 }
1438
1439 /**
1440 * @brief Disable update event generation.
1441 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1442 * @param TIMx Timer instance
1443 * @retval None
1444 */
1445 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1446 {
1447 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1448 }
1449
1450 /**
1451 * @brief Indicates whether update event generation is enabled.
1452 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1453 * @param TIMx Timer instance
1454 * @retval Inverted state of bit (0 or 1).
1455 */
1456 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1457 {
1458 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1459 }
1460
1461 /**
1462 * @brief Set update event source
1463 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1464 * generate an update interrupt or DMA request if enabled:
1465 * - Counter overflow/underflow
1466 * - Setting the UG bit
1467 * - Update generation through the slave mode controller
1468 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1469 * overflow/underflow generates an update interrupt or DMA request if enabled.
1470 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1471 * @param TIMx Timer instance
1472 * @param UpdateSource This parameter can be one of the following values:
1473 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1474 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1475 * @retval None
1476 */
1477 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1478 {
1479 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1480 }
1481
1482 /**
1483 * @brief Get actual event update source
1484 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1485 * @param TIMx Timer instance
1486 * @retval Returned value can be one of the following values:
1487 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1488 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1489 */
1490 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1491 {
1492 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1493 }
1494
1495 /**
1496 * @brief Set one pulse mode (one shot v.s. repetitive).
1497 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1498 * @param TIMx Timer instance
1499 * @param OnePulseMode This parameter can be one of the following values:
1500 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1501 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1502 * @retval None
1503 */
1504 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1505 {
1506 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1507 }
1508
1509 /**
1510 * @brief Get actual one pulse mode.
1511 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1512 * @param TIMx Timer instance
1513 * @retval Returned value can be one of the following values:
1514 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1515 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1516 */
1517 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1518 {
1519 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1520 }
1521
1522 /**
1523 * @brief Set the timer counter counting mode.
1524 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1525 * check whether or not the counter mode selection feature is supported
1526 * by a timer instance.
1527 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1528 * requires a timer reset to avoid unexpected direction
1529 * due to DIR bit readonly in center aligned mode.
1530 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1531 * CR1 CMS LL_TIM_SetCounterMode
1532 * @param TIMx Timer instance
1533 * @param CounterMode This parameter can be one of the following values:
1534 * @arg @ref LL_TIM_COUNTERMODE_UP
1535 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1536 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1537 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1538 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1539 * @retval None
1540 */
1541 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1542 {
1543 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1544 }
1545
1546 /**
1547 * @brief Get actual counter mode.
1548 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1549 * check whether or not the counter mode selection feature is supported
1550 * by a timer instance.
1551 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1552 * CR1 CMS LL_TIM_GetCounterMode
1553 * @param TIMx Timer instance
1554 * @retval Returned value can be one of the following values:
1555 * @arg @ref LL_TIM_COUNTERMODE_UP
1556 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1557 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1558 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1559 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1560 */
1561 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1562 {
1563 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
1564 }
1565
1566 /**
1567 * @brief Enable auto-reload (ARR) preload.
1568 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1569 * @param TIMx Timer instance
1570 * @retval None
1571 */
1572 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1573 {
1574 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1575 }
1576
1577 /**
1578 * @brief Disable auto-reload (ARR) preload.
1579 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1580 * @param TIMx Timer instance
1581 * @retval None
1582 */
1583 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1584 {
1585 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1586 }
1587
1588 /**
1589 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1590 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1591 * @param TIMx Timer instance
1592 * @retval State of bit (1 or 0).
1593 */
1594 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1595 {
1596 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1597 }
1598
1599 /**
1600 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1601 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1602 * whether or not the clock division feature is supported by the timer
1603 * instance.
1604 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1605 * @param TIMx Timer instance
1606 * @param ClockDivision This parameter can be one of the following values:
1607 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1608 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1609 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1610 * @retval None
1611 */
1612 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1613 {
1614 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1615 }
1616
1617 /**
1618 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1619 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1620 * whether or not the clock division feature is supported by the timer
1621 * instance.
1622 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1623 * @param TIMx Timer instance
1624 * @retval Returned value can be one of the following values:
1625 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1626 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1627 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1628 */
1629 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1630 {
1631 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1632 }
1633
1634 /**
1635 * @brief Set the counter value.
1636 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1637 * whether or not a timer instance supports a 32 bits counter.
1638 * @rmtoll CNT CNT LL_TIM_SetCounter
1639 * @param TIMx Timer instance
1640 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1641 * @retval None
1642 */
1643 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1644 {
1645 WRITE_REG(TIMx->CNT, Counter);
1646 }
1647
1648 /**
1649 * @brief Get the counter value.
1650 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1651 * whether or not a timer instance supports a 32 bits counter.
1652 * @rmtoll CNT CNT LL_TIM_GetCounter
1653 * @param TIMx Timer instance
1654 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1655 */
1656 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1657 {
1658 return (uint32_t)(READ_REG(TIMx->CNT));
1659 }
1660
1661 /**
1662 * @brief Get the current direction of the counter
1663 * @rmtoll CR1 DIR LL_TIM_GetDirection
1664 * @param TIMx Timer instance
1665 * @retval Returned value can be one of the following values:
1666 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1667 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1668 */
1669 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1670 {
1671 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1672 }
1673
1674 /**
1675 * @brief Set the prescaler value.
1676 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1677 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1678 * prescaler ratio is taken into account at the next update event.
1679 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1680 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1681 * @param TIMx Timer instance
1682 * @param Prescaler between Min_Data=0 and Max_Data=65535
1683 * @retval None
1684 */
1685 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1686 {
1687 WRITE_REG(TIMx->PSC, Prescaler);
1688 }
1689
1690 /**
1691 * @brief Get the prescaler value.
1692 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1693 * @param TIMx Timer instance
1694 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1695 */
1696 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1697 {
1698 return (uint32_t)(READ_REG(TIMx->PSC));
1699 }
1700
1701 /**
1702 * @brief Set the auto-reload value.
1703 * @note The counter is blocked while the auto-reload value is null.
1704 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1705 * whether or not a timer instance supports a 32 bits counter.
1706 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1707 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1708 * @param TIMx Timer instance
1709 * @param AutoReload between Min_Data=0 and Max_Data=65535
1710 * @retval None
1711 */
1712 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1713 {
1714 WRITE_REG(TIMx->ARR, AutoReload);
1715 }
1716
1717 /**
1718 * @brief Get the auto-reload value.
1719 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1720 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1721 * whether or not a timer instance supports a 32 bits counter.
1722 * @param TIMx Timer instance
1723 * @retval Auto-reload value
1724 */
1725 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1726 {
1727 return (uint32_t)(READ_REG(TIMx->ARR));
1728 }
1729
1730 /**
1731 * @brief Set the repetition counter value.
1732 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1733 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1734 * whether or not a timer instance supports a repetition counter.
1735 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1736 * @param TIMx Timer instance
1737 * @param RepetitionCounter between Min_Data=0 and Max_Data=255
1738 * @retval None
1739 */
1740 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1741 {
1742 WRITE_REG(TIMx->RCR, RepetitionCounter);
1743 }
1744
1745 /**
1746 * @brief Get the repetition counter value.
1747 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1748 * whether or not a timer instance supports a repetition counter.
1749 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1750 * @param TIMx Timer instance
1751 * @retval Repetition counter value
1752 */
1753 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1754 {
1755 return (uint32_t)(READ_REG(TIMx->RCR));
1756 }
1757
1758 /**
1759 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1760 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
1761 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1762 * @param TIMx Timer instance
1763 * @retval None
1764 */
1765 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1766 {
1767 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1768 }
1769
1770 /**
1771 * @brief Disable update interrupt flag (UIF) remapping.
1772 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1773 * @param TIMx Timer instance
1774 * @retval None
1775 */
1776 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1777 {
1778 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1779 }
1780
1781 /**
1782 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1783 * @param Counter Counter value
1784 * @retval State of bit (1 or 0).
1785 */
1786 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
1787 {
1788 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1789 }
1790
1791 /**
1792 * @}
1793 */
1794
1795 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1796 * @{
1797 */
1798 /**
1799 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1800 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1801 * they are updated only when a commutation event (COM) occurs.
1802 * @note Only on channels that have a complementary output.
1803 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1804 * whether or not a timer instance is able to generate a commutation event.
1805 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1806 * @param TIMx Timer instance
1807 * @retval None
1808 */
1809 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1810 {
1811 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1812 }
1813
1814 /**
1815 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1816 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1817 * whether or not a timer instance is able to generate a commutation event.
1818 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1819 * @param TIMx Timer instance
1820 * @retval None
1821 */
1822 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1823 {
1824 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1825 }
1826
1827 /**
1828 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1829 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1830 * whether or not a timer instance is able to generate a commutation event.
1831 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1832 * @param TIMx Timer instance
1833 * @param CCUpdateSource This parameter can be one of the following values:
1834 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1835 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1836 * @retval None
1837 */
1838 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1839 {
1840 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1841 }
1842
1843 /**
1844 * @brief Set the trigger of the capture/compare DMA request.
1845 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1846 * @param TIMx Timer instance
1847 * @param DMAReqTrigger This parameter can be one of the following values:
1848 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1849 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1850 * @retval None
1851 */
1852 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1853 {
1854 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1855 }
1856
1857 /**
1858 * @brief Get actual trigger of the capture/compare DMA request.
1859 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1860 * @param TIMx Timer instance
1861 * @retval Returned value can be one of the following values:
1862 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1863 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1864 */
1865 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1866 {
1867 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1868 }
1869
1870 /**
1871 * @brief Set the lock level to freeze the
1872 * configuration of several capture/compare parameters.
1873 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1874 * the lock mechanism is supported by a timer instance.
1875 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1876 * @param TIMx Timer instance
1877 * @param LockLevel This parameter can be one of the following values:
1878 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1879 * @arg @ref LL_TIM_LOCKLEVEL_1
1880 * @arg @ref LL_TIM_LOCKLEVEL_2
1881 * @arg @ref LL_TIM_LOCKLEVEL_3
1882 * @retval None
1883 */
1884 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1885 {
1886 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1887 }
1888
1889 /**
1890 * @brief Enable capture/compare channels.
1891 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1892 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1893 * CCER CC2E LL_TIM_CC_EnableChannel\n
1894 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1895 * CCER CC3E LL_TIM_CC_EnableChannel\n
1896 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1897 * CCER CC4E LL_TIM_CC_EnableChannel\n
1898 * CCER CC5E LL_TIM_CC_EnableChannel\n
1899 * CCER CC6E LL_TIM_CC_EnableChannel
1900 * @param TIMx Timer instance
1901 * @param Channels This parameter can be a combination of the following values:
1902 * @arg @ref LL_TIM_CHANNEL_CH1
1903 * @arg @ref LL_TIM_CHANNEL_CH1N
1904 * @arg @ref LL_TIM_CHANNEL_CH2
1905 * @arg @ref LL_TIM_CHANNEL_CH2N
1906 * @arg @ref LL_TIM_CHANNEL_CH3
1907 * @arg @ref LL_TIM_CHANNEL_CH3N
1908 * @arg @ref LL_TIM_CHANNEL_CH4
1909 * @arg @ref LL_TIM_CHANNEL_CH5
1910 * @arg @ref LL_TIM_CHANNEL_CH6
1911 * @retval None
1912 */
1913 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1914 {
1915 SET_BIT(TIMx->CCER, Channels);
1916 }
1917
1918 /**
1919 * @brief Disable capture/compare channels.
1920 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1921 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1922 * CCER CC2E LL_TIM_CC_DisableChannel\n
1923 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1924 * CCER CC3E LL_TIM_CC_DisableChannel\n
1925 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1926 * CCER CC4E LL_TIM_CC_DisableChannel\n
1927 * CCER CC5E LL_TIM_CC_DisableChannel\n
1928 * CCER CC6E LL_TIM_CC_DisableChannel
1929 * @param TIMx Timer instance
1930 * @param Channels This parameter can be a combination of the following values:
1931 * @arg @ref LL_TIM_CHANNEL_CH1
1932 * @arg @ref LL_TIM_CHANNEL_CH1N
1933 * @arg @ref LL_TIM_CHANNEL_CH2
1934 * @arg @ref LL_TIM_CHANNEL_CH2N
1935 * @arg @ref LL_TIM_CHANNEL_CH3
1936 * @arg @ref LL_TIM_CHANNEL_CH3N
1937 * @arg @ref LL_TIM_CHANNEL_CH4
1938 * @arg @ref LL_TIM_CHANNEL_CH5
1939 * @arg @ref LL_TIM_CHANNEL_CH6
1940 * @retval None
1941 */
1942 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1943 {
1944 CLEAR_BIT(TIMx->CCER, Channels);
1945 }
1946
1947 /**
1948 * @brief Indicate whether channel(s) is(are) enabled.
1949 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1950 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1951 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1952 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1953 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1954 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1955 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1956 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1957 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1958 * @param TIMx Timer instance
1959 * @param Channels This parameter can be a combination of the following values:
1960 * @arg @ref LL_TIM_CHANNEL_CH1
1961 * @arg @ref LL_TIM_CHANNEL_CH1N
1962 * @arg @ref LL_TIM_CHANNEL_CH2
1963 * @arg @ref LL_TIM_CHANNEL_CH2N
1964 * @arg @ref LL_TIM_CHANNEL_CH3
1965 * @arg @ref LL_TIM_CHANNEL_CH3N
1966 * @arg @ref LL_TIM_CHANNEL_CH4
1967 * @arg @ref LL_TIM_CHANNEL_CH5
1968 * @arg @ref LL_TIM_CHANNEL_CH6
1969 * @retval State of bit (1 or 0).
1970 */
1971 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1972 {
1973 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1974 }
1975
1976 /**
1977 * @}
1978 */
1979
1980 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1981 * @{
1982 */
1983 /**
1984 * @brief Configure an output channel.
1985 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1986 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1987 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1988 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1989 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1990 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1991 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1992 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1993 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1994 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1995 * CCER CC5P LL_TIM_OC_ConfigOutput\n
1996 * CCER CC6P LL_TIM_OC_ConfigOutput\n
1997 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1998 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1999 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2000 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2001 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2002 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2003 * @param TIMx Timer instance
2004 * @param Channel This parameter can be one of the following values:
2005 * @arg @ref LL_TIM_CHANNEL_CH1
2006 * @arg @ref LL_TIM_CHANNEL_CH2
2007 * @arg @ref LL_TIM_CHANNEL_CH3
2008 * @arg @ref LL_TIM_CHANNEL_CH4
2009 * @arg @ref LL_TIM_CHANNEL_CH5
2010 * @arg @ref LL_TIM_CHANNEL_CH6
2011 * @param Configuration This parameter must be a combination of all the following values:
2012 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2013 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2014 * @retval None
2015 */
2016 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2017 {
2018 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2019 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2020 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2021 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2022 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2023 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2024 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2025 }
2026
2027 /**
2028 * @brief Define the behavior of the output reference signal OCxREF from which
2029 * OCx and OCxN (when relevant) are derived.
2030 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2031 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2032 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2033 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2034 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2035 * CCMR3 OC6M LL_TIM_OC_SetMode
2036 * @param TIMx Timer instance
2037 * @param Channel This parameter can be one of the following values:
2038 * @arg @ref LL_TIM_CHANNEL_CH1
2039 * @arg @ref LL_TIM_CHANNEL_CH2
2040 * @arg @ref LL_TIM_CHANNEL_CH3
2041 * @arg @ref LL_TIM_CHANNEL_CH4
2042 * @arg @ref LL_TIM_CHANNEL_CH5
2043 * @arg @ref LL_TIM_CHANNEL_CH6
2044 * @param Mode This parameter can be one of the following values:
2045 * @arg @ref LL_TIM_OCMODE_FROZEN
2046 * @arg @ref LL_TIM_OCMODE_ACTIVE
2047 * @arg @ref LL_TIM_OCMODE_INACTIVE
2048 * @arg @ref LL_TIM_OCMODE_TOGGLE
2049 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2050 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2051 * @arg @ref LL_TIM_OCMODE_PWM1
2052 * @arg @ref LL_TIM_OCMODE_PWM2
2053 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2054 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2055 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2056 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2057 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2058 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2059 * @retval None
2060 */
2061 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2062 {
2063 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2064 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2065 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2066 }
2067
2068 /**
2069 * @brief Get the output compare mode of an output channel.
2070 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2071 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2072 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2073 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2074 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2075 * CCMR3 OC6M LL_TIM_OC_GetMode
2076 * @param TIMx Timer instance
2077 * @param Channel This parameter can be one of the following values:
2078 * @arg @ref LL_TIM_CHANNEL_CH1
2079 * @arg @ref LL_TIM_CHANNEL_CH2
2080 * @arg @ref LL_TIM_CHANNEL_CH3
2081 * @arg @ref LL_TIM_CHANNEL_CH4
2082 * @arg @ref LL_TIM_CHANNEL_CH5
2083 * @arg @ref LL_TIM_CHANNEL_CH6
2084 * @retval Returned value can be one of the following values:
2085 * @arg @ref LL_TIM_OCMODE_FROZEN
2086 * @arg @ref LL_TIM_OCMODE_ACTIVE
2087 * @arg @ref LL_TIM_OCMODE_INACTIVE
2088 * @arg @ref LL_TIM_OCMODE_TOGGLE
2089 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2090 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2091 * @arg @ref LL_TIM_OCMODE_PWM1
2092 * @arg @ref LL_TIM_OCMODE_PWM2
2093 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2094 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2095 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2096 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2097 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2098 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2099 */
2100 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
2101 {
2102 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2103 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2104 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2105 }
2106
2107 /**
2108 * @brief Set the polarity of an output channel.
2109 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2110 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2111 * CCER CC2P LL_TIM_OC_SetPolarity\n
2112 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2113 * CCER CC3P LL_TIM_OC_SetPolarity\n
2114 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2115 * CCER CC4P LL_TIM_OC_SetPolarity\n
2116 * CCER CC5P LL_TIM_OC_SetPolarity\n
2117 * CCER CC6P LL_TIM_OC_SetPolarity
2118 * @param TIMx Timer instance
2119 * @param Channel This parameter can be one of the following values:
2120 * @arg @ref LL_TIM_CHANNEL_CH1
2121 * @arg @ref LL_TIM_CHANNEL_CH1N
2122 * @arg @ref LL_TIM_CHANNEL_CH2
2123 * @arg @ref LL_TIM_CHANNEL_CH2N
2124 * @arg @ref LL_TIM_CHANNEL_CH3
2125 * @arg @ref LL_TIM_CHANNEL_CH3N
2126 * @arg @ref LL_TIM_CHANNEL_CH4
2127 * @arg @ref LL_TIM_CHANNEL_CH5
2128 * @arg @ref LL_TIM_CHANNEL_CH6
2129 * @param Polarity This parameter can be one of the following values:
2130 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2131 * @arg @ref LL_TIM_OCPOLARITY_LOW
2132 * @retval None
2133 */
2134 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2135 {
2136 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2137 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2138 }
2139
2140 /**
2141 * @brief Get the polarity of an output channel.
2142 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2143 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2144 * CCER CC2P LL_TIM_OC_GetPolarity\n
2145 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2146 * CCER CC3P LL_TIM_OC_GetPolarity\n
2147 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2148 * CCER CC4P LL_TIM_OC_GetPolarity\n
2149 * CCER CC5P LL_TIM_OC_GetPolarity\n
2150 * CCER CC6P LL_TIM_OC_GetPolarity
2151 * @param TIMx Timer instance
2152 * @param Channel This parameter can be one of the following values:
2153 * @arg @ref LL_TIM_CHANNEL_CH1
2154 * @arg @ref LL_TIM_CHANNEL_CH1N
2155 * @arg @ref LL_TIM_CHANNEL_CH2
2156 * @arg @ref LL_TIM_CHANNEL_CH2N
2157 * @arg @ref LL_TIM_CHANNEL_CH3
2158 * @arg @ref LL_TIM_CHANNEL_CH3N
2159 * @arg @ref LL_TIM_CHANNEL_CH4
2160 * @arg @ref LL_TIM_CHANNEL_CH5
2161 * @arg @ref LL_TIM_CHANNEL_CH6
2162 * @retval Returned value can be one of the following values:
2163 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2164 * @arg @ref LL_TIM_OCPOLARITY_LOW
2165 */
2166 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2167 {
2168 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2169 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2170 }
2171
2172 /**
2173 * @brief Set the IDLE state of an output channel
2174 * @note This function is significant only for the timer instances
2175 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2176 * can be used to check whether or not a timer instance provides
2177 * a break input.
2178 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2179 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2180 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2181 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2182 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2183 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2184 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2185 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2186 * CR2 OIS6 LL_TIM_OC_SetIdleState
2187 * @param TIMx Timer instance
2188 * @param Channel This parameter can be one of the following values:
2189 * @arg @ref LL_TIM_CHANNEL_CH1
2190 * @arg @ref LL_TIM_CHANNEL_CH1N
2191 * @arg @ref LL_TIM_CHANNEL_CH2
2192 * @arg @ref LL_TIM_CHANNEL_CH2N
2193 * @arg @ref LL_TIM_CHANNEL_CH3
2194 * @arg @ref LL_TIM_CHANNEL_CH3N
2195 * @arg @ref LL_TIM_CHANNEL_CH4
2196 * @arg @ref LL_TIM_CHANNEL_CH5
2197 * @arg @ref LL_TIM_CHANNEL_CH6
2198 * @param IdleState This parameter can be one of the following values:
2199 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2200 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2201 * @retval None
2202 */
2203 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2204 {
2205 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2206 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2207 }
2208
2209 /**
2210 * @brief Get the IDLE state of an output channel
2211 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2212 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2213 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2214 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2215 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2216 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2217 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2218 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2219 * CR2 OIS6 LL_TIM_OC_GetIdleState
2220 * @param TIMx Timer instance
2221 * @param Channel This parameter can be one of the following values:
2222 * @arg @ref LL_TIM_CHANNEL_CH1
2223 * @arg @ref LL_TIM_CHANNEL_CH1N
2224 * @arg @ref LL_TIM_CHANNEL_CH2
2225 * @arg @ref LL_TIM_CHANNEL_CH2N
2226 * @arg @ref LL_TIM_CHANNEL_CH3
2227 * @arg @ref LL_TIM_CHANNEL_CH3N
2228 * @arg @ref LL_TIM_CHANNEL_CH4
2229 * @arg @ref LL_TIM_CHANNEL_CH5
2230 * @arg @ref LL_TIM_CHANNEL_CH6
2231 * @retval Returned value can be one of the following values:
2232 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2233 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2234 */
2235 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2236 {
2237 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2238 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2239 }
2240
2241 /**
2242 * @brief Enable fast mode for the output channel.
2243 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2244 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2245 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2246 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2247 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2248 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2249 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2250 * @param TIMx Timer instance
2251 * @param Channel This parameter can be one of the following values:
2252 * @arg @ref LL_TIM_CHANNEL_CH1
2253 * @arg @ref LL_TIM_CHANNEL_CH2
2254 * @arg @ref LL_TIM_CHANNEL_CH3
2255 * @arg @ref LL_TIM_CHANNEL_CH4
2256 * @arg @ref LL_TIM_CHANNEL_CH5
2257 * @arg @ref LL_TIM_CHANNEL_CH6
2258 * @retval None
2259 */
2260 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2261 {
2262 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2263 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2264 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2265
2266 }
2267
2268 /**
2269 * @brief Disable fast mode for the output channel.
2270 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2271 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2272 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2273 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2274 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2275 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2276 * @param TIMx Timer instance
2277 * @param Channel This parameter can be one of the following values:
2278 * @arg @ref LL_TIM_CHANNEL_CH1
2279 * @arg @ref LL_TIM_CHANNEL_CH2
2280 * @arg @ref LL_TIM_CHANNEL_CH3
2281 * @arg @ref LL_TIM_CHANNEL_CH4
2282 * @arg @ref LL_TIM_CHANNEL_CH5
2283 * @arg @ref LL_TIM_CHANNEL_CH6
2284 * @retval None
2285 */
2286 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2287 {
2288 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2289 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2290 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2291
2292 }
2293
2294 /**
2295 * @brief Indicates whether fast mode is enabled for the output channel.
2296 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2297 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2298 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2299 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2300 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2301 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2302 * @param TIMx Timer instance
2303 * @param Channel This parameter can be one of the following values:
2304 * @arg @ref LL_TIM_CHANNEL_CH1
2305 * @arg @ref LL_TIM_CHANNEL_CH2
2306 * @arg @ref LL_TIM_CHANNEL_CH3
2307 * @arg @ref LL_TIM_CHANNEL_CH4
2308 * @arg @ref LL_TIM_CHANNEL_CH5
2309 * @arg @ref LL_TIM_CHANNEL_CH6
2310 * @retval State of bit (1 or 0).
2311 */
2312 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2313 {
2314 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2315 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2316 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2317 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2318 }
2319
2320 /**
2321 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2322 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2323 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2324 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2325 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2326 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2327 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2328 * @param TIMx Timer instance
2329 * @param Channel This parameter can be one of the following values:
2330 * @arg @ref LL_TIM_CHANNEL_CH1
2331 * @arg @ref LL_TIM_CHANNEL_CH2
2332 * @arg @ref LL_TIM_CHANNEL_CH3
2333 * @arg @ref LL_TIM_CHANNEL_CH4
2334 * @arg @ref LL_TIM_CHANNEL_CH5
2335 * @arg @ref LL_TIM_CHANNEL_CH6
2336 * @retval None
2337 */
2338 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2339 {
2340 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2341 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2342 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2343 }
2344
2345 /**
2346 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2347 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2348 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2349 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2350 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2351 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2352 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2353 * @param TIMx Timer instance
2354 * @param Channel This parameter can be one of the following values:
2355 * @arg @ref LL_TIM_CHANNEL_CH1
2356 * @arg @ref LL_TIM_CHANNEL_CH2
2357 * @arg @ref LL_TIM_CHANNEL_CH3
2358 * @arg @ref LL_TIM_CHANNEL_CH4
2359 * @arg @ref LL_TIM_CHANNEL_CH5
2360 * @arg @ref LL_TIM_CHANNEL_CH6
2361 * @retval None
2362 */
2363 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2364 {
2365 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2366 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2367 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2368 }
2369
2370 /**
2371 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2372 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2373 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2374 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2375 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2376 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2377 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2378 * @param TIMx Timer instance
2379 * @param Channel This parameter can be one of the following values:
2380 * @arg @ref LL_TIM_CHANNEL_CH1
2381 * @arg @ref LL_TIM_CHANNEL_CH2
2382 * @arg @ref LL_TIM_CHANNEL_CH3
2383 * @arg @ref LL_TIM_CHANNEL_CH4
2384 * @arg @ref LL_TIM_CHANNEL_CH5
2385 * @arg @ref LL_TIM_CHANNEL_CH6
2386 * @retval State of bit (1 or 0).
2387 */
2388 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2389 {
2390 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2391 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2392 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2393 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2394 }
2395
2396 /**
2397 * @brief Enable clearing the output channel on an external event.
2398 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2399 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2400 * or not a timer instance can clear the OCxREF signal on an external event.
2401 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2402 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2403 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2404 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2405 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2406 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2407 * @param TIMx Timer instance
2408 * @param Channel This parameter can be one of the following values:
2409 * @arg @ref LL_TIM_CHANNEL_CH1
2410 * @arg @ref LL_TIM_CHANNEL_CH2
2411 * @arg @ref LL_TIM_CHANNEL_CH3
2412 * @arg @ref LL_TIM_CHANNEL_CH4
2413 * @arg @ref LL_TIM_CHANNEL_CH5
2414 * @arg @ref LL_TIM_CHANNEL_CH6
2415 * @retval None
2416 */
2417 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2418 {
2419 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2420 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2421 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2422 }
2423
2424 /**
2425 * @brief Disable clearing the output channel on an external event.
2426 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2427 * or not a timer instance can clear the OCxREF signal on an external event.
2428 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2429 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2430 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2431 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2432 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2433 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2434 * @param TIMx Timer instance
2435 * @param Channel This parameter can be one of the following values:
2436 * @arg @ref LL_TIM_CHANNEL_CH1
2437 * @arg @ref LL_TIM_CHANNEL_CH2
2438 * @arg @ref LL_TIM_CHANNEL_CH3
2439 * @arg @ref LL_TIM_CHANNEL_CH4
2440 * @arg @ref LL_TIM_CHANNEL_CH5
2441 * @arg @ref LL_TIM_CHANNEL_CH6
2442 * @retval None
2443 */
2444 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2445 {
2446 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2447 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2448 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2449 }
2450
2451 /**
2452 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2453 * @note This function enables clearing the output channel on an external event.
2454 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2455 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2456 * or not a timer instance can clear the OCxREF signal on an external event.
2457 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2458 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2459 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2460 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2461 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2462 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2463 * @param TIMx Timer instance
2464 * @param Channel This parameter can be one of the following values:
2465 * @arg @ref LL_TIM_CHANNEL_CH1
2466 * @arg @ref LL_TIM_CHANNEL_CH2
2467 * @arg @ref LL_TIM_CHANNEL_CH3
2468 * @arg @ref LL_TIM_CHANNEL_CH4
2469 * @arg @ref LL_TIM_CHANNEL_CH5
2470 * @arg @ref LL_TIM_CHANNEL_CH6
2471 * @retval State of bit (1 or 0).
2472 */
2473 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2474 {
2475 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2476 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2477 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2478 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2479 }
2480
2481 /**
2482 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
2483 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2484 * dead-time insertion feature is supported by a timer instance.
2485 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2486 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2487 * @param TIMx Timer instance
2488 * @param DeadTime between Min_Data=0 and Max_Data=255
2489 * @retval None
2490 */
2491 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2492 {
2493 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2494 }
2495
2496 /**
2497 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2498 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2499 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2500 * whether or not a timer instance supports a 32 bits counter.
2501 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2502 * output channel 1 is supported by a timer instance.
2503 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2504 * @param TIMx Timer instance
2505 * @param CompareValue between Min_Data=0 and Max_Data=65535
2506 * @retval None
2507 */
2508 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2509 {
2510 WRITE_REG(TIMx->CCR1, CompareValue);
2511 }
2512
2513 /**
2514 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2515 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2516 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2517 * whether or not a timer instance supports a 32 bits counter.
2518 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2519 * output channel 2 is supported by a timer instance.
2520 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2521 * @param TIMx Timer instance
2522 * @param CompareValue between Min_Data=0 and Max_Data=65535
2523 * @retval None
2524 */
2525 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2526 {
2527 WRITE_REG(TIMx->CCR2, CompareValue);
2528 }
2529
2530 /**
2531 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2532 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2533 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2534 * whether or not a timer instance supports a 32 bits counter.
2535 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2536 * output channel is supported by a timer instance.
2537 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2538 * @param TIMx Timer instance
2539 * @param CompareValue between Min_Data=0 and Max_Data=65535
2540 * @retval None
2541 */
2542 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2543 {
2544 WRITE_REG(TIMx->CCR3, CompareValue);
2545 }
2546
2547 /**
2548 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2549 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2550 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2551 * whether or not a timer instance supports a 32 bits counter.
2552 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2553 * output channel 4 is supported by a timer instance.
2554 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2555 * @param TIMx Timer instance
2556 * @param CompareValue between Min_Data=0 and Max_Data=65535
2557 * @retval None
2558 */
2559 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2560 {
2561 WRITE_REG(TIMx->CCR4, CompareValue);
2562 }
2563
2564 /**
2565 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2566 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2567 * output channel 5 is supported by a timer instance.
2568 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2569 * @param TIMx Timer instance
2570 * @param CompareValue between Min_Data=0 and Max_Data=65535
2571 * @retval None
2572 */
2573 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2574 {
2575 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2576 }
2577
2578 /**
2579 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2580 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2581 * output channel 6 is supported by a timer instance.
2582 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2583 * @param TIMx Timer instance
2584 * @param CompareValue between Min_Data=0 and Max_Data=65535
2585 * @retval None
2586 */
2587 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2588 {
2589 WRITE_REG(TIMx->CCR6, CompareValue);
2590 }
2591
2592 /**
2593 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2594 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2595 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2596 * whether or not a timer instance supports a 32 bits counter.
2597 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2598 * output channel 1 is supported by a timer instance.
2599 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2600 * @param TIMx Timer instance
2601 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2602 */
2603 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2604 {
2605 return (uint32_t)(READ_REG(TIMx->CCR1));
2606 }
2607
2608 /**
2609 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2610 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2611 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2612 * whether or not a timer instance supports a 32 bits counter.
2613 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2614 * output channel 2 is supported by a timer instance.
2615 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2616 * @param TIMx Timer instance
2617 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2618 */
2619 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2620 {
2621 return (uint32_t)(READ_REG(TIMx->CCR2));
2622 }
2623
2624 /**
2625 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2626 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2627 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2628 * whether or not a timer instance supports a 32 bits counter.
2629 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2630 * output channel 3 is supported by a timer instance.
2631 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2632 * @param TIMx Timer instance
2633 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2634 */
2635 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2636 {
2637 return (uint32_t)(READ_REG(TIMx->CCR3));
2638 }
2639
2640 /**
2641 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2642 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2643 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2644 * whether or not a timer instance supports a 32 bits counter.
2645 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2646 * output channel 4 is supported by a timer instance.
2647 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2648 * @param TIMx Timer instance
2649 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2650 */
2651 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2652 {
2653 return (uint32_t)(READ_REG(TIMx->CCR4));
2654 }
2655
2656 /**
2657 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2658 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2659 * output channel 5 is supported by a timer instance.
2660 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2661 * @param TIMx Timer instance
2662 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2663 */
2664 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
2665 {
2666 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2667 }
2668
2669 /**
2670 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2671 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2672 * output channel 6 is supported by a timer instance.
2673 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2674 * @param TIMx Timer instance
2675 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2676 */
2677 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
2678 {
2679 return (uint32_t)(READ_REG(TIMx->CCR6));
2680 }
2681
2682 /**
2683 * @brief Select on which reference signal the OC5REF is combined to.
2684 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2685 * whether or not a timer instance supports the combined 3-phase PWM mode.
2686 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2687 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2688 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2689 * @param TIMx Timer instance
2690 * @param GroupCH5 This parameter can be a combination of the following values:
2691 * @arg @ref LL_TIM_GROUPCH5_NONE
2692 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2693 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2694 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2695 * @retval None
2696 */
2697 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2698 {
2699 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2700 }
2701
2702 /**
2703 * @}
2704 */
2705
2706 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2707 * @{
2708 */
2709 /**
2710 * @brief Configure input channel.
2711 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2712 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2713 * CCMR1 IC1F LL_TIM_IC_Config\n
2714 * CCMR1 CC2S LL_TIM_IC_Config\n
2715 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2716 * CCMR1 IC2F LL_TIM_IC_Config\n
2717 * CCMR2 CC3S LL_TIM_IC_Config\n
2718 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2719 * CCMR2 IC3F LL_TIM_IC_Config\n
2720 * CCMR2 CC4S LL_TIM_IC_Config\n
2721 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2722 * CCMR2 IC4F LL_TIM_IC_Config\n
2723 * CCER CC1P LL_TIM_IC_Config\n
2724 * CCER CC1NP LL_TIM_IC_Config\n
2725 * CCER CC2P LL_TIM_IC_Config\n
2726 * CCER CC2NP LL_TIM_IC_Config\n
2727 * CCER CC3P LL_TIM_IC_Config\n
2728 * CCER CC3NP LL_TIM_IC_Config\n
2729 * CCER CC4P LL_TIM_IC_Config\n
2730 * CCER CC4NP LL_TIM_IC_Config
2731 * @param TIMx Timer instance
2732 * @param Channel This parameter can be one of the following values:
2733 * @arg @ref LL_TIM_CHANNEL_CH1
2734 * @arg @ref LL_TIM_CHANNEL_CH2
2735 * @arg @ref LL_TIM_CHANNEL_CH3
2736 * @arg @ref LL_TIM_CHANNEL_CH4
2737 * @param Configuration This parameter must be a combination of all the following values:
2738 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2739 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2740 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2741 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2742 * @retval None
2743 */
2744 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2745 {
2746 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2747 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2748 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2749 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2750 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2751 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2752 }
2753
2754 /**
2755 * @brief Set the active input.
2756 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2757 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2758 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2759 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2760 * @param TIMx Timer instance
2761 * @param Channel This parameter can be one of the following values:
2762 * @arg @ref LL_TIM_CHANNEL_CH1
2763 * @arg @ref LL_TIM_CHANNEL_CH2
2764 * @arg @ref LL_TIM_CHANNEL_CH3
2765 * @arg @ref LL_TIM_CHANNEL_CH4
2766 * @param ICActiveInput This parameter can be one of the following values:
2767 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2768 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2769 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2770 * @retval None
2771 */
2772 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2773 {
2774 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2775 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2776 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2777 }
2778
2779 /**
2780 * @brief Get the current active input.
2781 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2782 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2783 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2784 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2785 * @param TIMx Timer instance
2786 * @param Channel This parameter can be one of the following values:
2787 * @arg @ref LL_TIM_CHANNEL_CH1
2788 * @arg @ref LL_TIM_CHANNEL_CH2
2789 * @arg @ref LL_TIM_CHANNEL_CH3
2790 * @arg @ref LL_TIM_CHANNEL_CH4
2791 * @retval Returned value can be one of the following values:
2792 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2793 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2794 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2795 */
2796 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2797 {
2798 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2799 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2800 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2801 }
2802
2803 /**
2804 * @brief Set the prescaler of input channel.
2805 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2806 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2807 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2808 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2809 * @param TIMx Timer instance
2810 * @param Channel This parameter can be one of the following values:
2811 * @arg @ref LL_TIM_CHANNEL_CH1
2812 * @arg @ref LL_TIM_CHANNEL_CH2
2813 * @arg @ref LL_TIM_CHANNEL_CH3
2814 * @arg @ref LL_TIM_CHANNEL_CH4
2815 * @param ICPrescaler This parameter can be one of the following values:
2816 * @arg @ref LL_TIM_ICPSC_DIV1
2817 * @arg @ref LL_TIM_ICPSC_DIV2
2818 * @arg @ref LL_TIM_ICPSC_DIV4
2819 * @arg @ref LL_TIM_ICPSC_DIV8
2820 * @retval None
2821 */
2822 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2823 {
2824 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2825 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2826 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2827 }
2828
2829 /**
2830 * @brief Get the current prescaler value acting on an input channel.
2831 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2832 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2833 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2834 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2835 * @param TIMx Timer instance
2836 * @param Channel This parameter can be one of the following values:
2837 * @arg @ref LL_TIM_CHANNEL_CH1
2838 * @arg @ref LL_TIM_CHANNEL_CH2
2839 * @arg @ref LL_TIM_CHANNEL_CH3
2840 * @arg @ref LL_TIM_CHANNEL_CH4
2841 * @retval Returned value can be one of the following values:
2842 * @arg @ref LL_TIM_ICPSC_DIV1
2843 * @arg @ref LL_TIM_ICPSC_DIV2
2844 * @arg @ref LL_TIM_ICPSC_DIV4
2845 * @arg @ref LL_TIM_ICPSC_DIV8
2846 */
2847 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2848 {
2849 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2850 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2851 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2852 }
2853
2854 /**
2855 * @brief Set the input filter duration.
2856 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2857 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2858 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2859 * CCMR2 IC4F LL_TIM_IC_SetFilter
2860 * @param TIMx Timer instance
2861 * @param Channel This parameter can be one of the following values:
2862 * @arg @ref LL_TIM_CHANNEL_CH1
2863 * @arg @ref LL_TIM_CHANNEL_CH2
2864 * @arg @ref LL_TIM_CHANNEL_CH3
2865 * @arg @ref LL_TIM_CHANNEL_CH4
2866 * @param ICFilter This parameter can be one of the following values:
2867 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2868 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2869 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2870 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2871 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2872 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2873 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2874 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2875 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2876 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2877 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2878 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2879 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2880 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2881 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2882 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2883 * @retval None
2884 */
2885 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2886 {
2887 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2888 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2889 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2890 }
2891
2892 /**
2893 * @brief Get the input filter duration.
2894 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2895 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2896 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2897 * CCMR2 IC4F LL_TIM_IC_GetFilter
2898 * @param TIMx Timer instance
2899 * @param Channel This parameter can be one of the following values:
2900 * @arg @ref LL_TIM_CHANNEL_CH1
2901 * @arg @ref LL_TIM_CHANNEL_CH2
2902 * @arg @ref LL_TIM_CHANNEL_CH3
2903 * @arg @ref LL_TIM_CHANNEL_CH4
2904 * @retval Returned value can be one of the following values:
2905 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2906 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2907 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2908 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2909 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2910 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2911 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2912 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2913 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2914 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2915 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2916 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2917 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2918 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2919 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2920 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2921 */
2922 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2923 {
2924 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2925 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2926 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2927 }
2928
2929 /**
2930 * @brief Set the input channel polarity.
2931 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2932 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2933 * CCER CC2P LL_TIM_IC_SetPolarity\n
2934 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2935 * CCER CC3P LL_TIM_IC_SetPolarity\n
2936 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2937 * CCER CC4P LL_TIM_IC_SetPolarity\n
2938 * CCER CC4NP LL_TIM_IC_SetPolarity
2939 * @param TIMx Timer instance
2940 * @param Channel This parameter can be one of the following values:
2941 * @arg @ref LL_TIM_CHANNEL_CH1
2942 * @arg @ref LL_TIM_CHANNEL_CH2
2943 * @arg @ref LL_TIM_CHANNEL_CH3
2944 * @arg @ref LL_TIM_CHANNEL_CH4
2945 * @param ICPolarity This parameter can be one of the following values:
2946 * @arg @ref LL_TIM_IC_POLARITY_RISING
2947 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2948 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2949 * @retval None
2950 */
2951 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2952 {
2953 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2954 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2955 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2956 }
2957
2958 /**
2959 * @brief Get the current input channel polarity.
2960 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2961 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2962 * CCER CC2P LL_TIM_IC_GetPolarity\n
2963 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2964 * CCER CC3P LL_TIM_IC_GetPolarity\n
2965 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2966 * CCER CC4P LL_TIM_IC_GetPolarity\n
2967 * CCER CC4NP LL_TIM_IC_GetPolarity
2968 * @param TIMx Timer instance
2969 * @param Channel This parameter can be one of the following values:
2970 * @arg @ref LL_TIM_CHANNEL_CH1
2971 * @arg @ref LL_TIM_CHANNEL_CH2
2972 * @arg @ref LL_TIM_CHANNEL_CH3
2973 * @arg @ref LL_TIM_CHANNEL_CH4
2974 * @retval Returned value can be one of the following values:
2975 * @arg @ref LL_TIM_IC_POLARITY_RISING
2976 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2977 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2978 */
2979 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2980 {
2981 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2982 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2983 SHIFT_TAB_CCxP[iChannel]);
2984 }
2985
2986 /**
2987 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2988 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2989 * a timer instance provides an XOR input.
2990 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2991 * @param TIMx Timer instance
2992 * @retval None
2993 */
2994 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2995 {
2996 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2997 }
2998
2999 /**
3000 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3001 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3002 * a timer instance provides an XOR input.
3003 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3004 * @param TIMx Timer instance
3005 * @retval None
3006 */
3007 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3008 {
3009 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3010 }
3011
3012 /**
3013 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3014 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3015 * a timer instance provides an XOR input.
3016 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3017 * @param TIMx Timer instance
3018 * @retval State of bit (1 or 0).
3019 */
3020 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3021 {
3022 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3023 }
3024
3025 /**
3026 * @brief Get captured value for input channel 1.
3027 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3028 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3029 * whether or not a timer instance supports a 32 bits counter.
3030 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3031 * input channel 1 is supported by a timer instance.
3032 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3033 * @param TIMx Timer instance
3034 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3035 */
3036 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
3037 {
3038 return (uint32_t)(READ_REG(TIMx->CCR1));
3039 }
3040
3041 /**
3042 * @brief Get captured value for input channel 2.
3043 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3044 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3045 * whether or not a timer instance supports a 32 bits counter.
3046 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3047 * input channel 2 is supported by a timer instance.
3048 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3049 * @param TIMx Timer instance
3050 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3051 */
3052 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
3053 {
3054 return (uint32_t)(READ_REG(TIMx->CCR2));
3055 }
3056
3057 /**
3058 * @brief Get captured value for input channel 3.
3059 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3060 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3061 * whether or not a timer instance supports a 32 bits counter.
3062 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3063 * input channel 3 is supported by a timer instance.
3064 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3065 * @param TIMx Timer instance
3066 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3067 */
3068 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
3069 {
3070 return (uint32_t)(READ_REG(TIMx->CCR3));
3071 }
3072
3073 /**
3074 * @brief Get captured value for input channel 4.
3075 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3076 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3077 * whether or not a timer instance supports a 32 bits counter.
3078 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3079 * input channel 4 is supported by a timer instance.
3080 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3081 * @param TIMx Timer instance
3082 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3083 */
3084 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
3085 {
3086 return (uint32_t)(READ_REG(TIMx->CCR4));
3087 }
3088
3089 /**
3090 * @}
3091 */
3092
3093 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3094 * @{
3095 */
3096 /**
3097 * @brief Enable external clock mode 2.
3098 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3099 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3100 * whether or not a timer instance supports external clock mode2.
3101 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3102 * @param TIMx Timer instance
3103 * @retval None
3104 */
3105 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3106 {
3107 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3108 }
3109
3110 /**
3111 * @brief Disable external clock mode 2.
3112 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3113 * whether or not a timer instance supports external clock mode2.
3114 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3115 * @param TIMx Timer instance
3116 * @retval None
3117 */
3118 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3119 {
3120 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3121 }
3122
3123 /**
3124 * @brief Indicate whether external clock mode 2 is enabled.
3125 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3126 * whether or not a timer instance supports external clock mode2.
3127 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3128 * @param TIMx Timer instance
3129 * @retval State of bit (1 or 0).
3130 */
3131 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
3132 {
3133 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3134 }
3135
3136 /**
3137 * @brief Set the clock source of the counter clock.
3138 * @note when selected clock source is external clock mode 1, the timer input
3139 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3140 * function. This timer input must be configured by calling
3141 * the @ref LL_TIM_IC_Config() function.
3142 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3143 * whether or not a timer instance supports external clock mode1.
3144 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3145 * whether or not a timer instance supports external clock mode2.
3146 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3147 * SMCR ECE LL_TIM_SetClockSource
3148 * @param TIMx Timer instance
3149 * @param ClockSource This parameter can be one of the following values:
3150 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3151 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3152 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3153 * @retval None
3154 */
3155 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3156 {
3157 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3158 }
3159
3160 /**
3161 * @brief Set the encoder interface mode.
3162 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3163 * whether or not a timer instance supports the encoder mode.
3164 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3165 * @param TIMx Timer instance
3166 * @param EncoderMode This parameter can be one of the following values:
3167 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3168 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3169 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3170 * @retval None
3171 */
3172 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3173 {
3174 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3175 }
3176
3177 /**
3178 * @}
3179 */
3180
3181 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3182 * @{
3183 */
3184 /**
3185 * @brief Set the trigger output (TRGO) used for timer synchronization .
3186 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3187 * whether or not a timer instance can operate as a master timer.
3188 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3189 * @param TIMx Timer instance
3190 * @param TimerSynchronization This parameter can be one of the following values:
3191 * @arg @ref LL_TIM_TRGO_RESET
3192 * @arg @ref LL_TIM_TRGO_ENABLE
3193 * @arg @ref LL_TIM_TRGO_UPDATE
3194 * @arg @ref LL_TIM_TRGO_CC1IF
3195 * @arg @ref LL_TIM_TRGO_OC1REF
3196 * @arg @ref LL_TIM_TRGO_OC2REF
3197 * @arg @ref LL_TIM_TRGO_OC3REF
3198 * @arg @ref LL_TIM_TRGO_OC4REF
3199 * @retval None
3200 */
3201 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3202 {
3203 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3204 }
3205
3206 /**
3207 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3208 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3209 * whether or not a timer instance can be used for ADC synchronization.
3210 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3211 * @param TIMx Timer Instance
3212 * @param ADCSynchronization This parameter can be one of the following values:
3213 * @arg @ref LL_TIM_TRGO2_RESET
3214 * @arg @ref LL_TIM_TRGO2_ENABLE
3215 * @arg @ref LL_TIM_TRGO2_UPDATE
3216 * @arg @ref LL_TIM_TRGO2_CC1F
3217 * @arg @ref LL_TIM_TRGO2_OC1
3218 * @arg @ref LL_TIM_TRGO2_OC2
3219 * @arg @ref LL_TIM_TRGO2_OC3
3220 * @arg @ref LL_TIM_TRGO2_OC4
3221 * @arg @ref LL_TIM_TRGO2_OC5
3222 * @arg @ref LL_TIM_TRGO2_OC6
3223 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3224 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3225 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3226 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3227 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3228 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3229 * @retval None
3230 */
3231 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3232 {
3233 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3234 }
3235
3236 /**
3237 * @brief Set the synchronization mode of a slave timer.
3238 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3239 * a timer instance can operate as a slave timer.
3240 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3241 * @param TIMx Timer instance
3242 * @param SlaveMode This parameter can be one of the following values:
3243 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3244 * @arg @ref LL_TIM_SLAVEMODE_RESET
3245 * @arg @ref LL_TIM_SLAVEMODE_GATED
3246 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3247 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3248 * @retval None
3249 */
3250 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3251 {
3252 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3253 }
3254
3255 /**
3256 * @brief Set the selects the trigger input to be used to synchronize the counter.
3257 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3258 * a timer instance can operate as a slave timer.
3259 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3260 * @param TIMx Timer instance
3261 * @param TriggerInput This parameter can be one of the following values:
3262 * @arg @ref LL_TIM_TS_ITR0
3263 * @arg @ref LL_TIM_TS_ITR1
3264 * @arg @ref LL_TIM_TS_ITR2
3265 * @arg @ref LL_TIM_TS_ITR3
3266 * @arg @ref LL_TIM_TS_TI1F_ED
3267 * @arg @ref LL_TIM_TS_TI1FP1
3268 * @arg @ref LL_TIM_TS_TI2FP2
3269 * @arg @ref LL_TIM_TS_ETRF
3270 * @arg @ref LL_TIM_TS_ITR4
3271 * @arg @ref LL_TIM_TS_ITR5
3272 * @arg @ref LL_TIM_TS_ITR6
3273 * @arg @ref LL_TIM_TS_ITR7
3274 * @arg @ref LL_TIM_TS_ITR8 (*)
3275 * @arg @ref LL_TIM_TS_ITR9 (*)
3276 * @arg @ref LL_TIM_TS_ITR10 (*)
3277 * @arg @ref LL_TIM_TS_ITR11 (*)
3278 * @arg @ref LL_TIM_TS_ITR12 (*)
3279 * @arg @ref LL_TIM_TS_ITR13 (*)
3280 *
3281 * (*) Value not defined in all devices.
3282 * @retval None
3283 */
3284 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3285 {
3286 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3287 }
3288
3289 /**
3290 * @brief Enable the Master/Slave mode.
3291 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3292 * a timer instance can operate as a slave timer.
3293 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3294 * @param TIMx Timer instance
3295 * @retval None
3296 */
3297 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3298 {
3299 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3300 }
3301
3302 /**
3303 * @brief Disable the Master/Slave mode.
3304 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3305 * a timer instance can operate as a slave timer.
3306 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3307 * @param TIMx Timer instance
3308 * @retval None
3309 */
3310 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3311 {
3312 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3313 }
3314
3315 /**
3316 * @brief Indicates whether the Master/Slave mode is enabled.
3317 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3318 * a timer instance can operate as a slave timer.
3319 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3320 * @param TIMx Timer instance
3321 * @retval State of bit (1 or 0).
3322 */
3323 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
3324 {
3325 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3326 }
3327
3328 /**
3329 * @brief Configure the external trigger (ETR) input.
3330 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3331 * a timer instance provides an external trigger input.
3332 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3333 * SMCR ETPS LL_TIM_ConfigETR\n
3334 * SMCR ETF LL_TIM_ConfigETR
3335 * @param TIMx Timer instance
3336 * @param ETRPolarity This parameter can be one of the following values:
3337 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3338 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3339 * @param ETRPrescaler This parameter can be one of the following values:
3340 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3341 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3342 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3343 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3344 * @param ETRFilter This parameter can be one of the following values:
3345 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3346 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3347 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3348 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3349 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3350 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3351 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3352 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3353 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3354 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3355 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3356 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3357 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3358 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3359 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3360 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3361 * @retval None
3362 */
3363 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3364 uint32_t ETRFilter)
3365 {
3366 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3367 }
3368
3369 /**
3370 * @brief Select the external trigger (ETR) input source.
3371 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3372 * not a timer instance supports ETR source selection.
3373 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3374 * @param TIMx Timer instance
3375 * @param ETRSource This parameter can be one of the following values:
3376 * For TIM1, the parameter is one of the following values:
3377 * @arg LL_TIM_TIM1_ETRSOURCE_GPIO: TIM1_ETR is connected to GPIO
3378 * @arg LL_TIM_TIM1_ETRSOURCE_COMP1: TIM1_ETR is connected to COMP1 output
3379 * @arg LL_TIM_TIM1_ETRSOURCE_COMP2: TIM1_ETR is connected to COMP2 output
3380 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
3381 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
3382 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
3383 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
3384 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
3385 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
3386 *
3387 * For TIM2, the parameter is one of the following values:
3388 * @arg LL_TIM_TIM2_ETRSOURCE_GPIO: TIM2_ETR is connected to GPIO
3389 * @arg LL_TIM_TIM2_ETRSOURCE_COMP1: TIM2_ETR is connected to COMP1 output
3390 * @arg LL_TIM_TIM2_ETRSOURCE_COMP2: TIM2_ETR is connected to COMP2 output
3391 * @arg LL_TIM_TIM2_ETRSOURCE_LSE: TIM2_ETR is connected to LSE
3392 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A
3393 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B
3394 *
3395 * For TIM3, the parameter is one of the following values:
3396 * @arg LL_TIM_TIM3_ETRSOURCE_GPIO: TIM3_ETR is connected to GPIO
3397 * @arg LL_TIM_TIM3_ETRSOURCE_COMP1: TIM3_ETR is connected to COMP1 output
3398 *
3399 * For TIM5, the parameter is one of the following values:
3400 * @arg LL_TIM_TIM5_ETRSOURCE_GPIO: TIM5_ETR is connected to GPIO
3401 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
3402 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
3403 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*)
3404 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*)
3405 *
3406 * For TIM8, the parameter is one of the following values:
3407 * @arg LL_TIM_TIM8_ETRSOURCE_GPIO: TIM8_ETR is connected to GPIO
3408 * @arg LL_TIM_TIM8_ETRSOURCE_COMP1: TIM8_ETR is connected to COMP1 output
3409 * @arg LL_TIM_TIM8_ETRSOURCE_COMP2: TIM8_ETR is connected to COMP2 output
3410 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
3411 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
3412 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
3413 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
3414 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
3415 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
3416 *
3417 * For TIM23, the parameter is one of the following values: (*)
3418 * @arg LL_TIM_TIM23_ETRSOURCE_GPIO TIM23_ETR is connected to GPIO
3419 * @arg LL_TIM_TIM23_ETRSOURCE_COMP1 TIM23_ETR is connected to COMP1 output
3420 * @arg LL_TIM_TIM23_ETRSOURCE_COMP2 TIM23_ETR is connected to COMP2 output
3421 *
3422 * For TIM24, the parameter is one of the following values: (*)
3423 * @arg LL_TIM_TIM24_ETRSOURCE_GPIO TIM24_ETR is connected to GPIO
3424 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A
3425 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B
3426 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A
3427 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B
3428 *
3429 * (*) Value not defined in all devices.
3430 * @retval None
3431 */
3432 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3433 {
3434
3435 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3436 }
3437
3438 /**
3439 * @}
3440 */
3441
3442 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3443 * @{
3444 */
3445 /**
3446 * @brief Enable the break function.
3447 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3448 * a timer instance provides a break input.
3449 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3450 * @param TIMx Timer instance
3451 * @retval None
3452 */
3453 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3454 {
3455 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3456 }
3457
3458 /**
3459 * @brief Disable the break function.
3460 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3461 * @param TIMx Timer instance
3462 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3463 * a timer instance provides a break input.
3464 * @retval None
3465 */
3466 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3467 {
3468 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3469 }
3470
3471 /**
3472 * @brief Configure the break input.
3473 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3474 * a timer instance provides a break input.
3475 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3476 * BDTR BKF LL_TIM_ConfigBRK
3477 * @param TIMx Timer instance
3478 * @param BreakPolarity This parameter can be one of the following values:
3479 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3480 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3481 * @param BreakFilter This parameter can be one of the following values:
3482 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3483 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3484 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3485 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3486 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3487 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3488 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3489 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3490 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3491 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3492 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3493 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3494 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3495 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3496 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3497 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3498 * @retval None
3499 */
3500 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3501 uint32_t BreakFilter)
3502 {
3503 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3504 }
3505
3506 /**
3507 * @brief Enable the break 2 function.
3508 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3509 * a timer instance provides a second break input.
3510 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3511 * @param TIMx Timer instance
3512 * @retval None
3513 */
3514 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3515 {
3516 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3517 }
3518
3519 /**
3520 * @brief Disable the break 2 function.
3521 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3522 * a timer instance provides a second break input.
3523 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3524 * @param TIMx Timer instance
3525 * @retval None
3526 */
3527 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3528 {
3529 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3530 }
3531
3532 /**
3533 * @brief Configure the break 2 input.
3534 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3535 * a timer instance provides a second break input.
3536 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3537 * BDTR BK2F LL_TIM_ConfigBRK2
3538 * @param TIMx Timer instance
3539 * @param Break2Polarity This parameter can be one of the following values:
3540 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3541 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3542 * @param Break2Filter This parameter can be one of the following values:
3543 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3544 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3545 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3546 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3547 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3548 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3549 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3550 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3551 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3552 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3553 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3554 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3555 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3556 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3557 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3558 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3559 * @retval None
3560 */
3561 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3562 {
3563 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3564 }
3565
3566 /**
3567 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3568 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3569 * a timer instance provides a break input.
3570 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3571 * BDTR OSSR LL_TIM_SetOffStates
3572 * @param TIMx Timer instance
3573 * @param OffStateIdle This parameter can be one of the following values:
3574 * @arg @ref LL_TIM_OSSI_DISABLE
3575 * @arg @ref LL_TIM_OSSI_ENABLE
3576 * @param OffStateRun This parameter can be one of the following values:
3577 * @arg @ref LL_TIM_OSSR_DISABLE
3578 * @arg @ref LL_TIM_OSSR_ENABLE
3579 * @retval None
3580 */
3581 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3582 {
3583 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3584 }
3585
3586 /**
3587 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3588 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3589 * a timer instance provides a break input.
3590 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3591 * @param TIMx Timer instance
3592 * @retval None
3593 */
3594 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3595 {
3596 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3597 }
3598
3599 /**
3600 * @brief Disable automatic output (MOE can be set only by software).
3601 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3602 * a timer instance provides a break input.
3603 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3604 * @param TIMx Timer instance
3605 * @retval None
3606 */
3607 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3608 {
3609 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3610 }
3611
3612 /**
3613 * @brief Indicate whether automatic output is enabled.
3614 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3615 * a timer instance provides a break input.
3616 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3617 * @param TIMx Timer instance
3618 * @retval State of bit (1 or 0).
3619 */
3620 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
3621 {
3622 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3623 }
3624
3625 /**
3626 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3627 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3628 * software and is reset in case of break or break2 event
3629 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3630 * a timer instance provides a break input.
3631 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3632 * @param TIMx Timer instance
3633 * @retval None
3634 */
3635 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3636 {
3637 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3638 }
3639
3640 /**
3641 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3642 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3643 * software and is reset in case of break or break2 event.
3644 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3645 * a timer instance provides a break input.
3646 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3647 * @param TIMx Timer instance
3648 * @retval None
3649 */
3650 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3651 {
3652 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3653 }
3654
3655 /**
3656 * @brief Indicates whether outputs are enabled.
3657 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3658 * a timer instance provides a break input.
3659 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3660 * @param TIMx Timer instance
3661 * @retval State of bit (1 or 0).
3662 */
3663 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3664 {
3665 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3666 }
3667
3668 #if defined(TIM_BREAK_INPUT_SUPPORT)
3669 /**
3670 * @brief Enable the signals connected to the designated timer break input.
3671 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3672 * or not a timer instance allows for break input selection.
3673 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3674 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3675 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3676 * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3677 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3678 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3679 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3680 * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3681 * @param TIMx Timer instance
3682 * @param BreakInput This parameter can be one of the following values:
3683 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3684 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3685 * @param Source This parameter can be one of the following values:
3686 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3687 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3688 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3689 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3690 * @retval None
3691 */
3692 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3693 {
3694 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3695 SET_BIT(*pReg, Source);
3696 }
3697
3698 /**
3699 * @brief Disable the signals connected to the designated timer break input.
3700 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3701 * or not a timer instance allows for break input selection.
3702 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3703 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3704 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3705 * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3706 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3707 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3708 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3709 * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3710 * @param TIMx Timer instance
3711 * @param BreakInput This parameter can be one of the following values:
3712 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3713 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3714 * @param Source This parameter can be one of the following values:
3715 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3716 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3717 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3718 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3719 * @retval None
3720 */
3721 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3722 {
3723 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3724 CLEAR_BIT(*pReg, Source);
3725 }
3726
3727 /**
3728 * @brief Set the polarity of the break signal for the timer break input.
3729 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3730 * or not a timer instance allows for break input selection.
3731 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3732 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3733 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3734 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3735 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3736 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3737 * @param TIMx Timer instance
3738 * @param BreakInput This parameter can be one of the following values:
3739 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3740 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3741 * @param Source This parameter can be one of the following values:
3742 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3743 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3744 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3745 * @param Polarity This parameter can be one of the following values:
3746 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3747 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3748 * @retval None
3749 */
3750 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3751 uint32_t Polarity)
3752 {
3753 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3754 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3755 }
3756 #endif /* TIM_BREAK_INPUT_SUPPORT */
3757 /**
3758 * @}
3759 */
3760
3761 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3762 * @{
3763 */
3764 /**
3765 * @brief Configures the timer DMA burst feature.
3766 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3767 * not a timer instance supports the DMA burst mode.
3768 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3769 * DCR DBA LL_TIM_ConfigDMABurst
3770 * @param TIMx Timer instance
3771 * @param DMABurstBaseAddress This parameter can be one of the following values:
3772 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3773 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3774 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3775 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3776 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3777 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3778 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3779 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3780 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3781 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3782 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3783 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3784 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3785 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3786 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3787 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3788 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3789 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3790 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3791 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3792 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3793 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3794 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3795 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
3796 *
3797 * @param DMABurstLength This parameter can be one of the following values:
3798 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3799 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3800 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3801 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3802 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3803 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3804 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3805 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3806 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3807 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3808 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3809 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3810 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3811 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3812 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3813 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3814 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3815 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3816 * @retval None
3817 */
3818 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3819 {
3820 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3821 }
3822
3823 /**
3824 * @}
3825 */
3826
3827 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3828 * @{
3829 */
3830 /**
3831 * @brief Remap TIM inputs (input channel, internal/external triggers).
3832 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3833 * a some timer inputs can be remapped.
3834 * TIM1: one of the following values:
3835 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
3836 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output
3837 *
3838 * TIM2: one of the following values:
3839 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
3840 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output
3841 * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output
3842 * @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
3843 *
3844 * TIM3: one of the following values:
3845 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
3846 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output
3847 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output
3848 * @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
3849 *
3850 * TIM5: one of the following values:
3851 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
3852 * @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP: TIM5 TI1 is connected to CAN TMP
3853 * @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP: TIM5 TI1 is connected to CAN RTP
3854 *
3855 * TIM8: one of the following values:
3856 * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
3857 * @arg LL_TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output
3858 *
3859 * TIM12: one of the following values: (*)
3860 * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO
3861 * @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
3862 *
3863 * TIM15: one of the following values:
3864 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
3865 * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2 CH1
3866 * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3 CH1
3867 * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4 CH1
3868 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
3869 * @arg LL_TIM_TIM15_TI1_RMP_CSI: TIM15 TI1 is connected to CSI
3870 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2
3871 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO
3872 * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI2 is connected to TIM2 CH2
3873 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI2 is connected to TIM3 CH2
3874 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI2 is connected to TIM4 CH2
3875 *
3876 * TIM16: one of the following values:
3877 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
3878 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
3879 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
3880 * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
3881 *
3882 * TIM17: one of the following values:
3883 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
3884 * @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
3885 * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
3886 * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1
3887 *
3888 * TIM23: one of the following values: (*)
3889 * @arg LL_TIM_TIM23_TI4_RMP_GPIO TIM23_TI4 is connected to GPIO
3890 * @arg LL_TIM_TIM23_TI4_RMP_COMP1 TIM23_TI4 is connected to COMP1 output
3891 * @arg LL_TIM_TIM23_TI4_RMP_COMP2 TIM23_TI4 is connected to COMP2 output
3892 * @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
3893 *
3894 * TIM24: one of the following values: (*)
3895 * @arg LL_TIM_TIM24_TI1_RMP_GPIO TIM24_TI1 is connected to GPIO
3896 * @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM24_TI1 is connected to CAN_TMP
3897 * @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM24_TI1 is connected to CAN_RTP
3898 * @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC TIM24_TI1 is connected to CAN_SOC
3899 *
3900 * (*) Value not defined in all devices. \n
3901 * @retval None
3902 */
3903 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3904 {
3905 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
3906 }
3907
3908 /**
3909 * @}
3910 */
3911
3912 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3913 * @{
3914 */
3915 /**
3916 * @brief Clear the update interrupt flag (UIF).
3917 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3918 * @param TIMx Timer instance
3919 * @retval None
3920 */
3921 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3922 {
3923 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3924 }
3925
3926 /**
3927 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3928 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3929 * @param TIMx Timer instance
3930 * @retval State of bit (1 or 0).
3931 */
3932 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3933 {
3934 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3935 }
3936
3937 /**
3938 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3939 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3940 * @param TIMx Timer instance
3941 * @retval None
3942 */
3943 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3944 {
3945 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3946 }
3947
3948 /**
3949 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3950 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3951 * @param TIMx Timer instance
3952 * @retval State of bit (1 or 0).
3953 */
3954 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
3955 {
3956 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3957 }
3958
3959 /**
3960 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3961 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3962 * @param TIMx Timer instance
3963 * @retval None
3964 */
3965 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3966 {
3967 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3968 }
3969
3970 /**
3971 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3972 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3973 * @param TIMx Timer instance
3974 * @retval State of bit (1 or 0).
3975 */
3976 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
3977 {
3978 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3979 }
3980
3981 /**
3982 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3983 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3984 * @param TIMx Timer instance
3985 * @retval None
3986 */
3987 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3988 {
3989 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3990 }
3991
3992 /**
3993 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3994 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3995 * @param TIMx Timer instance
3996 * @retval State of bit (1 or 0).
3997 */
3998 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
3999 {
4000 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4001 }
4002
4003 /**
4004 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4005 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4006 * @param TIMx Timer instance
4007 * @retval None
4008 */
4009 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4010 {
4011 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4012 }
4013
4014 /**
4015 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4016 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4017 * @param TIMx Timer instance
4018 * @retval State of bit (1 or 0).
4019 */
4020 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
4021 {
4022 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4023 }
4024
4025 /**
4026 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4027 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4028 * @param TIMx Timer instance
4029 * @retval None
4030 */
4031 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4032 {
4033 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4034 }
4035
4036 /**
4037 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4038 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4039 * @param TIMx Timer instance
4040 * @retval State of bit (1 or 0).
4041 */
4042 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
4043 {
4044 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4045 }
4046
4047 /**
4048 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4049 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4050 * @param TIMx Timer instance
4051 * @retval None
4052 */
4053 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4054 {
4055 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4056 }
4057
4058 /**
4059 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4060 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4061 * @param TIMx Timer instance
4062 * @retval State of bit (1 or 0).
4063 */
4064 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
4065 {
4066 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4067 }
4068
4069 /**
4070 * @brief Clear the commutation interrupt flag (COMIF).
4071 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4072 * @param TIMx Timer instance
4073 * @retval None
4074 */
4075 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4076 {
4077 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4078 }
4079
4080 /**
4081 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4082 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4083 * @param TIMx Timer instance
4084 * @retval State of bit (1 or 0).
4085 */
4086 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
4087 {
4088 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4089 }
4090
4091 /**
4092 * @brief Clear the trigger interrupt flag (TIF).
4093 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4094 * @param TIMx Timer instance
4095 * @retval None
4096 */
4097 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4098 {
4099 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4100 }
4101
4102 /**
4103 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4104 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4105 * @param TIMx Timer instance
4106 * @retval State of bit (1 or 0).
4107 */
4108 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
4109 {
4110 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4111 }
4112
4113 /**
4114 * @brief Clear the break interrupt flag (BIF).
4115 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4116 * @param TIMx Timer instance
4117 * @retval None
4118 */
4119 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4120 {
4121 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4122 }
4123
4124 /**
4125 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4126 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4127 * @param TIMx Timer instance
4128 * @retval State of bit (1 or 0).
4129 */
4130 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
4131 {
4132 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4133 }
4134
4135 /**
4136 * @brief Clear the break 2 interrupt flag (B2IF).
4137 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4138 * @param TIMx Timer instance
4139 * @retval None
4140 */
4141 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4142 {
4143 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4144 }
4145
4146 /**
4147 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4148 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4149 * @param TIMx Timer instance
4150 * @retval State of bit (1 or 0).
4151 */
4152 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
4153 {
4154 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4155 }
4156
4157 /**
4158 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4159 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4160 * @param TIMx Timer instance
4161 * @retval None
4162 */
4163 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4164 {
4165 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4166 }
4167
4168 /**
4169 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
4170 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4171 * @param TIMx Timer instance
4172 * @retval State of bit (1 or 0).
4173 */
4174 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
4175 {
4176 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4177 }
4178
4179 /**
4180 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4181 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4182 * @param TIMx Timer instance
4183 * @retval None
4184 */
4185 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4186 {
4187 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4188 }
4189
4190 /**
4191 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
4192 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4193 * @param TIMx Timer instance
4194 * @retval State of bit (1 or 0).
4195 */
4196 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
4197 {
4198 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4199 }
4200
4201 /**
4202 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4203 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4204 * @param TIMx Timer instance
4205 * @retval None
4206 */
4207 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4208 {
4209 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4210 }
4211
4212 /**
4213 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
4214 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4215 * @param TIMx Timer instance
4216 * @retval State of bit (1 or 0).
4217 */
4218 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
4219 {
4220 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4221 }
4222
4223 /**
4224 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4225 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4226 * @param TIMx Timer instance
4227 * @retval None
4228 */
4229 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4230 {
4231 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4232 }
4233
4234 /**
4235 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
4236 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4237 * @param TIMx Timer instance
4238 * @retval State of bit (1 or 0).
4239 */
4240 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
4241 {
4242 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4243 }
4244
4245 /**
4246 * @brief Clear the system break interrupt flag (SBIF).
4247 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4248 * @param TIMx Timer instance
4249 * @retval None
4250 */
4251 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4252 {
4253 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4254 }
4255
4256 /**
4257 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4258 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4259 * @param TIMx Timer instance
4260 * @retval State of bit (1 or 0).
4261 */
4262 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
4263 {
4264 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4265 }
4266
4267 /**
4268 * @}
4269 */
4270
4271 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4272 * @{
4273 */
4274 /**
4275 * @brief Enable update interrupt (UIE).
4276 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4277 * @param TIMx Timer instance
4278 * @retval None
4279 */
4280 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4281 {
4282 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4283 }
4284
4285 /**
4286 * @brief Disable update interrupt (UIE).
4287 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4288 * @param TIMx Timer instance
4289 * @retval None
4290 */
4291 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4292 {
4293 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4294 }
4295
4296 /**
4297 * @brief Indicates whether the update interrupt (UIE) is enabled.
4298 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4299 * @param TIMx Timer instance
4300 * @retval State of bit (1 or 0).
4301 */
4302 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
4303 {
4304 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4305 }
4306
4307 /**
4308 * @brief Enable capture/compare 1 interrupt (CC1IE).
4309 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4310 * @param TIMx Timer instance
4311 * @retval None
4312 */
4313 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4314 {
4315 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4316 }
4317
4318 /**
4319 * @brief Disable capture/compare 1 interrupt (CC1IE).
4320 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4321 * @param TIMx Timer instance
4322 * @retval None
4323 */
4324 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4325 {
4326 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4327 }
4328
4329 /**
4330 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4331 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4332 * @param TIMx Timer instance
4333 * @retval State of bit (1 or 0).
4334 */
4335 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
4336 {
4337 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4338 }
4339
4340 /**
4341 * @brief Enable capture/compare 2 interrupt (CC2IE).
4342 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4343 * @param TIMx Timer instance
4344 * @retval None
4345 */
4346 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4347 {
4348 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4349 }
4350
4351 /**
4352 * @brief Disable capture/compare 2 interrupt (CC2IE).
4353 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4354 * @param TIMx Timer instance
4355 * @retval None
4356 */
4357 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4358 {
4359 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4360 }
4361
4362 /**
4363 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4364 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4365 * @param TIMx Timer instance
4366 * @retval State of bit (1 or 0).
4367 */
4368 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
4369 {
4370 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4371 }
4372
4373 /**
4374 * @brief Enable capture/compare 3 interrupt (CC3IE).
4375 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4376 * @param TIMx Timer instance
4377 * @retval None
4378 */
4379 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4380 {
4381 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4382 }
4383
4384 /**
4385 * @brief Disable capture/compare 3 interrupt (CC3IE).
4386 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4387 * @param TIMx Timer instance
4388 * @retval None
4389 */
4390 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4391 {
4392 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4393 }
4394
4395 /**
4396 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4397 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4398 * @param TIMx Timer instance
4399 * @retval State of bit (1 or 0).
4400 */
4401 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
4402 {
4403 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4404 }
4405
4406 /**
4407 * @brief Enable capture/compare 4 interrupt (CC4IE).
4408 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4409 * @param TIMx Timer instance
4410 * @retval None
4411 */
4412 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4413 {
4414 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4415 }
4416
4417 /**
4418 * @brief Disable capture/compare 4 interrupt (CC4IE).
4419 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4420 * @param TIMx Timer instance
4421 * @retval None
4422 */
4423 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4424 {
4425 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4426 }
4427
4428 /**
4429 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4430 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4431 * @param TIMx Timer instance
4432 * @retval State of bit (1 or 0).
4433 */
4434 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
4435 {
4436 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4437 }
4438
4439 /**
4440 * @brief Enable commutation interrupt (COMIE).
4441 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4442 * @param TIMx Timer instance
4443 * @retval None
4444 */
4445 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4446 {
4447 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4448 }
4449
4450 /**
4451 * @brief Disable commutation interrupt (COMIE).
4452 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4453 * @param TIMx Timer instance
4454 * @retval None
4455 */
4456 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4457 {
4458 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4459 }
4460
4461 /**
4462 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4463 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4464 * @param TIMx Timer instance
4465 * @retval State of bit (1 or 0).
4466 */
4467 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
4468 {
4469 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4470 }
4471
4472 /**
4473 * @brief Enable trigger interrupt (TIE).
4474 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4475 * @param TIMx Timer instance
4476 * @retval None
4477 */
4478 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4479 {
4480 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4481 }
4482
4483 /**
4484 * @brief Disable trigger interrupt (TIE).
4485 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4486 * @param TIMx Timer instance
4487 * @retval None
4488 */
4489 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4490 {
4491 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4492 }
4493
4494 /**
4495 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4496 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4497 * @param TIMx Timer instance
4498 * @retval State of bit (1 or 0).
4499 */
4500 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
4501 {
4502 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4503 }
4504
4505 /**
4506 * @brief Enable break interrupt (BIE).
4507 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4508 * @param TIMx Timer instance
4509 * @retval None
4510 */
4511 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4512 {
4513 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4514 }
4515
4516 /**
4517 * @brief Disable break interrupt (BIE).
4518 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4519 * @param TIMx Timer instance
4520 * @retval None
4521 */
4522 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4523 {
4524 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4525 }
4526
4527 /**
4528 * @brief Indicates whether the break interrupt (BIE) is enabled.
4529 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4530 * @param TIMx Timer instance
4531 * @retval State of bit (1 or 0).
4532 */
4533 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
4534 {
4535 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4536 }
4537
4538 /**
4539 * @}
4540 */
4541
4542 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
4543 * @{
4544 */
4545 /**
4546 * @brief Enable update DMA request (UDE).
4547 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4548 * @param TIMx Timer instance
4549 * @retval None
4550 */
4551 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4552 {
4553 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4554 }
4555
4556 /**
4557 * @brief Disable update DMA request (UDE).
4558 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4559 * @param TIMx Timer instance
4560 * @retval None
4561 */
4562 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4563 {
4564 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4565 }
4566
4567 /**
4568 * @brief Indicates whether the update DMA request (UDE) is enabled.
4569 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4570 * @param TIMx Timer instance
4571 * @retval State of bit (1 or 0).
4572 */
4573 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
4574 {
4575 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4576 }
4577
4578 /**
4579 * @brief Enable capture/compare 1 DMA request (CC1DE).
4580 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4581 * @param TIMx Timer instance
4582 * @retval None
4583 */
4584 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4585 {
4586 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4587 }
4588
4589 /**
4590 * @brief Disable capture/compare 1 DMA request (CC1DE).
4591 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4592 * @param TIMx Timer instance
4593 * @retval None
4594 */
4595 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4596 {
4597 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4598 }
4599
4600 /**
4601 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4602 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4603 * @param TIMx Timer instance
4604 * @retval State of bit (1 or 0).
4605 */
4606 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
4607 {
4608 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4609 }
4610
4611 /**
4612 * @brief Enable capture/compare 2 DMA request (CC2DE).
4613 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4614 * @param TIMx Timer instance
4615 * @retval None
4616 */
4617 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4618 {
4619 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4620 }
4621
4622 /**
4623 * @brief Disable capture/compare 2 DMA request (CC2DE).
4624 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4625 * @param TIMx Timer instance
4626 * @retval None
4627 */
4628 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4629 {
4630 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4631 }
4632
4633 /**
4634 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4635 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4636 * @param TIMx Timer instance
4637 * @retval State of bit (1 or 0).
4638 */
4639 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
4640 {
4641 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4642 }
4643
4644 /**
4645 * @brief Enable capture/compare 3 DMA request (CC3DE).
4646 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4647 * @param TIMx Timer instance
4648 * @retval None
4649 */
4650 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4651 {
4652 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4653 }
4654
4655 /**
4656 * @brief Disable capture/compare 3 DMA request (CC3DE).
4657 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4658 * @param TIMx Timer instance
4659 * @retval None
4660 */
4661 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4662 {
4663 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4664 }
4665
4666 /**
4667 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4668 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4669 * @param TIMx Timer instance
4670 * @retval State of bit (1 or 0).
4671 */
4672 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
4673 {
4674 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4675 }
4676
4677 /**
4678 * @brief Enable capture/compare 4 DMA request (CC4DE).
4679 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4680 * @param TIMx Timer instance
4681 * @retval None
4682 */
4683 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4684 {
4685 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4686 }
4687
4688 /**
4689 * @brief Disable capture/compare 4 DMA request (CC4DE).
4690 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4691 * @param TIMx Timer instance
4692 * @retval None
4693 */
4694 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4695 {
4696 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4697 }
4698
4699 /**
4700 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4701 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4702 * @param TIMx Timer instance
4703 * @retval State of bit (1 or 0).
4704 */
4705 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
4706 {
4707 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4708 }
4709
4710 /**
4711 * @brief Enable commutation DMA request (COMDE).
4712 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4713 * @param TIMx Timer instance
4714 * @retval None
4715 */
4716 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4717 {
4718 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4719 }
4720
4721 /**
4722 * @brief Disable commutation DMA request (COMDE).
4723 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4724 * @param TIMx Timer instance
4725 * @retval None
4726 */
4727 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4728 {
4729 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4730 }
4731
4732 /**
4733 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4734 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4735 * @param TIMx Timer instance
4736 * @retval State of bit (1 or 0).
4737 */
4738 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
4739 {
4740 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4741 }
4742
4743 /**
4744 * @brief Enable trigger interrupt (TDE).
4745 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4746 * @param TIMx Timer instance
4747 * @retval None
4748 */
4749 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4750 {
4751 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4752 }
4753
4754 /**
4755 * @brief Disable trigger interrupt (TDE).
4756 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4757 * @param TIMx Timer instance
4758 * @retval None
4759 */
4760 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4761 {
4762 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4763 }
4764
4765 /**
4766 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4767 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4768 * @param TIMx Timer instance
4769 * @retval State of bit (1 or 0).
4770 */
4771 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
4772 {
4773 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4774 }
4775
4776 /**
4777 * @}
4778 */
4779
4780 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4781 * @{
4782 */
4783 /**
4784 * @brief Generate an update event.
4785 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4786 * @param TIMx Timer instance
4787 * @retval None
4788 */
4789 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4790 {
4791 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4792 }
4793
4794 /**
4795 * @brief Generate Capture/Compare 1 event.
4796 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4797 * @param TIMx Timer instance
4798 * @retval None
4799 */
4800 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4801 {
4802 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4803 }
4804
4805 /**
4806 * @brief Generate Capture/Compare 2 event.
4807 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4808 * @param TIMx Timer instance
4809 * @retval None
4810 */
4811 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4812 {
4813 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4814 }
4815
4816 /**
4817 * @brief Generate Capture/Compare 3 event.
4818 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4819 * @param TIMx Timer instance
4820 * @retval None
4821 */
4822 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4823 {
4824 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4825 }
4826
4827 /**
4828 * @brief Generate Capture/Compare 4 event.
4829 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4830 * @param TIMx Timer instance
4831 * @retval None
4832 */
4833 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4834 {
4835 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4836 }
4837
4838 /**
4839 * @brief Generate commutation event.
4840 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4841 * @param TIMx Timer instance
4842 * @retval None
4843 */
4844 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4845 {
4846 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4847 }
4848
4849 /**
4850 * @brief Generate trigger event.
4851 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4852 * @param TIMx Timer instance
4853 * @retval None
4854 */
4855 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4856 {
4857 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4858 }
4859
4860 /**
4861 * @brief Generate break event.
4862 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4863 * @param TIMx Timer instance
4864 * @retval None
4865 */
4866 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4867 {
4868 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4869 }
4870
4871 /**
4872 * @brief Generate break 2 event.
4873 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4874 * @param TIMx Timer instance
4875 * @retval None
4876 */
4877 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4878 {
4879 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4880 }
4881
4882 /**
4883 * @}
4884 */
4885
4886 #if defined(USE_FULL_LL_DRIVER)
4887 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4888 * @{
4889 */
4890
4891 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4892 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4893 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
4894 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4895 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4896 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4897 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4898 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4899 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4900 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4901 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4902 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4903 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4904 /**
4905 * @}
4906 */
4907 #endif /* USE_FULL_LL_DRIVER */
4908
4909 /**
4910 * @}
4911 */
4912
4913 /**
4914 * @}
4915 */
4916
4917 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 */
4918
4919 /**
4920 * @}
4921 */
4922
4923 #ifdef __cplusplus
4924 }
4925 #endif
4926
4927 #endif /* __STM32H7xx_LL_TIM_H */
4928 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software