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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_hal_qspi.c
blob4e3132e23c7def2d87532de97c30b6c6b7b5bf43
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_qspi.c
4 * @author MCD Application Team
5 * @brief QSPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the QuadSPI interface (QSPI).
8 * + Initialization and de-initialization functions
9 * + Indirect functional mode management
10 * + Memory-mapped functional mode management
11 * + Auto-polling functional mode management
12 * + Interrupts and flags management
13 * + MDMA channel configuration for indirect functional mode
14 * + Errors management and abort functionality
15 *
16 *
17 @verbatim
18 ===============================================================================
19 ##### How to use this driver #####
20 ===============================================================================
21 [..]
22 *** Initialization ***
23 ======================
24 [..]
25 (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
26 (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
27 (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
28 (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
29 (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
30 (++) If interrupt mode is used, enable and configure QuadSPI global
31 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
32 (++) If DMA mode is used, enable the clocks for the QuadSPI MDMA
33 with __HAL_RCC_MDMA_CLK_ENABLE(), configure MDMA with HAL_MDMA_Init(),
34 link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
35 MDMA global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
36 (#) Configure the flash size, the clock prescaler, the fifo threshold, the
37 clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
38
39 *** Indirect functional mode ***
40 ================================
41 [..]
42 (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
43 functions :
44 (++) Instruction phase : the mode used and if present the instruction opcode.
45 (++) Address phase : the mode used and if present the size and the address value.
46 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
47 bytes values.
48 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
49 (++) Data phase : the mode used and if present the number of bytes.
50 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
51 if activated.
52 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
53 (#) If no data is required for the command, it is sent directly to the memory :
54 (++) In polling mode, the output of the function is done when the transfer is complete.
55 (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
56 (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
57 HAL_QSPI_Transmit_IT() after the command configuration :
58 (++) In polling mode, the output of the function is done when the transfer is complete.
59 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
60 is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
61 (++) In DMA mode,HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
62 (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
63 HAL_QSPI_Receive_IT() after the command configuration :
64 (++) In polling mode, the output of the function is done when the transfer is complete.
65 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
66 is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
67 (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
68
69 *** Auto-polling functional mode ***
70 ====================================
71 [..]
72 (#) Configure the command sequence and the auto-polling functional mode using the
73 HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
74 (++) Instruction phase : the mode used and if present the instruction opcode.
75 (++) Address phase : the mode used and if present the size and the address value.
76 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
77 bytes values.
78 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
79 (++) Data phase : the mode used.
80 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
81 if activated.
82 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
83 (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
84 the polling interval and the automatic stop activation.
85 (#) After the configuration :
86 (++) In polling mode, the output of the function is done when the status match is reached. The
87 automatic stop is activated to avoid an infinite loop.
88 (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
89
90 *** MDMA functional mode ***
91 ====================================
92 [..]
93 (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() function :
94 (++) MDMA settings for write operation :
95 (+) The DestinationInc should be MDMA_DEST_INC_DISABLE
96 (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
97 (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
98 aligned with @ref MDMA_Source_increment_mode .
99 (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
100 (++) MDMA settings for read operation :
101 (+) The SourceInc should be MDMA_SRC_INC_DISABLE
102 (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
103 (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
104 (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
105 aligned with @ref MDMA_Destination_increment_mode.
106 (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi.
107 (#)In case of wrong MDMA setting
108 (++) For write operation :
109 (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_QSPI_Transmit_DMA().
110 (++) For read operation :
111 (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_QSPI_Receive_DMA().
112
113 *** Memory-mapped functional mode ***
114 =====================================
115 [..]
116 (#) Configure the command sequence and the memory-mapped functional mode using the
117 HAL_QSPI_MemoryMapped() functions :
118 (++) Instruction phase : the mode used and if present the instruction opcode.
119 (++) Address phase : the mode used and the size.
120 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
121 bytes values.
122 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
123 (++) Data phase : the mode used.
124 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
125 if activated.
126 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
127 (++) The timeout activation and the timeout period.
128 (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
129 the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
130
131 *** Errors management and abort functionality ***
132 =================================================
133 [..]
134 (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
135 (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
136 flushes the fifo :
137 (++) In polling mode, the output of the function is done when the transfer
138 complete bit is set and the busy bit cleared.
139 (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
140 the transfer complete bi is set.
141
142 *** Control functions ***
143 =========================
144 [..]
145 (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
146 (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
147 (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
148 (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
149
150 *** Callback registration ***
151 =============================================
152 [..]
153 The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
154 allows the user to configure dynamically the driver callbacks.
155
156 Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
157 it allows to register following callbacks:
158 (+) ErrorCallback : callback when error occurs.
159 (+) AbortCpltCallback : callback when abort is completed.
160 (+) FifoThresholdCallback : callback when the fifo threshold is reached.
161 (+) CmdCpltCallback : callback when a command without data is completed.
162 (+) RxCpltCallback : callback when a reception transfer is completed.
163 (+) TxCpltCallback : callback when a transmission transfer is completed.
164 (+) StatusMatchCallback : callback when a status match occurs.
165 (+) TimeOutCallback : callback when the timeout perioed expires.
166 (+) MspInitCallback : QSPI MspInit.
167 (+) MspDeInitCallback : QSPI MspDeInit.
168 This function takes as parameters the HAL peripheral handle, the Callback ID
169 and a pointer to the user callback function.
170
171 Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
172 weak (surcharged) function. It allows to reset following callbacks:
173 (+) ErrorCallback : callback when error occurs.
174 (+) AbortCpltCallback : callback when abort is completed.
175 (+) FifoThresholdCallback : callback when the fifo threshold is reached.
176 (+) CmdCpltCallback : callback when a command without data is completed.
177 (+) RxCpltCallback : callback when a reception transfer is completed.
178 (+) TxCpltCallback : callback when a transmission transfer is completed.
179 (+) StatusMatchCallback : callback when a status match occurs.
180 (+) TimeOutCallback : callback when the timeout perioed expires.
181 (+) MspInitCallback : QSPI MspInit.
182 (+) MspDeInitCallback : QSPI MspDeInit.
183 This function) takes as parameters the HAL peripheral handle and the Callback ID.
184
185 By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
186 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
187 Exception done for MspInit and MspDeInit callbacks that are respectively
188 reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
189 and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
190 If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
191 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
192
193 Callbacks can be registered/unregistered in READY state only.
194 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
195 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
196 during the Init/DeInit.
197 In that case first register the MspInit/MspDeInit user callbacks
198 using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
199 or @ref HAL_QSPI_Init function.
200
201 When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
202 not defined, the callback registering feature is not available
203 and weak (surcharged) callbacks are used.
204
205 *** Workarounds linked to Silicon Limitation ***
206 ====================================================
207 [..]
208 (#) Workarounds Implemented inside HAL Driver
209 (++) Extra data written in the FIFO at the end of a read transfer
210
211 @endverbatim
212 ******************************************************************************
213 * @attention
214 *
215 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
216 * All rights reserved.</center></h2>
217 *
218 * This software component is licensed by ST under BSD 3-Clause license,
219 * the "License"; You may not use this file except in compliance with the
220 * License. You may obtain a copy of the License at:
221 * opensource.org/licenses/BSD-3-Clause
222 *
223 ******************************************************************************
224 */
225
226 /* Includes ------------------------------------------------------------------*/
227 #include "stm32h7xx_hal.h"
228
229 /** @addtogroup STM32H7xx_HAL_Driver
230 * @{
231 */
232
233 #ifdef HAL_QSPI_MODULE_ENABLED
234
235 #if defined(QUADSPI)
236
237 /** @defgroup QSPI QSPI
238 * @brief QSPI HAL module driver
239 * @{
240 */
241
242 /* Private typedef -----------------------------------------------------------*/
243
244 /* Private define ------------------------------------------------------------*/
245 /** @defgroup QSPI_Private_Constants QSPI Private Constants
246 * @{
247 */
248 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!<Indirect write mode*/
249 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
250 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
251 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
252 /**
253 * @}
254 */
255
256 /* Private macro -------------------------------------------------------------*/
257 /** @defgroup QSPI_Private_Macros QSPI Private Macros
258 * @{
259 */
260 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
261 ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
262 ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
263 ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
264 /**
265 * @}
266 */
267
268 /* Private variables ---------------------------------------------------------*/
269
270 /* Private function prototypes -----------------------------------------------*/
271 static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma);
272 static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma);
273 static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma);
274 static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma);
275 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
276 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
277
278 /* Exported functions --------------------------------------------------------*/
279
280 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
281 * @{
282 */
283
284 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
285 * @brief Initialization and Configuration functions
286 *
287 @verbatim
288 ===============================================================================
289 ##### Initialization and Configuration functions #####
290 ===============================================================================
291 [..]
292 This subsection provides a set of functions allowing to :
293 (+) Initialize the QuadSPI.
294 (+) De-initialize the QuadSPI.
295
296 @endverbatim
297 * @{
298 */
299
300 /**
301 * @brief Initialize the QSPI mode according to the specified parameters
302 * in the QSPI_InitTypeDef and initialize the associated handle.
303 * @param hqspi: QSPI handle
304 * @retval HAL status
305 */
306 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
307 {
308 HAL_StatusTypeDef status;
309 uint32_t tickstart = HAL_GetTick();
310
311 /* Check the QSPI handle allocation */
312 if(hqspi == NULL)
313 {
314 return HAL_ERROR;
315 }
316
317 /* Check the parameters */
318 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
319 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
320 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
321 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
322 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
323 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
324 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
325 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
326
327 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
328 {
329 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
330 }
331
332 /* Process locked */
333 __HAL_LOCK(hqspi);
334
335 if(hqspi->State == HAL_QSPI_STATE_RESET)
336 {
337 /* Allocate lock resource and initialize it */
338 hqspi->Lock = HAL_UNLOCKED;
339
340 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
341 /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
342 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
343 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
344 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
345 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
346 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
347 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
348 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
349 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
350
351 if(hqspi->MspInitCallback == NULL)
352 {
353 hqspi->MspInitCallback = HAL_QSPI_MspInit;
354 }
355
356 /* Init the low level hardware */
357 hqspi->MspInitCallback(hqspi);
358 #else
359 /* Init the low level hardware : GPIO, CLOCK */
360 HAL_QSPI_MspInit(hqspi);
361 #endif
362 /* Configure the default timeout for the QSPI memory access */
363 HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
364 }
365
366 /* Configure QSPI FIFO Threshold */
367 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
368 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
369
370 /* Wait till BUSY flag reset */
371 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
372
373 if(status == HAL_OK)
374 {
375 /* Configure QSPI Clock Prescaler and Sample Shift */
376 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
377 ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
378 hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
379
380 /* Configure QSPI Flash Size, CS High Time and Clock Mode */
381 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
382 ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
383 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
384
385 /* Enable the QSPI peripheral */
386 __HAL_QSPI_ENABLE(hqspi);
387
388 /* Set QSPI error code to none */
389 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
390
391 /* Initialize the QSPI state */
392 hqspi->State = HAL_QSPI_STATE_READY;
393 }
394
395 /* Release Lock */
396 __HAL_UNLOCK(hqspi);
397
398 /* Return function status */
399 return status;
400 }
401
402 /**
403 * @brief De-Initialize the QSPI peripheral.
404 * @param hqspi: QSPI handle
405 * @retval HAL status
406 */
407 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
408 {
409 /* Check the QSPI handle allocation */
410 if(hqspi == NULL)
411 {
412 return HAL_ERROR;
413 }
414
415 /* Process locked */
416 __HAL_LOCK(hqspi);
417
418 /* Disable the QSPI Peripheral Clock */
419 __HAL_QSPI_DISABLE(hqspi);
420
421 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
422 if(hqspi->MspDeInitCallback == NULL)
423 {
424 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
425 }
426
427 /* DeInit the low level hardware */
428 hqspi->MspDeInitCallback(hqspi);
429 #else
430 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
431 HAL_QSPI_MspDeInit(hqspi);
432 #endif
433
434 /* Set QSPI error code to none */
435 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
436
437 /* Initialize the QSPI state */
438 hqspi->State = HAL_QSPI_STATE_RESET;
439
440 /* Release Lock */
441 __HAL_UNLOCK(hqspi);
442
443 return HAL_OK;
444 }
445
446 /**
447 * @brief Initialize the QSPI MSP.
448 * @param hqspi: QSPI handle
449 * @retval None
450 */
451 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
452 {
453 /* Prevent unused argument(s) compilation warning */
454 UNUSED(hqspi);
455
456 /* NOTE : This function should not be modified, when the callback is needed,
457 the HAL_QSPI_MspInit can be implemented in the user file
458 */
459 }
460
461 /**
462 * @brief DeInitialize the QSPI MSP.
463 * @param hqspi: QSPI handle
464 * @retval None
465 */
466 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
467 {
468 /* Prevent unused argument(s) compilation warning */
469 UNUSED(hqspi);
470
471 /* NOTE : This function should not be modified, when the callback is needed,
472 the HAL_QSPI_MspDeInit can be implemented in the user file
473 */
474 }
475
476 /**
477 * @}
478 */
479
480 /** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
481 * @brief QSPI Transmit/Receive functions
482 *
483 @verbatim
484 ===============================================================================
485 ##### IO operation functions #####
486 ===============================================================================
487 [..]
488 This subsection provides a set of functions allowing to :
489 (+) Handle the interrupts.
490 (+) Handle the command sequence.
491 (+) Transmit data in blocking, interrupt or DMA mode.
492 (+) Receive data in blocking, interrupt or DMA mode.
493 (+) Manage the auto-polling functional mode.
494 (+) Manage the memory-mapped functional mode.
495
496 @endverbatim
497 * @{
498 */
499
500 /**
501 * @brief Handle QSPI interrupt request.
502 * @param hqspi: QSPI handle
503 * @retval None
504 */
505 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
506 {
507 __IO uint32_t *data_reg;
508 uint32_t flag = READ_REG(hqspi->Instance->SR);
509 uint32_t itsource = READ_REG(hqspi->Instance->CR);
510
511 /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
512 if(((flag & QSPI_FLAG_FT) == QSPI_FLAG_FT) && ((itsource & QSPI_IT_FT) == QSPI_IT_FT))
513 {
514 data_reg = &hqspi->Instance->DR;
515
516 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
517 {
518 /* Transmission process */
519 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
520 {
521 if (hqspi->TxXferCount > 0U)
522 {
523 /* Fill the FIFO until the threshold is reached */
524 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
525 hqspi->pTxBuffPtr++;
526 hqspi->TxXferCount--;
527 }
528 else
529 {
530 /* No more data available for the transfer */
531 /* Disable the QSPI FIFO Threshold Interrupt */
532 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
533 break;
534 }
535 }
536 }
537 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
538 {
539 /* Receiving Process */
540 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
541 {
542 if (hqspi->RxXferCount > 0U)
543 {
544 /* Read the FIFO until the threshold is reached */
545 *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
546 hqspi->pRxBuffPtr++;
547 hqspi->RxXferCount--;
548 }
549 else
550 {
551 /* All data have been received for the transfer */
552 /* Disable the QSPI FIFO Threshold Interrupt */
553 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
554 break;
555 }
556 }
557 }
558 else
559 {
560 /* Nothing to do */
561 }
562 /* FIFO Threshold callback */
563 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
564 hqspi->FifoThresholdCallback(hqspi);
565 #else
566 HAL_QSPI_FifoThresholdCallback(hqspi);
567 #endif
568 }
569
570 /* QSPI Transfer Complete interrupt occurred -------------------------------*/
571 else if(((flag & QSPI_FLAG_TC) == QSPI_FLAG_TC) && ((itsource & QSPI_IT_TC) == QSPI_IT_TC))
572 {
573 /* Clear interrupt */
574 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
575
576 /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
577 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
578
579 /* Transfer complete callback */
580 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
581 {
582 if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
583 {
584 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
585 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
586
587 /* Disable the MDMA channel */
588 __HAL_MDMA_DISABLE(hqspi->hmdma);
589 }
590
591 /* Change state of QSPI */
592 hqspi->State = HAL_QSPI_STATE_READY;
593
594 /* TX Complete callback */
595 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
596 hqspi->TxCpltCallback(hqspi);
597 #else
598 HAL_QSPI_TxCpltCallback(hqspi);
599 #endif
600 }
601 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
602 {
603 if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
604 {
605 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
606 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
607
608 /* Disable the MDMA channel */
609 __HAL_MDMA_DISABLE(hqspi->hmdma);
610 }
611 else
612 {
613 data_reg = &hqspi->Instance->DR;
614 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
615 {
616 if (hqspi->RxXferCount > 0U)
617 {
618 /* Read the last data received in the FIFO until it is empty */
619 *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
620 hqspi->pRxBuffPtr++;
621 hqspi->RxXferCount--;
622 }
623 else
624 {
625 /* All data have been received for the transfer */
626 break;
627 }
628 }
629 }
630
631 /* Change state of QSPI */
632 hqspi->State = HAL_QSPI_STATE_READY;
633
634 /* RX Complete callback */
635 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
636 hqspi->RxCpltCallback(hqspi);
637 #else
638 HAL_QSPI_RxCpltCallback(hqspi);
639 #endif
640 }
641 else if(hqspi->State == HAL_QSPI_STATE_BUSY)
642 {
643 /* Change state of QSPI */
644 hqspi->State = HAL_QSPI_STATE_READY;
645
646 /* Command Complete callback */
647 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
648 hqspi->CmdCpltCallback(hqspi);
649 #else
650 HAL_QSPI_CmdCpltCallback(hqspi);
651 #endif
652 }
653 else if(hqspi->State == HAL_QSPI_STATE_ABORT)
654 {
655 /* Reset functional mode configuration to indirect write mode by default */
656 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
657
658 /* Change state of QSPI */
659 hqspi->State = HAL_QSPI_STATE_READY;
660
661 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
662 {
663 /* Abort called by the user */
664
665 /* Abort Complete callback */
666 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
667 hqspi->AbortCpltCallback(hqspi);
668 #else
669 HAL_QSPI_AbortCpltCallback(hqspi);
670 #endif
671 }
672 else
673 {
674 /* Abort due to an error (eg : MDMA error) */
675
676 /* Error callback */
677 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
678 hqspi->ErrorCallback(hqspi);
679 #else
680 HAL_QSPI_ErrorCallback(hqspi);
681 #endif
682 }
683 }
684 else
685 {
686 /* Nothing to do */
687 }
688 }
689
690 /* QSPI Status Match interrupt occurred ------------------------------------*/
691 else if(((flag & QSPI_FLAG_SM)== QSPI_FLAG_SM) && ((itsource & QSPI_IT_SM) == QSPI_IT_SM))
692 {
693 /* Clear interrupt */
694 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
695
696 /* Check if the automatic poll mode stop is activated */
697 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
698 {
699 /* Disable the QSPI Transfer Error and Status Match Interrupts */
700 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
701
702 /* Change state of QSPI */
703 hqspi->State = HAL_QSPI_STATE_READY;
704 }
705
706 /* Status match callback */
707 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
708 hqspi->StatusMatchCallback(hqspi);
709 #else
710 HAL_QSPI_StatusMatchCallback(hqspi);
711 #endif
712 }
713
714 /* QSPI Transfer Error interrupt occurred ----------------------------------*/
715 else if(((flag & QSPI_FLAG_TE) == QSPI_FLAG_TE) && ((itsource & QSPI_IT_TE) == QSPI_IT_TE))
716 {
717 /* Clear interrupt */
718 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
719
720 /* Disable all the QSPI Interrupts */
721 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
722
723 /* Set error code */
724 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
725
726 if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
727 {
728 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
729 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
730
731 /* Disable the MDMA channel */
732 hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
733 if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
734 {
735 /* Set error code to DMA */
736 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
737
738 /* Change state of QSPI */
739 hqspi->State = HAL_QSPI_STATE_READY;
740
741 /* Error callback */
742 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
743 hqspi->ErrorCallback(hqspi);
744 #else
745 HAL_QSPI_ErrorCallback(hqspi);
746 #endif
747 }
748 }
749 else
750 {
751 /* Change state of QSPI */
752 hqspi->State = HAL_QSPI_STATE_READY;
753
754 /* Error callback */
755 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
756 hqspi->ErrorCallback(hqspi);
757 #else
758 HAL_QSPI_ErrorCallback(hqspi);
759 #endif
760 }
761 }
762
763 /* QSPI Timeout interrupt occurred -----------------------------------------*/
764 else if(((flag & QSPI_FLAG_TO) == QSPI_FLAG_TO) && ((itsource & QSPI_IT_TO) == QSPI_IT_TO))
765 {
766 /* Clear interrupt */
767 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
768
769 /* Timeout callback */
770 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
771 hqspi->TimeOutCallback(hqspi);
772 #else
773 HAL_QSPI_TimeOutCallback(hqspi);
774 #endif
775 }
776 else
777 {
778 /* Nothing to do */
779 }
780 }
781
782 /**
783 * @brief Set the command configuration.
784 * @param hqspi: QSPI handle
785 * @param cmd : structure that contains the command configuration information
786 * @param Timeout : Timeout duration
787 * @note This function is used only in Indirect Read or Write Modes
788 * @retval HAL status
789 */
790 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
791 {
792 HAL_StatusTypeDef status;
793 uint32_t tickstart = HAL_GetTick();
794
795 /* Check the parameters */
796 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
797 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
798 {
799 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
800 }
801
802 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
803 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
804 {
805 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
806 }
807
808 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
809 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
810 {
811 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
812 }
813
814 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
815 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
816
817 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
818 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
819 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
820
821 /* Process locked */
822 __HAL_LOCK(hqspi);
823
824 if(hqspi->State == HAL_QSPI_STATE_READY)
825 {
826 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
827
828 /* Update QSPI state */
829 hqspi->State = HAL_QSPI_STATE_BUSY;
830
831 /* Wait till BUSY flag reset */
832 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
833
834 if (status == HAL_OK)
835 {
836 /* Call the configuration function */
837 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
838
839 if (cmd->DataMode == QSPI_DATA_NONE)
840 {
841 /* When there is no data phase, the transfer start as soon as the configuration is done
842 so wait until TC flag is set to go back in idle state */
843 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
844
845 if (status == HAL_OK)
846 {
847 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
848
849 /* Update QSPI state */
850 hqspi->State = HAL_QSPI_STATE_READY;
851 }
852
853 }
854 else
855 {
856 /* Update QSPI state */
857 hqspi->State = HAL_QSPI_STATE_READY;
858 }
859 }
860 }
861 else
862 {
863 status = HAL_BUSY;
864 }
865
866 /* Process unlocked */
867 __HAL_UNLOCK(hqspi);
868
869 /* Return function status */
870 return status;
871 }
872
873 /**
874 * @brief Set the command configuration in interrupt mode.
875 * @param hqspi: QSPI handle
876 * @param cmd : structure that contains the command configuration information
877 * @note This function is used only in Indirect Read or Write Modes
878 * @retval HAL status
879 */
880 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
881 {
882 HAL_StatusTypeDef status;
883 uint32_t tickstart = HAL_GetTick();
884
885 /* Check the parameters */
886 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
887 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
888 {
889 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
890 }
891
892 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
893 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
894 {
895 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
896 }
897
898 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
899 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
900 {
901 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
902 }
903
904 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
905 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
906
907 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
908 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
909 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
910
911 /* Process locked */
912 __HAL_LOCK(hqspi);
913
914 if(hqspi->State == HAL_QSPI_STATE_READY)
915 {
916 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
917
918 /* Update QSPI state */
919 hqspi->State = HAL_QSPI_STATE_BUSY;
920
921 /* Wait till BUSY flag reset */
922 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
923
924 if (status == HAL_OK)
925 {
926 if (cmd->DataMode == QSPI_DATA_NONE)
927 {
928 /* Clear interrupt */
929 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
930 }
931
932 /* Call the configuration function */
933 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
934
935 if (cmd->DataMode == QSPI_DATA_NONE)
936 {
937 /* When there is no data phase, the transfer start as soon as the configuration is done
938 so activate TC and TE interrupts */
939 /* Process unlocked */
940 __HAL_UNLOCK(hqspi);
941
942 /* Enable the QSPI Transfer Error Interrupt */
943 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
944 }
945 else
946 {
947 /* Update QSPI state */
948 hqspi->State = HAL_QSPI_STATE_READY;
949
950 /* Process unlocked */
951 __HAL_UNLOCK(hqspi);
952 }
953 }
954 else
955 {
956 /* Process unlocked */
957 __HAL_UNLOCK(hqspi);
958 }
959 }
960 else
961 {
962 status = HAL_BUSY;
963
964 /* Process unlocked */
965 __HAL_UNLOCK(hqspi);
966 }
967
968 /* Return function status */
969 return status;
970 }
971
972 /**
973 * @brief Transmit an amount of data in blocking mode.
974 * @param hqspi: QSPI handle
975 * @param pData: pointer to data buffer
976 * @param Timeout : Timeout duration
977 * @note This function is used only in Indirect Write Mode
978 * @retval HAL status
979 */
980 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
981 {
982 HAL_StatusTypeDef status = HAL_OK;
983 uint32_t tickstart = HAL_GetTick();
984 __IO uint32_t *data_reg = &hqspi->Instance->DR;
985
986 /* Process locked */
987 __HAL_LOCK(hqspi);
988
989 if(hqspi->State == HAL_QSPI_STATE_READY)
990 {
991 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
992
993 if(pData != NULL )
994 {
995 /* Update state */
996 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
997
998 /* Configure counters and size of the handle */
999 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
1000 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
1001 hqspi->pTxBuffPtr = pData;
1002
1003 /* Configure QSPI: CCR register with functional as indirect write */
1004 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1005
1006 while(hqspi->TxXferCount > 0U)
1007 {
1008 /* Wait until FT flag is set to send data */
1009 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
1010
1011 if (status != HAL_OK)
1012 {
1013 break;
1014 }
1015
1016 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
1017 hqspi->pTxBuffPtr++;
1018 hqspi->TxXferCount--;
1019 }
1020
1021 if (status == HAL_OK)
1022 {
1023 /* Wait until TC flag is set to go back in idle state */
1024 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
1025
1026 if (status == HAL_OK)
1027 {
1028 /* Clear Transfer Complete bit */
1029 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
1030
1031 }
1032 }
1033
1034 /* Update QSPI state */
1035 hqspi->State = HAL_QSPI_STATE_READY;
1036 }
1037 else
1038 {
1039 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1040 status = HAL_ERROR;
1041 }
1042 }
1043 else
1044 {
1045 status = HAL_BUSY;
1046 }
1047
1048 /* Process unlocked */
1049 __HAL_UNLOCK(hqspi);
1050
1051 return status;
1052 }
1053
1054
1055 /**
1056 * @brief Receive an amount of data in blocking mode.
1057 * @param hqspi: QSPI handle
1058 * @param pData: pointer to data buffer
1059 * @param Timeout : Timeout duration
1060 * @note This function is used only in Indirect Read Mode
1061 * @retval HAL status
1062 */
1063 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
1064 {
1065 HAL_StatusTypeDef status = HAL_OK;
1066 uint32_t tickstart = HAL_GetTick();
1067 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
1068 __IO uint32_t *data_reg = &hqspi->Instance->DR;
1069
1070 /* Process locked */
1071 __HAL_LOCK(hqspi);
1072
1073 if(hqspi->State == HAL_QSPI_STATE_READY)
1074 {
1075 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1076
1077 if(pData != NULL )
1078 {
1079 /* Update state */
1080 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
1081
1082 /* Configure counters and size of the handle */
1083 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
1084 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
1085 hqspi->pRxBuffPtr = pData;
1086
1087 /* Configure QSPI: CCR register with functional as indirect read */
1088 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1089
1090 /* Start the transfer by re-writing the address in AR register */
1091 WRITE_REG(hqspi->Instance->AR, addr_reg);
1092
1093 while(hqspi->RxXferCount > 0U)
1094 {
1095 /* Wait until FT or TC flag is set to read received data */
1096 status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
1097
1098 if (status != HAL_OK)
1099 {
1100 break;
1101 }
1102
1103 *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
1104 hqspi->pRxBuffPtr++;
1105 hqspi->RxXferCount--;
1106 }
1107
1108 if (status == HAL_OK)
1109 {
1110 /* Wait until TC flag is set to go back in idle state */
1111 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
1112
1113 if (status == HAL_OK)
1114 {
1115 /* Clear Transfer Complete bit */
1116 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
1117 }
1118 }
1119
1120 /* Update QSPI state */
1121 hqspi->State = HAL_QSPI_STATE_READY;
1122 }
1123 else
1124 {
1125 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1126 status = HAL_ERROR;
1127 }
1128 }
1129 else
1130 {
1131 status = HAL_BUSY;
1132 }
1133
1134 /* Process unlocked */
1135 __HAL_UNLOCK(hqspi);
1136
1137 return status;
1138 }
1139
1140 /**
1141 * @brief Send an amount of data in non-blocking mode with interrupt.
1142 * @param hqspi: QSPI handle
1143 * @param pData: pointer to data buffer
1144 * @note This function is used only in Indirect Write Mode
1145 * @retval HAL status
1146 */
1147 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1148 {
1149 HAL_StatusTypeDef status = HAL_OK;
1150
1151 /* Process locked */
1152 __HAL_LOCK(hqspi);
1153
1154 if(hqspi->State == HAL_QSPI_STATE_READY)
1155 {
1156 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1157
1158 if(pData != NULL )
1159 {
1160 /* Update state */
1161 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
1162
1163 /* Configure counters and size of the handle */
1164 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
1165 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
1166 hqspi->pTxBuffPtr = pData;
1167
1168 /* Clear interrupt */
1169 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
1170
1171 /* Configure QSPI: CCR register with functional as indirect write */
1172 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1173
1174 /* Process unlocked */
1175 __HAL_UNLOCK(hqspi);
1176
1177 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
1178 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
1179 }
1180 else
1181 {
1182 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1183 status = HAL_ERROR;
1184
1185 /* Process unlocked */
1186 __HAL_UNLOCK(hqspi);
1187 }
1188 }
1189 else
1190 {
1191 status = HAL_BUSY;
1192
1193 /* Process unlocked */
1194 __HAL_UNLOCK(hqspi);
1195 }
1196
1197 return status;
1198 }
1199
1200 /**
1201 * @brief Receive an amount of data in non-blocking mode with interrupt.
1202 * @param hqspi: QSPI handle
1203 * @param pData: pointer to data buffer
1204 * @note This function is used only in Indirect Read Mode
1205 * @retval HAL status
1206 */
1207 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1208 {
1209 HAL_StatusTypeDef status = HAL_OK;
1210 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
1211
1212 /* Process locked */
1213 __HAL_LOCK(hqspi);
1214
1215 if(hqspi->State == HAL_QSPI_STATE_READY)
1216 {
1217 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1218
1219 if(pData != NULL )
1220 {
1221 /* Update state */
1222 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
1223
1224 /* Configure counters and size of the handle */
1225 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
1226 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
1227 hqspi->pRxBuffPtr = pData;
1228
1229 /* Clear interrupt */
1230 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
1231
1232 /* Configure QSPI: CCR register with functional as indirect read */
1233 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1234
1235 /* Start the transfer by re-writing the address in AR register */
1236 WRITE_REG(hqspi->Instance->AR, addr_reg);
1237
1238 /* Process unlocked */
1239 __HAL_UNLOCK(hqspi);
1240
1241 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
1242 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
1243 }
1244 else
1245 {
1246 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1247 status = HAL_ERROR;
1248
1249 /* Process unlocked */
1250 __HAL_UNLOCK(hqspi);
1251 }
1252 }
1253 else
1254 {
1255 status = HAL_BUSY;
1256
1257 /* Process unlocked */
1258 __HAL_UNLOCK(hqspi);
1259 }
1260
1261 return status;
1262 }
1263
1264 /**
1265 * @brief Send an amount of data in non-blocking mode with DMA.
1266 * @param hqspi: QSPI handle
1267 * @param pData: pointer to data buffer
1268 * @note This function is used only in Indirect Write Mode
1269 * @note If MDMA peripheral access is configured as halfword, the number
1270 * of data and the fifo threshold should be aligned on halfword
1271 * @note If MDMA peripheral access is configured as word, the number
1272 * of data and the fifo threshold should be aligned on word
1273 * @retval HAL status
1274 */
1275 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1276 {
1277 HAL_StatusTypeDef status = HAL_OK;
1278
1279 /* Process locked */
1280 __HAL_LOCK(hqspi);
1281
1282 if(hqspi->State == HAL_QSPI_STATE_READY)
1283 {
1284 /* Clear the error code */
1285 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1286
1287 if(pData != NULL )
1288 {
1289
1290 /* Update state */
1291 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
1292
1293 /* Clear interrupt */
1294 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
1295
1296 /* Configure counters and size of the handle */
1297 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
1298 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
1299 hqspi->pTxBuffPtr = pData;
1300
1301 /* Configure QSPI: CCR register with functional mode as indirect write */
1302 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1303
1304 /* Set the QSPI MDMA transfer complete callback */
1305 hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
1306
1307 /* Set the MDMA error callback */
1308 hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
1309
1310 /* Clear the MDMA abort callback */
1311 hqspi->hmdma->XferAbortCallback = NULL;
1312
1313 /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
1314 MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
1315
1316 /* Update MDMA configuration with the correct SourceInc field for Write operation */
1317 if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
1318 {
1319 MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
1320 }
1321 else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
1322 {
1323 MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
1324 }
1325 else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
1326 {
1327 MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
1328 }
1329 else
1330 {
1331 /* in case of incorrect source data size */
1332 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
1333 status = HAL_ERROR;
1334 }
1335
1336 /* Enable the QSPI transfer error and complete Interrupts : Workaround for QSPI low kernel clock frequency */
1337 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE |QSPI_IT_TC);
1338
1339 /* Enable the QSPI transmit MDMA */
1340 if(HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
1341 {
1342 /* Process unlocked */
1343 __HAL_UNLOCK(hqspi);
1344
1345 /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
1346 }
1347 }
1348 else
1349 {
1350 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1351 status = HAL_ERROR;
1352
1353 /* Process unlocked */
1354 __HAL_UNLOCK(hqspi);
1355 }
1356 }
1357 else
1358 {
1359 status = HAL_BUSY;
1360
1361 /* Process unlocked */
1362 __HAL_UNLOCK(hqspi);
1363 }
1364
1365 return status;
1366 }
1367
1368 /**
1369 * @brief Receive an amount of data in non-blocking mode with DMA.
1370 * @param hqspi: QSPI handle
1371 * @param pData: pointer to data buffer.
1372 * @note This function is used only in Indirect Read Mode
1373 * @retval HAL status
1374 */
1375 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1376 {
1377 HAL_StatusTypeDef status = HAL_OK;
1378 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
1379
1380 /* Process locked */
1381 __HAL_LOCK(hqspi);
1382
1383 if(hqspi->State == HAL_QSPI_STATE_READY)
1384 {
1385 /* Clear the error code */
1386 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1387
1388 if(pData != NULL )
1389 {
1390
1391 /* Update state */
1392 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
1393
1394 /* Clear interrupt */
1395 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
1396
1397 /* Configure counters and size of the handle */
1398 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
1399 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
1400 hqspi->pRxBuffPtr = pData;
1401
1402 /* Set the QSPI DMA transfer complete callback */
1403 hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
1404
1405 /* Set the MDMA error callback */
1406 hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
1407
1408 /* Clear the MDMA abort callback */
1409 hqspi->hmdma->XferAbortCallback = NULL;
1410
1411
1412 /* QSPI need to be configured to indirect mode before starting
1413 the MDMA to avoid primatury triggering for the MDMA transfert */
1414 /* Configure QSPI: CCR register with functional as indirect read */
1415 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1416
1417 /* Start the transfer by re-writing the address in AR register */
1418 WRITE_REG(hqspi->Instance->AR, addr_reg);
1419
1420 /* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */
1421 MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
1422
1423 /* Update MDMA configuration with the correct DestinationInc field for read operation */
1424 if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
1425 {
1426 MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE);
1427 }
1428 else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
1429 {
1430 MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD);
1431 }
1432 else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
1433 {
1434 MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
1435 }
1436 else
1437 {
1438 /* in case of incorrect destination data size */
1439 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
1440 status = HAL_ERROR;
1441 }
1442
1443 /* Enable the MDMA */
1444 if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
1445 {
1446 /* Process unlocked */
1447 __HAL_UNLOCK(hqspi);
1448
1449 /* Enable the QSPI transfer error Interrupt */
1450 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
1451
1452 /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
1453 }
1454 }
1455 else
1456 {
1457 status = HAL_ERROR;
1458
1459 /* Process unlocked */
1460 __HAL_UNLOCK(hqspi);
1461 }
1462 }
1463 else
1464 {
1465 status = HAL_BUSY;
1466
1467 /* Process unlocked */
1468 __HAL_UNLOCK(hqspi);
1469 }
1470
1471 return status;
1472 }
1473
1474 /**
1475 * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
1476 * @param hqspi: QSPI handle
1477 * @param cmd: structure that contains the command configuration information.
1478 * @param cfg: structure that contains the polling configuration information.
1479 * @param Timeout : Timeout duration
1480 * @note This function is used only in Automatic Polling Mode
1481 * @retval HAL status
1482 */
1483 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
1484 {
1485 HAL_StatusTypeDef status;
1486 uint32_t tickstart = HAL_GetTick();
1487
1488 /* Check the parameters */
1489 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
1490 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
1491 {
1492 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
1493 }
1494
1495 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
1496 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
1497 {
1498 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
1499 }
1500
1501 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
1502 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
1503 {
1504 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
1505 }
1506
1507 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
1508 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
1509
1510 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
1511 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
1512 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
1513
1514 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
1515 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
1516 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
1517
1518 /* Process locked */
1519 __HAL_LOCK(hqspi);
1520
1521 if(hqspi->State == HAL_QSPI_STATE_READY)
1522 {
1523 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1524
1525 /* Update state */
1526 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
1527
1528 /* Wait till BUSY flag reset */
1529 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
1530
1531 if (status == HAL_OK)
1532 {
1533 /* Configure QSPI: PSMAR register with the status match value */
1534 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
1535
1536 /* Configure QSPI: PSMKR register with the status mask value */
1537 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
1538
1539 /* Configure QSPI: PIR register with the interval value */
1540 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
1541
1542 /* Configure QSPI: CR register with Match mode and Automatic stop enabled
1543 (otherwise there will be an infinite loop in blocking mode) */
1544 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
1545 (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
1546
1547 /* Call the configuration function */
1548 cmd->NbData = cfg->StatusBytesSize;
1549 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
1550
1551 /* Wait until SM flag is set to go back in idle state */
1552 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
1553
1554 if (status == HAL_OK)
1555 {
1556 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
1557
1558 /* Update state */
1559 hqspi->State = HAL_QSPI_STATE_READY;
1560 }
1561 }
1562 }
1563 else
1564 {
1565 status = HAL_BUSY;
1566 }
1567
1568 /* Process unlocked */
1569 __HAL_UNLOCK(hqspi);
1570
1571 /* Return function status */
1572 return status;
1573 }
1574
1575 /**
1576 * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
1577 * @param hqspi: QSPI handle
1578 * @param cmd: structure that contains the command configuration information.
1579 * @param cfg: structure that contains the polling configuration information.
1580 * @note This function is used only in Automatic Polling Mode
1581 * @retval HAL status
1582 */
1583 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
1584 {
1585 HAL_StatusTypeDef status;
1586 uint32_t tickstart = HAL_GetTick();
1587
1588 /* Check the parameters */
1589 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
1590 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
1591 {
1592 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
1593 }
1594
1595 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
1596 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
1597 {
1598 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
1599 }
1600
1601 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
1602 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
1603 {
1604 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
1605 }
1606
1607 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
1608 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
1609
1610 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
1611 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
1612 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
1613
1614 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
1615 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
1616 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
1617 assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
1618
1619 /* Process locked */
1620 __HAL_LOCK(hqspi);
1621
1622 if(hqspi->State == HAL_QSPI_STATE_READY)
1623 {
1624 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1625
1626 /* Update state */
1627 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
1628
1629 /* Wait till BUSY flag reset */
1630 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
1631
1632 if (status == HAL_OK)
1633 {
1634 /* Configure QSPI: PSMAR register with the status match value */
1635 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
1636
1637 /* Configure QSPI: PSMKR register with the status mask value */
1638 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
1639
1640 /* Configure QSPI: PIR register with the interval value */
1641 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
1642
1643 /* Configure QSPI: CR register with Match mode and Automatic stop mode */
1644 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
1645 (cfg->MatchMode | cfg->AutomaticStop));
1646
1647 /* Clear interrupt */
1648 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
1649
1650 /* Call the configuration function */
1651 cmd->NbData = cfg->StatusBytesSize;
1652 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
1653
1654 /* Process unlocked */
1655 __HAL_UNLOCK(hqspi);
1656
1657 /* Enable the QSPI Transfer Error and status match Interrupt */
1658 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
1659
1660 }
1661 else
1662 {
1663 /* Process unlocked */
1664 __HAL_UNLOCK(hqspi);
1665 }
1666 }
1667 else
1668 {
1669 status = HAL_BUSY;
1670
1671 /* Process unlocked */
1672 __HAL_UNLOCK(hqspi);
1673 }
1674
1675 /* Return function status */
1676 return status;
1677 }
1678
1679 /**
1680 * @brief Configure the Memory Mapped mode.
1681 * @param hqspi: QSPI handle
1682 * @param cmd: structure that contains the command configuration information.
1683 * @param cfg: structure that contains the memory mapped configuration information.
1684 * @note This function is used only in Memory mapped Mode
1685 * @retval HAL status
1686 */
1687 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
1688 {
1689 HAL_StatusTypeDef status;
1690 uint32_t tickstart = HAL_GetTick();
1691
1692 /* Check the parameters */
1693 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
1694 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
1695 {
1696 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
1697 }
1698
1699 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
1700 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
1701 {
1702 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
1703 }
1704
1705 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
1706 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
1707 {
1708 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
1709 }
1710
1711 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
1712 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
1713
1714 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
1715 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
1716 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
1717
1718 assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
1719
1720 /* Process locked */
1721 __HAL_LOCK(hqspi);
1722
1723 if(hqspi->State == HAL_QSPI_STATE_READY)
1724 {
1725 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1726
1727 /* Update state */
1728 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
1729
1730 /* Wait till BUSY flag reset */
1731 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
1732
1733 if (status == HAL_OK)
1734 {
1735 /* Configure QSPI: CR register with timeout counter enable */
1736 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
1737
1738 if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
1739 {
1740 assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
1741
1742 /* Configure QSPI: LPTR register with the low-power timeout value */
1743 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
1744
1745 /* Clear interrupt */
1746 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
1747
1748 /* Enable the QSPI TimeOut Interrupt */
1749 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
1750 }
1751
1752 /* Call the configuration function */
1753 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
1754 }
1755 }
1756 else
1757 {
1758 status = HAL_BUSY;
1759 }
1760
1761 /* Process unlocked */
1762 __HAL_UNLOCK(hqspi);
1763
1764 /* Return function status */
1765 return status;
1766 }
1767
1768 /**
1769 * @brief Transfer Error callback.
1770 * @param hqspi: QSPI handle
1771 * @retval None
1772 */
1773 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
1774 {
1775 /* Prevent unused argument(s) compilation warning */
1776 UNUSED(hqspi);
1777
1778 /* NOTE : This function should not be modified, when the callback is needed,
1779 the HAL_QSPI_ErrorCallback could be implemented in the user file
1780 */
1781 }
1782
1783 /**
1784 * @brief Abort completed callback.
1785 * @param hqspi: QSPI handle
1786 * @retval None
1787 */
1788 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
1789 {
1790 /* Prevent unused argument(s) compilation warning */
1791 UNUSED(hqspi);
1792
1793 /* NOTE: This function should not be modified, when the callback is needed,
1794 the HAL_QSPI_AbortCpltCallback could be implemented in the user file
1795 */
1796 }
1797
1798 /**
1799 * @brief Command completed callback.
1800 * @param hqspi: QSPI handle
1801 * @retval None
1802 */
1803 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
1804 {
1805 /* Prevent unused argument(s) compilation warning */
1806 UNUSED(hqspi);
1807
1808 /* NOTE: This function should not be modified, when the callback is needed,
1809 the HAL_QSPI_CmdCpltCallback could be implemented in the user file
1810 */
1811 }
1812
1813 /**
1814 * @brief Rx Transfer completed callback.
1815 * @param hqspi: QSPI handle
1816 * @retval None
1817 */
1818 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
1819 {
1820 /* Prevent unused argument(s) compilation warning */
1821 UNUSED(hqspi);
1822
1823 /* NOTE: This function should not be modified, when the callback is needed,
1824 the HAL_QSPI_RxCpltCallback could be implemented in the user file
1825 */
1826 }
1827
1828 /**
1829 * @brief Tx Transfer completed callback.
1830 * @param hqspi: QSPI handle
1831 * @retval None
1832 */
1833 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
1834 {
1835 /* Prevent unused argument(s) compilation warning */
1836 UNUSED(hqspi);
1837
1838 /* NOTE: This function should not be modified, when the callback is needed,
1839 the HAL_QSPI_TxCpltCallback could be implemented in the user file
1840 */
1841 }
1842
1843
1844 /**
1845 * @brief FIFO Threshold callback.
1846 * @param hqspi: QSPI handle
1847 * @retval None
1848 */
1849 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
1850 {
1851 /* Prevent unused argument(s) compilation warning */
1852 UNUSED(hqspi);
1853
1854 /* NOTE : This function should not be modified, when the callback is needed,
1855 the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
1856 */
1857 }
1858
1859 /**
1860 * @brief Status Match callback.
1861 * @param hqspi: QSPI handle
1862 * @retval None
1863 */
1864 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
1865 {
1866 /* Prevent unused argument(s) compilation warning */
1867 UNUSED(hqspi);
1868
1869 /* NOTE : This function should not be modified, when the callback is needed,
1870 the HAL_QSPI_StatusMatchCallback could be implemented in the user file
1871 */
1872 }
1873
1874 /**
1875 * @brief Timeout callback.
1876 * @param hqspi: QSPI handle
1877 * @retval None
1878 */
1879 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
1880 {
1881 /* Prevent unused argument(s) compilation warning */
1882 UNUSED(hqspi);
1883
1884 /* NOTE : This function should not be modified, when the callback is needed,
1885 the HAL_QSPI_TimeOutCallback could be implemented in the user file
1886 */
1887 }
1888 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
1889 /**
1890 * @brief Register a User QSPI Callback
1891 * To be used instead of the weak (surcharged) predefined callback
1892 * @param hqspi : QSPI handle
1893 * @param CallbackId : ID of the callback to be registered
1894 * This parameter can be one of the following values:
1895 * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
1896 * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
1897 * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
1898 * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
1899 * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
1900 * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
1901 * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
1902 * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
1903 * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
1904 * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
1905 * @param pCallback : pointer to the Callback function
1906 * @retval status
1907 */
1908 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
1909 {
1910 HAL_StatusTypeDef status = HAL_OK;
1911
1912 if(pCallback == NULL)
1913 {
1914 /* Update the error code */
1915 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
1916 return HAL_ERROR;
1917 }
1918
1919 /* Process locked */
1920 __HAL_LOCK(hqspi);
1921
1922 if(hqspi->State == HAL_QSPI_STATE_READY)
1923 {
1924 switch (CallbackId)
1925 {
1926 case HAL_QSPI_ERROR_CB_ID :
1927 hqspi->ErrorCallback = pCallback;
1928 break;
1929 case HAL_QSPI_ABORT_CB_ID :
1930 hqspi->AbortCpltCallback = pCallback;
1931 break;
1932 case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
1933 hqspi->FifoThresholdCallback = pCallback;
1934 break;
1935 case HAL_QSPI_CMD_CPLT_CB_ID :
1936 hqspi->CmdCpltCallback = pCallback;
1937 break;
1938 case HAL_QSPI_RX_CPLT_CB_ID :
1939 hqspi->RxCpltCallback = pCallback;
1940 break;
1941 case HAL_QSPI_TX_CPLT_CB_ID :
1942 hqspi->TxCpltCallback = pCallback;
1943 break;
1944 case HAL_QSPI_STATUS_MATCH_CB_ID :
1945 hqspi->StatusMatchCallback = pCallback;
1946 break;
1947 case HAL_QSPI_TIMEOUT_CB_ID :
1948 hqspi->TimeOutCallback = pCallback;
1949 break;
1950 case HAL_QSPI_MSP_INIT_CB_ID :
1951 hqspi->MspInitCallback = pCallback;
1952 break;
1953 case HAL_QSPI_MSP_DEINIT_CB_ID :
1954 hqspi->MspDeInitCallback = pCallback;
1955 break;
1956 default :
1957 /* Update the error code */
1958 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
1959 /* update return status */
1960 status = HAL_ERROR;
1961 break;
1962 }
1963 }
1964 else if (hqspi->State == HAL_QSPI_STATE_RESET)
1965 {
1966 switch (CallbackId)
1967 {
1968 case HAL_QSPI_MSP_INIT_CB_ID :
1969 hqspi->MspInitCallback = pCallback;
1970 break;
1971 case HAL_QSPI_MSP_DEINIT_CB_ID :
1972 hqspi->MspDeInitCallback = pCallback;
1973 break;
1974 default :
1975 /* Update the error code */
1976 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
1977 /* update return status */
1978 status = HAL_ERROR;
1979 break;
1980 }
1981 }
1982 else
1983 {
1984 /* Update the error code */
1985 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
1986 /* update return status */
1987 status = HAL_ERROR;
1988 }
1989
1990 /* Release Lock */
1991 __HAL_UNLOCK(hqspi);
1992 return status;
1993 }
1994
1995 /**
1996 * @brief Unregister a User QSPI Callback
1997 * QSPI Callback is redirected to the weak (surcharged) predefined callback
1998 * @param hqspi : QSPI handle
1999 * @param CallbackId : ID of the callback to be unregistered
2000 * This parameter can be one of the following values:
2001 * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
2002 * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
2003 * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
2004 * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
2005 * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
2006 * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
2007 * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
2008 * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
2009 * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
2010 * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
2011 * @retval status
2012 */
2013 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
2014 {
2015 HAL_StatusTypeDef status = HAL_OK;
2016
2017 /* Process locked */
2018 __HAL_LOCK(hqspi);
2019
2020 if(hqspi->State == HAL_QSPI_STATE_READY)
2021 {
2022 switch (CallbackId)
2023 {
2024 case HAL_QSPI_ERROR_CB_ID :
2025 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
2026 break;
2027 case HAL_QSPI_ABORT_CB_ID :
2028 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
2029 break;
2030 case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
2031 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
2032 break;
2033 case HAL_QSPI_CMD_CPLT_CB_ID :
2034 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
2035 break;
2036 case HAL_QSPI_RX_CPLT_CB_ID :
2037 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
2038 break;
2039 case HAL_QSPI_TX_CPLT_CB_ID :
2040 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
2041 break;
2042 case HAL_QSPI_STATUS_MATCH_CB_ID :
2043 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
2044 break;
2045 case HAL_QSPI_TIMEOUT_CB_ID :
2046 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
2047 break;
2048 case HAL_QSPI_MSP_INIT_CB_ID :
2049 hqspi->MspInitCallback = HAL_QSPI_MspInit;
2050 break;
2051 case HAL_QSPI_MSP_DEINIT_CB_ID :
2052 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
2053 break;
2054 default :
2055 /* Update the error code */
2056 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
2057 /* update return status */
2058 status = HAL_ERROR;
2059 break;
2060 }
2061 }
2062 else if (hqspi->State == HAL_QSPI_STATE_RESET)
2063 {
2064 switch (CallbackId)
2065 {
2066 case HAL_QSPI_MSP_INIT_CB_ID :
2067 hqspi->MspInitCallback = HAL_QSPI_MspInit;
2068 break;
2069 case HAL_QSPI_MSP_DEINIT_CB_ID :
2070 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
2071 break;
2072 default :
2073 /* Update the error code */
2074 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
2075 /* update return status */
2076 status = HAL_ERROR;
2077 break;
2078 }
2079 }
2080 else
2081 {
2082 /* Update the error code */
2083 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
2084 /* update return status */
2085 status = HAL_ERROR;
2086 }
2087
2088 /* Release Lock */
2089 __HAL_UNLOCK(hqspi);
2090 return status;
2091 }
2092 #endif
2093
2094 /**
2095 * @}
2096 */
2097
2098 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
2099 * @brief QSPI control and State functions
2100 *
2101 @verbatim
2102 ===============================================================================
2103 ##### Peripheral Control and State functions #####
2104 ===============================================================================
2105 [..]
2106 This subsection provides a set of functions allowing to :
2107 (+) Check in run-time the state of the driver.
2108 (+) Check the error code set during last operation.
2109 (+) Abort any operation.
2110
2111
2112 @endverbatim
2113 * @{
2114 */
2115
2116 /**
2117 * @brief Return the QSPI handle state.
2118 * @param hqspi: QSPI handle
2119 * @retval HAL state
2120 */
2121 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
2122 {
2123 /* Return QSPI handle state */
2124 return hqspi->State;
2125 }
2126
2127 /**
2128 * @brief Return the QSPI error code.
2129 * @param hqspi: QSPI handle
2130 * @retval QSPI Error Code
2131 */
2132 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
2133 {
2134 return hqspi->ErrorCode;
2135 }
2136
2137 /**
2138 * @brief Abort the current transmission.
2139 * @param hqspi: QSPI handle
2140 * @retval HAL status
2141 */
2142 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
2143 {
2144 HAL_StatusTypeDef status = HAL_OK;
2145 uint32_t tickstart = HAL_GetTick();
2146
2147 /* Check if the state is in one of the busy states */
2148 if (((uint32_t)hqspi->State & 0x2U) != 0U)
2149 {
2150 /* Process unlocked */
2151 __HAL_UNLOCK(hqspi);
2152
2153 if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
2154 {
2155 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
2156 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
2157
2158 /* Abort MDMA */
2159 status = HAL_MDMA_Abort(hqspi->hmdma);
2160 if(status != HAL_OK)
2161 {
2162 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
2163 }
2164 }
2165
2166 /* Configure QSPI: CR register with Abort request */
2167 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
2168
2169 /* Wait until TC flag is set to go back in idle state */
2170 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
2171
2172 if(status == HAL_OK)
2173 {
2174 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
2175
2176 /* Wait until BUSY flag is reset */
2177 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
2178 }
2179
2180 if (status == HAL_OK)
2181 {
2182 /* Update state */
2183 hqspi->State = HAL_QSPI_STATE_READY;
2184 }
2185 }
2186
2187 return status;
2188 }
2189
2190 /**
2191 * @brief Abort the current transmission (non-blocking function)
2192 * @param hqspi: QSPI handle
2193 * @retval HAL status
2194 */
2195 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
2196 {
2197 HAL_StatusTypeDef status = HAL_OK;
2198
2199 /* Check if the state is in one of the busy states */
2200 if (((uint32_t)hqspi->State & 0x2U) != 0U)
2201 {
2202 /* Process unlocked */
2203 __HAL_UNLOCK(hqspi);
2204
2205 /* Update QSPI state */
2206 hqspi->State = HAL_QSPI_STATE_ABORT;
2207
2208 /* Disable all interrupts */
2209 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
2210
2211 if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
2212 {
2213 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
2214 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
2215
2216 /* Abort MDMA channel */
2217 hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
2218 if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
2219 {
2220 /* Set error code to DMA */
2221 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
2222
2223 status = HAL_ERROR;
2224 }
2225 }
2226 else
2227 {
2228 /* Clear interrupt */
2229 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
2230
2231 /* Enable the QSPI Transfer Complete Interrupt */
2232 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2233
2234 /* Configure QSPI: CR register with Abort request */
2235 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
2236 }
2237 }
2238 return status;
2239 }
2240
2241 /** @brief Set QSPI timeout.
2242 * @param hqspi: QSPI handle.
2243 * @param Timeout: Timeout for the QSPI memory access.
2244 * @retval None
2245 */
2246 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
2247 {
2248 hqspi->Timeout = Timeout;
2249 }
2250
2251 /** @brief Set QSPI Fifo threshold.
2252 * @param hqspi: QSPI handle.
2253 * @param Threshold: Threshold of the Fifo (value between 1 and 16).
2254 * @retval HAL status
2255 */
2256 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
2257 {
2258 HAL_StatusTypeDef status = HAL_OK;
2259
2260 /* Process locked */
2261 __HAL_LOCK(hqspi);
2262
2263 if(hqspi->State == HAL_QSPI_STATE_READY)
2264 {
2265 /* Synchronize init structure with new FIFO threshold value */
2266 hqspi->Init.FifoThreshold = Threshold;
2267
2268 /* Configure QSPI FIFO Threshold */
2269 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
2270 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
2271 }
2272 else
2273 {
2274 status = HAL_BUSY;
2275 }
2276
2277 /* Process unlocked */
2278 __HAL_UNLOCK(hqspi);
2279
2280 /* Return function status */
2281 return status;
2282 }
2283
2284 /** @brief Get QSPI Fifo threshold.
2285 * @param hqspi: QSPI handle.
2286 * @retval Fifo threshold (value between 1 and 16)
2287 */
2288 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
2289 {
2290 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
2291 }
2292
2293 /** @brief Set FlashID.
2294 * @param hqspi : QSPI handle.
2295 * @param FlashID : Index of the flash memory to be accessed.
2296 * This parameter can be a value of @ref QSPI_Flash_Select.
2297 * @note The FlashID is ignored when dual flash mode is enabled.
2298 * @retval HAL status
2299 */
2300 HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
2301 {
2302 HAL_StatusTypeDef status = HAL_OK;
2303
2304 /* Check the parameter */
2305 assert_param(IS_QSPI_FLASH_ID(FlashID));
2306
2307 /* Process locked */
2308 __HAL_LOCK(hqspi);
2309
2310 if(hqspi->State == HAL_QSPI_STATE_READY)
2311 {
2312 /* Synchronize init structure with new FlashID value */
2313 hqspi->Init.FlashID = FlashID;
2314
2315 /* Configure QSPI FlashID */
2316 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
2317 }
2318 else
2319 {
2320 status = HAL_BUSY;
2321 }
2322
2323 /* Process unlocked */
2324 __HAL_UNLOCK(hqspi);
2325
2326 /* Return function status */
2327 return status;
2328 }
2329
2330 /**
2331 * @}
2332 */
2333
2334 /**
2335 * @brief DMA QSPI receive process complete callback.
2336 * @param hmdma: MDMA handle
2337 * @retval None
2338 */
2339 static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
2340 {
2341 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
2342 hqspi->RxXferCount = 0U;
2343
2344 /* Enable the QSPI transfer complete Interrupt */
2345 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2346 }
2347
2348 /**
2349 * @brief DMA QSPI transmit process complete callback.
2350 * @param hmdma: MDMA handle
2351 * @retval None
2352 */
2353 static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
2354 {
2355 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
2356 hqspi->TxXferCount = 0U;
2357
2358 /* Enable the QSPI transfer complete Interrupt */
2359 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2360 }
2361
2362 /**
2363 * @brief DMA QSPI communication error callback.
2364 * @param hmdma: MDMA handle
2365 * @retval None
2366 */
2367 static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
2368 {
2369 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
2370
2371 hqspi->RxXferCount = 0U;
2372 hqspi->TxXferCount = 0U;
2373 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
2374
2375 /* Disable the MDMA transfer by clearing the DMAEN bit in the QSPI CR register */
2376 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
2377
2378 /* Abort the QSPI */
2379 (void)HAL_QSPI_Abort_IT(hqspi);
2380
2381 }
2382
2383 /**
2384 * @brief MDMA QSPI abort complete callback.
2385 * @param hmdma: MDMA handle
2386 * @retval None
2387 */
2388 static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
2389 {
2390 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
2391
2392 hqspi->RxXferCount = 0U;
2393 hqspi->TxXferCount = 0U;
2394
2395 if(hqspi->State == HAL_QSPI_STATE_ABORT)
2396 {
2397 /* MDMA Abort called by QSPI abort */
2398 /* Clear interrupt */
2399 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
2400
2401 /* Enable the QSPI Transfer Complete Interrupt */
2402 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2403
2404 /* Configure QSPI: CR register with Abort request */
2405 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
2406 }
2407 else
2408 {
2409 /* MDMA Abort called due to a transfer error interrupt */
2410 /* Change state of QSPI */
2411 hqspi->State = HAL_QSPI_STATE_READY;
2412
2413 /* Error callback */
2414 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
2415 hqspi->ErrorCallback(hqspi);
2416 #else
2417 HAL_QSPI_ErrorCallback(hqspi);
2418 #endif
2419 }
2420 }
2421 /**
2422 * @brief Wait for a flag state until timeout.
2423 * @param hqspi: QSPI handle
2424 * @param Flag: Flag checked
2425 * @param State: Value of the flag expected
2426 * @param Tickstart: Tick start value
2427 * @param Timeout: Duration of the timeout
2428 * @retval HAL status
2429 */
2430 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
2431 FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
2432 {
2433 /* Wait until flag is in expected state */
2434 while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
2435 {
2436 /* Check for the Timeout */
2437 if (Timeout != HAL_MAX_DELAY)
2438 {
2439 if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
2440 {
2441 hqspi->State = HAL_QSPI_STATE_ERROR;
2442 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
2443
2444 return HAL_ERROR;
2445 }
2446 }
2447 }
2448 return HAL_OK;
2449 }
2450
2451 /**
2452 * @brief Configure the communication registers.
2453 * @param hqspi: QSPI handle
2454 * @param cmd: structure that contains the command configuration information
2455 * @param FunctionalMode: functional mode to configured
2456 * This parameter can be one of the following values:
2457 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
2458 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
2459 * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
2460 * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
2461 * @retval None
2462 */
2463 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
2464 {
2465 assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
2466
2467 if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
2468 {
2469 /* Configure QSPI: DLR register with the number of data to read or write */
2470 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
2471 }
2472
2473 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
2474 {
2475 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
2476 {
2477 /* Configure QSPI: ABR register with alternate bytes value */
2478 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
2479
2480 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2481 {
2482 /*---- Command with instruction, address and alternate bytes ----*/
2483 /* Configure QSPI: CCR register with all communications parameters */
2484 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2485 cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
2486 cmd->AlternateBytesSize | cmd->AlternateByteMode |
2487 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
2488 cmd->Instruction | FunctionalMode));
2489
2490 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2491 {
2492 /* Configure QSPI: AR register with address value */
2493 WRITE_REG(hqspi->Instance->AR, cmd->Address);
2494 }
2495 }
2496 else
2497 {
2498 /*---- Command with instruction and alternate bytes ----*/
2499 /* Configure QSPI: CCR register with all communications parameters */
2500 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2501 cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
2502 cmd->AlternateBytesSize | cmd->AlternateByteMode |
2503 cmd->AddressMode | cmd->InstructionMode |
2504 cmd->Instruction | FunctionalMode));
2505 }
2506 }
2507 else
2508 {
2509 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2510 {
2511 /*---- Command with instruction and address ----*/
2512 /* Configure QSPI: CCR register with all communications parameters */
2513 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2514 cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
2515 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
2516 cmd->InstructionMode | cmd->Instruction | FunctionalMode));
2517
2518 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2519 {
2520 /* Configure QSPI: AR register with address value */
2521 WRITE_REG(hqspi->Instance->AR, cmd->Address);
2522 }
2523 }
2524 else
2525 {
2526 /*---- Command with only instruction ----*/
2527 /* Configure QSPI: CCR register with all communications parameters */
2528 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2529 cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
2530 cmd->AlternateByteMode | cmd->AddressMode |
2531 cmd->InstructionMode | cmd->Instruction | FunctionalMode));
2532 }
2533 }
2534 }
2535 else
2536 {
2537 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
2538 {
2539 /* Configure QSPI: ABR register with alternate bytes value */
2540 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
2541
2542 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2543 {
2544 /*---- Command with address and alternate bytes ----*/
2545 /* Configure QSPI: CCR register with all communications parameters */
2546 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2547 cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
2548 cmd->AlternateBytesSize | cmd->AlternateByteMode |
2549 cmd->AddressSize | cmd->AddressMode |
2550 cmd->InstructionMode | FunctionalMode));
2551
2552 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2553 {
2554 /* Configure QSPI: AR register with address value */
2555 WRITE_REG(hqspi->Instance->AR, cmd->Address);
2556 }
2557 }
2558 else
2559 {
2560 /*---- Command with only alternate bytes ----*/
2561 /* Configure QSPI: CCR register with all communications parameters */
2562 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2563 cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
2564 cmd->AlternateBytesSize | cmd->AlternateByteMode |
2565 cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
2566 }
2567 }
2568 else
2569 {
2570 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2571 {
2572 /*---- Command with only address ----*/
2573 /* Configure QSPI: CCR register with all communications parameters */
2574 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2575 cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
2576 cmd->AlternateByteMode | cmd->AddressSize |
2577 cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
2578
2579 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2580 {
2581 /* Configure QSPI: AR register with address value */
2582 WRITE_REG(hqspi->Instance->AR, cmd->Address);
2583 }
2584 }
2585 else
2586 {
2587 /*---- Command with only data phase ----*/
2588 if (cmd->DataMode != QSPI_DATA_NONE)
2589 {
2590 /* Configure QSPI: CCR register with all communications parameters */
2591 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2592 cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
2593 cmd->AlternateByteMode | cmd->AddressMode |
2594 cmd->InstructionMode | FunctionalMode));
2595 }
2596 }
2597 }
2598 }
2599 }
2600
2601 /**
2602 * @}
2603 */
2604
2605 /**
2606 * @}
2607 */
2608
2609 /**
2610 * @}
2611 */
2612
2613 #endif /* QUADSPI */
2614
2615 #endif /* HAL_QSPI_MODULE_ENABLED */
2616
2617 /**
2618 * @}
2619 */
2620
2621 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software