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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_fmc.c
blob9271b02ef2c5967e51d1cde743c2b3de5e50f85c
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### FMC peripheral features #####
16 ==============================================================================
17 [..] The Flexible memory controller (FMC) includes following memory controllers:
18 (+) The NOR/PSRAM memory controller
19 (+) The NAND memory controller
20 (+) The Synchronous DRAM (SDRAM) controller
21
22 [..] The FMC functional block makes the interface with synchronous and asynchronous static
23 memories and SDRAM memories. Its main purposes are:
24 (+) to translate AHB transactions into the appropriate external device protocol
25 (+) to meet the access time requirements of the external memory devices
26
27 [..] All external memories share the addresses, data and control signals with the controller.
28 Each external device is accessed by means of a unique Chip Select. The FMC performs
29 only one access at a time to an external device.
30 The main features of the FMC controller are the following:
31 (+) Interface with static-memory mapped devices including:
32 (++) Static random access memory (SRAM)
33 (++) Read-only memory (ROM)
34 (++) NOR Flash memory/OneNAND Flash memory
35 (++) PSRAM (4 memory banks)
36 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
37 data
38 (+) Interface with synchronous DRAM (SDRAM) memories
39 (+) Independent Chip Select control for each memory bank
40 (+) Independent configuration for each memory bank
41
42 @endverbatim
43 ******************************************************************************
44 * @attention
45 *
46 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
47 * All rights reserved.</center></h2>
48 *
49 * This software component is licensed by ST under BSD 3-Clause license,
50 * the "License"; You may not use this file except in compliance with the
51 * License. You may obtain a copy of the License at:
52 * opensource.org/licenses/BSD-3-Clause
53 *
54 ******************************************************************************
55 */
56
57 /* Includes ------------------------------------------------------------------*/
58 #include "stm32h7xx_hal.h"
59
60 /** @addtogroup STM32H7xx_HAL_Driver
61 * @{
62 */
63 #if (((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED)) || defined HAL_NAND_MODULE_ENABLED || defined HAL_SDRAM_MODULE_ENABLED)
64
65 /** @defgroup FMC_LL FMC Low Layer
66 * @brief FMC driver modules
67 * @{
68 */
69
70 /* Private typedef -----------------------------------------------------------*/
71 /* Private define ------------------------------------------------------------*/
72
73 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
74 * @{
75 */
76
77 /* ----------------------- FMC registers bit mask --------------------------- */
78
79 /* --- BCR Register ---*/
80 /* BCR register clear mask */
81
82 /* --- BTR Register ---*/
83 /* BTR register clear mask */
84 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
85 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
86 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
87 FMC_BTRx_ACCMOD))
88
89 /* --- BWTR Register ---*/
90 /* BWTR register clear mask */
91 #if defined(FMC_BWTRx_BUSTURN)
92 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
93 FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
94 FMC_BWTRx_ACCMOD))
95 #else
96 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
97 FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
98 #endif /* FMC_BWTRx_BUSTURN */
99
100 /* --- PCR Register ---*/
101 /* PCR register clear mask */
102 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
103 FMC_PCR_PWID | FMC_PCR_ECCEN | \
104 FMC_PCR_TCLR | FMC_PCR_TAR | \
105 FMC_PCR_ECCPS))
106 /* --- PMEM Register ---*/
107 /* PMEM register clear mask */
108 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\
109 FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
110
111 /* --- PATT Register ---*/
112 /* PATT register clear mask */
113 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\
114 FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
115
116
117 /* --- SDCR Register ---*/
118 /* SDCR register clear mask */
119 #define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCRx_NC | FMC_SDCRx_NR | \
120 FMC_SDCRx_MWID | FMC_SDCRx_NB | \
121 FMC_SDCRx_CAS | FMC_SDCRx_WP | \
122 FMC_SDCRx_SDCLK | FMC_SDCRx_RBURST | \
123 FMC_SDCRx_RPIPE))
124
125 /* --- SDTR Register ---*/
126 /* SDTR register clear mask */
127 #define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTRx_TMRD | FMC_SDTRx_TXSR | \
128 FMC_SDTRx_TRAS | FMC_SDTRx_TRC | \
129 FMC_SDTRx_TWR | FMC_SDTRx_TRP | \
130 FMC_SDTRx_TRCD))
131
132 /**
133 * @}
134 */
135
136 /* Private macro -------------------------------------------------------------*/
137 /* Private variables ---------------------------------------------------------*/
138 /* Private function prototypes -----------------------------------------------*/
139 /* Exported functions --------------------------------------------------------*/
140
141 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
142 * @{
143 */
144
145
146 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
147 * @brief NORSRAM Controller functions
148 *
149 @verbatim
150 ==============================================================================
151 ##### How to use NORSRAM device driver #####
152 ==============================================================================
153
154 [..]
155 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
156 to run the NORSRAM external devices.
157
158 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
159 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
160 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
161 (+) FMC NORSRAM bank extended timing configuration using the function
162 FMC_NORSRAM_Extended_Timing_Init()
163 (+) FMC NORSRAM bank enable/disable write operation using the functions
164 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
165
166 @endverbatim
167 * @{
168 */
169
170 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
171 * @brief Initialization and Configuration functions
172 *
173 @verbatim
174 ==============================================================================
175 ##### Initialization and de_initialization functions #####
176 ==============================================================================
177 [..]
178 This section provides functions allowing to:
179 (+) Initialize and configure the FMC NORSRAM interface
180 (+) De-initialize the FMC NORSRAM interface
181 (+) Configure the FMC clock and associated GPIOs
182
183 @endverbatim
184 * @{
185 */
186
187 /**
188 * @brief Initialize the FMC_NORSRAM device according to the specified
189 * control parameters in the FMC_NORSRAM_InitTypeDef
190 * @param Device Pointer to NORSRAM device instance
191 * @param Init Pointer to NORSRAM Initialization structure
192 * @retval HAL status
193 */
194 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
195 {
196 uint32_t flashaccess;
197
198 /* Check the parameters */
199 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
200 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
201 assert_param(IS_FMC_MUX(Init->DataAddressMux));
202 assert_param(IS_FMC_MEMORY(Init->MemoryType));
203 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
204 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
205 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
206 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
207 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
208 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
209 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
210 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
211 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
212 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
213 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
214 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
215
216 /* Disable NORSRAM Device */
217 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
218
219 /* Set NORSRAM device control parameters */
220 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
221 {
222 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
223 }
224 else
225 {
226 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
227 }
228
229 MODIFY_REG(Device->BTCR[Init->NSBank],
230 (FMC_BCRx_MBKEN |
231 FMC_BCRx_MUXEN |
232 FMC_BCRx_MTYP |
233 FMC_BCRx_MWID |
234 FMC_BCRx_FACCEN |
235 FMC_BCRx_BURSTEN |
236 FMC_BCRx_WAITPOL |
237 FMC_BCRx_WAITCFG |
238 FMC_BCRx_WREN |
239 FMC_BCRx_WAITEN |
240 FMC_BCRx_EXTMOD |
241 FMC_BCRx_ASYNCWAIT |
242 FMC_BCRx_CBURSTRW |
243 FMC_BCR1_CCLKEN |
244 FMC_BCR1_WFDIS |
245 FMC_BCRx_CPSIZE),
246 (flashaccess |
247 Init->DataAddressMux |
248 Init->MemoryType |
249 Init->MemoryDataWidth |
250 Init->BurstAccessMode |
251 Init->WaitSignalPolarity |
252 Init->WaitSignalActive |
253 Init->WriteOperation |
254 Init->WaitSignal |
255 Init->ExtendedMode |
256 Init->AsynchronousWait |
257 Init->WriteBurst |
258 Init->ContinuousClock |
259 Init->WriteFifo |
260 Init->PageSize));
261
262 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
263 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
264 {
265 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
266 }
267
268 if (Init->NSBank != FMC_NORSRAM_BANK1)
269 {
270 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
271 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
272 }
273
274 return HAL_OK;
275 }
276
277 /**
278 * @brief DeInitialize the FMC_NORSRAM peripheral
279 * @param Device Pointer to NORSRAM device instance
280 * @param ExDevice Pointer to NORSRAM extended mode device instance
281 * @param Bank NORSRAM bank number
282 * @retval HAL status
283 */
284 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
285 {
286 /* Check the parameters */
287 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
288 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
289 assert_param(IS_FMC_NORSRAM_BANK(Bank));
290
291 /* Disable the FMC_NORSRAM device */
292 __FMC_NORSRAM_DISABLE(Device, Bank);
293
294 /* De-initialize the FMC_NORSRAM device */
295 /* FMC_NORSRAM_BANK1 */
296 if (Bank == FMC_NORSRAM_BANK1)
297 {
298 Device->BTCR[Bank] = 0x000030DBU;
299 }
300 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
301 else
302 {
303 Device->BTCR[Bank] = 0x000030D2U;
304 }
305
306 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
307 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
308
309 return HAL_OK;
310 }
311
312 /**
313 * @brief Initialize the FMC_NORSRAM Timing according to the specified
314 * parameters in the FMC_NORSRAM_TimingTypeDef
315 * @param Device Pointer to NORSRAM device instance
316 * @param Timing Pointer to NORSRAM Timing structure
317 * @param Bank NORSRAM bank number
318 * @retval HAL status
319 */
320 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
321 {
322 uint32_t tmpr;
323
324 /* Check the parameters */
325 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
326 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
327 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
328 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
329 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
330 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
331 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
332 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
333 assert_param(IS_FMC_NORSRAM_BANK(Bank));
334
335 /* Set FMC_NORSRAM device timing parameters */
336 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
337 ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
338 ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
339 ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
340 (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
341 (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
342 (Timing->AccessMode)));
343
344 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
345 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
346 {
347 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
348 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
349 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
350 }
351
352 return HAL_OK;
353 }
354
355 /**
356 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
357 * parameters in the FMC_NORSRAM_TimingTypeDef
358 * @param Device Pointer to NORSRAM device instance
359 * @param Timing Pointer to NORSRAM Timing structure
360 * @param Bank NORSRAM bank number
361 * @param ExtendedMode FMC Extended Mode
362 * This parameter can be one of the following values:
363 * @arg FMC_EXTENDED_MODE_DISABLE
364 * @arg FMC_EXTENDED_MODE_ENABLE
365 * @retval HAL status
366 */
367 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
368 {
369 /* Check the parameters */
370 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
371
372 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
373 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
374 {
375 /* Check the parameters */
376 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
377 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
378 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
379 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
380 #if defined(FMC_BWTRx_BUSTURN)
381 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
382 #endif /* FMC_BWTRx_BUSTURN */
383 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
384 assert_param(IS_FMC_NORSRAM_BANK(Bank));
385
386 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
387 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
388 ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
389 ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
390 #if defined(FMC_BWTRx_BUSTURN)
391 Timing->AccessMode |
392 ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
393 #else
394 Timing->AccessMode));
395 #endif /* FMC_BWTRx_BUSTURN */
396 }
397 else
398 {
399 Device->BWTR[Bank] = 0x0FFFFFFFU;
400 }
401
402 return HAL_OK;
403 }
404 /**
405 * @}
406 */
407
408 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
409 * @brief management functions
410 *
411 @verbatim
412 ==============================================================================
413 ##### FMC_NORSRAM Control functions #####
414 ==============================================================================
415 [..]
416 This subsection provides a set of functions allowing to control dynamically
417 the FMC NORSRAM interface.
418
419 @endverbatim
420 * @{
421 */
422
423 /**
424 * @brief Enables dynamically FMC_NORSRAM write operation.
425 * @param Device Pointer to NORSRAM device instance
426 * @param Bank NORSRAM bank number
427 * @retval HAL status
428 */
429 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
430 {
431 /* Check the parameters */
432 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
433 assert_param(IS_FMC_NORSRAM_BANK(Bank));
434
435 /* Enable write operation */
436 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
437
438 return HAL_OK;
439 }
440
441 /**
442 * @brief Disables dynamically FMC_NORSRAM write operation.
443 * @param Device Pointer to NORSRAM device instance
444 * @param Bank NORSRAM bank number
445 * @retval HAL status
446 */
447 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
448 {
449 /* Check the parameters */
450 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
451 assert_param(IS_FMC_NORSRAM_BANK(Bank));
452
453 /* Disable write operation */
454 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
455
456 return HAL_OK;
457 }
458
459 /**
460 * @}
461 */
462
463 /**
464 * @}
465 */
466
467
468 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
469 * @brief NAND Controller functions
470 *
471 @verbatim
472 ==============================================================================
473 ##### How to use NAND device driver #####
474 ==============================================================================
475 [..]
476 This driver contains a set of APIs to interface with the FMC NAND banks in order
477 to run the NAND external devices.
478
479 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
480 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
481 (+) FMC NAND bank common space timing configuration using the function
482 FMC_NAND_CommonSpace_Timing_Init()
483 (+) FMC NAND bank attribute space timing configuration using the function
484 FMC_NAND_AttributeSpace_Timing_Init()
485 (+) FMC NAND bank enable/disable ECC correction feature using the functions
486 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
487 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
488
489 @endverbatim
490 * @{
491 */
492
493 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
494 * @brief Initialization and Configuration functions
495 *
496 @verbatim
497 ==============================================================================
498 ##### Initialization and de_initialization functions #####
499 ==============================================================================
500 [..]
501 This section provides functions allowing to:
502 (+) Initialize and configure the FMC NAND interface
503 (+) De-initialize the FMC NAND interface
504 (+) Configure the FMC clock and associated GPIOs
505
506 @endverbatim
507 * @{
508 */
509
510 /**
511 * @brief Initializes the FMC_NAND device according to the specified
512 * control parameters in the FMC_NAND_HandleTypeDef
513 * @param Device Pointer to NAND device instance
514 * @param Init Pointer to NAND Initialization structure
515 * @retval HAL status
516 */
517 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
518 {
519 /* Check the parameters */
520 assert_param(IS_FMC_NAND_DEVICE(Device));
521 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
522 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
523 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
524 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
525 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
526 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
527 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
528
529 /* NAND bank 3 registers configuration */
530 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
531 FMC_PCR_MEMORY_TYPE_NAND |
532 Init->MemoryDataWidth |
533 Init->EccComputation |
534 Init->ECCPageSize |
535 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
536 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
537
538 return HAL_OK;
539 }
540
541 /**
542 * @brief Initializes the FMC_NAND Common space Timing according to the specified
543 * parameters in the FMC_NAND_PCC_TimingTypeDef
544 * @param Device Pointer to NAND device instance
545 * @param Timing Pointer to NAND timing structure
546 * @param Bank NAND bank number
547 * @retval HAL status
548 */
549 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
550 {
551 /* Check the parameters */
552 assert_param(IS_FMC_NAND_DEVICE(Device));
553 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
554 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
555 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
556 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
557 assert_param(IS_FMC_NAND_BANK(Bank));
558
559 /* NAND bank 3 registers configuration */
560 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
561 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
562 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
563 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)));
564
565 return HAL_OK;
566 }
567
568 /**
569 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
570 * parameters in the FMC_NAND_PCC_TimingTypeDef
571 * @param Device Pointer to NAND device instance
572 * @param Timing Pointer to NAND timing structure
573 * @param Bank NAND bank number
574 * @retval HAL status
575 */
576 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
577 {
578 /* Check the parameters */
579 assert_param(IS_FMC_NAND_DEVICE(Device));
580 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
581 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
582 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
583 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
584 assert_param(IS_FMC_NAND_BANK(Bank));
585
586 /* NAND bank 3 registers configuration */
587 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
588 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
589 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
590 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)));
591
592 return HAL_OK;
593 }
594
595 /**
596 * @brief DeInitializes the FMC_NAND device
597 * @param Device Pointer to NAND device instance
598 * @param Bank NAND bank number
599 * @retval HAL status
600 */
601 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
602 {
603 /* Check the parameters */
604 assert_param(IS_FMC_NAND_DEVICE(Device));
605 assert_param(IS_FMC_NAND_BANK(Bank));
606
607 /* Disable the NAND Bank */
608 __FMC_NAND_DISABLE(Device, Bank);
609
610 /* De-initialize the NAND Bank */
611 /* Set the FMC_NAND_BANK3 registers to their reset values */
612 WRITE_REG(Device->PCR, 0x00000018U);
613 WRITE_REG(Device->SR, 0x00000040U);
614 WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
615 WRITE_REG(Device->PATT, 0xFCFCFCFCU);
616
617 return HAL_OK;
618 }
619
620 /**
621 * @}
622 */
623
624 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
625 * @brief management functions
626 *
627 @verbatim
628 ==============================================================================
629 ##### FMC_NAND Control functions #####
630 ==============================================================================
631 [..]
632 This subsection provides a set of functions allowing to control dynamically
633 the FMC NAND interface.
634
635 @endverbatim
636 * @{
637 */
638
639
640 /**
641 * @brief Enables dynamically FMC_NAND ECC feature.
642 * @param Device Pointer to NAND device instance
643 * @param Bank NAND bank number
644 * @retval HAL status
645 */
646 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
647 {
648 /* Check the parameters */
649 assert_param(IS_FMC_NAND_DEVICE(Device));
650 assert_param(IS_FMC_NAND_BANK(Bank));
651
652 /* Enable ECC feature */
653 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
654
655 return HAL_OK;
656 }
657
658
659 /**
660 * @brief Disables dynamically FMC_NAND ECC feature.
661 * @param Device Pointer to NAND device instance
662 * @param Bank NAND bank number
663 * @retval HAL status
664 */
665 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
666 {
667 /* Check the parameters */
668 assert_param(IS_FMC_NAND_DEVICE(Device));
669 assert_param(IS_FMC_NAND_BANK(Bank));
670
671 /* Disable ECC feature */
672 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
673
674 return HAL_OK;
675 }
676
677 /**
678 * @brief Disables dynamically FMC_NAND ECC feature.
679 * @param Device Pointer to NAND device instance
680 * @param ECCval Pointer to ECC value
681 * @param Bank NAND bank number
682 * @param Timeout Timeout wait value
683 * @retval HAL status
684 */
685 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
686 {
687 uint32_t tickstart;
688
689 /* Check the parameters */
690 assert_param(IS_FMC_NAND_DEVICE(Device));
691 assert_param(IS_FMC_NAND_BANK(Bank));
692
693 /* Get tick */
694 tickstart = HAL_GetTick();
695
696 /* Wait until FIFO is empty */
697 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
698 {
699 /* Check for the Timeout */
700 if (Timeout != HAL_MAX_DELAY)
701 {
702 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
703 {
704 return HAL_TIMEOUT;
705 }
706 }
707 }
708
709 /* Get the ECCR register value */
710 *ECCval = (uint32_t)Device->ECCR;
711
712 return HAL_OK;
713 }
714
715 /**
716 * @}
717 */
718
719
720
721 /** @defgroup FMC_LL_SDRAM
722 * @brief SDRAM Controller functions
723 *
724 @verbatim
725 ==============================================================================
726 ##### How to use SDRAM device driver #####
727 ==============================================================================
728 [..]
729 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
730 to run the SDRAM external devices.
731
732 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
733 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
734 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
735 (+) FMC SDRAM bank enable/disable write operation using the functions
736 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
737 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
738
739 @endverbatim
740 * @{
741 */
742
743 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
744 * @brief Initialization and Configuration functions
745 *
746 @verbatim
747 ==============================================================================
748 ##### Initialization and de_initialization functions #####
749 ==============================================================================
750 [..]
751 This section provides functions allowing to:
752 (+) Initialize and configure the FMC SDRAM interface
753 (+) De-initialize the FMC SDRAM interface
754 (+) Configure the FMC clock and associated GPIOs
755
756 @endverbatim
757 * @{
758 */
759
760 /**
761 * @brief Initializes the FMC_SDRAM device according to the specified
762 * control parameters in the FMC_SDRAM_InitTypeDef
763 * @param Device Pointer to SDRAM device instance
764 * @param Init Pointer to SDRAM Initialization structure
765 * @retval HAL status
766 */
767 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
768 {
769 /* Check the parameters */
770 assert_param(IS_FMC_SDRAM_DEVICE(Device));
771 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
772 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
773 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
774 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
775 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
776 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
777 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
778 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
779 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
780 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
781
782 /* Set SDRAM bank configuration parameters */
783 if (Init->SDBank == FMC_SDRAM_BANK1)
784 {
785 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
786 SDCR_CLEAR_MASK,
787 (Init->ColumnBitsNumber |
788 Init->RowBitsNumber |
789 Init->MemoryDataWidth |
790 Init->InternalBankNumber |
791 Init->CASLatency |
792 Init->WriteProtection |
793 Init->SDClockPeriod |
794 Init->ReadBurst |
795 Init->ReadPipeDelay));
796 }
797 else /* FMC_Bank2_SDRAM */
798 {
799 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
800 FMC_SDCRx_SDCLK |
801 FMC_SDCRx_RBURST |
802 FMC_SDCRx_RPIPE,
803 (Init->SDClockPeriod |
804 Init->ReadBurst |
805 Init->ReadPipeDelay));
806
807 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
808 SDCR_CLEAR_MASK,
809 (Init->ColumnBitsNumber |
810 Init->RowBitsNumber |
811 Init->MemoryDataWidth |
812 Init->InternalBankNumber |
813 Init->CASLatency |
814 Init->WriteProtection));
815 }
816
817 return HAL_OK;
818 }
819
820
821 /**
822 * @brief Initializes the FMC_SDRAM device timing according to the specified
823 * parameters in the FMC_SDRAM_TimingTypeDef
824 * @param Device Pointer to SDRAM device instance
825 * @param Timing Pointer to SDRAM Timing structure
826 * @param Bank SDRAM bank number
827 * @retval HAL status
828 */
829 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
830 {
831 /* Check the parameters */
832 assert_param(IS_FMC_SDRAM_DEVICE(Device));
833 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
834 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
835 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
836 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
837 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
838 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
839 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
840 assert_param(IS_FMC_SDRAM_BANK(Bank));
841
842 /* Set SDRAM device timing parameters */
843 if (Bank == FMC_SDRAM_BANK1)
844 {
845 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
846 SDTR_CLEAR_MASK,
847 (((Timing->LoadToActiveDelay) - 1U) |
848 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
849 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) |
850 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) |
851 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) |
852 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos) |
853 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos)));
854 }
855 else /* FMC_Bank2_SDRAM */
856 {
857 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
858 FMC_SDTRx_TRC |
859 FMC_SDTRx_TRP,
860 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) |
861 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos));
862
863 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
864 SDTR_CLEAR_MASK,
865 (((Timing->LoadToActiveDelay) - 1U) |
866 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
867 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) |
868 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) |
869 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos)));
870 }
871
872 return HAL_OK;
873 }
874
875 /**
876 * @brief DeInitializes the FMC_SDRAM peripheral
877 * @param Device Pointer to SDRAM device instance
878 * @retval HAL status
879 */
880 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
881 {
882 /* Check the parameters */
883 assert_param(IS_FMC_SDRAM_DEVICE(Device));
884 assert_param(IS_FMC_SDRAM_BANK(Bank));
885
886 /* De-initialize the SDRAM device */
887 Device->SDCR[Bank] = 0x000002D0U;
888 Device->SDTR[Bank] = 0x0FFFFFFFU;
889 Device->SDCMR = 0x00000000U;
890 Device->SDRTR = 0x00000000U;
891 Device->SDSR = 0x00000000U;
892
893 return HAL_OK;
894 }
895
896 /**
897 * @}
898 */
899
900 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
901 * @brief management functions
902 *
903 @verbatim
904 ==============================================================================
905 ##### FMC_SDRAM Control functions #####
906 ==============================================================================
907 [..]
908 This subsection provides a set of functions allowing to control dynamically
909 the FMC SDRAM interface.
910
911 @endverbatim
912 * @{
913 */
914
915 /**
916 * @brief Enables dynamically FMC_SDRAM write protection.
917 * @param Device Pointer to SDRAM device instance
918 * @param Bank SDRAM bank number
919 * @retval HAL status
920 */
921 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
922 {
923 /* Check the parameters */
924 assert_param(IS_FMC_SDRAM_DEVICE(Device));
925 assert_param(IS_FMC_SDRAM_BANK(Bank));
926
927 /* Enable write protection */
928 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
929
930 return HAL_OK;
931 }
932
933 /**
934 * @brief Disables dynamically FMC_SDRAM write protection.
935 * @param hsdram FMC_SDRAM handle
936 * @retval HAL status
937 */
938 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
939 {
940 /* Check the parameters */
941 assert_param(IS_FMC_SDRAM_DEVICE(Device));
942 assert_param(IS_FMC_SDRAM_BANK(Bank));
943
944 /* Disable write protection */
945 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
946
947 return HAL_OK;
948 }
949
950 /**
951 * @brief Send Command to the FMC SDRAM bank
952 * @param Device Pointer to SDRAM device instance
953 * @param Command Pointer to SDRAM command structure
954 * @param Timing Pointer to SDRAM Timing structure
955 * @param Timeout Timeout wait value
956 * @retval HAL state
957 */
958 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
959 {
960 /* Check the parameters */
961 assert_param(IS_FMC_SDRAM_DEVICE(Device));
962 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
963 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
964 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
965 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
966
967 /* Set command register */
968 SET_BIT(Device->SDCMR, ((Command->CommandMode) |
969 (Command->CommandTarget) |
970 (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
971 ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
972 /* Prevent unused argument(s) compilation warning */
973 UNUSED(Timeout);
974 return HAL_OK;
975 }
976
977 /**
978 * @brief Program the SDRAM Memory Refresh rate.
979 * @param Device Pointer to SDRAM device instance
980 * @param RefreshRate The SDRAM refresh rate value.
981 * @retval HAL state
982 */
983 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
984 {
985 /* Check the parameters */
986 assert_param(IS_FMC_SDRAM_DEVICE(Device));
987 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
988
989 /* Set the refresh rate in command register */
990 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
991
992 return HAL_OK;
993 }
994
995 /**
996 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
997 * @param Device Pointer to SDRAM device instance
998 * @param AutoRefreshNumber Specifies the auto Refresh number.
999 * @retval None
1000 */
1001 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
1002 {
1003 /* Check the parameters */
1004 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1005 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1006
1007 /* Set the Auto-refresh number in command register */
1008 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1009
1010 return HAL_OK;
1011 }
1012
1013 /**
1014 * @brief Returns the indicated FMC SDRAM bank mode status.
1015 * @param Device Pointer to SDRAM device instance
1016 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1017 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1018 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1019 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1020 * FMC_SDRAM_POWER_DOWN_MODE.
1021 */
1022 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1023 {
1024 uint32_t tmpreg;
1025
1026 /* Check the parameters */
1027 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1028 assert_param(IS_FMC_SDRAM_BANK(Bank));
1029
1030 /* Get the corresponding bank mode */
1031 if (Bank == FMC_SDRAM_BANK1)
1032 {
1033 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1034 }
1035 else
1036 {
1037 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1038 }
1039
1040 /* Return the mode status */
1041 return tmpreg;
1042 }
1043
1044 /**
1045 * @}
1046 */
1047
1048 /**
1049 * @}
1050 */
1051
1052
1053 /**
1054 * @}
1055 */
1056
1057 /**
1058 * @}
1059 */
1060
1061 #endif /* HAL_NOR_MODULE_ENABLED */
1062 /**
1063 * @}
1064 */
1065
1066 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software