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Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_mdma.c
blob5e3ab2b4c242f305c857fd7379b2e155c099ce76
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_mdma.c
4 * @author MCD Application Team
5 * @brief MDMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_mdma.h"
23 #include "stm32h7xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (MDMA)
35
36 /** @defgroup MDMA_LL MDMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup MDMA_LL_Private_Macros
45 * @{
46 */
47
48 #define IS_LL_MDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) (((INSTANCE) == MDMA) && \
49 (((CHANNEL) == LL_MDMA_CHANNEL_0) || \
50 ((CHANNEL) == LL_MDMA_CHANNEL_1) || \
51 ((CHANNEL) == LL_MDMA_CHANNEL_2) || \
52 ((CHANNEL) == LL_MDMA_CHANNEL_3) || \
53 ((CHANNEL) == LL_MDMA_CHANNEL_4) || \
54 ((CHANNEL) == LL_MDMA_CHANNEL_5) || \
55 ((CHANNEL) == LL_MDMA_CHANNEL_6) || \
56 ((CHANNEL) == LL_MDMA_CHANNEL_7) || \
57 ((CHANNEL) == LL_MDMA_CHANNEL_8) || \
58 ((CHANNEL) == LL_MDMA_CHANNEL_9) || \
59 ((CHANNEL) == LL_MDMA_CHANNEL_10)|| \
60 ((CHANNEL) == LL_MDMA_CHANNEL_11)|| \
61 ((CHANNEL) == LL_MDMA_CHANNEL_12)|| \
62 ((CHANNEL) == LL_MDMA_CHANNEL_13)|| \
63 ((CHANNEL) == LL_MDMA_CHANNEL_14)|| \
64 ((CHANNEL) == LL_MDMA_CHANNEL_15)|| \
65 ((CHANNEL) == LL_MDMA_CHANNEL_ALL)))
66
67 #define IS_LL_MDMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0x00010000U)
68
69 #define IS_LL_MDMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x00000FFFU)
70
71 #define IS_LL_MDMA_WORDENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_PRESERVE) || \
72 ((__VALUE__) == LL_MDMA_WORD_ENDIANNESS_EXCHANGE))
73
74 #define IS_LL_MDMA_HALFWORDENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE) || \
75 ((__VALUE__) == LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE))
76
77 #define IS_LL_MDMA_BYTEENDIANESS(__VALUE__) (((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_PRESERVE) || \
78 ((__VALUE__) == LL_MDMA_BYTE_ENDIANNESS_EXCHANGE))
79
80 #define IS_LL_MDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_MDMA_PRIORITY_LOW) || \
81 ((__VALUE__) == LL_MDMA_PRIORITY_MEDIUM) || \
82 ((__VALUE__) == LL_MDMA_PRIORITY_HIGH) || \
83 ((__VALUE__) == LL_MDMA_PRIORITY_VERYHIGH))
84
85 #define IS_LL_MDMA_BUFFWRITEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BUFF_WRITE_DISABLE) || \
86 ((__VALUE__) == LL_MDMA_BUFF_WRITE_ENABLE))
87
88 #define IS_LL_MDMA_REQUESTMODE(__VALUE__) (((__VALUE__) == LL_MDMA_REQUEST_MODE_HW) || \
89 ((__VALUE__) == LL_MDMA_REQUEST_MODE_SW))
90
91 #define IS_LL_MDMA_TRIGGERMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BUFFER_TRANSFER) || \
92 ((__VALUE__) == LL_MDMA_BLOCK_TRANSFER) || \
93 ((__VALUE__) == LL_MDMA_REPEAT_BLOCK_TRANSFER) || \
94 ((__VALUE__) == LL_MDMA_FULL_TRANSFER))
95
96 #define IS_LL_MDMA_PADDINGALIGNEMENT(__VALUE__) (((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT) || \
97 ((__VALUE__) == LL_MDMA_DATAALIGN_RIGHT_SIGNED) || \
98 ((__VALUE__) == LL_MDMA_DATAALIGN_LEFT))
99
100 #define IS_LL_MDMA_PACKMODE(__VALUE__) (((__VALUE__) == LL_MDMA_PACK_DISABLE) || \
101 ((__VALUE__) == LL_MDMA_PACK_ENABLE))
102
103 #define IS_LL_MDMA_BUFFER_XFERLENGTH(__VALUE__) ((__VALUE__) <= 0x0000007FU)
104
105 #define IS_LL_MDMA_DESTBURST(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_BURST_SINGLE) || \
106 ((__VALUE__) == LL_MDMA_DEST_BURST_2BEATS) || \
107 ((__VALUE__) == LL_MDMA_DEST_BURST_4BEATS) || \
108 ((__VALUE__) == LL_MDMA_DEST_BURST_8BEATS) || \
109 ((__VALUE__) == LL_MDMA_DEST_BURST_16BEATS)|| \
110 ((__VALUE__) == LL_MDMA_DEST_BURST_32BEATS)|| \
111 ((__VALUE__) == LL_MDMA_DEST_BURST_64BEATS)|| \
112 ((__VALUE__) == LL_MDMA_DEST_BURST_128BEATS))
113
114 #define IS_LL_MDMA_SRCTBURST(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_BURST_SINGLE) || \
115 ((__VALUE__) == LL_MDMA_SRC_BURST_2BEATS) || \
116 ((__VALUE__) == LL_MDMA_SRC_BURST_4BEATS) || \
117 ((__VALUE__) == LL_MDMA_SRC_BURST_8BEATS) || \
118 ((__VALUE__) == LL_MDMA_SRC_BURST_16BEATS)|| \
119 ((__VALUE__) == LL_MDMA_SRC_BURST_32BEATS)|| \
120 ((__VALUE__) == LL_MDMA_SRC_BURST_64BEATS)|| \
121 ((__VALUE__) == LL_MDMA_SRC_BURST_128BEATS))
122
123 #define IS_LL_MDMA_DESTINCSIZE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_BYTE) || \
124 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_HALFWORD) || \
125 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_WORD) || \
126 ((__VALUE__) == LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD))
127
128 #define IS_LL_MDMA_SRCINCSIZE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_BYTE) || \
129 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_HALFWORD) || \
130 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_WORD) || \
131 ((__VALUE__) == LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD))
132
133 #define IS_LL_MDMA_DESTDATASIZE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_BYTE) || \
134 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_HALFWORD) || \
135 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_WORD) || \
136 ((__VALUE__) == LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD))
137
138 #define IS_LL_MDMA_SRCDATASIZE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_BYTE) || \
139 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_HALFWORD) || \
140 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_WORD) || \
141 ((__VALUE__) == LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD))
142
143 #define IS_LL_MDMA_DESTINCMODE(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_FIXED) || \
144 ((__VALUE__) == LL_MDMA_DEST_INCREMENT) || \
145 ((__VALUE__) == LL_MDMA_DEST_DECREMENT))
146
147 #define IS_LL_MDMA_SRCINCMODE(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_FIXED) || \
148 ((__VALUE__) == LL_MDMA_SRC_INCREMENT) || \
149 ((__VALUE__) == LL_MDMA_SRC_DECREMENT))
150
151 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT) || \
152 ((__VALUE__) == LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT))
153
154
155 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(__VALUE__) (((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT) || \
156 ((__VALUE__) == LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT))
157
158 #define IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
159
160 #define IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
161
162 #define IS_LL_MDMA_DEST_BUS(__VALUE__) (((__VALUE__) == LL_MDMA_DEST_BUS_SYSTEM_AXI) || \
163 ((__VALUE__) == LL_MDMA_DEST_BUS_AHB_TCM))
164
165 #define IS_LL_MDMA_SRC_BUS(__VALUE__) (((__VALUE__) == LL_MDMA_SRC_BUS_SYSTEM_AXI) || \
166 ((__VALUE__) == LL_MDMA_SRC_BUS_AHB_TCM))
167 #if defined (QUADSPI) && defined (JPEG) && defined (DSI) /* STM32H747/57 devices */
168 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
169 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
170 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
171 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
172 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
173 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
174 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
175 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
176 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
177 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
178 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
179 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
180 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
181 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
182 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
183 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
184 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
185 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \
186 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \
187 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \
188 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \
189 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \
190 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \
191 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \
192 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
193 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
194 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
195 ((__VALUE__) == LL_MDMA_REQ_DSI_TEARING_EFFECT) || \
196 ((__VALUE__) == LL_MDMA_REQ_DSI_END_REFRESH) || \
197 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
198 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
199 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
200 #elif defined (QUADSPI) && defined (JPEG) /* STM32H743/53/45/55 devices */
201 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
202 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
203 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
204 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
205 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
206 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
207 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
208 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
209 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
210 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
211 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
212 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
213 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
214 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
215 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
216 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
217 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
218 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \
219 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \
220 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \
221 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \
222 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \
223 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \
224 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \
225 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
226 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
227 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
228 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
229 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
230 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
231 #elif defined (QUADSPI) /* STM32H742 devices */
232 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
233 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
234 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
235 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
236 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
237 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
238 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
239 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
240 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
241 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
242 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
243 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
244 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
245 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
246 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
247 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
248 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_FIFO_TH) || \
249 ((__VALUE__) == LL_MDMA_REQ_QUADSPI_TC) || \
250 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
251 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
252 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
253 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
254 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
255 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END))
256
257 #else /* STM32H7A3/B3 devices */
258 #define IS_LL_MDMA_HWTRIGGER(__VALUE__) (((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM0_TC) || \
259 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM1_TC) || \
260 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM2_TC) || \
261 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM3_TC) || \
262 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM4_TC) || \
263 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM5_TC) || \
264 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM6_TC) || \
265 ((__VALUE__) == LL_MDMA_REQ_DMA1_STREAM7_TC) || \
266 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM0_TC) || \
267 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM1_TC) || \
268 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM2_TC) || \
269 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM3_TC) || \
270 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM4_TC) || \
271 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM5_TC) || \
272 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM6_TC) || \
273 ((__VALUE__) == LL_MDMA_REQ_DMA2_STREAM7_TC) || \
274 ((__VALUE__) == LL_MDMA_REQ_LTDC_LINE_IT) || \
275 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_TH) || \
276 ((__VALUE__) == LL_MDMA_REQ_JPEG_INFIFO_NF) || \
277 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_TH) || \
278 ((__VALUE__) == LL_MDMA_REQ_JPEG_OUTFIFO_NE) || \
279 ((__VALUE__) == LL_MDMA_REQ_JPEG_END_CONVERSION) || \
280 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_FIFO_TH) || \
281 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI1_TC) || \
282 ((__VALUE__) == LL_MDMA_REQ_DMA2D_CLUT_TC) || \
283 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TC) || \
284 ((__VALUE__) == LL_MDMA_REQ_DMA2D_TW) || \
285 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_END_DATA) || \
286 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER) || \
287 ((__VALUE__) == LL_MDMA_REQ_SDMMC1_COMMAND_END) || \
288 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_FIFO_TH) || \
289 ((__VALUE__) == LL_MDMA_REQ_OCTOSPI2_TC))
290
291 #endif /* QUADSPI && JPEG && DSI */
292 /**
293 * @}
294 */
295
296 /* Private function prototypes -----------------------------------------------*/
297
298 /* Exported functions --------------------------------------------------------*/
299 /** @addtogroup MDMA_LL_Exported_Functions
300 * @{
301 */
302
303 /** @addtogroup MDMA_LL_EF_Init
304 * @{
305 */
306
307 /**
308 * @brief De-initialize the MDMA registers to their default reset values.
309 * @param MDMAx MDMAx Instance
310 * @param Channel This parameter can be one of the following values:
311 * @arg @ref LL_MDMA_CHANNEL_0
312 * @arg @ref LL_MDMA_CHANNEL_1
313 * @arg @ref LL_MDMA_CHANNEL_2
314 * @arg @ref LL_MDMA_CHANNEL_3
315 * @arg @ref LL_MDMA_CHANNEL_4
316 * @arg @ref LL_MDMA_CHANNEL_5
317 * @arg @ref LL_MDMA_CHANNEL_6
318 * @arg @ref LL_MDMA_CHANNEL_7
319 * @arg @ref LL_MDMA_CHANNEL_8
320 * @arg @ref LL_MDMA_CHANNEL_9
321 * @arg @ref LL_MDMA_CHANNEL_10
322 * @arg @ref LL_MDMA_CHANNEL_11
323 * @arg @ref LL_MDMA_CHANNEL_12
324 * @arg @ref LL_MDMA_CHANNEL_13
325 * @arg @ref LL_MDMA_CHANNEL_14
326 * @arg @ref LL_MDMA_CHANNEL_15
327 * @arg @ref LL_MDMA_CHANNEL_ALL
328 * @retval An ErrorStatus enumeration value:
329 * - SUCCESS: MDMA registers are de-initialized
330 * - ERROR: Not applicable
331 */
332 uint32_t LL_MDMA_DeInit(MDMA_TypeDef *MDMAx, uint32_t Channel)
333 {
334 MDMA_Channel_TypeDef *tmp;
335 ErrorStatus status = SUCCESS;
336
337 /* Check the MDMA Instance MDMAx and Channel parameters*/
338 assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
339
340 if (Channel == LL_MDMA_CHANNEL_ALL)
341 {
342 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_MDMA);
343 LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_MDMA);
344 }
345 else
346 {
347 /* Disable the selected Channel */
348 LL_MDMA_DisableChannel(MDMAx,Channel);
349
350 /* Get the MDMA Channel Instance */
351 tmp = (MDMA_Channel_TypeDef *)(LL_MDMA_GET_CHANNEL_INSTANCE(MDMAx, Channel));
352
353 /* Reset MDMAx_Channely control register */
354 LL_MDMA_WriteReg(tmp, CCR, 0U);
355
356 /* Reset MDMAx_Channely Configuration register */
357 LL_MDMA_WriteReg(tmp, CTCR, 0U);
358
359 /* Reset MDMAx_Channely block number of data register */
360 LL_MDMA_WriteReg(tmp, CBNDTR, 0U);
361
362 /* Reset MDMAx_Channely source address register */
363 LL_MDMA_WriteReg(tmp, CSAR, 0U);
364
365 /* Reset MDMAx_Channely destination address register */
366 LL_MDMA_WriteReg(tmp, CDAR, 0U);
367
368 /* Reset MDMAx_Channely Block Repeat address Update register */
369 LL_MDMA_WriteReg(tmp, CBRUR, 0U);
370
371 /* Reset MDMAx_Channely Link Address register */
372 LL_MDMA_WriteReg(tmp, CLAR, 0U);
373
374 /* Reset MDMAx_Channely Trigger and Bus selection register */
375 LL_MDMA_WriteReg(tmp, CTBR, 0U);
376
377 /* Reset MDMAx_Channely Mask address register */
378 LL_MDMA_WriteReg(tmp, CMAR, 0U);
379
380 /* Reset MDMAx_Channely Mask Data register */
381 LL_MDMA_WriteReg(tmp, CMDR, 0U);
382
383 /* Reset the Channel pending flags */
384 LL_MDMA_WriteReg(tmp, CIFCR, 0x0000001FU);
385 }
386
387 return (uint32_t)status;
388 }
389
390 /**
391 * @brief Initialize the MDMA registers according to the specified parameters in MDMA_InitStruct.
392 * @note To convert MDMAx_Channely Instance to MDMAx Instance and Channely, use helper macros :
393 * @arg @ref LL_MDMA_GET_INSTANCE
394 * @arg @ref LL_MDMA_GET_CHANNEL
395 * @param MDMAx MDMAx Instance
396 * @param Channel This parameter can be one of the following values:
397 * @arg @ref LL_MDMA_CHANNEL_0
398 * @arg @ref LL_MDMA_CHANNEL_1
399 * @arg @ref LL_MDMA_CHANNEL_2
400 * @arg @ref LL_MDMA_CHANNEL_3
401 * @arg @ref LL_MDMA_CHANNEL_4
402 * @arg @ref LL_MDMA_CHANNEL_5
403 * @arg @ref LL_MDMA_CHANNEL_6
404 * @arg @ref LL_MDMA_CHANNEL_7
405 * @arg @ref LL_MDMA_CHANNEL_8
406 * @arg @ref LL_MDMA_CHANNEL_9
407 * @arg @ref LL_MDMA_CHANNEL_10
408 * @arg @ref LL_MDMA_CHANNEL_11
409 * @arg @ref LL_MDMA_CHANNEL_12
410 * @arg @ref LL_MDMA_CHANNEL_13
411 * @arg @ref LL_MDMA_CHANNEL_14
412 * @arg @ref LL_MDMA_CHANNEL_15
413 * @param MDMA_InitStruct pointer to a @ref LL_MDMA_InitTypeDef structure.
414 * @retval An ErrorStatus enumeration value:
415 * - SUCCESS: MDMA registers are initialized
416 * - ERROR: Not applicable
417 */
418 uint32_t LL_MDMA_Init(MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct)
419 {
420 /* Check the MDMA Instance MDMAx and Channel parameters*/
421 assert_param(IS_LL_MDMA_ALL_CHANNEL_INSTANCE(MDMAx, Channel));
422
423 /* Check the MDMA parameters from MDMA_InitStruct */
424 assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
425 assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
426 assert_param(IS_LL_MDMA_WORDENDIANESS(MDMA_InitStruct->WordEndianess));
427 assert_param(IS_LL_MDMA_HALFWORDENDIANESS(MDMA_InitStruct->HalfWordEndianess));
428 assert_param(IS_LL_MDMA_BYTEENDIANESS(MDMA_InitStruct->ByteEndianess));
429 assert_param(IS_LL_MDMA_PRIORITY(MDMA_InitStruct->Priority));
430 assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
431 assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
432 assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
433 assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
434 assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
435 assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
436 assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
437 assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
438 assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
439 assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
440 assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
441 assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
442 assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
443 assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
444 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
445 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
446 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
447 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
448 assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
449 assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
450 assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
451
452
453 /*-------------------------- MDMAx CCR Configuration --------------------------
454 * Configure the Transfer endianness na priority with parameter :
455 * - WordEndianess: MDMA_CCR_WEX[14] bit
456 * - HalfWordEndianess: MDMA_CCR_HEX[13] bit
457 * - WordEndianess: MDMA_CCR_BEX[12] bit
458 * - Priority: MDMA_CCR_BEX[7:6] bits
459 */
460 LL_MDMA_ConfigXferEndianness(MDMAx, Channel, MDMA_InitStruct->WordEndianess | \
461 MDMA_InitStruct->HalfWordEndianess | \
462 MDMA_InitStruct->ByteEndianess);
463
464 LL_MDMA_SetChannelPriorityLevel(MDMAx, Channel, MDMA_InitStruct->Priority);
465
466 /*-------------------------- MDMAx CTCR Configuration --------------------------
467 * Configure the Transfer parameter :
468 * - BufferableWriteMode: MDMA_CTCR_BWM[31] bit
469 * - RequestMode: MDMA_CTCR_SWRM[30] bit
470 * - TriggerMode: MDMA_CTCR_TRGM[29:28] bits
471 * - PaddingAlignment: MDMA_CTCR_PAM[27:26] bits
472 * - PackMode: MDMA_CTCR_PKE[25] bit
473 * - BufferTransferLength: MDMA_CTCR_TLEN[24:18] bits
474 * - DestBurst: MDMA_CTCR_DBURST[17:15] bits
475 * - SrctBurst: MDMA_CTCR_SBURST[14:12] bits
476 * - DestIncSize: MDMA_CTCR_DINCOS[11:10] bits
477 * - SrcIncSize: MDMA_CTCR_SINCOS[9:8] bits
478 * - DestDataSize: MDMA_CTCR_DSIZE[7:6] bits
479 * - SrcDataSize: MDMA_CTCR_SSIZE[5:4] bits
480 * - DestIncMode: MDMA_CTCR_DINC[3:2] bits
481 * - SrcIncMode: MDMA_CTCR_SINC[1:0] bits
482 */
483 LL_MDMA_ConfigTransfer(MDMAx, Channel, MDMA_InitStruct->BufferableWriteMode | \
484 MDMA_InitStruct->RequestMode | \
485 MDMA_InitStruct->TriggerMode | \
486 MDMA_InitStruct->PaddingAlignment | \
487 MDMA_InitStruct->PackMode | \
488 MDMA_InitStruct->DestBurst | \
489 MDMA_InitStruct->SrctBurst | \
490 MDMA_InitStruct->DestIncSize | \
491 MDMA_InitStruct->SrcIncSize | \
492 MDMA_InitStruct->DestDataSize | \
493 MDMA_InitStruct->SrcDataSize | \
494 MDMA_InitStruct->DestIncMode | \
495 MDMA_InitStruct->SrcIncMode, MDMA_InitStruct->BufferTransferLength);
496
497 /*-------------------------- MDMAx CBNDTR Configuration --------------------------
498 * Configure the Transfer Block counters and update mode with parameter :
499 * - BlockRepeatCount: MDMA_CBNDTR_BRC[31:20] bits
500 * - BlockDataLength: MDMA_CBNDTR_BNDT[16:0] bits
501 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRDUM[19] bit
502 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRSUM[18] bit
503 */
504 LL_MDMA_ConfigBlkCounters(MDMAx, Channel, MDMA_InitStruct->BlockRepeatCount, MDMA_InitStruct->BlockDataLength);
505
506 LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMAx, Channel, MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \
507 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode);
508
509
510
511 /*-------------------------- MDMAx CSAR Configuration --------------------------
512 * Configure the Transfer source address with parameter :
513 * - SrcAddress: MDMA_CSAR_SAR[31:0] bits
514 */
515 LL_MDMA_SetSourceAddress(MDMAx, Channel, MDMA_InitStruct->SrcAddress);
516
517 /*-------------------------- MDMAx CDAR Configuration --------------------------
518 * Configure the Transfer destination address with parameter :
519 * - DstAddress: MDMA_CDAR_DAR[31:0] bits
520 */
521 LL_MDMA_SetDestinationAddress(MDMAx, Channel, MDMA_InitStruct->DstAddress);
522
523 /*-------------------------- MDMAx CBRUR Configuration --------------------------
524 * Configure the Transfer Block repeat address update value with parameter :
525 * - BlockRepeatDestAddrUpdateVal: MDMA_CBRUR_DUV[31:16] bits
526 * - BlockRepeatSrcAddrUpdateVal: MDMA_CBRUR_SUV[15:0] bits
527 */
528 LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMAx, Channel, MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal, \
529 MDMA_InitStruct->BlockRepeatDestAddrUpdateVal);
530
531 /*-------------------------- MDMAx CLAR Configuration --------------------------
532 * Configure the Transfer linked list address with parameter :
533 * - LinkAddress: MDMA_CLAR_LAR[31:0] bits
534 */
535 LL_MDMA_SetLinkAddress(MDMAx, Channel, MDMA_InitStruct->LinkAddress);
536
537 /*-------------------------- MDMAx CTBR Configuration --------------------------
538 * Configure the Transfer HW trigger and bus selection with parameter :
539 * - DestBus: MDMA_TBR_DBUS[17] bit
540 * - SrcBus: MDMA_TBR_SBUS[16] bit
541 * - HWTrigger: MDMA_TBR_TSEL[5:0] bits
542 */
543 LL_MDMA_ConfigBusSelection(MDMAx, Channel, MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus);
544
545 LL_MDMA_SetHWTrigger(MDMAx, Channel, MDMA_InitStruct->HWTrigger);
546
547 /*-------------------------- MDMAx CMAR Configuration --------------------------
548 * Configure the mask address with parameter :
549 * - MaskAddress: MDMA_CMAR_MAR[31:0] bits
550 */
551 LL_MDMA_SetMaskAddress(MDMAx, Channel, MDMA_InitStruct->MaskAddress);
552
553 /*-------------------------- MDMAx CMDR Configuration --------------------------
554 * Configure the mask data with parameter :
555 * - MaskData: MDMA_CMDR_MDR[31:0] bits
556 */
557 LL_MDMA_SetMaskData(MDMAx, Channel, MDMA_InitStruct->MaskData);
558
559 return (uint32_t)SUCCESS;
560 }
561
562 /**
563 * @brief Set each @ref LL_MDMA_InitTypeDef field to default value.
564 * @param MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure.
565 * @retval None
566 */
567 void LL_MDMA_StructInit(LL_MDMA_InitTypeDef *MDMA_InitStruct)
568 {
569 /* Set DMA_InitStruct fields to default values */
570 MDMA_InitStruct->SrcAddress = 0x00000000U;
571 MDMA_InitStruct->DstAddress = 0x00000000U;
572 MDMA_InitStruct->BlockDataLength = 0x00000000U;
573 MDMA_InitStruct->BlockRepeatCount = 0x00000000U;
574 MDMA_InitStruct->WordEndianess = LL_MDMA_WORD_ENDIANNESS_PRESERVE;
575 MDMA_InitStruct->HalfWordEndianess = LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE;
576 MDMA_InitStruct->ByteEndianess = LL_MDMA_BYTE_ENDIANNESS_PRESERVE;
577 MDMA_InitStruct->Priority = LL_MDMA_PRIORITY_LOW;
578 MDMA_InitStruct->BufferableWriteMode = LL_MDMA_BUFF_WRITE_DISABLE;
579 MDMA_InitStruct->RequestMode = LL_MDMA_REQUEST_MODE_HW;
580 MDMA_InitStruct->TriggerMode = LL_MDMA_BUFFER_TRANSFER;
581 MDMA_InitStruct->PaddingAlignment = LL_MDMA_DATAALIGN_RIGHT;
582 MDMA_InitStruct->PackMode = LL_MDMA_PACK_DISABLE;
583 MDMA_InitStruct->BufferTransferLength = 0x00000000U;
584 MDMA_InitStruct->DestBurst = LL_MDMA_DEST_BURST_SINGLE;
585 MDMA_InitStruct->SrctBurst = LL_MDMA_SRC_BURST_SINGLE;
586 MDMA_InitStruct->DestIncSize = LL_MDMA_DEST_INC_OFFSET_BYTE;
587 MDMA_InitStruct->SrcIncSize = LL_MDMA_SRC_INC_OFFSET_BYTE;
588 MDMA_InitStruct->DestDataSize = LL_MDMA_DEST_DATA_SIZE_BYTE;
589 MDMA_InitStruct->SrcDataSize = LL_MDMA_SRC_DATA_SIZE_BYTE;
590 MDMA_InitStruct->DestIncMode = LL_MDMA_DEST_FIXED;
591 MDMA_InitStruct->SrcIncMode = LL_MDMA_SRC_FIXED;
592 MDMA_InitStruct->BlockRepeatDestAddrUpdateMode = LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT;
593 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode = LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT;
594 MDMA_InitStruct->BlockRepeatDestAddrUpdateVal = 0x00000000U;
595 MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal = 0x00000000U;
596 MDMA_InitStruct->LinkAddress = 0x00000000U;
597 MDMA_InitStruct->DestBus = LL_MDMA_DEST_BUS_SYSTEM_AXI;
598 MDMA_InitStruct->SrcBus = LL_MDMA_SRC_BUS_SYSTEM_AXI;
599 MDMA_InitStruct->HWTrigger = LL_MDMA_REQ_DMA1_STREAM0_TC;
600 MDMA_InitStruct->MaskAddress = 0x00000000U;
601 MDMA_InitStruct->MaskData = 0x00000000U;
602 }
603
604 /**
605 * @brief Initializes MDMA linked list node according to the specified
606 * parameters in the MDMA_InitStruct.
607 * @param MDMA_InitStruct Pointer to a @ref LL_MDMA_InitTypeDef structure that contains
608 * linked list node registers configurations.
609 * @param pNode Pointer to linked list node to fill according to MDMA_InitStruct parameters.
610 * @retval None
611 */
612 void LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode)
613 {
614
615 /* Check the MDMA parameters from MDMA_InitStruct */
616 assert_param(IS_LL_MDMA_BLK_DATALENGTH(MDMA_InitStruct->BlockDataLength));
617 assert_param(IS_LL_MDMA_BLK_REPEATCOUNT(MDMA_InitStruct->BlockRepeatCount));
618
619 assert_param(IS_LL_MDMA_BUFFWRITEMODE(MDMA_InitStruct->BufferableWriteMode));
620 assert_param(IS_LL_MDMA_REQUESTMODE(MDMA_InitStruct->RequestMode));
621 assert_param(IS_LL_MDMA_TRIGGERMODE(MDMA_InitStruct->TriggerMode));
622 assert_param(IS_LL_MDMA_PADDINGALIGNEMENT(MDMA_InitStruct->PaddingAlignment));
623 assert_param(IS_LL_MDMA_PACKMODE(MDMA_InitStruct->PackMode));
624 assert_param(IS_LL_MDMA_BUFFER_XFERLENGTH(MDMA_InitStruct->BufferTransferLength));
625 assert_param(IS_LL_MDMA_DESTBURST(MDMA_InitStruct->DestBurst));
626 assert_param(IS_LL_MDMA_SRCTBURST(MDMA_InitStruct->SrctBurst));
627 assert_param(IS_LL_MDMA_DESTINCSIZE(MDMA_InitStruct->DestIncSize));
628 assert_param(IS_LL_MDMA_SRCINCSIZE(MDMA_InitStruct->SrcIncSize));
629 assert_param(IS_LL_MDMA_DESTDATASIZE(MDMA_InitStruct->DestDataSize));
630 assert_param(IS_LL_MDMA_SRCDATASIZE(MDMA_InitStruct->SrcDataSize));
631 assert_param(IS_LL_MDMA_DESTINCMODE(MDMA_InitStruct->DestIncMode));
632 assert_param(IS_LL_MDMA_SRCINCMODE(MDMA_InitStruct->SrcIncMode));
633 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatDestAddrUpdateMode));
634 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEMODE(MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode));
635 assert_param(IS_LL_MDMA_BLKRPT_DEST_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatDestAddrUpdateVal));
636 assert_param(IS_LL_MDMA_BLKRPT_SRC_ADDRUPDATEVAL(MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal));
637 assert_param(IS_LL_MDMA_DEST_BUS(MDMA_InitStruct->DestBus));
638 assert_param(IS_LL_MDMA_SRC_BUS(MDMA_InitStruct->SrcBus));
639 assert_param(IS_LL_MDMA_HWTRIGGER(MDMA_InitStruct->HWTrigger));
640
641
642 /*-------------------------- MDMAx CTCR Configuration --------------------------
643 * Configure the Transfer parameter :
644 * - BufferableWriteMode: MDMA_CTCR_BWM[31] bit
645 * - RequestMode: MDMA_CTCR_SWRM[30] bit
646 * - TriggerMode: MDMA_CTCR_TRGM[29:28] bits
647 * - PaddingAlignment: MDMA_CTCR_PAM[27:26] bits
648 * - PackMode: MDMA_CTCR_PKE[25] bit
649 * - BufferTransferLength: MDMA_CTCR_TLEN[24:18] bits
650 * - DestBurst: MDMA_CTCR_DBURST[17:15] bits
651 * - SrctBurst: MDMA_CTCR_SBURST[14:12] bits
652 * - DestIncSize: MDMA_CTCR_DINCOS[11:10] bits
653 * - SrcIncSize: MDMA_CTCR_SINCOS[9:8] bits
654 * - DestDataSize: MDMA_CTCR_DSIZE[7:6] bits
655 * - SrcDataSize: MDMA_CTCR_SSIZE[5:4] bits
656 * - DestIncMode: MDMA_CTCR_DINC[3:2] bits
657 * - SrcIncMode: MDMA_CTCR_SINC[1:0] bits
658 */
659 pNode->CTCR = MDMA_InitStruct->BufferableWriteMode | \
660 MDMA_InitStruct->RequestMode | \
661 MDMA_InitStruct->TriggerMode | \
662 MDMA_InitStruct->PaddingAlignment | \
663 MDMA_InitStruct->PackMode | \
664 MDMA_InitStruct->DestBurst | \
665 MDMA_InitStruct->SrctBurst | \
666 MDMA_InitStruct->DestIncSize | \
667 MDMA_InitStruct->SrcIncSize | \
668 MDMA_InitStruct->DestDataSize | \
669 MDMA_InitStruct->SrcDataSize | \
670 MDMA_InitStruct->DestIncMode | \
671 MDMA_InitStruct->SrcIncMode | \
672 ((MDMA_InitStruct->BufferTransferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk);
673
674
675
676 /*-------------------------- MDMAx CBNDTR Configuration --------------------------
677 * Configure the Transfer Block counters and update mode with parameter :
678 * - BlockRepeatCount: MDMA_CBNDTR_BRC[31:20] bits
679 * - BlockDataLength: MDMA_CBNDTR_BNDT[16:0] bits
680 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRDUM[19] bit
681 * - BlockRepeatDestAddrUpdateMode: MDMA_CBNDTR_BRSUM[18] bit
682 */
683 pNode->CBNDTR = ((MDMA_InitStruct->BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk) | \
684 MDMA_InitStruct->BlockRepeatDestAddrUpdateMode | \
685 MDMA_InitStruct->BlockRepeatSrcAddrUpdateMode | \
686 (MDMA_InitStruct->BlockDataLength & MDMA_CBNDTR_BNDT_Msk);
687
688
689 /*-------------------------- MDMAx CSAR Configuration --------------------------
690 * Configure the Transfer source address with parameter :
691 * - SrcAddress: MDMA_CSAR_SAR[31:0] bits
692 */
693 pNode->CSAR = MDMA_InitStruct->SrcAddress;
694
695
696 /*-------------------------- MDMAx CDAR Configuration --------------------------
697 * Configure the Transfer destination address with parameter :
698 * - DstAddress: MDMA_CDAR_DAR[31:0] bits
699 */
700 pNode->CDAR = MDMA_InitStruct->DstAddress;
701
702 /*-------------------------- MDMAx CBRUR Configuration --------------------------
703 * Configure the Transfer Block repeat address update value with parameter :
704 * - BlockRepeatDestAddrUpdateVal: MDMA_CBRUR_DUV[31:16] bits
705 * - BlockRepeatSrcAddrUpdateVal: MDMA_CBRUR_SUV[15:0] bits
706 */
707 pNode->CBRUR = (MDMA_InitStruct->BlockRepeatSrcAddrUpdateVal & MDMA_CBRUR_SUV_Msk) | \
708 ((MDMA_InitStruct->BlockRepeatDestAddrUpdateVal << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk) ;
709
710 /*-------------------------- MDMAx CLAR Configuration --------------------------
711 * Configure the Transfer linked list address with parameter :
712 * - LinkAddress: MDMA_CLAR_LAR[31:0] bits
713 */
714 pNode->CLAR = MDMA_InitStruct->LinkAddress;
715
716 /*-------------------------- MDMAx CTBR Configuration --------------------------
717 * Configure the Transfer HW trigger and bus selection with parameter :
718 * - DestBus: MDMA_TBR_DBUS[17] bit
719 * - SrcBus: MDMA_TBR_SBUS[16] bit
720 * - HWTrigger: MDMA_TBR_TSEL[5:0] bits
721 */
722 pNode->CTBR = MDMA_InitStruct->DestBus | MDMA_InitStruct->SrcBus | MDMA_InitStruct->HWTrigger;
723
724 /*-------------------------- MDMAx CMAR Configuration --------------------------
725 * Configure the mask address with parameter :
726 * - MaskAddress: MDMA_CMAR_MAR[31:0] bits
727 */
728 pNode->CMAR = MDMA_InitStruct->MaskAddress;
729
730 /*-------------------------- MDMAx CMDR Configuration --------------------------
731 * Configure the mask data with parameter :
732 * - MaskData: MDMA_CMDR_MDR[31:0] bits
733 */
734 pNode->CMDR = MDMA_InitStruct->MaskData;
735
736
737 pNode->Reserved = 0;
738
739 }
740
741 /**
742 * @brief Connect Linked list Nodes.
743 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Lined list node.
744 * @param pNewLinkNode Pointer to new Linked list.
745 * @retval None
746 */
747 void LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode)
748 {
749 pPrevLinkNode->CLAR = (uint32_t)pNewLinkNode;
750 }
751
752 /**
753 * @brief Disconnect the next linked list node.
754 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
755 * @retval None
756 */
757 void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode)
758 {
759 pLinkNode->CLAR = 0;
760 }
761
762 /**
763 * @}
764 */
765
766 /**
767 * @}
768 */
769
770 /**
771 * @}
772 */
773
774 #endif /* MDMA */
775
776 /**
777 * @}
778 */
779
780 #endif /* USE_FULL_LL_DRIVER */
781
782 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software