?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Set blackbox file handler to NULL after closing file
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Src / stm32h7xx_ll_rcc.c
blob9dd56c539db7476068b0edbff0850ece61a69512
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_rcc.h"
23 #include "stm32h7xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @addtogroup RCC_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @addtogroup RCC_LL_Private_Macros
46 * @{
47 */
48 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \
49 || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))
50
51
52 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \
53 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
54
55 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
56 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
58
59 #if defined(LL_RCC_SAI4A_CLKSOURCE)
60 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
63 || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
64 #else
65 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
66 || ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))
68 #endif /* LL_RCC_SAI4A_CLKSOURCE */
69
70 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
71 || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
73
74 /**
75 * @}
76 */
77
78 /* Private function prototypes -----------------------------------------------*/
79 /** @defgroup RCC_LL_Private_Functions RCC Private functions
80 * @{
81 */
82 uint32_t RCC_GetSystemClockFreq(void);
83 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
84 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
85 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
86 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
87 uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
88
89 /**
90 * @}
91 */
92
93
94 /* Exported functions --------------------------------------------------------*/
95 /** @addtogroup RCC_LL_Exported_Functions
96 * @{
97 */
98
99 /** @addtogroup RCC_LL_EF_Init
100 * @{
101 */
102
103 /**
104 * @brief Resets the RCC clock configuration to the default reset state.
105 * @note The default reset state of the clock configuration is given below:
106 * - HSI ON and used as system clock source
107 * - HSE, PLL1, PLL2 and PLL3 OFF
108 * - AHB, APB Bus pre-scaler set to 1.
109 * - CSS, MCO1 and MCO2 OFF
110 * - All interrupts disabled
111 * @note This function doesn't modify the configuration of the
112 * - Peripheral clocks
113 * - LSI, LSE and RTC clocks
114 * @retval None
115 */
116 void LL_RCC_DeInit(void)
117 {
118 /* Set HSION bit */
119 SET_BIT(RCC->CR, RCC_CR_HSION);
120
121 /* Wait for HSI READY bit */
122 while(LL_RCC_HSI_IsReady() == 0U)
123 {}
124
125 /* Reset CFGR register */
126 CLEAR_REG(RCC->CFGR);
127
128 /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
129 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON \
130 |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
131
132 /* Wait for PLL1 READY bit to be reset */
133 while(LL_RCC_PLL1_IsReady() != 0U)
134 {}
135
136 /* Wait for PLL2 READY bit to be reset */
137 while(LL_RCC_PLL2_IsReady() != 0U)
138 {}
139
140 /* Wait for PLL3 READY bit to be reset */
141 while(LL_RCC_PLL3_IsReady() != 0U)
142 {}
143
144 #if defined(RCC_D1CFGR_HPRE)
145 /* Reset D1CFGR register */
146 CLEAR_REG(RCC->D1CFGR);
147
148 /* Reset D2CFGR register */
149 CLEAR_REG(RCC->D2CFGR);
150
151 /* Reset D3CFGR register */
152 CLEAR_REG(RCC->D3CFGR);
153 #else
154 /* Reset CDCFGR1 register */
155 CLEAR_REG(RCC->CDCFGR1);
156
157 /* Reset CDCFGR2 register */
158 CLEAR_REG(RCC->CDCFGR2);
159
160 /* Reset SRDCFGR register */
161 CLEAR_REG(RCC->SRDCFGR);
162
163 #endif /* RCC_D1CFGR_HPRE */
164
165 /* Reset PLLCKSELR register to default value */
166 RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
167
168 /* Reset PLLCFGR register to default value */
169 LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U);
170
171 /* Reset PLL1DIVR register to default value */
172 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
173
174 /* Reset PLL1FRACR register */
175 CLEAR_REG(RCC->PLL1FRACR);
176
177 /* Reset PLL2DIVR register to default value */
178 LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
179
180 /* Reset PLL2FRACR register */
181 CLEAR_REG(RCC->PLL2FRACR);
182
183 /* Reset PLL3DIVR register to default value */
184 LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
185
186 /* Reset PLL3FRACR register */
187 CLEAR_REG(RCC->PLL3FRACR);
188
189 /* Reset HSEBYP bit */
190 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
191
192 /* Disable all interrupts */
193 CLEAR_REG(RCC->CIER);
194
195 /* Clear all interrupts */
196 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
197 | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
198 | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
199
200 /* Clear reset source flags */
201 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
202 }
203
204 /**
205 * @}
206 */
207
208 /** @addtogroup RCC_LL_EF_Get_Freq
209 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
210 * and different peripheral clocks available on the device.
211 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
212 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
213 * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
214 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
215 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
216 * @note (*) HSI_VALUE is a constant defined in header file (default value
217 * 64 MHz) divider by HSIDIV, but the real value may vary depending on
218 * on the variations in voltage and temperature.
219 * @note (**) HSE_VALUE is a constant defined in header file (default value
220 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
221 * frequency of the crystal used. Otherwise, this function may
222 * have wrong result.
223 * @note (***) CSI_VALUE is a constant defined in header file (default value
224 * 4 MHz) but the real value may vary depending on the variations
225 * in voltage and temperature.
226 * @note The result of this function could be incorrect when using fractional
227 * value for HSE crystal.
228 * @note This function can be used by the user application to compute the
229 * baud-rate for the communication peripherals or configure other parameters.
230 * @{
231 */
232
233 /**
234 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
235 * @note Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function
236 * must be called to update structure fields. Otherwise, any
237 * configuration based on this function will be incorrect.
238 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
239 * @retval None
240 */
241 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
242 {
243 /* Get SYSCLK frequency */
244 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
245
246 /* HCLK clock frequency */
247 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
248
249 /* PCLK1 clock frequency */
250 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
251
252 /* PCLK2 clock frequency */
253 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
254
255 /* PCLK3 clock frequency */
256 RCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
257
258 /* PCLK4 clock frequency */
259 RCC_Clocks->PCLK4_Frequency = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
260 }
261
262 /**
263 * @brief Return PLL1 clocks frequencies
264 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
265 * @retval None
266 */
267 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
268 {
269 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
270 uint32_t m, n, fracn = 0U;
271
272 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
273 SYSCLK = PLL_VCO / PLLP
274 */
275 pllsource = LL_RCC_PLL_GetSource();
276
277 switch (pllsource)
278 {
279 case LL_RCC_PLLSOURCE_HSI:
280 if (LL_RCC_HSI_IsReady() != 0U)
281 {
282 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
283 }
284 break;
285
286 case LL_RCC_PLLSOURCE_CSI:
287 if (LL_RCC_CSI_IsReady() != 0U)
288 {
289 pllinputfreq = CSI_VALUE;
290 }
291 break;
292
293 case LL_RCC_PLLSOURCE_HSE:
294 if (LL_RCC_HSE_IsReady() != 0U)
295 {
296 pllinputfreq = HSE_VALUE;
297 }
298 break;
299
300 case LL_RCC_PLLSOURCE_NONE:
301 default:
302 /* PLL clock disabled */
303 break;
304 }
305
306 PLL_Clocks->PLL_P_Frequency = 0U;
307 PLL_Clocks->PLL_Q_Frequency = 0U;
308 PLL_Clocks->PLL_R_Frequency = 0U;
309
310 m = LL_RCC_PLL1_GetM();
311 n = LL_RCC_PLL1_GetN();
312 if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
313 {
314 fracn = LL_RCC_PLL1_GetFRACN();
315 }
316
317 if (m != 0U)
318 {
319 if (LL_RCC_PLL1P_IsEnabled() != 0U)
320 {
321 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP());
322 }
323
324 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
325 {
326 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ());
327 }
328
329 if (LL_RCC_PLL1R_IsEnabled() != 0U)
330 {
331 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR());
332 }
333 }
334 }
335
336 /**
337 * @brief Return PLL2 clocks frequencies
338 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
339 * @retval None
340 */
341 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
342 {
343 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
344 uint32_t m, n, fracn = 0U;
345
346 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
347 SYSCLK = PLL_VCO / PLLP
348 */
349 pllsource = LL_RCC_PLL_GetSource();
350
351 switch (pllsource)
352 {
353 case LL_RCC_PLLSOURCE_HSI:
354 if (LL_RCC_HSI_IsReady() != 0U)
355 {
356 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
357 }
358 break;
359
360 case LL_RCC_PLLSOURCE_CSI:
361 if (LL_RCC_CSI_IsReady() != 0U)
362 {
363 pllinputfreq = CSI_VALUE;
364 }
365 break;
366
367 case LL_RCC_PLLSOURCE_HSE:
368 if (LL_RCC_HSE_IsReady() != 0U)
369 {
370 pllinputfreq = HSE_VALUE;
371 }
372 break;
373
374 case LL_RCC_PLLSOURCE_NONE:
375 default:
376 /* PLL clock disabled */
377 break;
378 }
379
380 PLL_Clocks->PLL_P_Frequency = 0U;
381 PLL_Clocks->PLL_Q_Frequency = 0U;
382 PLL_Clocks->PLL_R_Frequency = 0U;
383
384 m = LL_RCC_PLL2_GetM();
385 n = LL_RCC_PLL2_GetN();
386 if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
387 {
388 fracn = LL_RCC_PLL2_GetFRACN();
389 }
390
391 if (m != 0U)
392 {
393 if (LL_RCC_PLL2P_IsEnabled() != 0U)
394 {
395 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP());
396 }
397
398 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
399 {
400 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ());
401 }
402
403 if (LL_RCC_PLL2R_IsEnabled() != 0U)
404 {
405 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR());
406 }
407 }
408 }
409
410 /**
411 * @brief Return PLL3 clocks frequencies
412 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
413 * @retval None
414 */
415 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
416 {
417 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
418 uint32_t m, n, fracn = 0U;
419
420 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
421 SYSCLK = PLL_VCO / PLLP
422 */
423 pllsource = LL_RCC_PLL_GetSource();
424
425 switch (pllsource)
426 {
427 case LL_RCC_PLLSOURCE_HSI:
428 if (LL_RCC_HSI_IsReady() != 0U)
429 {
430 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
431 }
432 break;
433
434 case LL_RCC_PLLSOURCE_CSI:
435 if (LL_RCC_CSI_IsReady() != 0U)
436 {
437 pllinputfreq = CSI_VALUE;
438 }
439 break;
440
441 case LL_RCC_PLLSOURCE_HSE:
442 if (LL_RCC_HSE_IsReady() != 0U)
443 {
444 pllinputfreq = HSE_VALUE;
445 }
446 break;
447
448 case LL_RCC_PLLSOURCE_NONE:
449 default:
450 /* PLL clock disabled */
451 break;
452 }
453
454 PLL_Clocks->PLL_P_Frequency = 0U;
455 PLL_Clocks->PLL_Q_Frequency = 0U;
456 PLL_Clocks->PLL_R_Frequency = 0U;
457
458 m = LL_RCC_PLL3_GetM();
459 n = LL_RCC_PLL3_GetN();
460 if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
461 {
462 fracn = LL_RCC_PLL3_GetFRACN();
463 }
464
465 if ((m != 0U) && (pllinputfreq != 0U))
466 {
467 if (LL_RCC_PLL3P_IsEnabled() != 0U)
468 {
469 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP());
470 }
471
472 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
473 {
474 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ());
475 }
476
477 if (LL_RCC_PLL3R_IsEnabled() != 0U)
478 {
479 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR());
480 }
481 }
482 }
483
484 /**
485 * @brief Helper function to calculate the PLL frequency output
486 * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
487 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
488 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
489 * @param M Between 1 and 63
490 * @param N Between 4 and 512
491 * @param FRACN Between 0 and 0x1FFF
492 * @param PQR VCO output divider (P, Q or R)
493 * Between 1 and 128, except for PLL1P Odd value not allowed
494 * @retval PLL1 clock frequency (in Hz)
495 */
496 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
497 {
498 float_t freq;
499
500 freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN/(float_t)0x2000));
501
502 freq = freq/(float_t)PQR;
503
504 return (uint32_t)freq;
505 }
506
507 /**
508 * @brief Return USARTx clock frequency
509 * @param USARTxSource This parameter can be one of the following values:
510 * @arg @ref LL_RCC_USART16_CLKSOURCE
511 * @arg @ref LL_RCC_USART234578_CLKSOURCE
512 * @retval USART clock frequency (in Hz)
513 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
514 */
515 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
516 {
517 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
518 LL_PLL_ClocksTypeDef PLL_Clocks;
519
520 /* Check parameter */
521 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
522
523 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
524 {
525 case LL_RCC_USART16_CLKSOURCE_PCLK2:
526 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
527 break;
528
529 case LL_RCC_USART234578_CLKSOURCE_PCLK1:
530 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
531 break;
532
533 case LL_RCC_USART16_CLKSOURCE_PLL2Q:
534 case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
535 if (LL_RCC_PLL2_IsReady() != 0U)
536 {
537 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
538 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
539 }
540 break;
541
542 case LL_RCC_USART16_CLKSOURCE_PLL3Q:
543 case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
544 if (LL_RCC_PLL3_IsReady() != 0U)
545 {
546 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
547 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
548 }
549 break;
550
551 case LL_RCC_USART16_CLKSOURCE_HSI:
552 case LL_RCC_USART234578_CLKSOURCE_HSI:
553 if (LL_RCC_HSI_IsReady() != 0U)
554 {
555 usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
556 }
557 break;
558
559 case LL_RCC_USART16_CLKSOURCE_CSI:
560 case LL_RCC_USART234578_CLKSOURCE_CSI:
561 if (LL_RCC_CSI_IsReady() != 0U)
562 {
563 usart_frequency = CSI_VALUE;
564 }
565 break;
566
567 case LL_RCC_USART16_CLKSOURCE_LSE:
568 case LL_RCC_USART234578_CLKSOURCE_LSE:
569 if (LL_RCC_LSE_IsReady() != 0U)
570 {
571 usart_frequency = LSE_VALUE;
572 }
573 break;
574
575 default:
576 /* Kernel clock disabled */
577 break;
578 }
579
580 return usart_frequency;
581 }
582
583 /**
584 * @brief Return LPUART clock frequency
585 * @param LPUARTxSource This parameter can be one of the following values:
586 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
587 * @retval LPUART clock frequency (in Hz)
588 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
589 */
590 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
591 {
592 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
593 LL_PLL_ClocksTypeDef PLL_Clocks;
594
595 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
596 {
597 case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
598 lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
599 break;
600
601 case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
602 if (LL_RCC_PLL2_IsReady() != 0U)
603 {
604 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
605 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
606 }
607 break;
608
609 case LL_RCC_LPUART1_CLKSOURCE_PLL3Q:
610 if (LL_RCC_PLL3_IsReady() != 0U)
611 {
612 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
613 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
614 }
615 break;
616
617 case LL_RCC_LPUART1_CLKSOURCE_HSI:
618 if (LL_RCC_HSI_IsReady() != 0U)
619 {
620 lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
621 }
622 break;
623
624 case LL_RCC_LPUART1_CLKSOURCE_CSI:
625 if (LL_RCC_CSI_IsReady() != 0U)
626 {
627 lpuart_frequency = CSI_VALUE;
628 }
629 break;
630
631 case LL_RCC_LPUART1_CLKSOURCE_LSE:
632 if (LL_RCC_LSE_IsReady() != 0U)
633 {
634 lpuart_frequency = LSE_VALUE;
635 }
636 break;
637
638 default:
639 /* Kernel clock disabled */
640 break;
641 }
642
643 return lpuart_frequency;
644 }
645
646 /**
647 * @brief Return I2Cx clock frequency
648 * @param I2CxSource This parameter can be one of the following values:
649 * @arg @ref LL_RCC_I2C123_CLKSOURCE
650 * @arg @ref LL_RCC_I2C4_CLKSOURCE
651 * @retval I2C clock frequency (in Hz)
652 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
653 */
654 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
655 {
656 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
657 LL_PLL_ClocksTypeDef PLL_Clocks;
658
659 /* Check parameter */
660 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
661
662 switch (LL_RCC_GetI2CClockSource(I2CxSource))
663 {
664 case LL_RCC_I2C123_CLKSOURCE_PCLK1:
665 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
666 break;
667
668 case LL_RCC_I2C4_CLKSOURCE_PCLK4:
669 i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
670 break;
671
672 case LL_RCC_I2C123_CLKSOURCE_PLL3R:
673 case LL_RCC_I2C4_CLKSOURCE_PLL3R:
674 if (LL_RCC_PLL3_IsReady() != 0U)
675 {
676 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
677 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
678 }
679 break;
680
681 case LL_RCC_I2C123_CLKSOURCE_HSI:
682 case LL_RCC_I2C4_CLKSOURCE_HSI:
683 if (LL_RCC_HSI_IsReady() != 0U)
684 {
685 i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
686 }
687 break;
688
689 case LL_RCC_I2C123_CLKSOURCE_CSI:
690 case LL_RCC_I2C4_CLKSOURCE_CSI:
691 if (LL_RCC_CSI_IsReady() != 0U)
692 {
693 i2c_frequency = CSI_VALUE;
694 }
695 break;
696
697 default:
698 /* Nothing to do */
699 break;
700 }
701
702 return i2c_frequency;
703 }
704
705 /**
706 * @brief Return LPTIMx clock frequency
707 * @param LPTIMxSource This parameter can be one of the following values:
708 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
709 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
710 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE
711 * @retval LPTIM clock frequency (in Hz)
712 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
713 */
714 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
715 {
716 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
717 LL_PLL_ClocksTypeDef PLL_Clocks;
718
719 /* Check parameter */
720 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
721
722 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
723 {
724 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
725 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
726 break;
727
728 case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
729 case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
730 lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
731 break;
732
733 case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
734 case LL_RCC_LPTIM2_CLKSOURCE_PLL2P:
735 case LL_RCC_LPTIM345_CLKSOURCE_PLL2P:
736 if (LL_RCC_PLL2_IsReady() != 0U)
737 {
738 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
739 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
740 }
741 break;
742
743 case LL_RCC_LPTIM1_CLKSOURCE_PLL3R:
744 case LL_RCC_LPTIM2_CLKSOURCE_PLL3R:
745 case LL_RCC_LPTIM345_CLKSOURCE_PLL3R:
746 if (LL_RCC_PLL3_IsReady() != 0U)
747 {
748 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
749 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
750 }
751 break;
752
753 case LL_RCC_LPTIM1_CLKSOURCE_LSE:
754 case LL_RCC_LPTIM2_CLKSOURCE_LSE:
755 case LL_RCC_LPTIM345_CLKSOURCE_LSE:
756 if (LL_RCC_LSE_IsReady() != 0U)
757 {
758 lptim_frequency = LSE_VALUE;
759 }
760 break;
761
762 case LL_RCC_LPTIM1_CLKSOURCE_LSI:
763 case LL_RCC_LPTIM2_CLKSOURCE_LSI:
764 case LL_RCC_LPTIM345_CLKSOURCE_LSI:
765 if (LL_RCC_LSI_IsReady() != 0U)
766 {
767 lptim_frequency = LSI_VALUE;
768 }
769 break;
770
771 case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
772 case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
773 case LL_RCC_LPTIM345_CLKSOURCE_CLKP:
774 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
775 break;
776
777 default:
778 /* Kernel clock disabled */
779 break;
780 }
781
782 return lptim_frequency;
783 }
784
785 /**
786 * @brief Return SAIx clock frequency
787 * @param SAIxSource This parameter can be one of the following values:
788 * @arg @ref LL_RCC_SAI1_CLKSOURCE
789 * @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
790 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
791 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
792 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
793 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
794 * @retval SAI clock frequency (in Hz)
795 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
796 *
797 * (*) : Available on some STM32H7 lines only.
798 */
799 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
800 {
801 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
802 LL_PLL_ClocksTypeDef PLL_Clocks;
803
804 /* Check parameter */
805 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
806
807 switch (LL_RCC_GetSAIClockSource(SAIxSource))
808 {
809 case LL_RCC_SAI1_CLKSOURCE_PLL1Q:
810 #if defined(SAI3)
811 case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
812 #endif /* SAI3 */
813 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
814 case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
815 case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
816 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
817 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
818 case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
819 case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
820 #endif /* (SAI4_Block_A) || (SAI4_Block_B) */
821 if (LL_RCC_PLL1_IsReady() != 0U)
822 {
823 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
824 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
825 }
826 break;
827
828 case LL_RCC_SAI1_CLKSOURCE_PLL2P:
829 #if defined(SAI3)
830 case LL_RCC_SAI23_CLKSOURCE_PLL2P:
831 #endif /* SAI3 */
832 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
833 case LL_RCC_SAI2A_CLKSOURCE_PLL2P:
834 case LL_RCC_SAI2B_CLKSOURCE_PLL2P:
835 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
836 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
837 case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
838 case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
839 #endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
840 if (LL_RCC_PLL2_IsReady() != 0U)
841 {
842 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
843 sai_frequency = PLL_Clocks.PLL_P_Frequency;
844 }
845 break;
846
847 case LL_RCC_SAI1_CLKSOURCE_PLL3P:
848 #if defined(SAI3)
849 case LL_RCC_SAI23_CLKSOURCE_PLL3P:
850 #endif /* SAI3 */
851 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
852 case LL_RCC_SAI2A_CLKSOURCE_PLL3P:
853 case LL_RCC_SAI2B_CLKSOURCE_PLL3P:
854 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
855 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
856 case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
857 case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
858 #endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
859 if (LL_RCC_PLL3_IsReady() != 0U)
860 {
861 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
862 sai_frequency = PLL_Clocks.PLL_P_Frequency;
863 }
864 break;
865
866 case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
867 #if defined(SAI3)
868 case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
869 #endif /* SAI3 */
870 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
871 case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN:
872 case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN:
873 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
874 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
875 case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
876 case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
877 #endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
878 sai_frequency = EXTERNAL_CLOCK_VALUE;
879 break;
880
881 case LL_RCC_SAI1_CLKSOURCE_CLKP:
882 #if defined(SAI3)
883 case LL_RCC_SAI23_CLKSOURCE_CLKP:
884 #endif /* SAI3 */
885 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
886 case LL_RCC_SAI2A_CLKSOURCE_CLKP:
887 case LL_RCC_SAI2B_CLKSOURCE_CLKP:
888 #endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
889 #if defined(SAI4_Block_A) || defined(SAI4_Block_B)
890 case LL_RCC_SAI4A_CLKSOURCE_CLKP:
891 case LL_RCC_SAI4B_CLKSOURCE_CLKP:
892 #endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
893 sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
894 break;
895
896 default:
897 /* Kernel clock disabled */
898 break;
899 }
900
901 return sai_frequency;
902 }
903
904 /**
905 * @brief Return ADC clock frequency
906 * @param ADCxSource This parameter can be one of the following values:
907 * @arg @ref LL_RCC_ADC_CLKSOURCE
908 * @retval ADC clock frequency (in Hz)
909 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
910 */
911 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
912 {
913 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
914 LL_PLL_ClocksTypeDef PLL_Clocks;
915
916 switch (LL_RCC_GetADCClockSource(ADCxSource))
917 {
918 case LL_RCC_ADC_CLKSOURCE_PLL2P:
919 if (LL_RCC_PLL2_IsReady() != 0U)
920 {
921 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
922 adc_frequency = PLL_Clocks.PLL_P_Frequency;
923 }
924 break;
925
926 case LL_RCC_ADC_CLKSOURCE_PLL3R:
927 if (LL_RCC_PLL3_IsReady() != 0U)
928 {
929 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
930 adc_frequency = PLL_Clocks.PLL_R_Frequency;
931 }
932 break;
933
934 case LL_RCC_ADC_CLKSOURCE_CLKP:
935 adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
936 break;
937
938 default:
939 /* Kernel clock disabled */
940 break;
941 }
942
943 return adc_frequency;
944 }
945
946 /**
947 * @brief Return SDMMC clock frequency
948 * @param SDMMCxSource This parameter can be one of the following values:
949 * @arg @ref LL_RCC_SDMMC_CLKSOURCE
950 * @retval SDMMC clock frequency (in Hz)
951 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
952 */
953 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
954 {
955 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
956 LL_PLL_ClocksTypeDef PLL_Clocks;
957
958 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
959 {
960 case LL_RCC_SDMMC_CLKSOURCE_PLL1Q:
961 if (LL_RCC_PLL1_IsReady() != 0U)
962 {
963 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
964 sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
965 }
966 break;
967
968 case LL_RCC_SDMMC_CLKSOURCE_PLL2R:
969 if (LL_RCC_PLL2_IsReady() != 0U)
970 {
971 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
972 sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
973 }
974 break;
975
976 default:
977 /* Nothing to do */
978 break;
979 }
980
981 return sdmmc_frequency;
982 }
983
984 /**
985 * @brief Return RNG clock frequency
986 * @param RNGxSource This parameter can be one of the following values:
987 * @arg @ref LL_RCC_RNG_CLKSOURCE
988 * @retval RNG clock frequency (in Hz)
989 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
990 */
991 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
992 {
993 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
994 LL_PLL_ClocksTypeDef PLL_Clocks;
995
996 switch (LL_RCC_GetRNGClockSource(RNGxSource))
997 {
998 case LL_RCC_RNG_CLKSOURCE_PLL1Q:
999 if (LL_RCC_PLL1_IsReady() != 0U)
1000 {
1001 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1002 rng_frequency = PLL_Clocks.PLL_Q_Frequency;
1003 }
1004 break;
1005
1006 case LL_RCC_RNG_CLKSOURCE_HSI48:
1007 if (LL_RCC_HSI48_IsReady() != 0U)
1008 {
1009 rng_frequency = 48000000U;
1010 }
1011 break;
1012
1013 case LL_RCC_RNG_CLKSOURCE_LSE:
1014 if (LL_RCC_LSE_IsReady() != 0U)
1015 {
1016 rng_frequency = LSE_VALUE;
1017 }
1018 break;
1019
1020 case LL_RCC_RNG_CLKSOURCE_LSI:
1021 if (LL_RCC_LSI_IsReady() != 0U)
1022 {
1023 rng_frequency = LSI_VALUE;
1024 }
1025 break;
1026
1027 default:
1028 /* Nothing to do */
1029 break;
1030 }
1031
1032 return rng_frequency;
1033 }
1034
1035 /**
1036 * @brief Return CEC clock frequency
1037 * @param CECxSource This parameter can be one of the following values:
1038 * @arg @ref LL_RCC_RNG_CLKSOURCE
1039 * @retval CEC clock frequency (in Hz)
1040 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1041 */
1042 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
1043 {
1044 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1045
1046 switch (LL_RCC_GetCECClockSource(CECxSource))
1047 {
1048 case LL_RCC_CEC_CLKSOURCE_LSE:
1049 if (LL_RCC_LSE_IsReady() != 0U)
1050 {
1051 cec_frequency = LSE_VALUE;
1052 }
1053 break;
1054
1055 case LL_RCC_CEC_CLKSOURCE_LSI:
1056 if (LL_RCC_LSI_IsReady() != 0U)
1057 {
1058 cec_frequency = LSI_VALUE;
1059 }
1060 break;
1061
1062 case LL_RCC_CEC_CLKSOURCE_CSI_DIV122:
1063 if (LL_RCC_CSI_IsReady() != 0U)
1064 {
1065 cec_frequency = CSI_VALUE / 122U;
1066 }
1067 break;
1068
1069 default:
1070 /* Kernel clock disabled */
1071 break;
1072 }
1073
1074 return cec_frequency;
1075 }
1076
1077 /**
1078 * @brief Return USB clock frequency
1079 * @param USBxSource This parameter can be one of the following values:
1080 * @arg @ref LL_RCC_USB_CLKSOURCE
1081 * @retval USB clock frequency (in Hz)
1082 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
1083 */
1084 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1085 {
1086 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1087 LL_PLL_ClocksTypeDef PLL_Clocks;
1088
1089 switch (LL_RCC_GetUSBClockSource(USBxSource))
1090 {
1091 case LL_RCC_USB_CLKSOURCE_PLL1Q:
1092 if (LL_RCC_PLL1_IsReady() != 0U)
1093 {
1094 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1095 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
1096 }
1097 break;
1098
1099 case LL_RCC_USB_CLKSOURCE_PLL3Q:
1100 if (LL_RCC_PLL3_IsReady() != 0U)
1101 {
1102 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1103 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
1104 }
1105 break;
1106
1107 case LL_RCC_USB_CLKSOURCE_HSI48:
1108 if (LL_RCC_HSI48_IsReady() != 0U)
1109 {
1110 usb_frequency = HSI48_VALUE;
1111 }
1112 break;
1113
1114 case LL_RCC_USB_CLKSOURCE_DISABLE:
1115 default:
1116 /* Nothing to do */
1117 break;
1118 }
1119
1120 return usb_frequency;
1121 }
1122
1123 /**
1124 * @brief Return DFSDM clock frequency
1125 * @param DFSDMxSource This parameter can be one of the following values:
1126 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1127 * @retval DFSDM clock frequency (in Hz)
1128 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1129 */
1130 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1131 {
1132 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1133
1134 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1135 {
1136 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:
1137 dfsdm_frequency = RCC_GetSystemClockFreq();
1138 break;
1139
1140 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
1141 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1142 break;
1143
1144 default:
1145 /* Nothing to do */
1146 break;
1147 }
1148
1149 return dfsdm_frequency;
1150 }
1151
1152 #if defined(DFSDM2_BASE)
1153 /**
1154 * @brief Return DFSDM clock frequency
1155 * @param DFSDMxSource This parameter can be one of the following values:
1156 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE
1157 * @retval DFSDM clock frequency (in Hz)
1158 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1159 */
1160 uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)
1161 {
1162 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1163
1164
1165 switch (LL_RCC_GetDFSDM2ClockSource(DFSDMxSource))
1166 {
1167
1168 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK:
1169 dfsdm_frequency = RCC_GetSystemClockFreq();
1170 break;
1171
1172 case LL_RCC_DFSDM2_CLKSOURCE_PCLK4:
1173 dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1174 break;
1175
1176 default:
1177 /* Nothing to do */
1178 break;
1179 }
1180
1181 return dfsdm_frequency;
1182 }
1183 #endif /* DFSDM2_BASE */
1184
1185 #if defined(DSI)
1186 /**
1187 * @brief Return DSI clock frequency
1188 * @param DSIxSource This parameter can be one of the following values:
1189 * @arg @ref LL_RCC_DSI_CLKSOURCE
1190 * @retval DSI clock frequency (in Hz)
1191 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1192 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1193 */
1194 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1195 {
1196 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1197 LL_PLL_ClocksTypeDef PLL_Clocks;
1198
1199 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1200 {
1201 case LL_RCC_DSI_CLKSOURCE_PLL2Q:
1202 if (LL_RCC_PLL2_IsReady() != 0U)
1203 {
1204 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1205 dsi_frequency = PLL_Clocks.PLL_Q_Frequency;
1206 }
1207 break;
1208
1209 case LL_RCC_DSI_CLKSOURCE_PHY:
1210 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1211 break;
1212
1213 default:
1214 /* Nothing to do */
1215 break;
1216 }
1217
1218 return dsi_frequency;
1219 }
1220 #endif /* DSI */
1221
1222 /**
1223 * @brief Return SPDIF clock frequency
1224 * @param SPDIFxSource This parameter can be one of the following values:
1225 * @arg @ref LL_RCC_SPDIF_CLKSOURCE
1226 * @retval SPDIF clock frequency (in Hz)
1227 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1228 */
1229 uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
1230 {
1231 uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1232 LL_PLL_ClocksTypeDef PLL_Clocks;
1233
1234 switch (LL_RCC_GetSPDIFClockSource(SPDIFxSource))
1235 {
1236 case LL_RCC_SPDIF_CLKSOURCE_PLL1Q:
1237 if (LL_RCC_PLL1_IsReady() != 0U)
1238 {
1239 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1240 spdif_frequency = PLL_Clocks.PLL_Q_Frequency;
1241 }
1242 break;
1243
1244 case LL_RCC_SPDIF_CLKSOURCE_PLL2R:
1245 if (LL_RCC_PLL2_IsReady() != 0U)
1246 {
1247 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1248 spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1249 }
1250 break;
1251
1252 case LL_RCC_SPDIF_CLKSOURCE_PLL3R:
1253 if (LL_RCC_PLL3_IsReady() != 0U)
1254 {
1255 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1256 spdif_frequency = PLL_Clocks.PLL_R_Frequency;
1257 }
1258 break;
1259
1260 case LL_RCC_SPDIF_CLKSOURCE_HSI:
1261 if (LL_RCC_HSI_IsReady() != 0U)
1262 {
1263 spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1264 }
1265 break;
1266
1267 default:
1268 /* Nothing to do */
1269 break;
1270 }
1271
1272 return spdif_frequency;
1273 }
1274
1275 /**
1276 * @brief Return SPIx clock frequency
1277 * @param SPIxSource This parameter can be one of the following values:
1278 * @arg @ref LL_RCC_SPI123_CLKSOURCE
1279 * @arg @ref LL_RCC_SPI45_CLKSOURCE
1280 * @arg @ref LL_RCC_SPI6_CLKSOURCE
1281 * @retval SPI clock frequency (in Hz)
1282 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1283 */
1284 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
1285 {
1286 uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1287 LL_PLL_ClocksTypeDef PLL_Clocks;
1288
1289 /* Check parameter */
1290 assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
1291
1292 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1293 {
1294 case LL_RCC_SPI123_CLKSOURCE_PLL1Q:
1295 if (LL_RCC_PLL1_IsReady() != 0U)
1296 {
1297 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1298 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1299 }
1300 break;
1301
1302 case LL_RCC_SPI123_CLKSOURCE_PLL2P:
1303 if (LL_RCC_PLL2_IsReady() != 0U)
1304 {
1305 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1306 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1307 }
1308 break;
1309
1310 case LL_RCC_SPI123_CLKSOURCE_PLL3P:
1311 if (LL_RCC_PLL3_IsReady() != 0U)
1312 {
1313 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1314 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1315 }
1316 break;
1317
1318 case LL_RCC_SPI123_CLKSOURCE_I2S_CKIN:
1319 #if defined(LL_RCC_SPI6_CLKSOURCE_I2S_CKIN)
1320 case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
1321 #endif /* LL_RCC_SPI6_CLKSOURCE_I2S_CKIN */
1322 spi_frequency = EXTERNAL_CLOCK_VALUE;
1323 break;
1324
1325 case LL_RCC_SPI123_CLKSOURCE_CLKP:
1326 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1327 break;
1328
1329 case LL_RCC_SPI45_CLKSOURCE_PCLK2:
1330 spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1331 break;
1332
1333 case LL_RCC_SPI6_CLKSOURCE_PCLK4:
1334 spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1335 break;
1336
1337 case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
1338 case LL_RCC_SPI6_CLKSOURCE_PLL2Q:
1339 if (LL_RCC_PLL2_IsReady() != 0U)
1340 {
1341 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1342 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1343 }
1344 break;
1345
1346 case LL_RCC_SPI45_CLKSOURCE_PLL3Q:
1347 case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
1348 if (LL_RCC_PLL3_IsReady() != 0U)
1349 {
1350 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1351 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1352 }
1353 break;
1354
1355 case LL_RCC_SPI45_CLKSOURCE_HSI:
1356 case LL_RCC_SPI6_CLKSOURCE_HSI:
1357 if (LL_RCC_HSI_IsReady() != 0U)
1358 {
1359 spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1360 }
1361 break;
1362
1363 case LL_RCC_SPI45_CLKSOURCE_CSI:
1364 case LL_RCC_SPI6_CLKSOURCE_CSI:
1365 if (LL_RCC_CSI_IsReady() != 0U)
1366 {
1367 spi_frequency = CSI_VALUE;
1368 }
1369 break;
1370
1371 case LL_RCC_SPI45_CLKSOURCE_HSE:
1372 case LL_RCC_SPI6_CLKSOURCE_HSE:
1373 if (LL_RCC_HSE_IsReady() != 0U)
1374 {
1375 spi_frequency = HSE_VALUE;
1376 }
1377 break;
1378
1379 default:
1380 /* Kernel clock disabled */
1381 break;
1382 }
1383
1384 return spi_frequency;
1385 }
1386
1387 /**
1388 * @brief Return SWP clock frequency
1389 * @param SWPxSource This parameter can be one of the following values:
1390 * @arg @ref LL_RCC_SWP_CLKSOURCE
1391 * @retval SWP clock frequency (in Hz)
1392 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1393 */
1394 uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
1395 {
1396 uint32_t swp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1397
1398 switch (LL_RCC_GetSWPClockSource(SWPxSource))
1399 {
1400 case LL_RCC_SWP_CLKSOURCE_PCLK1:
1401 swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
1402 break;
1403
1404 case LL_RCC_SWP_CLKSOURCE_HSI:
1405 if (LL_RCC_HSI_IsReady() != 0U)
1406 {
1407 swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1408 }
1409 break;
1410
1411 default:
1412 /* Nothing to do */
1413 break;
1414 }
1415
1416 return swp_frequency;
1417 }
1418
1419 /**
1420 * @brief Return FDCAN clock frequency
1421 * @param FDCANxSource This parameter can be one of the following values:
1422 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1423 * @retval FDCAN clock frequency (in Hz)
1424 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1425 */
1426 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
1427 {
1428 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1429 LL_PLL_ClocksTypeDef PLL_Clocks;
1430
1431 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
1432 {
1433 case LL_RCC_FDCAN_CLKSOURCE_HSE:
1434 if (LL_RCC_HSE_IsReady() != 0U)
1435 {
1436 fdcan_frequency = HSE_VALUE;
1437 }
1438 break;
1439
1440 case LL_RCC_FDCAN_CLKSOURCE_PLL1Q:
1441 if (LL_RCC_PLL1_IsReady() != 0U)
1442 {
1443 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1444 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1445 }
1446 break;
1447
1448 case LL_RCC_FDCAN_CLKSOURCE_PLL2Q:
1449 if (LL_RCC_PLL2_IsReady() != 0U)
1450 {
1451 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1452 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1453 }
1454 break;
1455
1456 default:
1457 /* Kernel clock disabled */
1458 break;
1459 }
1460
1461 return fdcan_frequency;
1462 }
1463
1464 /**
1465 * @brief Return FMC clock frequency
1466 * @param FMCxSource This parameter can be one of the following values:
1467 * @arg @ref LL_RCC_FMC_CLKSOURCE
1468 * @retval FMC clock frequency (in Hz)
1469 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1470 */
1471 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
1472 {
1473 uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1474 LL_PLL_ClocksTypeDef PLL_Clocks;
1475
1476 switch (LL_RCC_GetFMCClockSource(FMCxSource))
1477 {
1478 case LL_RCC_FMC_CLKSOURCE_HCLK:
1479 fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
1480 break;
1481
1482 case LL_RCC_FMC_CLKSOURCE_PLL1Q:
1483 if (LL_RCC_PLL1_IsReady() != 0U)
1484 {
1485 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1486 fmc_frequency = PLL_Clocks.PLL_Q_Frequency;
1487 }
1488 break;
1489
1490 case LL_RCC_FMC_CLKSOURCE_PLL2R:
1491 if (LL_RCC_PLL2_IsReady() != 0U)
1492 {
1493 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1494 fmc_frequency = PLL_Clocks.PLL_R_Frequency;
1495 }
1496 break;
1497
1498 case LL_RCC_FMC_CLKSOURCE_CLKP:
1499 fmc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1500 break;
1501
1502 default:
1503 /* Nothing to do */
1504 break;
1505 }
1506
1507 return fmc_frequency;
1508 }
1509
1510 #if defined(QUADSPI)
1511 /**
1512 * @brief Return QSPI clock frequency
1513 * @param QSPIxSource This parameter can be one of the following values:
1514 * @arg @ref LL_RCC_QSPI_CLKSOURCE
1515 * @retval QSPI clock frequency (in Hz)
1516 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1517 */
1518 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
1519 {
1520 uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1521 LL_PLL_ClocksTypeDef PLL_Clocks;
1522
1523 switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
1524 {
1525 case LL_RCC_QSPI_CLKSOURCE_HCLK:
1526 qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
1527 break;
1528
1529 case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
1530 if (LL_RCC_PLL1_IsReady() != 0U)
1531 {
1532 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1533 qspi_frequency = PLL_Clocks.PLL_Q_Frequency;
1534 }
1535 break;
1536
1537 case LL_RCC_QSPI_CLKSOURCE_PLL2R:
1538 if (LL_RCC_PLL2_IsReady() != 0U)
1539 {
1540 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1541 qspi_frequency = PLL_Clocks.PLL_R_Frequency;
1542 }
1543 break;
1544
1545 case LL_RCC_QSPI_CLKSOURCE_CLKP:
1546 qspi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1547 break;
1548
1549 default:
1550 /* Nothing to do */
1551 break;
1552 }
1553
1554 return qspi_frequency;
1555 }
1556 #endif /* QUADSPI */
1557
1558 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1559 /**
1560 * @brief Return OSPI clock frequency
1561 * @param QSPIxSource This parameter can be one of the following values:
1562 * @arg @ref LL_RCC_OSPI_CLKSOURCE
1563 * @retval OSPI clock frequency (in Hz)
1564 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1565 */
1566
1567 uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)
1568 {
1569 uint32_t ospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1570 LL_PLL_ClocksTypeDef PLL_Clocks;
1571
1572 switch (LL_RCC_GetOSPIClockSource(OSPIxSource))
1573 {
1574 case LL_RCC_OSPI_CLKSOURCE_HCLK:
1575 ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
1576 break;
1577
1578 case LL_RCC_OSPI_CLKSOURCE_PLL1Q:
1579 if (LL_RCC_PLL1_IsReady() != 0U)
1580 {
1581 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1582 ospi_frequency = PLL_Clocks.PLL_Q_Frequency;
1583 }
1584 break;
1585
1586 case LL_RCC_OSPI_CLKSOURCE_PLL2R:
1587 if (LL_RCC_PLL2_IsReady() != 0U)
1588 {
1589 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1590 ospi_frequency = PLL_Clocks.PLL_R_Frequency;
1591 }
1592 break;
1593
1594 case LL_RCC_OSPI_CLKSOURCE_CLKP:
1595 ospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1596 break;
1597
1598 default:
1599 /* Nothing to do */
1600 break;
1601 }
1602
1603 return ospi_frequency;
1604 }
1605 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
1606
1607 /**
1608 * @brief Return CLKP clock frequency
1609 * @param CLKPxSource This parameter can be one of the following values:
1610 * @arg @ref LL_RCC_CLKP_CLKSOURCE
1611 * @retval CLKP clock frequency (in Hz)
1612 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1613 */
1614 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
1615 {
1616 uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1617
1618 switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
1619 {
1620 case LL_RCC_CLKP_CLKSOURCE_HSI:
1621 if (LL_RCC_HSI_IsReady() != 0U)
1622 {
1623 clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1624 }
1625 break;
1626
1627 case LL_RCC_CLKP_CLKSOURCE_CSI:
1628 if (LL_RCC_CSI_IsReady() != 0U)
1629 {
1630 clkp_frequency = CSI_VALUE;
1631 }
1632 break;
1633
1634 case LL_RCC_CLKP_CLKSOURCE_HSE:
1635 if (LL_RCC_HSE_IsReady() != 0U)
1636 {
1637 clkp_frequency = HSE_VALUE;
1638 }
1639 break;
1640
1641 default:
1642 /* CLKP clock disabled */
1643 break;
1644 }
1645
1646 return clkp_frequency;
1647 }
1648
1649 /**
1650 * @}
1651 */
1652
1653 /**
1654 * @}
1655 */
1656
1657 /** @addtogroup RCC_LL_Private_Functions
1658 * @{
1659 */
1660
1661 /**
1662 * @brief Return SYSTEM clock frequency
1663 * @retval SYSTEM clock frequency (in Hz)
1664 */
1665 uint32_t RCC_GetSystemClockFreq(void)
1666 {
1667 uint32_t frequency = 0U;
1668 LL_PLL_ClocksTypeDef PLL_Clocks;
1669
1670 /* Get SYSCLK source -------------------------------------------------------*/
1671 switch (LL_RCC_GetSysClkSource())
1672 {
1673 /* No check on Ready: Won't be selected by hardware if not */
1674 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
1675 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
1676 break;
1677
1678 case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
1679 frequency = CSI_VALUE;
1680 break;
1681
1682 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
1683 frequency = HSE_VALUE;
1684 break;
1685
1686 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
1687 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1688 frequency = PLL_Clocks.PLL_P_Frequency;
1689 break;
1690
1691 default:
1692 /* Nothing to do */
1693 break;
1694 }
1695
1696 return frequency;
1697 }
1698
1699 /**
1700 * @brief Return HCLK clock frequency
1701 * @param SYSCLK_Frequency SYSCLK clock frequency
1702 * @retval HCLK clock frequency (in Hz)
1703 */
1704 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1705 {
1706 /* HCLK clock frequency */
1707 return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1708 }
1709
1710 /**
1711 * @brief Return PCLK1 clock frequency
1712 * @param HCLK_Frequency HCLK clock frequency
1713 * @retval PCLK1 clock frequency (in Hz)
1714 */
1715 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1716 {
1717 /* PCLK1 clock frequency */
1718 return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1719 }
1720
1721 /**
1722 * @brief Return PCLK2 clock frequency
1723 * @param HCLK_Frequency HCLK clock frequency
1724 * @retval PCLK2 clock frequency (in Hz)
1725 */
1726 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1727 {
1728 /* PCLK2 clock frequency */
1729 return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1730 }
1731
1732 /**
1733 * @brief Return PCLK3 clock frequency
1734 * @param HCLK_Frequency HCLK clock frequency
1735 * @retval PCLK3 clock frequency (in Hz)
1736 */
1737 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
1738 {
1739 /* PCLK3 clock frequency */
1740 return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
1741 }
1742
1743 /**
1744 * @brief Return PCLK4 clock frequency
1745 * @param HCLK_Frequency HCLK clock frequency
1746 * @retval PCLK4 clock frequency (in Hz)
1747 */
1748 uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
1749 {
1750 /* PCLK4 clock frequency */
1751 return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
1752 }
1753
1754 /**
1755 * @}
1756 */
1757
1758 /**
1759 * @}
1760 */
1761
1762 #endif /* defined(RCC) */
1763
1764 /**
1765 * @}
1766 */
1767
1768 #endif /* USE_FULL_LL_DRIVER */
1769
1770 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software