lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_ll_utils.c
   4   * @author  MCD Application Team
   5   * @brief   UTILS LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19 /* Includes ------------------------------------------------------------------*/
  20 #include "stm32h7xx_ll_utils.h"
  21 #include "stm32h7xx_ll_rcc.h"
  22 #include "stm32h7xx_ll_pwr.h"
  23
  24 #ifdef  USE_FULL_ASSERT
  25   #include "stm32_assert.h"
  26 #else
  27   #define assert_param(expr) ((void)0U)
  28 #endif /* USE_FULL_ASSERT */
  29
  30 /** @addtogroup STM32H7xx_LL_Driver
  31   * @{
  32   */
  33
  34 /** @addtogroup UTILS_LL
  35   * @{
  36   */
  37
  38 /* Private types -------------------------------------------------------------*/
  39 /* Private variables ---------------------------------------------------------*/
  40 /* Private constants ---------------------------------------------------------*/
  41 /** @addtogroup UTILS_LL_Private_Constants
  42   * @{
  43   */
  44 #if (POWER_DOMAINS_NUMBER == 3U)
  45 #define UTILS_MAX_FREQUENCY_SCALE1  400000000U      /*!< Maximum frequency for system clock at power scale1, in Hz */
  46 #define UTILS_MAX_FREQUENCY_SCALE2  300000000U      /*!< Maximum frequency for system clock at power scale2, in Hz */
  47 #define UTILS_MAX_FREQUENCY_SCALE3  200000000U      /*!< Maximum frequency for system clock at power scale3, in Hz */
  48 #else
  49 #define UTILS_MAX_FREQUENCY_SCALE0  280000000U      /*!< Maximum frequency for system clock at power scale0, in Hz */
  50 #define UTILS_MAX_FREQUENCY_SCALE1  225000000U      /*!< Maximum frequency for system clock at power scale1, in Hz */
  51 #define UTILS_MAX_FREQUENCY_SCALE2  160000000U      /*!< Maximum frequency for system clock at power scale2, in Hz */
  52 #define UTILS_MAX_FREQUENCY_SCALE3   88000000U      /*!< Maximum frequency for system clock at power scale3, in Hz */
  53 #endif /*POWER_DOMAINS_NUMBER == 3U*/
  54
  55 /* Defines used for PLL range */
  56 #define UTILS_PLLVCO_INPUT_MIN1       1000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
  57 #define UTILS_PLLVCO_INPUT_MAX1       2000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
  58 #define UTILS_PLLVCO_INPUT_MIN2       2000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
  59 #define UTILS_PLLVCO_INPUT_MAX2       4000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
  60 #define UTILS_PLLVCO_INPUT_MIN3       4000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
  61 #define UTILS_PLLVCO_INPUT_MAX3       8000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
  62 #define UTILS_PLLVCO_INPUT_MIN4       8000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
  63 #define UTILS_PLLVCO_INPUT_MAX4      16000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
  64
  65 #if (POWER_DOMAINS_NUMBER == 3U)
  66 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN    150000000U      /*!< Frequency min for the medium range PLLVCO output, in Hz   */
  67 #define UTILS_PLLVCO_WIDE_OUTPUT_MIN      192000000U      /*!< Frequency min for the wide range PLLVCO output, in Hz   */
  68 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX    420000000U      /*!< Frequency max for the medium range PLLVCO output, in Hz  */
  69 #define UTILS_PLLVCO_WIDE_OUTPUT_MAX      836000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
  70 #else
  71 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN    150000000U      /*!< Frequency min for the medium range PLLVCO output, in Hz   */
  72 #define UTILS_PLLVCO_WIDE_OUTPUT_MIN      128000000U      /*!< Frequency min for the wide range PLLVCO output, in Hz   */
  73 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX    420000000U      /*!< Frequency max for the medium range PLLVCO output, in Hz  */
  74 #define UTILS_PLLVCO_WIDE_OUTPUT_MAX      560000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
  75 #endif /*POWER_DOMAINS_NUMBER == 3U*/
  76
  77 /* Defines used for HSE range */
  78 #define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */
  79 #define UTILS_HSE_FREQUENCY_MAX     48000000U        /*!< Frequency max for HSE frequency, in Hz   */
  80
  81 /* Defines used for FLASH latency according to HCLK Frequency */
  82 #if (POWER_DOMAINS_NUMBER == 2U)
  83 #define UTILS_SCALE0_LATENCY0_FREQ   44000000U       /*!< HCLK frequency to set FLASH latency 0 in power scale 0  */
  84 #define UTILS_SCALE0_LATENCY1_FREQ   88000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 0  */
  85 #define UTILS_SCALE0_LATENCY2_FREQ  132000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 0  */
  86 #define UTILS_SCALE0_LATENCY3_FREQ  176000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 0  */
  87 #define UTILS_SCALE0_LATENCY4_FREQ  220000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 0  */
  88 #define UTILS_SCALE0_LATENCY5_FREQ  264000000U       /*!< HCLK frequency to set FLASH latency 5 in power scale 0  */
  89 #define UTILS_SCALE0_LATENCY6_FREQ  280000000U       /*!< HCLK frequency to set FLASH latency 6 in power scale 0  */
  90
  91 #define UTILS_SCALE1_LATENCY0_FREQ   42000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 1  */
  92 #define UTILS_SCALE1_LATENCY1_FREQ   84000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
  93 #define UTILS_SCALE1_LATENCY2_FREQ  126000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
  94 #define UTILS_SCALE1_LATENCY3_FREQ  168000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
  95 #define UTILS_SCALE1_LATENCY4_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
  96 #define UTILS_SCALE1_LATENCY5_FREQ  225000000U      /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
  97
  98 #define UTILS_SCALE2_LATENCY0_FREQ   34000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 2  */
  99 #define UTILS_SCALE2_LATENCY1_FREQ   68000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
 100 #define UTILS_SCALE2_LATENCY2_FREQ  102000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
 101 #define UTILS_SCALE2_LATENCY3_FREQ  136000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
 102 #define UTILS_SCALE2_LATENCY4_FREQ  160000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
 103
 104 #define UTILS_SCALE3_LATENCY0_FREQ   22000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 3  */
 105 #define UTILS_SCALE3_LATENCY1_FREQ   44000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
 106 #define UTILS_SCALE3_LATENCY2_FREQ   66000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
 107 #define UTILS_SCALE3_LATENCY3_FREQ   88000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
 108
 109 #else
 110
 111 #define UTILS_SCALE1_LATENCY0_FREQ   70000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 1  */
 112 #define UTILS_SCALE1_LATENCY1_FREQ  140000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
 113 #define UTILS_SCALE1_LATENCY2_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
 114
 115 #define UTILS_SCALE2_LATENCY0_FREQ   55000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 2  */
 116 #define UTILS_SCALE2_LATENCY1_FREQ  110000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
 117 #define UTILS_SCALE2_LATENCY2_FREQ  165000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
 118 #define UTILS_SCALE2_LATENCY3_FREQ  220000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
 119
 120 #define UTILS_SCALE3_LATENCY0_FREQ   45000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 3  */
 121 #define UTILS_SCALE3_LATENCY1_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
 122 #define UTILS_SCALE3_LATENCY2_FREQ  135000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
 123 #define UTILS_SCALE3_LATENCY3_FREQ  180000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
 124 #define UTILS_SCALE3_LATENCY4_FREQ  225000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 3  */
 125 #endif /*POWER_DOMAINS_NUMBER == 2U*/
 126 /**
 127   * @}
 128   */
 129
 130 /* Private macros ------------------------------------------------------------*/
 131 /** @addtogroup UTILS_LL_Private_Macros
 132   * @{
 133   */
 134 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
 135                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
 136                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
 137                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
 138                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
 139                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
 140                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
 141                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
 142                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
 143
 144 #define IS_LL_UTILS_AHB_DIV(__VALUE__)    (((__VALUE__) == LL_RCC_AHB_DIV_1)   \
 145                                         || ((__VALUE__) == LL_RCC_AHB_DIV_2)   \
 146                                         || ((__VALUE__) == LL_RCC_AHB_DIV_4)   \
 147                                         || ((__VALUE__) == LL_RCC_AHB_DIV_8)   \
 148                                         || ((__VALUE__) == LL_RCC_AHB_DIV_16)  \
 149                                         || ((__VALUE__) == LL_RCC_AHB_DIV_64)  \
 150                                         || ((__VALUE__) == LL_RCC_AHB_DIV_128) \
 151                                         || ((__VALUE__) == LL_RCC_AHB_DIV_256) \
 152                                         || ((__VALUE__) == LL_RCC_AHB_DIV_512))
 153
 154 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
 155                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
 156                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
 157                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
 158                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
 159
 160 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
 161                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
 162                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
 163                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
 164                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
 165
 166 #define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \
 167                                       || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
 168                                       || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
 169                                       || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
 170                                       || ((__VALUE__) == LL_RCC_APB3_DIV_16))
 171
 172 #define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \
 173                                       || ((__VALUE__) == LL_RCC_APB4_DIV_2) \
 174                                       || ((__VALUE__) == LL_RCC_APB4_DIV_4) \
 175                                       || ((__VALUE__) == LL_RCC_APB4_DIV_8) \
 176                                       || ((__VALUE__) == LL_RCC_APB4_DIV_16))
 177
 178 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
 179
 180 #if (POWER_DOMAINS_NUMBER == 3U)
 181 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
 182 #else
 183 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 420U))
 184 #endif /*POWER_DOMAINS_NUMBER == 3U*/
 185
 186 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
 187
 188 #define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
 189
 190 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__)  ( \
 191 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \
 192 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \
 193 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \
 194 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4)))
 195
 196 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \
 197 (((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \
 198 (((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX)))
 199
 200 #define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \
 201 (((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
 202 (((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))
 203
 204 #if (POWER_DOMAINS_NUMBER == 3U)
 205 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
 206                                               (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
 207                                               ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
 208 #else
 209 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : \
 210                                               (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
 211                                               (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
 212                                               ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
 213 #endif /*POWER_DOMAINS_NUMBER == 3U*/
 214
 215 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
 216                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
 217
 218 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
 219 /**
 220   * @}
 221   */
 222 /* Private function prototypes -----------------------------------------------*/
 223 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
 224   * @{
 225   */
 226 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
 227 static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency);
 228 static ErrorStatus UTILS_SetFlashLatency(uint32_t latency);
 229 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
 230 static ErrorStatus UTILS_IsPLLsReady(void);
 231 /**
 232   * @}
 233   */
 234
 235 /* Exported functions --------------------------------------------------------*/
 236 /** @addtogroup UTILS_LL_Exported_Functions
 237   * @{
 238   */
 239
 240 /** @addtogroup UTILS_LL_EF_DELAY
 241   * @{
 242   */
 243 #if defined (DUAL_CORE)
 244 /**
 245   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
 246   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
 247   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
 248   * @param  CPU_Frequency Core frequency in Hz
 249   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
 250   *         @ref LL_RCC_GetSystemClocksFreq
 251   *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
 252   *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
 253   * @retval None
 254   */
 255 #else
 256 /**
 257   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
 258   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
 259   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
 260   * @param  CPU_Frequency Core frequency in Hz
 261   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
 262   *         @ref LL_RCC_GetSystemClocksFreq
 263   * @retval None
 264   */
 265 #endif /* DUAL_CORE */
 266 void LL_Init1msTick(uint32_t CPU_Frequency)
 267 {
 268   /* Use frequency provided in argument */
 269   LL_InitTick(CPU_Frequency, 1000U);
 270 }
 271
 272
 273 /**
 274   * @brief  This function provides accurate delay (in milliseconds) based
 275   *         on SysTick counter flag
 276   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
 277   *         and use rather osDelay service.
 278   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
 279   *         will configure Systick to 1ms
 280   * @param  Delay specifies the delay time length, in milliseconds.
 281   * @retval None
 282   */
 283 void LL_mDelay(uint32_t Delay)
 284 {
 285   uint32_t count = Delay;
 286   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
 287   /* Add this code to indicate that local variable is not used */
 288   ((void)tmp);
 289
 290   /* Add a period to guaranty minimum wait */
 291   if(count < LL_MAX_DELAY)
 292   {
 293     count++;
 294   }
 295
 296   while (count != 0U)
 297   {
 298     if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
 299     {
 300       count--;
 301     }
 302   }
 303 }
 304
 305 /**
 306   * @}
 307   */
 308
 309 /** @addtogroup UTILS_EF_SYSTEM
 310   *  @brief    System Configuration functions
 311   *
 312   @verbatim
 313  ===============================================================================
 314            ##### System Configuration functions #####
 315  ===============================================================================
 316     [..]
 317          System, AHB and APB buses clocks configuration
 318
 319 #if (POWER_DOMAINS_NUMBER == 3U)
 320          (+) The maximum frequency of the SYSCLK is 400 MHz and HCLK is 200 MHz.
 321          (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 100 MHz.
 322   @endverbatim
 323   @internal
 324              Depending on the device voltage range, the maximum frequency should be
 325              adapted accordingly:
 326              (++) +----------------------------------------------------------------------------+
 327              (++) |  Wait states   |                           HCLK clock frequency (MHz)      |
 328              (++) |                |-----------------------------------------------------------|
 329              (++) |  (Latency)     |   voltage range 1 |   voltage range 2 |   voltage range 3 |
 330              (++) |                |    1.15V - 1.26V  |    1.05V - 1.15V  |    0.95V - 1.05V  |
 331              (++) |----------------|-------------------|-------------------|-------------------|
 332              (++) |0WS(1CPU cycle) |   0 < HCLK <= 70  |   0 < HCLK <= 55  |   0 < HCLK <= 45  |
 333              (++) |----------------|-------------------|-------------------|-------------------|
 334              (++) |1WS(2CPU cycle) |  70 < HCLK <= 140 |  55 < HCLK <= 110 |  45 < HCLK <= 90  |
 335              (++) |----------------|-------------------|-------------------|-------------------|
 336              (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 110 < HCLK <= 165 |  90 < HCLK <= 135 |
 337              (++) |----------------|-------------------|-------------------|-------------------|
 338              (++) |3WS(4CPU cycle) |        --         | 165 < HCLK <= 220 | 135 < HCLK <= 180 |
 339              (++) |----------------|-------------------|-------------------|-------------------|
 340              (++) |4WS(5CPU cycle) |        --         |        --         | 180 < HCLK <= 225 |
 341              (++) +----------------------------------------------------------------------------+
 342
 343 #else
 344          (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 140 MHz.
 345          (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz.
 346   @endverbatim
 347   @internal
 348              Depending on the device voltage range, the maximum frequency should be
 349              adapted accordingly:
 350              (++) +------------------------------------------------------------------------------------------------+
 351              (++) |  Wait states   |                          HCLK clock frequency (MHz)                           |
 352              (++) |                |-------------------------------------------------------------------------------|
 353              (++) |  (Latency)     |   voltage range 0 |   voltage range 1 |   voltage range 2 |   voltage range 3 |
 354              (++) |                |    1.26V - 1.35V  |    1.15V - 1.26V  |    1.05V - 1.15V  |    0.95V - 1.05V  |
 355              (++) |----------------|-------------------|-------------------|-------------------|-------------------|
 356              (++) |0WS(1CPU cycle) |   0 < HCLK <= 44  |   0 < HCLK <= 42  |   0 < HCLK <= 34  |   0 < HCLK <= 22  |
 357              (++) |----------------|-------------------|-------------------|-------------------|-------------------|
 358              (++) |1WS(2CPU cycle) |  44 < HCLK <= 88  |  42 < HCLK <= 84  |  34 < HCLK <= 68  |  22 < HCLK <= 44  |
 359              (++) |----------------|-------------------|-------------------|-------------------|-------------------|
 360              (++) |2WS(3CPU cycle) |  88 < HCLK <= 132 |  84 < HCLK <= 126 |  68 < HCLK <= 102 |  44 < HCLK <= 66  |
 361              (++) |----------------|-------------------|-------------------|-------------------|-------------------|
 362              (++) |3WS(4CPU cycle) | 132 < HCLK <= 176 | 126 < HCLK <= 168 | 102 < HCLK <= 136 |  66 < HCLK <= 88  |
 363              (++) |----------------|-------------------|-------------------|-------------------|-------------------|
 364              (++) |4WS(5CPU cycle) | 176 < HCLK <= 220 | 168 < HCLK <= 210 | 136 < HCLK <= 160 |        --         |
 365              (++) +------------------------------------------------------------------------------------------------+
 366              (++) |5WS(6CPU cycle) | 220 < HCLK <= 264 | 210 < HCLK <= 225 |        --         |        --         |
 367              (++) +------------------------------------------------------------------------------------------------+
 368              (++) |6WS(7CPU cycle) | 264 < HCLK <= 280 |        --         |        --         |        --         |
 369              (++) +------------------------------------------------------------------------------------------------+
 370              (++) |7WS(8CPU cycle) |        --         |        --         |        --         |        --         |
 371              (++) +------------------------------------------------------------------------------------------------+
 372
 373 #endif
 374   @endinternal
 375   * @{
 376   */
 377 #if defined (DUAL_CORE)
 378 /**
 379   * @brief  This function sets directly SystemCoreClock CMSIS variable.
 380   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
 381   * @param  CPU_Frequency Core frequency in Hz
 382   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
 383   *         @ref LL_RCC_GetSystemClocksFreq
 384   *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
 385   *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
 386   * @retval None
 387   */
 388 #else
 389 /**
 390   * @brief  This function sets directly SystemCoreClock CMSIS variable.
 391   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
 392   * @param  CPU_Frequency Core frequency in Hz
 393   * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
 394   *         @ref LL_RCC_GetSystemClocksFreq
 395   * @retval None
 396   */
 397 #endif /* DUAL_CORE */
 398 void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
 399 {
 400   /* HCLK clock frequency */
 401   SystemCoreClock = CPU_Frequency;
 402
 403   /* Update the SystemD2Clock global variable */
 404 #if defined(RCC_D1CFGR_HPRE)
 405   SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 406 #else
 407   SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
 408 #endif
 409
 410 }
 411
 412 /**
 413   * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
 414   * @note   The application need to ensure that PLL is disabled.
 415   * @note   Function is based on the following formula:
 416   *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
 417   *         - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
 418   *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
 419   *         - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz is reach (PLLVCO_output / PLLP)
 420   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
 421   *                             the configuration information for the PLL.
 422   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
 423   *                             the configuration information for the BUS prescalers.
 424   * @retval An ErrorStatus enumeration value:
 425   *          - SUCCESS: Max frequency configuration done
 426   *          - ERROR: Max frequency configuration not done
 427   *
 428   * (*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
 429   *
 430   */
 431 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
 432                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
 433 {
 434   ErrorStatus status;
 435 #ifdef  USE_FULL_ASSERT
 436   uint32_t vcoinput_freq, vcooutput_freq;
 437 #endif
 438   uint32_t pllfreq, hsi_clk;
 439
 440   /* Check the parameters */
 441   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
 442   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
 443   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
 444   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
 445
 446   hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos));
 447
 448   /* Check VCO Input frequency */
 449 #ifdef  USE_FULL_ASSERT
 450   vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM;
 451 #endif
 452   assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
 453
 454   /* Check VCO Output frequency */
 455 #ifdef  USE_FULL_ASSERT
 456   vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
 457 #endif
 458   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
 459
 460   /* Check VCO Input ranges */
 461   assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
 462
 463   /* Check if one of the PLL is enabled */
 464   if(UTILS_IsPLLsReady() == SUCCESS)
 465   {
 466     /* Calculate the new PLL output frequency */
 467     pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct);
 468
 469     /* Enable HSI if not enabled */
 470     if(LL_RCC_HSI_IsReady() != 1U)
 471     {
 472       LL_RCC_HSI_Enable();
 473       while (LL_RCC_HSI_IsReady() != 1U)
 474       {
 475         /* Wait for HSI ready */
 476       }
 477     }
 478
 479     /* Configure PLL */
 480     LL_RCC_PLL1P_Enable();
 481     LL_RCC_PLL1FRACN_Enable();
 482     LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
 483     LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
 484     LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
 485     LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
 486     LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
 487     LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
 488     LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
 489
 490     /* Enable PLL and switch system clock to PLL */
 491     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
 492   }
 493   else
 494   {
 495     /* Current PLL configuration cannot be modified */
 496     status = ERROR;
 497   }
 498
 499   return status;
 500 }
 501
 502 /**
 503   * @brief  This function configures system clock with HSE as clock source of the PLL
 504   * @note   The application need to ensure that PLL is disabled.
 505   * @note   Function is based on the following formula:
 506   *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
 507   *         - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
 508   *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
 509   *         - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz(*) is reached (PLLVCO_output / PLLP)
 510   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
 511   * @param  HSEBypass This parameter can be one of the following values:
 512   *         @arg @ref LL_UTILS_HSEBYPASS_ON
 513   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
 514   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
 515   *                             the configuration information for the PLL.
 516   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
 517   *                             the configuration information for the BUS prescalers.
 518   * @retval An ErrorStatus enumeration value:
 519   *          - SUCCESS: Max frequency configuration done
 520   *          - ERROR: Max frequency configuration not done
 521   *
 522   * (*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
 523   *
 524   */
 525 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
 526                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
 527 {
 528   ErrorStatus status;
 529 #ifdef  USE_FULL_ASSERT
 530   uint32_t vcoinput_freq, vcooutput_freq;
 531 #endif
 532   uint32_t pllfreq;
 533
 534   /* Check the parameters */
 535   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
 536   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
 537   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
 538   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
 539   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
 540   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
 541
 542   /* Check VCO Input frequency */
 543 #ifdef  USE_FULL_ASSERT
 544   vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM;
 545 #endif
 546   assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
 547
 548   /* Check VCO output frequency */
 549 #ifdef  USE_FULL_ASSERT
 550   vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
 551 #endif
 552   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
 553
 554   /* Check VCO Input/output ranges compatibility */
 555   assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
 556
 557   /* Check if one of the PLL is enabled */
 558   if(UTILS_IsPLLsReady() == SUCCESS)
 559   {
 560     /* Calculate the new PLL output frequency */
 561     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
 562
 563     /* Enable HSE if not enabled */
 564     if(LL_RCC_HSE_IsReady() != 1U)
 565     {
 566       /* Check if need to enable HSE bypass feature or not */
 567       if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
 568       {
 569         LL_RCC_HSE_EnableBypass();
 570       }
 571       else
 572       {
 573         LL_RCC_HSE_DisableBypass();
 574       }
 575
 576       /* Enable HSE */
 577       LL_RCC_HSE_Enable();
 578       while (LL_RCC_HSE_IsReady() != 1U)
 579       {
 580         /* Wait for HSE ready */
 581       }
 582     }
 583
 584     /* Configure PLL */
 585     LL_RCC_PLL1P_Enable();
 586     LL_RCC_PLL1FRACN_Enable();
 587     LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
 588     LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
 589     LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
 590     LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
 591     LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
 592     LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
 593     LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
 594
 595     /* Enable PLL and switch system clock to PLL */
 596     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
 597   }
 598   else
 599   {
 600     /* Current PLL configuration cannot be modified */
 601     status = ERROR;
 602   }
 603
 604   return status;
 605 }
 606
 607 /**
 608   * @}
 609   */
 610
 611 /**
 612   * @}
 613   */
 614
 615 /** @addtogroup UTILS_LL_Private_Functions
 616   * @{
 617   */
 618
 619 /**
 620   * @brief  Calculate and check the Flash wait states number according to the
 621             new HCLK frequency and current voltage range.
 622   * @param  HCLK_Frequency  HCLK frequency
 623   * @param  latency This parameter can be one of the following values:
 624   *         @arg @ref LL_FLASH_LATENCY_0
 625   *         @arg @ref LL_FLASH_LATENCY_1
 626   *         @arg @ref LL_FLASH_LATENCY_2
 627   *         @arg @ref LL_FLASH_LATENCY_3
 628   *         @arg @ref LL_FLASH_LATENCY_4
 629   *         @arg @ref LL_FLASH_LATENCY_5
 630   *         @arg @ref LL_FLASH_LATENCY_6
 631   *         @arg @ref LL_FLASH_LATENCY_7
 632   * @retval An ErrorStatus enumeration value:
 633   *          - SUCCESS: Latency has been modified
 634   *          - ERROR: Latency cannot be modified
 635   */
 636 static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency)
 637 {
 638   ErrorStatus status = SUCCESS;
 639
 640   /* Frequency cannot be equal to 0 */
 641   if(HCLK_Frequency == 0U)
 642   {
 643     status = ERROR;
 644   }
 645   else
 646   {
 647 #if (POWER_DOMAINS_NUMBER == 2U)
 648     if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0)
 649     {
 650       if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ))
 651       {
 652         /* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */
 653         *latency = LL_FLASH_LATENCY_6;
 654       }
 655       else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ))
 656       {
 657         /* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */
 658         *latency = LL_FLASH_LATENCY_5;
 659       }
 660       else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ))
 661       {
 662         /* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */
 663         *latency = LL_FLASH_LATENCY_4;
 664       }
 665       else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
 666       {
 667         /* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */
 668         *latency = LL_FLASH_LATENCY_3;
 669       }
 670       else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ))
 671       {
 672         /* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */
 673         *latency = LL_FLASH_LATENCY_2;
 674       }
 675       else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
 676       {
 677         /* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */
 678         *latency = LL_FLASH_LATENCY_1;
 679       }
 680       else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
 681       {
 682         /* HCLK <= 44 => 0WS (1 CPU cycles) */
 683         *latency = LL_FLASH_LATENCY_0;
 684       }
 685       else
 686       {
 687         status = ERROR;
 688       }
 689     }
 690     else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
 691     {
 692       if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
 693       {
 694         /* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */
 695         *latency = LL_FLASH_LATENCY_5;
 696       }
 697       else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ))
 698       {
 699         /* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */
 700         *latency = LL_FLASH_LATENCY_4;
 701       }
 702       else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ))
 703       {
 704         /* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */
 705         *latency = LL_FLASH_LATENCY_3;
 706       }
 707       else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
 708 #else
 709     if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
 710     {
 711       if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
 712 #endif /*POWER_DOMAINS_NUMBER == 2U*/
 713       {
 714         /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
 715         *latency = LL_FLASH_LATENCY_2;
 716       }
 717       else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
 718       {
 719         /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
 720         *latency = LL_FLASH_LATENCY_1;
 721       }
 722       else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
 723       {
 724         /* HCLK <= 70 => 0WS (1 CPU cycles) */
 725         *latency = LL_FLASH_LATENCY_0;
 726       }
 727       else
 728       {
 729         status = ERROR;
 730       }
 731     }
 732     else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
 733     {
 734 #if (POWER_DOMAINS_NUMBER == 2U)
 735       if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ))
 736       {
 737         /* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */
 738         *latency = LL_FLASH_LATENCY_4;
 739       }
 740       else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
 741 #else
 742       if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
 743 #endif /*POWER_DOMAINS_NUMBER == 2U*/
 744       {
 745         /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
 746         *latency = LL_FLASH_LATENCY_3;
 747       }
 748       else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
 749       {
 750         /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
 751         *latency = LL_FLASH_LATENCY_2;
 752       }
 753       else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
 754       {
 755         /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
 756         *latency = LL_FLASH_LATENCY_1;
 757       }
 758       else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
 759       {
 760         /* HCLK <= 55 => 0WS (1 CPU cycles) */
 761         *latency = LL_FLASH_LATENCY_0;
 762       }
 763       else
 764       {
 765         status = ERROR;
 766       }
 767     }
 768     else /* Scale 3 */
 769     {
 770 #if (POWER_DOMAINS_NUMBER == 3U)
 771       if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
 772       {
 773         /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
 774         *latency = LL_FLASH_LATENCY_4;
 775       }
 776       else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
 777 #else
 778       if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
 779 #endif /*POWER_DOMAINS_NUMBER == 3U*/
 780       {
 781         /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
 782         *latency = LL_FLASH_LATENCY_3;
 783       }
 784       else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
 785       {
 786         /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
 787         *latency = LL_FLASH_LATENCY_2;
 788       }
 789       else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
 790       {
 791         /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
 792         *latency = LL_FLASH_LATENCY_1;
 793       }
 794       else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
 795       {
 796         /* HCLK <= 45 => 0WS (1 CPU cycles) */
 797         *latency = LL_FLASH_LATENCY_0;
 798       }
 799       else
 800       {
 801         status = ERROR;
 802       }
 803     }
 804   }
 805
 806   return status;
 807 }
 808
 809 /**
 810   * @brief  Update number of Flash wait states
 811   * @param  latency  Flash Latency
 812   * @retval An ErrorStatus enumeration value:
 813   *          - SUCCESS: Latency has been modified
 814   *          - ERROR: Latency cannot be modified
 815   */
 816 static ErrorStatus UTILS_SetFlashLatency(uint32_t latency)
 817 {
 818   ErrorStatus status = SUCCESS;
 819
 820   LL_FLASH_SetLatency(latency);
 821
 822   /* Check that the new number of wait states is taken into account to access the Flash
 823      memory by reading the FLASH_ACR register */
 824   if(LL_FLASH_GetLatency() != latency)
 825   {
 826     status = ERROR;
 827   }
 828
 829   return status;
 830 }
 831
 832 /**
 833   * @brief  Function to check that PLL can be modified
 834   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
 835   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
 836   *                             the configuration information for the PLL.
 837   * @retval PLL output frequency (in Hz)
 838   */
 839 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
 840 {
 841   uint32_t pllfreq;
 842
 843   /* Check the parameters */
 844   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
 845   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
 846   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
 847   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
 848
 849   pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
 850
 851   return pllfreq;
 852 }
 853
 854 /**
 855   * @brief  Check that all PLLs are ready therefore configuration can be done
 856   * @retval An ErrorStatus enumeration value:
 857   *          - SUCCESS: All PLLs are ready so configuration can be done
 858   *          - ERROR: One PLL at least is busy
 859   */
 860 static ErrorStatus UTILS_IsPLLsReady(void)
 861 {
 862   ErrorStatus status = SUCCESS;
 863
 864   /* Check if one of the PLL1 is busy */
 865   if(LL_RCC_PLL1_IsReady() != 0U)
 866   {
 867     /* PLL1 configuration cannot be done */
 868     status = ERROR;
 869   }
 870
 871   /* Check if one of the PLL2 is busy */
 872   if(LL_RCC_PLL2_IsReady() != 0U)
 873   {
 874     /* PLL2 configuration cannot be done */
 875     status = ERROR;
 876   }
 877
 878   /* Check if one of the PLL3 is busy */
 879   if(LL_RCC_PLL3_IsReady() != 0U)
 880   {
 881     /* PLL3 configuration cannot be done */
 882     status = ERROR;
 883   }
 884
 885   return status;
 886 }
 887
 888 /**
 889   * @brief  Function to enable PLL and switch system clock to PLL
 890   * @param  SYSCLK_Frequency SYSCLK frequency
 891   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
 892   *                             the configuration information for the BUS prescalers.
 893   * @retval An ErrorStatus enumeration value:
 894   *          - SUCCESS: No problem to switch system to PLL
 895   *          - ERROR: Problem to switch system to PLL
 896   */
 897 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
 898 {
 899   ErrorStatus status;
 900   uint32_t new_hclk_frequency, new_latency;
 901
 902   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
 903   assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
 904   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
 905   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
 906   assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
 907   assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider));
 908
 909   /* Calculate the new HCLK frequency */
 910   new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
 911
 912   /* Calculate the new FLASH latency according to the new HCLK frequency */
 913   status = UTILS_CalculateFlashLatency(new_hclk_frequency, &new_latency);
 914
 915   if(status == SUCCESS)
 916   {
 917     /* Increasing the number of wait states because of higher CPU frequency */
 918     if(LL_FLASH_GetLatency() < new_latency)
 919     {
 920       status = UTILS_SetFlashLatency(new_latency);
 921     }
 922
 923     /* Update system clock configuration */
 924     if(status == SUCCESS)
 925     {
 926       /* Enable PLL */
 927       LL_RCC_PLL1_Enable();
 928       while (LL_RCC_PLL1_IsReady() != 1U)
 929       {
 930         /* Wait for PLL ready */
 931       }
 932
 933       /* Set All APBxPrescaler to the Highest Divider */
 934       LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
 935       LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
 936       LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
 937       LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
 938
 939       /* Set SYS prescaler*/
 940       LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
 941
 942       /* Set AHB prescaler*/
 943       LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
 944
 945       /* Sysclk activation on the main PLL */
 946       LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
 947       while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
 948       {
 949         /* Wait for system clock switch to PLL */
 950       }
 951
 952       /* Set APBn prescaler*/
 953       LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
 954       LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
 955       LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
 956       LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
 957
 958       /* Update SystemCoreClock variable */
 959       LL_SetSystemCoreClock(SYSCLK_Frequency);
 960     }
 961
 962     /* Decreasing the number of wait states because of lower CPU frequency */
 963     if(LL_FLASH_GetLatency() > new_latency)
 964     {
 965       status = UTILS_SetFlashLatency(new_latency);
 966     }
 967   }
 968
 969   return status;
 970 }
 971
 972 /**
 973   * @}
 974   */
 975
 976 /**
 977   * @}
 978   */
 979
 980 /**
 981   * @}
 982   */
 983
 984 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/