src/main/startup/startup_stm32h743xx.s

   1 /**
   2   ******************************************************************************
   3   * @file      startup_stm32h743xx.s
   4   * @author    MCD Application Team
   5   * @brief     STM32H743xx Devices vector table for GCC based toolchain.
   6   *            This module performs:
   7   *                - Set the initial SP
   8   *                - Set the initial PC == Reset_Handler,
   9   *                - Set the vector table entries with the exceptions ISR address
  10   *                - Branches to main in the C library (which eventually
  11   *                  calls main()).
  12   *            After Reset the Cortex-M processor is in Thread mode,
  13   *            priority is Privileged, and the Stack is set to Main.
  14   ******************************************************************************
  15   * @attention
  16   *
  17   * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
  18   *
  19   * Redistribution and use in source and binary forms, with or without modification,
  20   * are permitted provided that the following conditions are met:
  21   *   1. Redistributions of source code must retain the above copyright notice,
  22   *      this list of conditions and the following disclaimer.
  23   *   2. Redistributions in binary form must reproduce the above copyright notice,
  24   *      this list of conditions and the following disclaimer in the documentation
  25   *      and/or other materials provided with the distribution.
  26   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  27   *      may be used to endorse or promote products derived from this software
  28   *      without specific prior written permission.
  29   *
  30   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  31   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  32   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  34   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  36   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  37   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  38   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40   *
  41   ******************************************************************************
  42   */
  43
  44   .syntax unified
  45   .cpu cortex-m7
  46   .fpu softvfp
  47   .thumb
  48
  49 .global  g_pfnVectors
  50 .global  Default_Handler
  51
  52 /* start address for the initialization values of the .data section.
  53 defined in linker script */
  54 .word  _sidata
  55 /* start address for the .data section. defined in linker script */
  56 .word  _sdata
  57 /* end address for the .data section. defined in linker script */
  58 .word  _edata
  59 /* start address for the .bss section. defined in linker script */
  60 .word  _sbss
  61 /* end address for the .bss section. defined in linker script */
  62 .word  _ebss
  63 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
  64
  65 /**
  66  * @brief  This is the code that gets called when the processor first
  67  *          starts execution following a reset event. Only the absolutely
  68  *          necessary set is performed, after which the application
  69  *          supplied main() routine is called.
  70  * @param  None
  71  * @retval : None
  72 */
  73
  74     .section  .text.Reset_Handler
  75   .weak  Reset_Handler
  76   .type  Reset_Handler, %function
  77 Reset_Handler:
  78   ldr   sp, =_estack      /* set stack pointer */
  79
  80   bl persistentObjectInit
  81
  82 /* Copy the data segment initializers from flash to SRAM */
  83   movs  r1, #0
  84   b  LoopCopyDataInit
  85
  86 CopyDataInit:
  87   ldr  r3, =_sidata
  88   ldr  r3, [r3, r1]
  89   str  r3, [r0, r1]
  90   adds  r1, r1, #4
  91
  92 LoopCopyDataInit:
  93   ldr  r0, =_sdata
  94   ldr  r3, =_edata
  95   adds  r2, r0, r1
  96   cmp  r2, r3
  97   bcc  CopyDataInit
  98   ldr  r2, =_sbss
  99   b  LoopFillZerobss
 100
 101 /* Zero fill the bss segment. */
 102 FillZerobss:
 103   movs  r3, #0
 104   str  r3, [r2], #4
 105
 106 LoopFillZerobss:
 107   ldr  r3, = _ebss
 108   cmp  r2, r3
 109   bcc  FillZerobss
 110
 111 /* Zero fill FASTRAM */
 112   ldr  r2, =__fastram_bss_start__
 113   b  LoopFillZeroFASTRAM
 114
 115 FillZeroFASTRAM:
 116   movs  r3, #0
 117   str  r3, [r2], #4
 118
 119 LoopFillZeroFASTRAM:
 120   ldr  r3, = __fastram_bss_end__
 121   cmp  r2, r3
 122   bcc  FillZeroFASTRAM
 123
 124 /* Mark the heap and stack */
 125     ldr r2, =_heap_stack_begin
 126     b LoopMarkHeapStack
 127
 128 MarkHeapStack:
 129   movs  r3, 0xa5a5a5a5
 130   str r3, [r2], #4
 131
 132 LoopMarkHeapStack:
 133   ldr r3, = _heap_stack_end
 134   cmp r2, r3
 135   bcc MarkHeapStack
 136
 137 /* Call the clock system intitialization function.*/
 138   bl  SystemInit
 139 /* Call static constructors */
 140 /*  bl __libc_init_array */
 141 /* Call the application's entry point.*/
 142   bl  main
 143   bx  lr
 144 .size  Reset_Handler, .-Reset_Handler
 145
 146 /**
 147  * @brief  This is the code that gets called when the processor receives an
 148  *         unexpected interrupt.  This simply enters an infinite loop, preserving
 149  *         the system state for examination by a debugger.
 150  * @param  None
 151  * @retval None
 152 */
 153     .section  .text.Default_Handler,"ax",%progbits
 154 Default_Handler:
 155 Infinite_Loop:
 156   b  Infinite_Loop
 157   .size  Default_Handler, .-Default_Handler
 158 /******************************************************************************
 159 *
 160 * The minimal vector table for a Cortex M. Note that the proper constructs
 161 * must be placed on this to ensure that it ends up at physical address
 162 * 0x0000.0000.
 163 *
 164 *******************************************************************************/
 165    .section  .isr_vector,"a",%progbits
 166   .type  g_pfnVectors, %object
 167   .size  g_pfnVectors, .-g_pfnVectors
 168
 169
 170 g_pfnVectors:
 171   .word  _estack
 172   .word  Reset_Handler
 173
 174   .word  NMI_Handler
 175   .word  HardFault_Handler
 176   .word  MemManage_Handler
 177   .word  BusFault_Handler
 178   .word  UsageFault_Handler
 179   .word  0
 180   .word  0
 181   .word  0
 182   .word  0
 183   .word  SVC_Handler
 184   .word  DebugMon_Handler
 185   .word  0
 186   .word  PendSV_Handler
 187   .word  SysTick_Handler
 188
 189   /* External Interrupts */
 190   .word     WWDG_IRQHandler                   /* Window WatchDog              */
 191   .word     PVD_AVD_IRQHandler                /* PVD/AVD through EXTI Line detection */
 192   .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
 193   .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
 194   .word     FLASH_IRQHandler                  /* FLASH                        */
 195   .word     RCC_IRQHandler                    /* RCC                          */
 196   .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
 197   .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
 198   .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
 199   .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
 200   .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
 201   .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
 202   .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
 203   .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
 204   .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
 205   .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
 206   .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
 207   .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
 208   .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
 209   .word     FDCAN1_IT0_IRQHandler             /* FDCAN1 interrupt line 0      */
 210   .word     FDCAN2_IT0_IRQHandler             /* FDCAN2 interrupt line 0      */
 211   .word     FDCAN1_IT1_IRQHandler             /* FDCAN1 interrupt line 1      */
 212   .word     FDCAN2_IT1_IRQHandler             /* FDCAN2 interrupt line 1      */
 213   .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
 214   .word     TIM1_BRK_IRQHandler               /* TIM1 Break interrupt         */
 215   .word     TIM1_UP_IRQHandler                /* TIM1 Update interrupt        */
 216   .word     TIM1_TRG_COM_IRQHandler           /* TIM1 Trigger and Commutation interrupt */
 217   .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
 218   .word     TIM2_IRQHandler                   /* TIM2                         */
 219   .word     TIM3_IRQHandler                   /* TIM3                         */
 220   .word     TIM4_IRQHandler                   /* TIM4                         */
 221   .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
 222   .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
 223   .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
 224   .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
 225   .word     SPI1_IRQHandler                   /* SPI1                         */
 226   .word     SPI2_IRQHandler                   /* SPI2                         */
 227   .word     USART1_IRQHandler                 /* USART1                       */
 228   .word     USART2_IRQHandler                 /* USART2                       */
 229   .word     USART3_IRQHandler                 /* USART3                       */
 230   .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
 231   .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
 232   .word     0                                 /* Reserved                     */
 233   .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
 234   .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
 235   .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
 236   .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
 237   .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
 238   .word     FMC_IRQHandler                    /* FMC                          */
 239   .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
 240   .word     TIM5_IRQHandler                   /* TIM5                         */
 241   .word     SPI3_IRQHandler                   /* SPI3                         */
 242   .word     UART4_IRQHandler                  /* UART4                        */
 243   .word     UART5_IRQHandler                  /* UART5                        */
 244   .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
 245   .word     TIM7_IRQHandler                   /* TIM7                         */
 246   .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
 247   .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
 248   .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
 249   .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
 250   .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
 251   .word     ETH_IRQHandler                    /* Ethernet                     */
 252   .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
 253   .word     FDCAN_CAL_IRQHandler              /* FDCAN calibration unit interrupt*/
 254   .word     0                                 /* Reserved                     */
 255   .word     0                                 /* Reserved                     */
 256   .word     0                                 /* Reserved                     */
 257   .word     0                                 /* Reserved                     */
 258   .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
 259   .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
 260   .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
 261   .word     USART6_IRQHandler                 /* USART6                       */
 262   .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
 263   .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
 264   .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
 265   .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
 266   .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
 267   .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
 268   .word     DCMI_IRQHandler                   /* DCMI                         */
 269   .word     0                                 /* Reserved                     */
 270   .word     RNG_IRQHandler                    /* Rng                          */
 271   .word     FPU_IRQHandler                    /* FPU                          */
 272   .word     UART7_IRQHandler                  /* UART7                        */
 273   .word     UART8_IRQHandler                  /* UART8                        */
 274   .word     SPI4_IRQHandler                   /* SPI4                         */
 275   .word     SPI5_IRQHandler                   /* SPI5                         */
 276   .word     SPI6_IRQHandler                   /* SPI6                         */
 277   .word     SAI1_IRQHandler                   /* SAI1                         */
 278   .word     LTDC_IRQHandler                   /* LTDC                         */
 279   .word     LTDC_ER_IRQHandler                /* LTDC error                   */
 280   .word     DMA2D_IRQHandler                  /* DMA2D                        */
 281   .word     SAI2_IRQHandler                   /* SAI2                         */
 282   .word     QUADSPI_IRQHandler                /* QUADSPI                      */
 283   .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
 284   .word     CEC_IRQHandler                    /* HDMI_CEC                     */
 285   .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
 286   .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
 287   .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
 288   .word     OTG_FS_EP1_OUT_IRQHandler         /* USB OTG FS End Point 1 Out   */
 289   .word     OTG_FS_EP1_IN_IRQHandler          /* USB OTG FS End Point 1 In    */
 290   .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI */
 291   .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
 292   .word     DMAMUX1_OVR_IRQHandler            /* DMAMUX1 Overrun interrupt    */
 293   .word     HRTIM1_Master_IRQHandler          /* HRTIM Master Timer global Interrupt */
 294   .word     HRTIM1_TIMA_IRQHandler            /* HRTIM Timer A global Interrupt */
 295   .word     HRTIM1_TIMB_IRQHandler            /* HRTIM Timer B global Interrupt */
 296   .word     HRTIM1_TIMC_IRQHandler            /* HRTIM Timer C global Interrupt */
 297   .word     HRTIM1_TIMD_IRQHandler            /* HRTIM Timer D global Interrupt */
 298   .word     HRTIM1_TIME_IRQHandler            /* HRTIM Timer E global Interrupt */
 299   .word     HRTIM1_FLT_IRQHandler             /* HRTIM Fault global Interrupt   */
 300   .word     DFSDM1_FLT0_IRQHandler            /* DFSDM Filter0 Interrupt        */
 301   .word     DFSDM1_FLT1_IRQHandler            /* DFSDM Filter1 Interrupt        */
 302   .word     DFSDM1_FLT2_IRQHandler            /* DFSDM Filter2 Interrupt        */
 303   .word     DFSDM1_FLT3_IRQHandler            /* DFSDM Filter3 Interrupt        */
 304   .word     SAI3_IRQHandler                   /* SAI3 global Interrupt          */
 305   .word     SWPMI1_IRQHandler                 /* Serial Wire Interface 1 global interrupt */
 306   .word     TIM15_IRQHandler                  /* TIM15 global Interrupt      */
 307   .word     TIM16_IRQHandler                  /* TIM16 global Interrupt      */
 308   .word     TIM17_IRQHandler                  /* TIM17 global Interrupt      */
 309   .word     MDIOS_WKUP_IRQHandler             /* MDIOS Wakeup  Interrupt     */
 310   .word     MDIOS_IRQHandler                  /* MDIOS global Interrupt      */
 311   .word     JPEG_IRQHandler                   /* JPEG global Interrupt       */
 312   .word     MDMA_IRQHandler                   /* MDMA global Interrupt       */
 313   .word     0                                 /* Reserved                    */
 314   .word     SDMMC2_IRQHandler                 /* SDMMC2 global Interrupt     */
 315   .word     HSEM1_IRQHandler                  /* HSEM1 global Interrupt      */
 316   .word     0                                 /* Reserved                    */
 317   .word     ADC3_IRQHandler                   /* ADC3 global Interrupt       */
 318   .word     DMAMUX2_OVR_IRQHandler            /* DMAMUX Overrun interrupt    */
 319   .word     BDMA_Channel0_IRQHandler          /* BDMA Channel 0 global Interrupt */
 320   .word     BDMA_Channel1_IRQHandler          /* BDMA Channel 1 global Interrupt */
 321   .word     BDMA_Channel2_IRQHandler          /* BDMA Channel 2 global Interrupt */
 322   .word     BDMA_Channel3_IRQHandler          /* BDMA Channel 3 global Interrupt */
 323   .word     BDMA_Channel4_IRQHandler          /* BDMA Channel 4 global Interrupt */
 324   .word     BDMA_Channel5_IRQHandler          /* BDMA Channel 5 global Interrupt */
 325   .word     BDMA_Channel6_IRQHandler          /* BDMA Channel 6 global Interrupt */
 326   .word     BDMA_Channel7_IRQHandler          /* BDMA Channel 7 global Interrupt */
 327   .word     COMP1_IRQHandler                  /* COMP1 global Interrupt     */
 328   .word     LPTIM2_IRQHandler                 /* LP TIM2 global interrupt   */
 329   .word     LPTIM3_IRQHandler                 /* LP TIM3 global interrupt   */
 330   .word     LPTIM4_IRQHandler                 /* LP TIM4 global interrupt   */
 331   .word     LPTIM5_IRQHandler                 /* LP TIM5 global interrupt   */
 332   .word     LPUART1_IRQHandler                /* LP UART1 interrupt         */
 333   .word     0                                 /* Reserved                   */
 334   .word     CRS_IRQHandler                    /* Clock Recovery Global Interrupt */
 335   .word     0                                 /* Reserved                   */
 336   .word     SAI4_IRQHandler                   /* SAI4 global interrupt      */
 337   .word     0                                 /* Reserved                   */
 338   .word     0                                 /* Reserved                   */
 339   .word     WAKEUP_PIN_IRQHandler             /* Interrupt for all 6 wake-up pins */
 340
 341 /*******************************************************************************
 342 *
 343 * Provide weak aliases for each Exception handler to the Default_Handler.
 344 * As they are weak aliases, any function with the same name will override
 345 * this definition.
 346 *
 347 *******************************************************************************/
 348    .weak      NMI_Handler
 349    .thumb_set NMI_Handler,Default_Handler
 350
 351    .weak      HardFault_Handler
 352    .thumb_set HardFault_Handler,Default_Handler
 353
 354    .weak      MemManage_Handler
 355    .thumb_set MemManage_Handler,Default_Handler
 356
 357    .weak      BusFault_Handler
 358    .thumb_set BusFault_Handler,Default_Handler
 359
 360    .weak      UsageFault_Handler
 361    .thumb_set UsageFault_Handler,Default_Handler
 362
 363    .weak      SVC_Handler
 364    .thumb_set SVC_Handler,Default_Handler
 365
 366    .weak      DebugMon_Handler
 367    .thumb_set DebugMon_Handler,Default_Handler
 368
 369    .weak      PendSV_Handler
 370    .thumb_set PendSV_Handler,Default_Handler
 371
 372    .weak      SysTick_Handler
 373    .thumb_set SysTick_Handler,Default_Handler
 374
 375    .weak      WWDG_IRQHandler
 376    .thumb_set WWDG_IRQHandler,Default_Handler
 377
 378    .weak      PVD_AVD_IRQHandler
 379    .thumb_set PVD_AVD_IRQHandler,Default_Handler
 380
 381    .weak      TAMP_STAMP_IRQHandler
 382    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
 383
 384    .weak      RTC_WKUP_IRQHandler
 385    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
 386
 387    .weak      FLASH_IRQHandler
 388    .thumb_set FLASH_IRQHandler,Default_Handler
 389
 390    .weak      RCC_IRQHandler
 391    .thumb_set RCC_IRQHandler,Default_Handler
 392
 393    .weak      EXTI0_IRQHandler
 394    .thumb_set EXTI0_IRQHandler,Default_Handler
 395
 396    .weak      EXTI1_IRQHandler
 397    .thumb_set EXTI1_IRQHandler,Default_Handler
 398
 399    .weak      EXTI2_IRQHandler
 400    .thumb_set EXTI2_IRQHandler,Default_Handler
 401
 402    .weak      EXTI3_IRQHandler
 403    .thumb_set EXTI3_IRQHandler,Default_Handler
 404
 405    .weak      EXTI4_IRQHandler
 406    .thumb_set EXTI4_IRQHandler,Default_Handler
 407
 408    .weak      DMA1_Stream0_IRQHandler
 409    .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
 410
 411    .weak      DMA1_Stream1_IRQHandler
 412    .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
 413
 414    .weak      DMA1_Stream2_IRQHandler
 415    .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
 416
 417    .weak      DMA1_Stream3_IRQHandler
 418    .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
 419
 420    .weak      DMA1_Stream4_IRQHandler
 421    .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
 422
 423    .weak      DMA1_Stream5_IRQHandler
 424    .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
 425
 426    .weak      DMA1_Stream6_IRQHandler
 427    .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
 428
 429    .weak      ADC_IRQHandler
 430    .thumb_set ADC_IRQHandler,Default_Handler
 431
 432    .weak      FDCAN1_IT0_IRQHandler
 433    .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
 434
 435    .weak      FDCAN2_IT0_IRQHandler
 436    .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
 437
 438    .weak      FDCAN1_IT1_IRQHandler
 439    .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
 440
 441    .weak      FDCAN2_IT1_IRQHandler
 442    .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
 443
 444    .weak      EXTI9_5_IRQHandler
 445    .thumb_set EXTI9_5_IRQHandler,Default_Handler
 446
 447    .weak      TIM1_BRK_IRQHandler
 448    .thumb_set TIM1_BRK_IRQHandler,Default_Handler
 449
 450    .weak      TIM1_UP_IRQHandler
 451    .thumb_set TIM1_UP_IRQHandler,Default_Handler
 452
 453    .weak      TIM1_TRG_COM_IRQHandler
 454    .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
 455
 456    .weak      TIM1_CC_IRQHandler
 457    .thumb_set TIM1_CC_IRQHandler,Default_Handler
 458
 459    .weak      TIM2_IRQHandler
 460    .thumb_set TIM2_IRQHandler,Default_Handler
 461
 462    .weak      TIM3_IRQHandler
 463    .thumb_set TIM3_IRQHandler,Default_Handler
 464
 465    .weak      TIM4_IRQHandler
 466    .thumb_set TIM4_IRQHandler,Default_Handler
 467
 468    .weak      I2C1_EV_IRQHandler
 469    .thumb_set I2C1_EV_IRQHandler,Default_Handler
 470
 471    .weak      I2C1_ER_IRQHandler
 472    .thumb_set I2C1_ER_IRQHandler,Default_Handler
 473
 474    .weak      I2C2_EV_IRQHandler
 475    .thumb_set I2C2_EV_IRQHandler,Default_Handler
 476
 477    .weak      I2C2_ER_IRQHandler
 478    .thumb_set I2C2_ER_IRQHandler,Default_Handler
 479
 480    .weak      SPI1_IRQHandler
 481    .thumb_set SPI1_IRQHandler,Default_Handler
 482
 483    .weak      SPI2_IRQHandler
 484    .thumb_set SPI2_IRQHandler,Default_Handler
 485
 486    .weak      USART1_IRQHandler
 487    .thumb_set USART1_IRQHandler,Default_Handler
 488
 489    .weak      USART2_IRQHandler
 490    .thumb_set USART2_IRQHandler,Default_Handler
 491
 492    .weak      USART3_IRQHandler
 493    .thumb_set USART3_IRQHandler,Default_Handler
 494
 495    .weak      EXTI15_10_IRQHandler
 496    .thumb_set EXTI15_10_IRQHandler,Default_Handler
 497
 498    .weak      RTC_Alarm_IRQHandler
 499    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
 500
 501    .weak      TIM8_BRK_TIM12_IRQHandler
 502    .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
 503
 504    .weak      TIM8_UP_TIM13_IRQHandler
 505    .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
 506
 507    .weak      TIM8_TRG_COM_TIM14_IRQHandler
 508    .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
 509
 510    .weak      TIM8_CC_IRQHandler
 511    .thumb_set TIM8_CC_IRQHandler,Default_Handler
 512
 513    .weak      DMA1_Stream7_IRQHandler
 514    .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
 515
 516    .weak      FMC_IRQHandler
 517    .thumb_set FMC_IRQHandler,Default_Handler
 518
 519    .weak      SDMMC1_IRQHandler
 520    .thumb_set SDMMC1_IRQHandler,Default_Handler
 521
 522    .weak      TIM5_IRQHandler
 523    .thumb_set TIM5_IRQHandler,Default_Handler
 524
 525    .weak      SPI3_IRQHandler
 526    .thumb_set SPI3_IRQHandler,Default_Handler
 527
 528    .weak      UART4_IRQHandler
 529    .thumb_set UART4_IRQHandler,Default_Handler
 530
 531    .weak      UART5_IRQHandler
 532    .thumb_set UART5_IRQHandler,Default_Handler
 533
 534    .weak      TIM6_DAC_IRQHandler
 535    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
 536
 537    .weak      TIM7_IRQHandler
 538    .thumb_set TIM7_IRQHandler,Default_Handler
 539
 540    .weak      DMA2_Stream0_IRQHandler
 541    .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
 542
 543    .weak      DMA2_Stream1_IRQHandler
 544    .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
 545
 546    .weak      DMA2_Stream2_IRQHandler
 547    .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
 548
 549    .weak      DMA2_Stream3_IRQHandler
 550    .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
 551
 552    .weak      DMA2_Stream4_IRQHandler
 553    .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
 554
 555    .weak      ETH_IRQHandler
 556    .thumb_set ETH_IRQHandler,Default_Handler
 557
 558    .weak      ETH_WKUP_IRQHandler
 559    .thumb_set ETH_WKUP_IRQHandler,Default_Handler
 560
 561    .weak      FDCAN_CAL_IRQHandler
 562    .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
 563
 564    .weak      DMA2_Stream5_IRQHandler
 565    .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
 566
 567    .weak      DMA2_Stream6_IRQHandler
 568    .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
 569
 570    .weak      DMA2_Stream7_IRQHandler
 571    .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
 572
 573    .weak      USART6_IRQHandler
 574    .thumb_set USART6_IRQHandler,Default_Handler
 575
 576    .weak      I2C3_EV_IRQHandler
 577    .thumb_set I2C3_EV_IRQHandler,Default_Handler
 578
 579    .weak      I2C3_ER_IRQHandler
 580    .thumb_set I2C3_ER_IRQHandler,Default_Handler
 581
 582    .weak      OTG_HS_EP1_OUT_IRQHandler
 583    .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
 584
 585    .weak      OTG_HS_EP1_IN_IRQHandler
 586    .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
 587
 588    .weak      OTG_HS_WKUP_IRQHandler
 589    .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
 590
 591    .weak      OTG_HS_IRQHandler
 592    .thumb_set OTG_HS_IRQHandler,Default_Handler
 593
 594    .weak      DCMI_IRQHandler
 595    .thumb_set DCMI_IRQHandler,Default_Handler
 596
 597    .weak      RNG_IRQHandler
 598    .thumb_set RNG_IRQHandler,Default_Handler
 599
 600    .weak      FPU_IRQHandler
 601    .thumb_set FPU_IRQHandler,Default_Handler
 602
 603    .weak      UART7_IRQHandler
 604    .thumb_set UART7_IRQHandler,Default_Handler
 605
 606    .weak      UART8_IRQHandler
 607    .thumb_set UART8_IRQHandler,Default_Handler
 608
 609    .weak      SPI4_IRQHandler
 610    .thumb_set SPI4_IRQHandler,Default_Handler
 611
 612    .weak      SPI5_IRQHandler
 613    .thumb_set SPI5_IRQHandler,Default_Handler
 614
 615    .weak      SPI6_IRQHandler
 616    .thumb_set SPI6_IRQHandler,Default_Handler
 617
 618    .weak      SAI1_IRQHandler
 619    .thumb_set SAI1_IRQHandler,Default_Handler
 620
 621    .weak      LTDC_IRQHandler
 622    .thumb_set LTDC_IRQHandler,Default_Handler
 623
 624    .weak      LTDC_ER_IRQHandler
 625    .thumb_set LTDC_ER_IRQHandler,Default_Handler
 626
 627    .weak      DMA2D_IRQHandler
 628    .thumb_set DMA2D_IRQHandler,Default_Handler
 629
 630    .weak      SAI2_IRQHandler
 631    .thumb_set SAI2_IRQHandler,Default_Handler
 632
 633    .weak      QUADSPI_IRQHandler
 634    .thumb_set QUADSPI_IRQHandler,Default_Handler
 635
 636    .weak      LPTIM1_IRQHandler
 637    .thumb_set LPTIM1_IRQHandler,Default_Handler
 638
 639    .weak      CEC_IRQHandler
 640    .thumb_set CEC_IRQHandler,Default_Handler
 641
 642    .weak      I2C4_EV_IRQHandler
 643    .thumb_set I2C4_EV_IRQHandler,Default_Handler
 644
 645    .weak      I2C4_ER_IRQHandler
 646    .thumb_set I2C4_ER_IRQHandler,Default_Handler
 647
 648    .weak      SPDIF_RX_IRQHandler
 649    .thumb_set SPDIF_RX_IRQHandler,Default_Handler
 650
 651    .weak      OTG_FS_EP1_OUT_IRQHandler
 652    .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
 653
 654    .weak      OTG_FS_EP1_IN_IRQHandler
 655    .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
 656
 657    .weak      OTG_FS_WKUP_IRQHandler
 658    .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
 659
 660    .weak      OTG_FS_IRQHandler
 661    .thumb_set OTG_FS_IRQHandler,Default_Handler
 662
 663    .weak      DMAMUX1_OVR_IRQHandler
 664    .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
 665
 666    .weak      HRTIM1_Master_IRQHandler
 667    .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
 668
 669    .weak      HRTIM1_TIMA_IRQHandler
 670    .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
 671
 672    .weak      HRTIM1_TIMB_IRQHandler
 673    .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
 674
 675    .weak      HRTIM1_TIMC_IRQHandler
 676    .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
 677
 678    .weak      HRTIM1_TIMD_IRQHandler
 679    .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
 680
 681    .weak      HRTIM1_TIME_IRQHandler
 682    .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
 683
 684    .weak      HRTIM1_FLT_IRQHandler
 685    .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
 686
 687    .weak      DFSDM1_FLT0_IRQHandler
 688    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
 689
 690    .weak      DFSDM1_FLT1_IRQHandler
 691    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
 692
 693    .weak      DFSDM1_FLT2_IRQHandler
 694    .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
 695
 696    .weak      DFSDM1_FLT3_IRQHandler
 697    .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
 698
 699    .weak      SAI3_IRQHandler
 700    .thumb_set SAI3_IRQHandler,Default_Handler
 701
 702    .weak      SWPMI1_IRQHandler
 703    .thumb_set SWPMI1_IRQHandler,Default_Handler
 704
 705    .weak      TIM15_IRQHandler
 706    .thumb_set TIM15_IRQHandler,Default_Handler
 707
 708    .weak      TIM16_IRQHandler
 709    .thumb_set TIM16_IRQHandler,Default_Handler
 710
 711    .weak      TIM17_IRQHandler
 712    .thumb_set TIM17_IRQHandler,Default_Handler
 713
 714    .weak      MDIOS_WKUP_IRQHandler
 715    .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
 716
 717    .weak      MDIOS_IRQHandler
 718    .thumb_set MDIOS_IRQHandler,Default_Handler
 719
 720    .weak      JPEG_IRQHandler
 721    .thumb_set JPEG_IRQHandler,Default_Handler
 722
 723    .weak      MDMA_IRQHandler
 724    .thumb_set MDMA_IRQHandler,Default_Handler
 725
 726    .weak      SDMMC2_IRQHandler
 727    .thumb_set SDMMC2_IRQHandler,Default_Handler
 728
 729    .weak      HSEM1_IRQHandler
 730    .thumb_set HSEM1_IRQHandler,Default_Handler
 731
 732    .weak      ADC3_IRQHandler
 733    .thumb_set ADC3_IRQHandler,Default_Handler
 734
 735    .weak      DMAMUX2_OVR_IRQHandler
 736    .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
 737
 738    .weak      BDMA_Channel0_IRQHandler
 739    .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
 740
 741    .weak      BDMA_Channel1_IRQHandler
 742    .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
 743
 744    .weak      BDMA_Channel2_IRQHandler
 745    .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
 746
 747    .weak      BDMA_Channel3_IRQHandler
 748    .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
 749
 750    .weak      BDMA_Channel4_IRQHandler
 751    .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
 752
 753    .weak      BDMA_Channel5_IRQHandler
 754    .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
 755
 756    .weak      BDMA_Channel6_IRQHandler
 757    .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
 758
 759    .weak      BDMA_Channel7_IRQHandler
 760    .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
 761
 762    .weak      COMP1_IRQHandler
 763    .thumb_set COMP1_IRQHandler,Default_Handler
 764
 765    .weak      LPTIM2_IRQHandler
 766    .thumb_set LPTIM2_IRQHandler,Default_Handler
 767
 768    .weak      LPTIM3_IRQHandler
 769    .thumb_set LPTIM3_IRQHandler,Default_Handler
 770
 771    .weak      LPTIM4_IRQHandler
 772    .thumb_set LPTIM4_IRQHandler,Default_Handler
 773
 774    .weak      LPTIM5_IRQHandler
 775    .thumb_set LPTIM5_IRQHandler,Default_Handler
 776
 777    .weak      LPUART1_IRQHandler
 778    .thumb_set LPUART1_IRQHandler,Default_Handler
 779
 780    .weak      CRS_IRQHandler
 781    .thumb_set CRS_IRQHandler,Default_Handler
 782
 783    .weak      SAI4_IRQHandler
 784    .thumb_set SAI4_IRQHandler,Default_Handler
 785
 786    .weak      WAKEUP_PIN_IRQHandler
 787    .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
 788
 789 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 790