prism54_usb.h

   1 /*
   2  * Prism54 USB driver
   3
   4 T:  Bus=01 Lev=01 Prnt=01 Port=03 Cnt=01 Dev#=  2 Spd=480 MxCh= 0
   5 D:  Ver= 2.00 Cls=ff(vend.) Sub=00 Prot=00 MxPS=64 #Cfgs=  1
   6 P:  Vendor=5041 ProdID=2234 Rev= 2.02
   7 C:* #Ifs= 1 Cfg#= 1 Atr=80 MxPwr=500mA
   8 I:  If#= 0 Alt= 0 #EPs=11 Cls=ff(vend.) Sub=00 Prot=00 Driver=(none)
   9 E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  10 E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  11 E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  12 E:  Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  13 E:  Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  14 E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  15 E:  Ad=8d(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  16 E:  Ad=0d(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  17 E:  Ad=8e(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  18 E:  Ad=0e(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
  19 E:  Ad=8f(I) Atr=03(Int.) MxPS=   4 Ivl=125us
  20
  21  */
  22 #include <linux/usb.h>
  23 #include <linux/wireless.h>
  24
  25 #include "net2280.h"
  26 #include "p54u_protocol.h"
  27
  28
  29 //#undef CONFIG_USB_DEBUG
  30 #define CONFIG_USB_DEBUG y
  31
  32 #ifdef CONFIG_USB_DEBUG
  33 #define p54u_dbg(format, arg...) if(debug > 1) printk(format "\n" ,##arg)
  34 #else
  35 #define p54u_dbg(format, arg...)
  36 #endif
  37 #define p54u_info(format, arg...) if(debug) printk(KERN_INFO __FILE__ ": " format "\n" , ##arg)
  38 #define p54u_warn(format, arg...) printk(KERN_WARN __FILE__ ": " format "\n" , ##arg)
  39 #define p54u_err(format, arg...) printk(KERN_ERR __FILE__ ": " format "\n" ,##arg)
  40
  41 #define p54u_time(arg...) 0LL
  42 //#define p54u_time(arg...) (get_jiffies_64(##arg) - p54u->time)
  43
  44 #define P54U_TX_TIMEOUT         (2*HZ)
  45
  46 #define P54U_REG_WSIZE          (sizeof(struct p54u_reg))
  47 #define P54U_REG_RSIZE          (P54U_REG_WSIZE - (sizeof(u32)))
  48
  49 #define P54U_PORT_BRG           0x0010
  50 #define P54U_PORT_BRG_CFG       0x0000
  51 #define P54U_PORT_DEV           0x0800
  52 #define P54U_PORT_DEV_CFG       0x0880
  53 #define P54U_PORT_U16           0x0003
  54 #define P54U_PORT_U32           0x000f
  55
  56 #define P54U_PORT_BRG_U32       (P54U_PORT_BRG | P54U_PORT_U32)
  57 #define P54U_PORT_BRG_CFG_U32   (P54U_PORT_BRG_CFG | P54U_PORT_U32)
  58 #define P54U_PORT_BRG_CFG_U16   (P54U_PORT_BRG_CFG | P54U_PORT_U16)
  59
  60 #define P54U_PORT_DEV_U32       (P54U_PORT_DEV | P54U_PORT_U32)
  61 #define P54U_PORT_DEV_CFG_U32   (P54U_PORT_DEV_CFG | P54U_PORT_U32)
  62 #define P54U_PORT_DEV_CFG_U16   (P54U_PORT_DEV_CFG | P54U_PORT_U16)
  63
  64 /* pci */
  65 #define NET2280_BASE            0x10000000
  66 #define NET2280_BASE2           0x20000000
  67
  68 /* gpio */
  69 #define P54U_BRG_POWER_UP       (1 << GPIO0_DATA)
  70 #define P54U_BRG_POWER_DOWN     (1 << GPIO1_DATA)
  71
  72 /* devinit */
  73 #define NET2280_CLK_4Mhz        (15 << LOCAL_CLOCK_FREQUENCY)
  74 #define NET2280_CLK_30Mhz       (2 << LOCAL_CLOCK_FREQUENCY)
  75 #define NET2280_CLK_60Mhz       (1 << LOCAL_CLOCK_FREQUENCY)
  76 #define NET2280_CLK_STOP        (0 << LOCAL_CLOCK_FREQUENCY)
  77 #define NET2280_PCI_ENABLE      (1 << PCI_ENABLE)
  78 #define NET2280_PCI_SOFT_RESET  (1 << PCI_SOFT_RESET)
  79
  80 /* enpoints */
  81 #define NET2280_CLEAR_NAK_OUT_PACKETS_MODE      (1 << CLEAR_NAK_OUT_PACKETS_MODE)
  82 #define NET2280_FIFO_FLUSH                      (1 << FIFO_FLUSH)
  83
  84 /* irq */
  85 #define NET2280_USB_INTERRUPT_ENABLE            (1 << USB_INTERRUPT_ENABLE)
  86 #define NET2280_PCI_INTA_INTERRUPT              (1 << PCI_INTA_INTERRUPT)
  87 #define NET2280_PCI_INTA_INTERRUPT_ENABLE       (1 << PCI_INTA_INTERRUPT_ENABLE)
  88
  89 /* registers */
  90 #define NET2280_DEVINIT         0x00
  91 #define NET2280_USBIRQENB1      0x24
  92 #define NET2280_IRQSTAT1        0x2c
  93 #define NET2280_FIFOCTL     0x38
  94 #define NET2280_GPIOCTL         0x50
  95 #define NET2280_RELNUM          0x88
  96 #define NET2280_EPA_RSP         0x324
  97 #define NET2280_EPA_STAT        0x32c
  98 #define NET2280_EPB_STAT        0x34c
  99 #define NET2280_EPC_RSP         0x364
 100 #define NET2280_EPC_STAT        0x36c
 101 #define NET2280_EPD_STAT        0x38c
 102
 103 #define NET2280_EPA_CFG     0x320
 104 #define NET2280_EPB_CFG     0x340
 105 #define NET2280_EPC_CFG     0x360
 106 #define NET2280_EPD_CFG     0x380
 107 #define NET2280_EPE_CFG     0x3A0
 108 #define NET2280_EPF_CFG     0x3C0
 109
 110
 111 #define P54U_DEV_BASE           0x40000000
 112
 113 #define P54U_TRDY_TIMEOUT       0x40
 114 #define P54U_RETRY_TIMEOUTG     0x41
 115
 116 #define P54U_IMAGE_FILE         "isl3890usb"
 117
 118 //#define P54U_MAX_FRAME_SIZE   16384
 119 #define P54U_MAX_FRAME_SIZE     4096
 120 //#define P54U_QUEUE_LEN        16
 121 #define P54U_QUEUE_LEN          2
 122 #define P54U_FW_BLOCK           512
 123 #define P54U_INIT_BLOCK         0x03fc
 124 #define P54U_MGMT_MEM_SIZE      0x2000
 125
 126 #define p54u_brg_writel(dev, addr, val)         p54u_reg_rw(dev, 1, P54U_PIPE_BRG, P54U_PORT_BRG_U32, addr, val)
 127 #define p54u_pcicfg_brg_writel(dev, addr, val)  p54u_reg_rw(dev, 1, P54U_PIPE_BRG, P54U_PORT_BRG_CFG_U32, addr, val)
 128 #define p54u_pcicfg_brg_writew(dev, addr, val)  p54u_reg_rw(dev, 1, P54U_PIPE_BRG, P54U_PORT_BRG_CFG_U16, addr, (val & 0xffff))
 129
 130 #define p54u_dev_writel(dev, reg, val)          p54u_reg_rw(dev, 1, P54U_PIPE_DEV, P54U_PORT_DEV_U32, (P54U_DEV_BASE | reg), val)
 131 #define p54u_pcicfg_dev_writel(dev, addr, val)  p54u_reg_rw(dev, 1, P54U_PIPE_DEV, P54U_PORT_DEV_CFG_U32, addr, val)
 132 #define p54u_pcicfg_dev_writew(dev, addr, val)  p54u_reg_rw(dev, 1, P54U_PIPE_DEV, P54U_PORT_DEV_CFG_U16, addr, (val & 0xffff))
 133
 134 #define p54u_brg_readl(dev, addr)               p54u_reg_rw(dev, 0, P54U_PIPE_BRG, P54U_PORT_BRG_U32, addr, 0)
 135 #define p54u_pcicfg_brg_readl(dev, addr)        p54u_reg_rw(dev, 0, P54U_PIPE_BRG, P54U_PORT_BRG_CFG_U32, addr, 0)
 136 #define p54u_pcicfg_brg_readw(dev, addr)        (p54u_reg_rw(dev, 0, P54U_PIPE_BRG, P54U_PORT_BRG_CFG_U16, addr, 0) & 0xffff)
 137
 138 #define p54u_dev_readl(dev, reg)                p54u_reg_rw(dev, 0, P54U_PIPE_DEV, P54U_PORT_DEV_U32, (P54U_DEV_BASE | reg), 0)
 139 #define p54u_pcicfg_dev_readl(dev, addr)        p54u_reg_rw(dev, 0, P54U_PIPE_DEV, P54U_PORT_DEV_CFG_U32, addr, 0)
 140 #define p54u_pcicfg_dev_readw(dev, addr)        (p54u_reg_rw(dev, 0, P54U_PIPE_DEV, P54U_PORT_DEV_CFG_U16, addr, 0) & 0xffff)
 141
 142 enum p54u_pipe_addr {
 143         P54U_PIPE_DATA =        0x01,
 144         P54U_PIPE_MGMT =        0x02,
 145         P54U_PIPE_3 =           0x03,
 146         P54U_PIPE_4 =           0x04,
 147         P54U_PIPE_BRG =         0x0d,
 148         P54U_PIPE_DEV =         0x0e,
 149         P54U_PIPE_INT =         0x0f,
 150 };
 151
 152 enum p54u_pipe_index {
 153         P54U_TX_DATA,
 154         P54U_TX_MGMT,
 155         P54U_TX_BRG,
 156         P54U_TX_DEV,
 157         P54U_RX_DATA,
 158         P54U_RX_MGMT,
 159         P54U_RX_3,
 160         P54U_RX_4,
 161         P54U_RX_BRG,
 162         P54U_RX_DEV,
 163         P54U_RX_INT,
 164         P54U_PIPES,
 165 };
 166
 167 enum p54u_state {
 168         P54U_BOOT,
 169         P54U_RUN,
 170         P54U_SHUTDOWN,
 171 };
 172
 173 struct p54u_reg {
 174         u16     port;
 175         u32     addr;
 176         u32     val;
 177 } __attribute__ ((packed));
 178
 179 struct p54u_mgmt_tx {
 180         u32     magic1;
 181         u32     magic2;
 182         u32     magic3;
 183         u16     pos;
 184         u16     len;
 185 } __attribute__ ((packed));
 186
 187
 188 struct p54u_pipe_desc {
 189         u8              addr;   /* the address of the endpoint */
 190         u8              type;   /* the transfer type of the endpoint */
 191         size_t          p_size; /* the size of the packet */
 192         void            (*callback)(struct urb *urb, struct pt_regs *regs);
 193 };
 194
 195 struct p54u_pipe {
 196         struct urb      **urb;  /* the urb used to send data */
 197         void            **buf;  /* the buffer */
 198         size_t          *size;  /* the size of the buffer */
 199         int             len;    /* the length of the ringbufer */
 200         int             head;
 201         int             tail;
 202
 203         atomic_t        busy;   /* true if an urb has been submitted */
 204         wait_queue_head_t wqh;
 205         struct completion comp; /* wait for the operation to finish */
 206         int done;
 207
 208         u8              addr;   /* the address of the endpoint */
 209         u8              type;   /* the transfer type of the endpoint */
 210         size_t          pkt_size; /* the size of the packet */
 211 };
 212
 213 /* Structure to hold all of our device specific stuff */
 214 struct p54u {
 215         struct usb_device       *usbdev;        /* save off the usb device pointer */
 216         struct usb_interface    *interface;     /* save off the usb device pointer */
 217         struct net_device       *netdev;
 218
 219         int                     running;
 220         int                     state;
 221         int                     err;
 222
 223         struct workqueue_struct *queue;
 224         struct work             *boot;
 225         struct completion       *comp;
 226
 227         struct p54u_pipe        data_tx;
 228         struct p54u_pipe        data_rx;
 229         struct p54u_pipe        mgmt_tx;
 230         struct p54u_pipe        mgmt_rx;
 231         struct p54u_pipe        int_rx;
 232
 233         struct semaphore        disconnect_sem; /* prevent races between open() and disconnect() */
 234
 235         const struct firmware   *fw_entry;
 236         u64                     time;
 237         u32                     pending;
 238
 239         /* added, not proper maybe */
 240         struct work_struct      int_ack;
 241   struct work_struct data_bh;
 242         struct p54u_mgmt_rx_frame mgmt_frame;
 243         struct net_device_stats statistics;
 244         struct iw_statistics iwstatistics;
 245 };
 246
 247 extern int load_fw;
 248 extern int debug;
 249 extern const char dummy_mac[ETH_ALEN];
 250
 251 int p54u_setup_net(struct net_device *netdev);
 252 int p54u_boot(struct net_device *netdev);
 253 int p54u_shutdown(struct net_device *netdev);
 254
 255 void p54u_mdelay(int ms);
 256 u32 p54u_reg_rw(struct net_device *netdev, int write, int ep, int port, u32 addr, u32 val);
 257 int p54u_readi(struct net_device *netdev);
 258
 259 void p54u_int_rx_cb(struct urb *urb, struct pt_regs *p);
 260 void p54u_int_ack(void *data);
 261 void p54u_data_rx(void *data);
 262
 263 void p54u_data_rx_cb(struct urb *urb, struct pt_regs *p);
 264 void p54u_mgmt_rx_cb(struct urb *urb, struct pt_regs *p);
 265
 266 int p54u_wait_int(struct net_device *netdev);
 267 int p54u_wait_data(struct net_device *netdev);
 268 int p54u_wait_mgmt_response(struct net_device *netdev);
 269
 270 int p54u_mgmt_rx_submit(struct net_device *netdev);
 271 int p54u_data_rx_submit(struct net_device *netdev);
 272
 273 int p54u_bulk_msg(struct net_device *netdev, unsigned int ep, void *data, int len);
 274 void p54u_data_debug(struct net_device *netdev, unsigned int ep, void *_data, int len);
 275
 276 int p54u_annouced_msg(struct net_device *netdev, unsigned int pipe, void *data, int data_len);
 277
 278 void make_tx_control_channel(struct p54u *p54u, void *buf, int chan);
 279
 280 #define p54u_control_msg(a,b,c) p54u_annouced_msg(a,P54U_PIPE_DATA,b,c)
 281 #define p54u_mgmt_msg(a,b,c) p54u_annouced_msg(a,P54U_PIPE_MGMT,b,c)