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sq3: show SQLite error messages on stderr by default
[iv.d.git] / olly / disasm2.d
blobacc23bfd666d9c170a1faab557167ef8580dd4e3
1 /*
2 * OllyDbg Disassembling Engine v2.01
3 *
4 * Copyright (c) 2007-2013 Oleh Yuschuk, ollydbg@t-online.de
5 *
6 * This code is part of the OllyDbg Disassembler v2.01
7 *
8 * Disassembling engine is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as published
10 * by the Free Software Foundation; either version 3 of the License, or (at
11 * your option) any later version.
12 *
13 * This code is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 * This is a fast disassembler that can be used to determine the length of
22 * the binary 80x86 32-bit command and its attributes, to convert it to the
23 * human-readable text form, highlight its operands, and create hexadecimal
24 * dump of the binary command.
25 *
26 * It is a stripped down version of the disassembler used by OllyDbg 2.01.
27 * It can't analyse and comment the contents of the operands, or predict the
28 * results of the command execution. Analysis-dependent features are not
29 * included, too. Most other features are kept.
30 *
31 * Disassembler supports integer, FPU, MMX, 3DNow, SSE1-SSE4.1 and AVX
32 * instructions. 64-bit mode, AVX2, FMA and XOP are not (yet) supported.
33 *
34 * This code is reentrant (thread-safe, feature not available in the original
35 * OllyDbg code).
36 */
37 module iv.olly.disasm2 /*is aliced*/;
38 import iv.alice;
39
40 enum TEXTLEN = 256; // Max length of text string
41 enum SHORTNAME = 32; // Max length of short or module name
42
43 enum NOPERAND = 4; // Maximal allowed number of operands
44 enum NREG = 8; // Number of registers (of any type)
45 enum NSEG = 6; // Number of valid segment registers
46 enum MAXCMDSIZE = 16; // Maximal length of valid 80x86 command
47 private enum NEGLIMIT = -16384; // Limit to decode offsets as negative
48 private enum DECLIMIT = 16384; // Limit to decode constants as decimal
49
50
51 // CMDMASK can be used to balance between the necessary memory size and the disassembly time.
52 private enum CMDMASK = 0x3FFF; // Search mask for Disassembler, 2**n-1
53 private enum NCHAIN = 44300; // Max allowed number of chain links
54
55 // Registers.
56 // Codes of general purpose registers
57 enum {
58 REG_UNDEF = -1,
59 REG_EAX = 0,
60 REG_ECX = 1,
61 REG_EDX = 2,
62 REG_EBX = 3,
63 REG_ESP = 4,
64 REG_EBP = 5,
65 REG_ESI = 6,
66 REG_EDI = 7,
67 }
68
69 // Symbolic indices of 8-bit registers
70 enum {
71 REG_AL = 0,
72 REG_CL = 1,
73 REG_DL = 2,
74 REG_BL = 3,
75 REG_AH = 4,
76 REG_CH = 5,
77 REG_DH = 6,
78 REG_BH = 7,
79 }
80
81 // Codes of segment/selector registers
82 enum {
83 SEG_UNDEF = -1,
84 SEG_ES = 0,
85 SEG_CS = 1,
86 SEG_SS = 2,
87 SEG_DS = 3,
88 SEG_FS = 4,
89 SEG_GS = 5,
90 }
91
92 // Command highlighting.
93 enum DRAW_PLAIN = '.'; //0x0000000C // Plain commands
94 enum DRAW_JUMP = '>'; //0x0000000D // Unconditional jump commands
95 enum DRAW_CJMP = '?'; //0x0000000E // Conditional jump commands
96 enum DRAW_PUSHPOP = '='; //0x0000000F // PUSH/POP commands
97 enum DRAW_CALL = '@'; //0x00000010 // CALL commands
98 enum DRAW_RET = '<'; //0x00000011 // RET commands
99 enum DRAW_FPU = '1'; //0x00000012 // FPU, MMX, 3DNow! and SSE commands
100 enum DRAW_SUSPECT = '!'; //0x00000013 // Bad, system and privileged commands
101 // Operand highlighting.
102 enum DRAW_IREG = 'R'; //0x00000018 // General purpose registers
103 enum DRAW_FREG = 'F'; //0x00000019 // FPU, MMX and SSE registers
104 enum DRAW_SYSREG = 'S'; //0x0000001A // Segment and system registers
105 enum DRAW_STKMEM = 'K'; //0x0000001B // Memory accessed over ESP or EBP
106 enum DRAW_MEM = 'M'; //0x0000001C // Any other memory
107 enum DRAW_CONST = 'C'; //0x0000001E // Constant
108
109 enum D_NONE = 0x00000000; // No special features
110 // General type of command, only one is allowed.
111 enum D_CMDTYPE = 0x0000001F; // Mask to extract type of command
112 enum D_CMD = 0x00000000; // Ordinary (none of listed below)
113 enum D_MOV = 0x00000001; // Move to or from integer register
114 enum D_MOVC = 0x00000002; // Conditional move to integer register
115 enum D_SETC = 0x00000003; // Conditional set integer register
116 enum D_TEST = 0x00000004; // Used to test data (CMP, TEST, AND...)
117 enum D_STRING = 0x00000005; // String command with REPxxx prefix
118 enum D_JMP = 0x00000006; // Unconditional near jump
119 enum D_JMPFAR = 0x00000007; // Unconditional far jump
120 enum D_JMC = 0x00000008; // Conditional jump on flags
121 enum D_JMCX = 0x00000009; // Conditional jump on (E)CX (and flags)
122 enum D_PUSH = 0x0000000A; // PUSH exactly 1 (d)word of data
123 enum D_POP = 0x0000000B; // POP exactly 1 (d)word of data
124 enum D_CALL = 0x0000000C; // Plain near call
125 enum D_CALLFAR = 0x0000000D; // Far call
126 enum D_INT = 0x0000000E; // Interrupt
127 enum D_RET = 0x0000000F; // Plain near return from call
128 enum D_RETFAR = 0x00000010; // Far return or IRET
129 enum D_FPU = 0x00000011; // FPU command
130 enum D_MMX = 0x00000012; // MMX instruction, incl. SSE extensions
131 enum D_3DNOW = 0x00000013; // 3DNow! instruction
132 enum D_SSE = 0x00000014; // SSE instruction
133 enum D_IO = 0x00000015; // Accesses I/O ports
134 enum D_SYS = 0x00000016; // Legal but useful in system code only
135 enum D_PRIVILEGED = 0x00000017; // Privileged (non-Ring3) command
136 enum D_AVX = 0x00000018; // AVX instruction
137 enum D_XOP = 0x00000019; // AMD instruction with XOP prefix
138 enum D_DATA = 0x0000001C; // Data recognized by Analyser
139 enum D_PSEUDO = 0x0000001D; // Pseudocommand, for search models only
140 enum D_PREFIX = 0x0000001E; // Standalone prefix
141 enum D_BAD = 0x0000001F; // Bad or unrecognized command
142 // Additional parts of the command.
143 enum D_SIZE01 = 0x00000020; // Bit 0x01 in last cmd is data size
144 enum D_POSTBYTE = 0x00000040; // Command continues in postbyte
145 // For string commands, either long or short form can be selected.
146 enum D_LONGFORM = 0x00000080; // Long form of string command
147 // Decoding of some commands depends on data or address size.
148 enum D_SIZEMASK = 0x00000F00; // Mask for data/address size dependence
149 enum D_DATA16 = 0x00000100; // Requires 16-bit data size
150 enum D_DATA32 = 0x00000200; // Requires 32-bit data size
151 enum D_ADDR16 = 0x00000400; // Requires 16-bit address size
152 enum D_ADDR32 = 0x00000800; // Requires 32-bit address size
153 // Prefixes that command may, must or must not possess.
154 enum D_MUSTMASK = 0x0000F000; // Mask for fixed set of prefixes
155 enum D_NOMUST = 0x00000000; // No obligatory prefixes (default)
156 enum D_MUST66 = 0x00001000; // (SSE,AVX) Requires 66, no F2 or F3
157 enum D_MUSTF2 = 0x00002000; // (SSE,AVX) Requires F2, no 66 or F3
158 enum D_MUSTF3 = 0x00003000; // (SSE,AVX) Requires F3, no 66 or F2
159 enum D_MUSTNONE = 0x00004000; // (MMX,SSE,AVX) Requires no 66, F2, F3
160 enum D_NEEDF2 = 0x00005000; // (SSE,AVX) Requires F2, no F3
161 enum D_NEEDF3 = 0x00006000; // (SSE,AVX) Requires F3, no F2
162 enum D_NOREP = 0x00007000; // Must not include F2 or F3
163 enum D_MUSTREP = 0x00008000; // Must include F3 (REP)
164 enum D_MUSTREPE = 0x00009000; // Must include F3 (REPE)
165 enum D_MUSTREPNE = 0x0000A000; // Must include F2 (REPNE)
166 enum D_LOCKABLE = 0x00010000; // Allows for F0 (LOCK, memory only)
167 enum D_BHINT = 0x00020000; // Allows for branch hints (2E, 3E)
168 // Decoding of some commands with ModRM-SIB depends whether register or memory.
169 enum D_MEMORY = 0x00040000; // Mod field must indicate memory
170 enum D_REGISTER = 0x00080000; // Mod field must indicate register
171 // Side effects caused by command.
172 enum D_FLAGMASK = 0x00700000; // Mask to extract modified flags
173 enum D_NOFLAGS = 0x00000000; // Flags S,Z,P,O,C remain unchanged
174 enum D_ALLFLAGS = 0x00100000; // Modifies flags S,Z,P,O,C
175 enum D_FLAGZ = 0x00200000; // Modifies flag Z only
176 enum D_FLAGC = 0x00300000; // Modifies flag C only
177 enum D_FLAGSCO = 0x00400000; // Modifies flag C and O only
178 enum D_FLAGD = 0x00500000; // Modifies flag D only
179 enum D_FLAGSZPC = 0x00600000; // Modifies flags Z, P and C only (FPU)
180 enum D_NOCFLAG = 0x00700000; // S,Z,P,O modified, C unaffected
181 enum D_FPUMASK = 0x01800000; // Mask for effects on FPU stack
182 enum D_FPUSAME = 0x00000000; // Doesn't rotate FPU stack (default)
183 enum D_FPUPOP = 0x00800000; // Pops FPU stack
184 enum D_FPUPOP2 = 0x01000000; // Pops FPU stack twice
185 enum D_FPUPUSH = 0x01800000; // Pushes FPU stack
186 enum D_CHGESP = 0x02000000; // Command indirectly modifies ESP
187 // Command features.
188 enum D_HLADIR = 0x04000000; // Nonstandard order of operands in HLA
189 enum D_WILDCARD = 0x08000000; // Mnemonics contains W/D wildcard ('*')
190 enum D_COND = 0x10000000; // Conditional (action depends on flags)
191 enum D_USESCARRY = 0x20000000; // Uses Carry flag
192 enum D_USEMASK = 0xC0000000; // Mask to detect unusual commands
193 enum D_RARE = 0x40000000; // Rare or obsolete in Win32 apps
194 enum D_SUSPICIOUS = 0x80000000; // Suspicious command
195 enum D_UNDOC = 0xC0000000; // Undocumented command
196
197 // Extension of D_xxx.
198 enum DX_ZEROMASK = 0x00000003; // How to decode FLAGS.Z flag
199 enum DX_JE = 0x00000001; // JE, JNE instead of JZ, JNZ
200 enum DX_JZ = 0x00000002; // JZ, JNZ instead of JE, JNE
201 enum DX_CARRYMASK = 0x0000000C; // How to decode FLAGS.C flag
202 enum DX_JB = 0x00000004; // JAE, JB instead of JC, JNC
203 enum DX_JC = 0x00000008; // JC, JNC instead of JAE, JB
204 enum DX_RETN = 0x00000010; // The mnemonics is RETN
205 enum DX_VEX = 0x00000100; // Requires VEX prefix
206 enum DX_VLMASK = 0x00000600; // Mask to extract VEX operand length
207 enum DX_LSHORT = 0x00000000; // 128-bit only
208 enum DX_LBOTH = 0x00000200; // Both 128- and 256-bit versions
209 enum DX_LLONG = 0x00000400; // 256-bit only
210 enum DX_IGNOREL = 0x00000600; // Ignore VEX.L
211 enum DX_NOVREG = 0x00000800; // VEX.vvvv must be set to all 1's
212 enum DX_VWMASK = 0x00003000; // Mask to extract VEX.W
213 enum DX_W0 = 0x00001000; // VEX.W must be 0
214 enum DX_W1 = 0x00002000; // VEX.W must be 1
215 enum DX_LEADMASK = 0x00070000; // Mask to extract leading opcode bytes
216 enum DX_LEAD0F = 0x00000000; // Implied 0F leading byte (default)
217 enum DX_LEAD38 = 0x00010000; // Implied 0F 38 leading opcode bytes
218 enum DX_LEAD3A = 0x00020000; // Implied 0F 3A leading opcode bytes
219 enum DX_WONKYTRAP = 0x00800000; // Don't single-step this command
220 enum DX_TYPEMASK = 0xFF000000; // Precised command type mask
221 enum DX_ADD = 0x01000000; // The command is integer ADD
222 enum DX_SUB = 0x02000000; // The command is integer SUB
223 enum DX_LEA = 0x03000000; // The command is LEA
224 enum DX_NOP = 0x04000000; // The command is NOP
225
226 //enum DX_LVEX = (DX_VEX|DX_LBOTH);
227 //enum DX_GVEX = (DX_VEX|DX_LLONG);
228
229 // Type of operand, only one is allowed. Size of SSE operands is given for the
230 // case of 128-bit operations and usually doubles for 256-bit AVX commands. If
231 // B_NOVEXSIZE is set, memory may double but XMM registers are not promoted to
232 // YMM.
233 enum B_ARGMASK = 0x000000FF; // Mask to extract type of argument
234 enum B_NONE = 0x00000000; // Operand absent
235 enum B_AL = 0x00000001; // Register AL
236 enum B_AH = 0x00000002; // Register AH
237 enum B_AX = 0x00000003; // Register AX
238 enum B_CL = 0x00000004; // Register CL
239 enum B_CX = 0x00000005; // Register CX
240 enum B_DX = 0x00000006; // Register DX
241 enum B_DXPORT = 0x00000007; // Register DX as I/O port address
242 enum B_EAX = 0x00000008; // Register EAX
243 enum B_EBX = 0x00000009; // Register EBX
244 enum B_ECX = 0x0000000A; // Register ECX
245 enum B_EDX = 0x0000000B; // Register EDX
246 enum B_ACC = 0x0000000C; // Accumulator (AL/AX/EAX)
247 enum B_STRCNT = 0x0000000D; // Register CX or ECX as REPxx counter
248 enum B_DXEDX = 0x0000000E; // Register DX or EDX in DIV/MUL
249 enum B_BPEBP = 0x0000000F; // Register BP or EBP in ENTER/LEAVE
250 enum B_REG = 0x00000010; // 8/16/32-bit register in Reg
251 enum B_REG16 = 0x00000011; // 16-bit register in Reg
252 enum B_REG32 = 0x00000012; // 32-bit register in Reg
253 enum B_REGCMD = 0x00000013; // 16/32-bit register in last cmd byte
254 enum B_REGCMD8 = 0x00000014; // 8-bit register in last cmd byte
255 enum B_ANYREG = 0x00000015; // Reg field is unused, any allowed
256 enum B_INT = 0x00000016; // 8/16/32-bit register/memory in ModRM
257 enum B_INT8 = 0x00000017; // 8-bit register/memory in ModRM
258 enum B_INT16 = 0x00000018; // 16-bit register/memory in ModRM
259 enum B_INT32 = 0x00000019; // 32-bit register/memory in ModRM
260 enum B_INT1632 = 0x0000001A; // 16/32-bit register/memory in ModRM
261 enum B_INT64 = 0x0000001B; // 64-bit integer in ModRM, memory only
262 enum B_INT128 = 0x0000001C; // 128-bit integer in ModRM, memory only
263 enum B_IMMINT = 0x0000001D; // 8/16/32-bit int at immediate addr
264 enum B_INTPAIR = 0x0000001E; // Two signed 16/32 in ModRM, memory only
265 enum B_SEGOFFS = 0x0000001F; // 16:16/16:32 absolute address in memory
266 enum B_STRDEST = 0x00000020; // 8/16/32-bit string dest, [ES:(E)DI]
267 enum B_STRDEST8 = 0x00000021; // 8-bit string destination, [ES:(E)DI]
268 enum B_STRSRC = 0x00000022; // 8/16/32-bit string source, [(E)SI]
269 enum B_STRSRC8 = 0x00000023; // 8-bit string source, [(E)SI]
270 enum B_XLATMEM = 0x00000024; // 8-bit memory in XLAT, [(E)BX+AL]
271 enum B_EAXMEM = 0x00000025; // Reference to memory addressed by [EAX]
272 enum B_LONGDATA = 0x00000026; // Long data in ModRM, mem only
273 enum B_ANYMEM = 0x00000027; // Reference to memory, data unimportant
274 enum B_STKTOP = 0x00000028; // 16/32-bit int top of stack
275 enum B_STKTOPFAR = 0x00000029; // Top of stack (16:16/16:32 far addr)
276 enum B_STKTOPEFL = 0x0000002A; // 16/32-bit flags on top of stack
277 enum B_STKTOPA = 0x0000002B; // 16/32-bit top of stack all registers
278 enum B_PUSH = 0x0000002C; // 16/32-bit int push to stack
279 enum B_PUSHRET = 0x0000002D; // 16/32-bit push of return address
280 enum B_PUSHRETF = 0x0000002E; // 16:16/16:32-bit push of far retaddr
281 enum B_PUSHA = 0x0000002F; // 16/32-bit push all registers
282 enum B_EBPMEM = 0x00000030; // 16/32-bit int at [EBP]
283 enum B_SEG = 0x00000031; // Segment register in Reg
284 enum B_SEGNOCS = 0x00000032; // Segment register in Reg, but not CS
285 enum B_SEGCS = 0x00000033; // Segment register CS
286 enum B_SEGDS = 0x00000034; // Segment register DS
287 enum B_SEGES = 0x00000035; // Segment register ES
288 enum B_SEGFS = 0x00000036; // Segment register FS
289 enum B_SEGGS = 0x00000037; // Segment register GS
290 enum B_SEGSS = 0x00000038; // Segment register SS
291 enum B_ST = 0x00000039; // 80-bit FPU register in last cmd byte
292 enum B_ST0 = 0x0000003A; // 80-bit FPU register ST0
293 enum B_ST1 = 0x0000003B; // 80-bit FPU register ST1
294 enum B_FLOAT32 = 0x0000003C; // 32-bit float in ModRM, memory only
295 enum B_FLOAT64 = 0x0000003D; // 64-bit float in ModRM, memory only
296 enum B_FLOAT80 = 0x0000003E; // 80-bit float in ModRM, memory only
297 enum B_BCD = 0x0000003F; // 80-bit BCD in ModRM, memory only
298 enum B_MREG8x8 = 0x00000040; // MMX register as 8 8-bit integers
299 enum B_MMX8x8 = 0x00000041; // MMX reg/memory as 8 8-bit integers
300 enum B_MMX8x8DI = 0x00000042; // MMX 8 8-bit integers at [DS:(E)DI]
301 enum B_MREG16x4 = 0x00000043; // MMX register as 4 16-bit integers
302 enum B_MMX16x4 = 0x00000044; // MMX reg/memory as 4 16-bit integers
303 enum B_MREG32x2 = 0x00000045; // MMX register as 2 32-bit integers
304 enum B_MMX32x2 = 0x00000046; // MMX reg/memory as 2 32-bit integers
305 enum B_MREG64 = 0x00000047; // MMX register as 1 64-bit integer
306 enum B_MMX64 = 0x00000048; // MMX reg/memory as 1 64-bit integer
307 enum B_3DREG = 0x00000049; // 3DNow! register as 2 32-bit floats
308 enum B_3DNOW = 0x0000004A; // 3DNow! reg/memory as 2 32-bit floats
309 enum B_XMM0I32x4 = 0x0000004B; // XMM0 as 4 32-bit integers
310 enum B_XMM0I64x2 = 0x0000004C; // XMM0 as 2 64-bit integers
311 enum B_XMM0I8x16 = 0x0000004D; // XMM0 as 16 8-bit integers
312 enum B_SREGF32x4 = 0x0000004E; // SSE register as 4 32-bit floats
313 enum B_SREGF32L = 0x0000004F; // Low 32-bit float in SSE register
314 enum B_SREGF32x2L = 0x00000050; // Low 2 32-bit floats in SSE register
315 enum B_SSEF32x4 = 0x00000051; // SSE reg/memory as 4 32-bit floats
316 enum B_SSEF32L = 0x00000052; // Low 32-bit float in SSE reg/memory
317 enum B_SSEF32x2L = 0x00000053; // Low 2 32-bit floats in SSE reg/memory
318 enum B_SREGF64x2 = 0x00000054; // SSE register as 2 64-bit floats
319 enum B_SREGF64L = 0x00000055; // Low 64-bit float in SSE register
320 enum B_SSEF64x2 = 0x00000056; // SSE reg/memory as 2 64-bit floats
321 enum B_SSEF64L = 0x00000057; // Low 64-bit float in SSE reg/memory
322 enum B_SREGI8x16 = 0x00000058; // SSE register as 16 8-bit sigints
323 enum B_SSEI8x16 = 0x00000059; // SSE reg/memory as 16 8-bit sigints
324 enum B_SSEI8x16DI = 0x0000005A; // SSE 16 8-bit sigints at [DS:(E)DI]
325 enum B_SSEI8x8L = 0x0000005B; // Low 8 8-bit ints in SSE reg/memory
326 enum B_SSEI8x4L = 0x0000005C; // Low 4 8-bit ints in SSE reg/memory
327 enum B_SSEI8x2L = 0x0000005D; // Low 2 8-bit ints in SSE reg/memory
328 enum B_SREGI16x8 = 0x0000005E; // SSE register as 8 16-bit sigints
329 enum B_SSEI16x8 = 0x0000005F; // SSE reg/memory as 8 16-bit sigints
330 enum B_SSEI16x4L = 0x00000060; // Low 4 16-bit ints in SSE reg/memory
331 enum B_SSEI16x2L = 0x00000061; // Low 2 16-bit ints in SSE reg/memory
332 enum B_SREGI32x4 = 0x00000062; // SSE register as 4 32-bit sigints
333 enum B_SREGI32L = 0x00000063; // Low 32-bit sigint in SSE register
334 enum B_SREGI32x2L = 0x00000064; // Low 2 32-bit sigints in SSE register
335 enum B_SSEI32x4 = 0x00000065; // SSE reg/memory as 4 32-bit sigints
336 enum B_SSEI32x2L = 0x00000066; // Low 2 32-bit sigints in SSE reg/memory
337 enum B_SREGI64x2 = 0x00000067; // SSE register as 2 64-bit sigints
338 enum B_SSEI64x2 = 0x00000068; // SSE reg/memory as 2 64-bit sigints
339 enum B_SREGI64L = 0x00000069; // Low 64-bit sigint in SSE register
340 enum B_EFL = 0x0000006A; // Flags register EFL
341 enum B_FLAGS8 = 0x0000006B; // Flags (low byte)
342 enum B_OFFSET = 0x0000006C; // 16/32 const offset from next command
343 enum B_BYTEOFFS = 0x0000006D; // 8-bit sxt const offset from next cmd
344 enum B_FARCONST = 0x0000006E; // 16:16/16:32 absolute address constant
345 enum B_DESCR = 0x0000006F; // 16:32 descriptor in ModRM
346 enum B_1 = 0x00000070; // Immediate constant 1
347 enum B_CONST8 = 0x00000071; // Immediate 8-bit constant
348 enum B_CONST8_2 = 0x00000072; // Immediate 8-bit const, second in cmd
349 enum B_CONST16 = 0x00000073; // Immediate 16-bit constant
350 enum B_CONST = 0x00000074; // Immediate 8/16/32-bit constant
351 enum B_CONSTL = 0x00000075; // Immediate 16/32-bit constant
352 enum B_SXTCONST = 0x00000076; // Immediate 8-bit sign-extended to size
353 enum B_CR = 0x00000077; // Control register in Reg
354 enum B_CR0 = 0x00000078; // Control register CR0
355 enum B_DR = 0x00000079; // Debug register in Reg
356 enum B_FST = 0x0000007A; // FPU status register
357 enum B_FCW = 0x0000007B; // FPU control register
358 enum B_MXCSR = 0x0000007C; // SSE media control and status register
359 enum B_SVEXF32x4 = 0x0000007D; // SSE reg in VEX as 4 32-bit floats
360 enum B_SVEXF32L = 0x0000007E; // Low 32-bit float in SSE in VEX
361 enum B_SVEXF64x2 = 0x0000007F; // SSE reg in VEX as 2 64-bit floats
362 enum B_SVEXF64L = 0x00000080; // Low 64-bit float in SSE in VEX
363 enum B_SVEXI8x16 = 0x00000081; // SSE reg in VEX as 16 8-bit sigints
364 enum B_SVEXI16x8 = 0x00000082; // SSE reg in VEX as 8 16-bit sigints
365 enum B_SVEXI32x4 = 0x00000083; // SSE reg in VEX as 4 32-bit sigints
366 enum B_SVEXI64x2 = 0x00000084; // SSE reg in VEX as 2 64-bit sigints
367 enum B_SIMMI8x16 = 0x00000085; // SSE reg in immediate 8-bit constant
368 // Type modifiers, used for interpretation of contents, only one is allowed.
369 enum B_MODMASK = 0x000F0000; // Mask to extract type modifier
370 enum B_NONSPEC = 0x00000000; // Non-specific operand
371 enum B_UNSIGNED = 0x00010000; // Decode as unsigned decimal
372 enum B_SIGNED = 0x00020000; // Decode as signed decimal
373 enum B_BINARY = 0x00030000; // Decode as binary (full hex) data
374 enum B_BITCNT = 0x00040000; // Bit count
375 enum B_SHIFTCNT = 0x00050000; // Shift count
376 enum B_COUNT = 0x00060000; // General-purpose count
377 enum B_NOADDR = 0x00070000; // Not an address
378 enum B_JMPCALL = 0x00080000; // Near jump/call/return destination
379 enum B_JMPCALLFAR = 0x00090000; // Far jump/call/return destination
380 enum B_STACKINC = 0x000A0000; // Unsigned stack increment/decrement
381 enum B_PORT = 0x000B0000; // I/O port
382 enum B_ADDR = 0x000F0000; // Used internally
383 // Validity markers.
384 enum B_MEMORY = 0x00100000; // Memory only, reg version different
385 enum B_REGISTER = 0x00200000; // Register only, mem version different
386 enum B_MEMONLY = 0x00400000; // Warn if operand in register
387 enum B_REGONLY = 0x00800000; // Warn if operand in memory
388 enum B_32BITONLY = 0x01000000; // Warn if 16-bit operand
389 enum B_NOESP = 0x02000000; // ESP is not allowed
390 // Miscellaneous options.
391 enum B_NOVEXSIZE = 0x04000000; // Always 128-bit SSE in 256-bit AVX
392 enum B_SHOWSIZE = 0x08000000; // Always show argument size in disasm
393 enum B_CHG = 0x10000000; // Changed, old contents is not used
394 enum B_UPD = 0x20000000; // Modified using old contents
395 enum B_PSEUDO = 0x40000000; // Pseoudooperand, not in assembler cmd
396 enum B_NOSEG = 0x80000000; // Don't add offset of selector
397
398 // Location of operand, only one bit is allowed.
399 enum OP_SOMEREG = 0x000000FF; // Mask for any kind of register
400 enum OP_REGISTER = 0x00000001; // Operand is a general-purpose register
401 enum OP_SEGREG = 0x00000002; // Operand is a segment register
402 enum OP_FPUREG = 0x00000004; // Operand is a FPU register
403 enum OP_MMXREG = 0x00000008; // Operand is a MMX register
404 enum OP_3DNOWREG = 0x00000010; // Operand is a 3DNow! register
405 enum OP_SSEREG = 0x00000020; // Operand is a SSE register
406 enum OP_CREG = 0x00000040; // Operand is a control register
407 enum OP_DREG = 0x00000080; // Operand is a debug register
408 enum OP_MEMORY = 0x00000100; // Operand is in memory
409 enum OP_CONST = 0x00000200; // Operand is an immediate constant
410 // Additional operand properties.
411 enum OP_PORT = 0x00000400; // Used to access I/O port
412 enum OP_OTHERREG = 0x00000800; // Special register like EFL or MXCSR
413 enum OP_INVALID = 0x00001000; // Invalid operand, like reg in mem-only
414 enum OP_PSEUDO = 0x00002000; // Pseudooperand (not in mnenonics)
415 enum OP_MOD = 0x00004000; // Command may change/update operand
416 enum OP_MODREG = 0x00008000; // Memory, but modifies reg (POP,MOVSD)
417 enum OP_IMPORT = 0x00020000; // Value imported from different module
418 enum OP_SELECTOR = 0x00040000; // Includes immediate selector
419 // Additional properties of memory address.
420 enum OP_INDEXED = 0x00080000; // Memory address contains registers
421 enum OP_OPCONST = 0x00100000; // Memory address contains constant
422 enum OP_ADDR16 = 0x00200000; // 16-bit memory address
423 enum OP_ADDR32 = 0x00400000; // Explicit 32-bit memory address
424
425 enum DAMODE_MASM = 0; // MASM assembling/disassembling style
426 enum DAMODE_IDEAL = 1; // IDEAL assembling/disassembling style
427 enum DAMODE_HLA = 2; // HLA assembling/disassembling style
428 enum DAMODE_ATT = 3; // AT&T disassembling style
429
430 enum NUM_STYLE = 0x0003; // Mask to extract hex style
431 enum NUM_STD = 0x0000; // 123, 12345678h, 0ABCD1234h
432 enum NUM_X = 0x0001; // 123, 0x12345678, 0xABCD1234
433 enum NUM_OLLY = 0x0002; // 123., 12345678, 0ABCD1234
434 enum NUM_LONG = 0x0010; // 00001234h instead of 1234h
435 enum NUM_DECIMAL = 0x0020; // 123 instead of 7Bh if under DECLIMIT
436
437 // Disassembling options.
438 enum DA_TEXT = 0x00000001; // Decode command to text and comment
439 enum DA_HILITE = 0x00000002; // Use syntax highlighting
440 enum DA_JZ = 0x00000004; // JZ, JNZ instead of JE, JNE
441 enum DA_JC = 0x00000008; // JC, JNC instead of JAE, JB
442 enum DA_DUMP = 0x00000020; // Dump command to hexadecimal text
443 enum DA_PSEUDO = 0x00000400; // List pseudooperands
444
445 // Disassembling errors.
446 enum DAE_NOERR = 0x00000000; // No errors
447 enum DAE_BADCMD = 0x00000001; // Unrecognized command
448 enum DAE_CROSS = 0x00000002; // Command crosses end of memory block
449 enum DAE_MEMORY = 0x00000004; // Register where only memory allowed
450 enum DAE_REGISTER = 0x00000008; // Memory where only register allowed
451 enum DAE_LOCK = 0x00000010; // LOCK prefix is not allowed
452 enum DAE_BADSEG = 0x00000020; // Invalid segment register
453 enum DAE_SAMEPREF = 0x00000040; // Two prefixes from the same group
454 enum DAE_MANYPREF = 0x00000080; // More than 4 prefixes
455 enum DAE_BADCR = 0x00000100; // Invalid CR register
456 enum DAE_INTERN = 0x00000200; // Internal error
457
458 // Disassembling warnings.
459 enum DAW_NOWARN = 0x00000000; // No warnings
460 enum DAW_DATASIZE = 0x00000001; // Superfluous data size prefix
461 enum DAW_ADDRSIZE = 0x00000002; // Superfluous address size prefix
462 enum DAW_SEGPREFIX = 0x00000004; // Superfluous segment override prefix
463 enum DAW_REPPREFIX = 0x00000008; // Superfluous REPxx prefix
464 enum DAW_DEFSEG = 0x00000010; // Segment prefix coincides with default
465 enum DAW_JMP16 = 0x00000020; // 16-bit jump, call or return
466 enum DAW_FARADDR = 0x00000040; // Far jump or call
467 enum DAW_SEGMOD = 0x00000080; // Modifies segment register
468 enum DAW_PRIV = 0x00000100; // Privileged command
469 enum DAW_IO = 0x00000200; // I/O command
470 enum DAW_SHIFT = 0x00000400; // Shift out of range 1..31
471 enum DAW_LOCK = 0x00000800; // Command with valid LOCK prefix
472 enum DAW_STACK = 0x00001000; // Unaligned stack operation
473 enum DAW_NOESP = 0x00002000; // Suspicious use of stack pointer
474 enum DAW_RARE = 0x00004000; // Rare, seldom used command
475 enum DAW_NONCLASS = 0x00008000; // Non-standard or non-documented code
476 enum DAW_INTERRUPT = 0x00010000; // Interrupt command
477
478 // List of prefixes.
479 enum PF_SEGMASK = 0x0000003F; // Mask for segment override prefixes
480 enum PF_ES = 0x00000001; // 0x26, ES segment override
481 enum PF_CS = 0x00000002; // 0x2E, CS segment override
482 enum PF_SS = 0x00000004; // 0x36, SS segment override
483 enum PF_DS = 0x00000008; // 0x3E, DS segment override
484 enum PF_FS = 0x00000010; // 0x64, FS segment override
485 enum PF_GS = 0x00000020; // 0x65, GS segment override
486 enum PF_DSIZE = 0x00000040; // 0x66, data size override
487 enum PF_ASIZE = 0x00000080; // 0x67, address size override
488 enum PF_LOCK = 0x00000100; // 0xF0, bus lock
489 enum PF_REPMASK = 0x00000600; // Mask for repeat prefixes
490 enum PF_REPNE = 0x00000200; // 0xF2, REPNE prefix
491 enum PF_REP = 0x00000400; // 0xF3, REP/REPE prefix
492 enum PF_BYTE = 0x00000800; // Size bit in command, used in cmdexec
493 enum PF_MUSTMASK = D_MUSTMASK; // Necessary prefixes, used in t_asmmod
494 enum PF_VEX2 = 0x00010000; // 2-byte VEX prefix
495 enum PF_VEX3 = 0x00020000; // 3-byte VEX prefix
496 // Useful shortcuts.
497 enum PF_66 = PF_DSIZE; // Alternative names for SSE prefixes
498 enum PF_F2 = PF_REPNE;
499 enum PF_F3 = PF_REP;
500 enum PF_HINT = (PF_CS|PF_DS); // Alternative names for branch hints
501 enum PF_NOTTAKEN = PF_CS;
502 enum PF_TAKEN = PF_DS;
503 enum PF_VEX = (PF_VEX2|PF_VEX3);
504
505 // Disassembler configuration
506 struct DAConfig {
507 uint disasmmode = DAMODE_IDEAL; // Main style, one of DAMODE_xxx
508 uint memmode = NUM_X|NUM_DECIMAL; // Constant part of address, NUM_xxx
509 uint jmpmode = NUM_X|NUM_LONG; // Jump/call destination, NUM_xxx
510 uint binconstmode = NUM_X|NUM_LONG; // Binary constants, NUM_xxx
511 uint constmode = NUM_X|NUM_DECIMAL; // Numeric constants, NUM_xxx
512 bool lowercase = true; // Force lowercase display
513 bool tabarguments = false; // Tab between mnemonic and arguments
514 bool extraspace = false; // Extra space between arguments
515 bool useretform = false; // Use RET instead of RETN
516 bool shortstringcmds = true; // Use short form of string commands
517 bool putdefseg = false; // Display default segments in listing
518 bool showmemsize = false; // Always show memory size
519 bool shownear = false; // Show NEAR modifiers
520 bool ssesizemode = false; // How to decode size of SSE operands
521 bool jumphintmode = false; // How to decode jump hints (true: prefix with '+' or '-')
522 ubyte sizesens = 0; // How to decode size-sensitive mnemonics (0,1,2)
523 bool simplifiedst = false; // How to decode top of FPU stack
524 bool hiliteoperands = true; // Highlight operands
525 }
526
527 // Description of disassembled operand
528 struct AsmOperand {
529 // Description of operand.
530 uint features; // Operand features, set of OP_xxx
531 uint arg; // Operand type, set of B_xxx
532 uint opsize; // Total size of data, bytes
533 int granularity; // Size of element (opsize exc. MMX/SSE)
534 int reg; // REG_xxx (also ESP in POP) or REG_UNDEF
535 uint uses; // List of used regs (not in address!)
536 uint modifies; // List of modified regs (not in addr!)
537 // Description of memory address.
538 int seg; // Selector (SEG_xxx)
539 ubyte[NREG] scale; // Scales of registers in memory address
540 uint aregs; // List of registers used in address
541 uint opconst; // Constant or const part of address
542 uint selector; // Immediate selector in far jump/call
543 // Textual decoding.
544 char[TEXTLEN] text; // Operand, decoded to text
545
546 @property inout(char)[] str () inout nothrow @trusted @nogc { foreach (immutable idx; 0..text.length) if (text.ptr[idx] == 0) return text[0..idx]; return text[]; }
547 }
548
549 // Note that used registers are those which contents is necessary to create
550 // result. Modified registers are those which value is changed. For example,
551 // command MOV EAX,[EBX+ECX] uses EBX and ECX and modifies EAX. Command
552 // ADD ESI,EDI uses ESI and EDI and modifies ESI.
553 // Disassembled command
554 struct DisasmData {
555 uint ip; // Address of first command byte
556 uint size; // Full length of command, bytes
557 uint cmdtype; // Type of command, D_xxx
558 uint exttype; // More features, set of DX_xxx
559 uint prefixes; // List of prefixes, set of PF_xxx
560 uint nprefix; // Number of prefixes, including SSE2
561 int memfixup; // Offset of first 4-byte fixup or -1
562 int immfixup; // Offset of second 4-byte fixup or -1
563 uint errors; // Set of DAE_xxx
564 uint warnings; // Set of DAW_xxx
565 uint uses; // List of used registers
566 uint modifies; // List of modified registers
567 uint memconst; // Constant in memory address or 0
568 uint stackinc; // Data size in ENTER/RETN/RETF
569 AsmOperand[NOPERAND] op; // Operands
570 char[TEXTLEN] dump; // Hex dump of the command
571 char[TEXTLEN] result; // Fully decoded command as text
572 char[TEXTLEN] mask; // Mask to highlight result
573 int masksize; // Length of mask corresponding to result
574
575 @property inout(char)[] dumpstr () inout nothrow @trusted @nogc { foreach (immutable idx; 0..dump.length) if (dump.ptr[idx] == 0) return dump[0..idx]; return dump[]; }
576 @property inout(char)[] resstr () inout nothrow @trusted @nogc { foreach (immutable idx; 0..result.length) if (result.ptr[idx] == 0) return result[0..idx]; return result[]; }
577 @property inout(char)[] maskstr () inout nothrow @trusted @nogc { return (masksize >= 0 && masksize < mask.length ? mask[0..masksize] : null); }
578 }
579
580
581 // ////////////////////////////////////////////////////////////////////////// //
582 private:
583 // Description of 80x86 command
584 public struct AsmInstrDsc {
585 string name; // Symbolic name for this command
586 uint cmdtype; // Command's features, set of D_xxx
587 uint exttype; // More features, set of DX_xxx
588 uint length; // Length of main code (before ModRM/SIB)
589 uint mask; // Mask for first 4 bytes of the command
590 uint code; // Compare masked bytes with this
591 ubyte postbyte; // Postbyte
592 uint[NOPERAND] arg; // Types of arguments, set of B_xxx
593 }
594
595
596 // '*' in name meads "size modifier" (like in "PUSHAD", for example)
597 public static immutable AsmInstrDsc[1388] asmInstrTable = [
598 AsmInstrDsc("PAUSE\0",D_SSE|D_MUSTF3,0,1,0x000000FF,0x00000090,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
599 AsmInstrDsc("NOP\0",D_CMD,DX_NOP,1,0x000000FF,0x00000090,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
600 AsmInstrDsc("NOP\0",D_CMD|D_UNDOC,DX_NOP,2,0x0000FFFF,0x0000190F,0x00,[B_INT,B_NONE,B_NONE,B_NONE]),
601 AsmInstrDsc("NOP\0",D_CMD|D_UNDOC,DX_NOP,2,0x0000FFFF,0x00001A0F,0x00,[B_INT,B_NONE,B_NONE,B_NONE]),
602 AsmInstrDsc("NOP\0",D_CMD|D_UNDOC,DX_NOP,2,0x0000FFFF,0x00001B0F,0x00,[B_INT,B_NONE,B_NONE,B_NONE]),
603 AsmInstrDsc("NOP\0",D_CMD|D_UNDOC,DX_NOP,2,0x0000FFFF,0x00001C0F,0x00,[B_INT,B_NONE,B_NONE,B_NONE]),
604 AsmInstrDsc("NOP\0",D_CMD|D_UNDOC,DX_NOP,2,0x0000FFFF,0x00001D0F,0x00,[B_INT,B_NONE,B_NONE,B_NONE]),
605 AsmInstrDsc("NOP\0",D_CMD|D_UNDOC,DX_NOP,2,0x0000FFFF,0x00001E0F,0x00,[B_INT,B_NONE,B_NONE,B_NONE]),
606 AsmInstrDsc("NOP\0",D_CMD,DX_NOP,2,0x0000FFFF,0x00001F0F,0x00,[B_INT,B_NONE,B_NONE,B_NONE]),
607 AsmInstrDsc("MONITOR\0",D_SYS|D_RARE,0,3,0x00FFFFFF,0x00C8010F,0x00,[B_EAXMEM|B_PSEUDO,B_ECX|B_BINARY|B_PSEUDO,B_EDX|B_BINARY|B_PSEUDO,B_NONE]),
608 AsmInstrDsc("MWAIT\0",D_SYS|D_RARE,0,3,0x00FFFFFF,0x00C9010F,0x00,[B_EAX|B_BINARY|B_PSEUDO,B_ECX|B_BINARY|B_PSEUDO,B_NONE,B_NONE]),
609 AsmInstrDsc("CLAC\0",D_SYS|D_RARE,0,3,0x00FFFFFF,0x00CA010F,0x00,[B_EAX|B_BINARY|B_PSEUDO,B_ECX|B_BINARY|B_PSEUDO,B_NONE,B_NONE]),
610 AsmInstrDsc("STAC\0",D_SYS|D_RARE,0,3,0x00FFFFFF,0x00CB010F,0x00,[B_EAX|B_BINARY|B_PSEUDO,B_ECX|B_BINARY|B_PSEUDO,B_NONE,B_NONE]),
611 AsmInstrDsc("AAA\0",D_CMD|D_ALLFLAGS|D_RARE,0,1,0x000000FF,0x00000037,0x00,[B_AL|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
612 AsmInstrDsc("AAD\0",D_CMD|D_ALLFLAGS|D_RARE,0,2,0x0000FFFF,0x00000AD5,0x00,[B_AX|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
613 AsmInstrDsc("AAD\0",D_CMD|D_ALLFLAGS|D_RARE,0,1,0x000000FF,0x000000D5,0x00,[B_AX|B_UPD|B_PSEUDO,B_CONST8|B_UNSIGNED,B_NONE,B_NONE]),
614 AsmInstrDsc("AAM\0",D_CMD|D_ALLFLAGS|D_RARE,0,2,0x0000FFFF,0x00000AD4,0x00,[B_AX|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
615 AsmInstrDsc("AAM\0",D_CMD|D_ALLFLAGS|D_RARE,0,1,0x000000FF,0x000000D4,0x00,[B_AX|B_UPD|B_PSEUDO,B_CONST8|B_UNSIGNED,B_NONE,B_NONE]),
616 AsmInstrDsc("AAS\0",D_CMD|D_ALLFLAGS|D_RARE,0,1,0x000000FF,0x0000003F,0x00,[B_AL|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
617 AsmInstrDsc("ADC\0",D_CMD|D_SIZE01|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000000FE,0x00000014,0x00,[B_ACC|B_UPD,B_CONST|B_NOADDR,B_NONE,B_NONE]),
618 AsmInstrDsc("ADC\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000038FE,0x00001080,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_CONST|B_NOADDR,B_NONE,B_NONE]),
619 AsmInstrDsc("ADC\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000038FE,0x00001082,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_SXTCONST,B_NONE,B_NONE]),
620 AsmInstrDsc("ADC\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000000FE,0x00000010,0x00,[B_INT|B_UPD,B_REG,B_NONE,B_NONE]),
621 AsmInstrDsc("ADC\0",D_CMD|D_SIZE01|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000000FE,0x00000012,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
622 AsmInstrDsc("ADD\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JB|DX_ADD,1,0x000000FE,0x00000004,0x00,[B_ACC|B_UPD,B_CONST,B_NONE,B_NONE]),
623 AsmInstrDsc("ADD\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JB|DX_ADD,1,0x000038FE,0x00000080,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_CONST,B_NONE,B_NONE]),
624 AsmInstrDsc("ADD\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JB|DX_ADD,1,0x000038FE,0x00000082,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_SXTCONST,B_NONE,B_NONE]),
625 AsmInstrDsc("ADD\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JB|DX_ADD,1,0x000000FE,0x00000000,0x00,[B_INT|B_UPD,B_REG,B_NONE,B_NONE]),
626 AsmInstrDsc("ADD\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JB|DX_ADD,1,0x000000FE,0x00000002,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
627 AsmInstrDsc("AND\0",D_TEST|D_SIZE01|D_ALLFLAGS,DX_JZ,1,0x000000FE,0x00000024,0x00,[B_ACC|B_BINARY|B_UPD,B_CONST|B_BINARY,B_NONE,B_NONE]),
628 AsmInstrDsc("AND\0",D_TEST|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ,1,0x000038FE,0x00002080,0x00,[B_INT|B_BINARY|B_SHOWSIZE|B_UPD,B_CONST|B_BINARY,B_NONE,B_NONE]),
629 AsmInstrDsc("AND\0",D_TEST|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ,1,0x000038FE,0x00002082,0x00,[B_INT|B_BINARY|B_SHOWSIZE|B_UPD,B_SXTCONST|B_BINARY,B_NONE,B_NONE]),
630 AsmInstrDsc("AND\0",D_TEST|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ,1,0x000000FE,0x00000020,0x00,[B_INT|B_BINARY|B_UPD,B_REG|B_BINARY,B_NONE,B_NONE]),
631 AsmInstrDsc("AND\0",D_TEST|D_SIZE01|D_ALLFLAGS,DX_JZ,1,0x000000FE,0x00000022,0x00,[B_REG|B_BINARY|B_UPD,B_INT|B_BINARY,B_NONE,B_NONE]),
632 AsmInstrDsc("ARPL\0",D_SYS|D_FLAGZ|D_RARE,0,1,0x000000FF,0x00000063,0x00,[B_INT16|B_UPD,B_REG16,B_NONE,B_NONE]),
633 AsmInstrDsc("BOUND\0",D_CMD|D_RARE,0,1,0x000000FF,0x00000062,0x00,[B_REG|B_SIGNED,B_INTPAIR|B_MEMONLY,B_NONE,B_NONE]),
634 AsmInstrDsc("BSF\0",D_CMD|D_ALLFLAGS,DX_JZ,2,0x0000FFFF,0x0000BC0F,0x00,[B_REG|B_CHG,B_INT|B_BINARY,B_NONE,B_NONE]),
635 AsmInstrDsc("BSR\0",D_CMD|D_NOREP|D_ALLFLAGS,DX_JZ,2,0x0000FFFF,0x0000BD0F,0x00,[B_REG|B_CHG,B_INT|B_BINARY,B_NONE,B_NONE]),
636 AsmInstrDsc("BSWAP\0",D_CMD,0,2,0x0000F8FF,0x0000C80F,0x00,[B_REGCMD|B_32BITONLY|B_NOESP|B_UPD,B_NONE,B_NONE,B_NONE]),
637 AsmInstrDsc("BT\0",D_TEST|D_ALLFLAGS,DX_JC,2,0x0000FFFF,0x0000A30F,0x00,[B_INT|B_BINARY,B_REG|B_BITCNT,B_NONE,B_NONE]),
638 AsmInstrDsc("BT\0",D_TEST|D_ALLFLAGS,DX_JC,2,0x0038FFFF,0x0020BA0F,0x00,[B_INT|B_BINARY|B_SHOWSIZE,B_CONST8|B_BITCNT,B_NONE,B_NONE]),
639 AsmInstrDsc("BTC\0",D_CMD|D_LOCKABLE|D_ALLFLAGS,DX_JC,2,0x0000FFFF,0x0000BB0F,0x00,[B_INT|B_BINARY|B_NOESP|B_UPD,B_REG|B_BITCNT,B_NONE,B_NONE]),
640 AsmInstrDsc("BTC\0",D_CMD|D_LOCKABLE|D_ALLFLAGS,DX_JC,2,0x0038FFFF,0x0038BA0F,0x00,[B_INT|B_BINARY|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_BITCNT,B_NONE,B_NONE]),
641 AsmInstrDsc("BTR\0",D_CMD|D_LOCKABLE|D_ALLFLAGS,DX_JC,2,0x0000FFFF,0x0000B30F,0x00,[B_INT|B_BINARY|B_NOESP|B_UPD,B_REG|B_BITCNT,B_NONE,B_NONE]),
642 AsmInstrDsc("BTR\0",D_CMD|D_LOCKABLE|D_ALLFLAGS,DX_JC,2,0x0038FFFF,0x0030BA0F,0x00,[B_INT|B_BINARY|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_BITCNT,B_NONE,B_NONE]),
643 AsmInstrDsc("BTS\0",D_CMD|D_LOCKABLE|D_ALLFLAGS,DX_JC,2,0x0000FFFF,0x0000AB0F,0x00,[B_INT|B_BINARY|B_NOESP|B_UPD,B_REG|B_BITCNT,B_NONE,B_NONE]),
644 AsmInstrDsc("BTS\0",D_CMD|D_LOCKABLE|D_ALLFLAGS,DX_JC,2,0x0038FFFF,0x0028BA0F,0x00,[B_INT|B_BINARY|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_BITCNT,B_NONE,B_NONE]),
645 AsmInstrDsc("CALL\0",D_CALL|D_CHGESP,0,1,0x000000FF,0x000000E8,0x00,[B_OFFSET|B_JMPCALL,B_PUSHRET|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
646 AsmInstrDsc("CALL\0",D_CALL|D_CHGESP,0,1,0x000038FF,0x000010FF,0x00,[B_INT|B_JMPCALL,B_PUSHRET|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
647 AsmInstrDsc("CALL\0",D_CALLFAR|D_CHGESP|D_RARE,0,1,0x000000FF,0x0000009A,0x00,[B_FARCONST|B_JMPCALLFAR,B_PUSHRETF|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
648 AsmInstrDsc("CALL\0",D_CALLFAR|D_CHGESP|D_RARE,0,1,0x000038FF,0x000018FF,0x00,[B_SEGOFFS|B_JMPCALLFAR|B_MEMONLY,B_PUSHRETF|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
649 AsmInstrDsc("CBW\0",D_CMD|D_DATA16,0,1,0x000000FF,0x00000098,0x00,[B_AX|B_UPD|B_PSEUDO,B_AL|B_PSEUDO,B_NONE,B_NONE]),
650 AsmInstrDsc("CBW\0",D_CMD|D_DATA16,0,1,0x000000FF,0x00000098,0x00,[B_AX|B_UPD|B_PSEUDO,B_AL,B_NONE,B_NONE]),
651 AsmInstrDsc("CDQ\0",D_CMD|D_DATA32,0,1,0x000000FF,0x00000099,0x00,[B_EDX|B_CHG|B_PSEUDO,B_EAX|B_PSEUDO,B_NONE,B_NONE]),
652 AsmInstrDsc("CDQ\0",D_CMD|D_DATA32,0,1,0x000000FF,0x00000099,0x00,[B_EDX|B_CHG|B_PSEUDO,B_EAX,B_NONE,B_NONE]),
653 AsmInstrDsc("CLC\0",D_CMD|D_FLAGC,0,1,0x000000FF,0x000000F8,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
654 AsmInstrDsc("CLD\0",D_CMD|D_FLAGD,0,1,0x000000FF,0x000000FC,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
655 AsmInstrDsc("CLFLUSH\0",D_CMD|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0038AE0F,0x00,[B_ANYMEM|B_MEMONLY,B_NONE,B_NONE,B_NONE]),
656 AsmInstrDsc("CLI\0",D_CMD|D_RARE,0,1,0x000000FF,0x000000FA,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
657 AsmInstrDsc("CLTS\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000060F,0x00,[B_CR0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
658 AsmInstrDsc("CMC\0",D_CMD|D_FLAGC,0,1,0x000000FF,0x000000F5,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
659 AsmInstrDsc("CMOVO\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x0000400F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
660 AsmInstrDsc("CMOVNO\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x0000410F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
661 AsmInstrDsc("CMOVB\0",D_MOVC|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000420F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
662 AsmInstrDsc("CMOVC\0",D_MOVC|D_COND|D_USESCARRY,DX_JC,2,0x0000FFFF,0x0000420F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
663 AsmInstrDsc("CMOVNAE\0",D_MOVC|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000420F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
664 AsmInstrDsc("CMOVAE\0",D_MOVC|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000430F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
665 AsmInstrDsc("CMOVNB\0",D_MOVC|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000430F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
666 AsmInstrDsc("CMOVNC\0",D_MOVC|D_COND|D_USESCARRY,DX_JC,2,0x0000FFFF,0x0000430F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
667 AsmInstrDsc("CMOVE\0",D_MOVC|D_COND,DX_JE,2,0x0000FFFF,0x0000440F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
668 AsmInstrDsc("CMOVZ\0",D_MOVC|D_COND,DX_JZ,2,0x0000FFFF,0x0000440F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
669 AsmInstrDsc("CMOVNE\0",D_MOVC|D_COND,DX_JE,2,0x0000FFFF,0x0000450F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
670 AsmInstrDsc("CMOVNZ\0",D_MOVC|D_COND,DX_JZ,2,0x0000FFFF,0x0000450F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
671 AsmInstrDsc("CMOVBE\0",D_MOVC|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000460F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
672 AsmInstrDsc("CMOVNA\0",D_MOVC|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000460F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
673 AsmInstrDsc("CMOVA\0",D_MOVC|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000470F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
674 AsmInstrDsc("CMOVNBE\0",D_MOVC|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000470F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
675 AsmInstrDsc("CMOVS\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x0000480F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
676 AsmInstrDsc("CMOVNS\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x0000490F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
677 AsmInstrDsc("CMOVPE\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004A0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
678 AsmInstrDsc("CMOVP\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004A0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
679 AsmInstrDsc("CMOVPO\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004B0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
680 AsmInstrDsc("CMOVNP\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004B0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
681 AsmInstrDsc("CMOVL\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004C0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
682 AsmInstrDsc("CMOVNGE\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004C0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
683 AsmInstrDsc("CMOVGE\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004D0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
684 AsmInstrDsc("CMOVNL\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004D0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
685 AsmInstrDsc("CMOVLE\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004E0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
686 AsmInstrDsc("CMOVNG\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004E0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
687 AsmInstrDsc("CMOVG\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004F0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
688 AsmInstrDsc("CMOVNLE\0",D_MOVC|D_COND,0,2,0x0000FFFF,0x00004F0F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
689 AsmInstrDsc("CMP\0",D_TEST|D_SIZE01|D_ALLFLAGS|D_HLADIR,DX_JE|DX_JB,1,0x000000FE,0x0000003C,0x00,[B_ACC,B_CONST,B_NONE,B_NONE]),
690 AsmInstrDsc("CMP\0",D_TEST|D_SIZE01|D_ALLFLAGS|D_HLADIR,DX_JE|DX_JB,1,0x000038FE,0x00003880,0x00,[B_INT|B_SHOWSIZE,B_CONST,B_NONE,B_NONE]),
691 AsmInstrDsc("CMP\0",D_TEST|D_SIZE01|D_ALLFLAGS|D_HLADIR,DX_JE|DX_JB,1,0x000038FE,0x00003882,0x00,[B_INT|B_SHOWSIZE,B_SXTCONST,B_NONE,B_NONE]),
692 AsmInstrDsc("CMP\0",D_TEST|D_SIZE01|D_ALLFLAGS|D_HLADIR,DX_JE|DX_JB,1,0x000000FE,0x00000038,0x00,[B_INT,B_REG,B_NONE,B_NONE]),
693 AsmInstrDsc("CMP\0",D_TEST|D_SIZE01|D_ALLFLAGS|D_HLADIR,DX_JE|DX_JB,1,0x000000FE,0x0000003A,0x00,[B_REG,B_INT,B_NONE,B_NONE]),
694 AsmInstrDsc("CMPXCHG\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS|D_HLADIR,DX_JE|DX_JB,2,0x0000FEFF,0x0000B00F,0x00,[B_INT|B_UPD,B_REG,B_ACC|B_UPD|B_PSEUDO,B_NONE]),
695 AsmInstrDsc("CMPXCHG8B\0",D_CMD|D_LOCKABLE|D_MEMORY|D_ALLFLAGS,DX_JE|DX_JB,2,0x0038FFFF,0x0008C70F,0x00,[B_INT64|B_MEMONLY|B_UPD,B_EAX|B_UPD|B_PSEUDO,B_EDX|B_UPD|B_PSEUDO,B_EBX|B_PSEUDO]),
696 AsmInstrDsc("CPUID\0",D_CMD,0,2,0x0000FFFF,0x0000A20F,0x00,[B_EAX|B_CHG|B_PSEUDO,B_EBX|B_CHG|B_PSEUDO,B_ECX|B_CHG|B_PSEUDO,B_EDX|B_CHG|B_PSEUDO]),
697 AsmInstrDsc("CWD\0",D_CMD|D_DATA16,0,1,0x000000FF,0x00000099,0x00,[B_DX|B_CHG|B_PSEUDO,B_AX|B_PSEUDO,B_NONE,B_NONE]),
698 AsmInstrDsc("CWD\0",D_CMD|D_DATA16,0,1,0x000000FF,0x00000099,0x00,[B_DX|B_CHG|B_PSEUDO,B_AX,B_NONE,B_NONE]),
699 AsmInstrDsc("CWDE\0",D_CMD|D_DATA32,0,1,0x000000FF,0x00000098,0x00,[B_EAX|B_UPD|B_PSEUDO,B_AX|B_PSEUDO,B_NONE,B_NONE]),
700 AsmInstrDsc("CWDE\0",D_CMD|D_DATA32,0,1,0x000000FF,0x00000098,0x00,[B_EAX|B_UPD|B_PSEUDO,B_AX,B_NONE,B_NONE]),
701 AsmInstrDsc("DAA\0",D_CMD|D_ALLFLAGS|D_USESCARRY|D_RARE,DX_JC,1,0x000000FF,0x00000027,0x00,[B_AL|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
702 AsmInstrDsc("DAS\0",D_CMD|D_ALLFLAGS|D_USESCARRY|D_RARE,DX_JC,1,0x000000FF,0x0000002F,0x00,[B_AL|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
703 AsmInstrDsc("DEC\0",D_CMD|D_SIZE01|D_LOCKABLE|D_NOCFLAG,DX_JZ,1,0x000038FE,0x000008FE,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_NONE,B_NONE,B_NONE]),
704 AsmInstrDsc("DEC\0",D_CMD|D_NOCFLAG,DX_JZ,1,0x000000F8,0x00000048,0x00,[B_REGCMD|B_UPD,B_NONE,B_NONE,B_NONE]),
705 AsmInstrDsc("DIV\0",D_CMD|D_ALLFLAGS,0,1,0x000038FF,0x000030F6,0x00,[B_INT8|B_SHOWSIZE,B_AX|B_UPD|B_PSEUDO,B_NONE,B_NONE]),
706 AsmInstrDsc("DIV\0",D_CMD|D_ALLFLAGS,0,1,0x000038FF,0x000030F7,0x00,[B_INT1632|B_UNSIGNED|B_NOESP|B_SHOWSIZE,B_DXEDX|B_UPD|B_PSEUDO,B_ACC|B_UPD|B_PSEUDO,B_NONE]),
707 AsmInstrDsc("EMMS\0",D_CMD,0,2,0x0000FFFF,0x0000770F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
708 AsmInstrDsc("ENTER\0",D_CMD|D_CHGESP,0,1,0x000000FF,0x000000C8,0x00,[B_CONST16|B_STACKINC,B_CONST8_2|B_UNSIGNED,B_PUSH|B_CHG|B_PSEUDO,B_BPEBP|B_CHG|B_PSEUDO]),
709 AsmInstrDsc("WAIT\0",D_CMD,0,1,0x000000FF,0x0000009B,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
710 AsmInstrDsc("FWAIT\0",D_CMD,0,1,0x000000FF,0x0000009B,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
711 AsmInstrDsc("HLT\0",D_PRIVILEGED|D_RARE,0,1,0x000000FF,0x000000F4,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
712 AsmInstrDsc("IDIV\0",D_CMD|D_ALLFLAGS,0,1,0x000038FF,0x000038F6,0x00,[B_INT8|B_SIGNED|B_SHOWSIZE,B_AX|B_UPD|B_PSEUDO,B_NONE,B_NONE]),
713 AsmInstrDsc("IDIV\0",D_CMD|D_ALLFLAGS,0,1,0x000038FF,0x000038F7,0x00,[B_INT1632|B_SIGNED|B_NOESP|B_SHOWSIZE,B_DXEDX|B_UPD|B_PSEUDO,B_ACC|B_UPD|B_PSEUDO,B_NONE]),
714 AsmInstrDsc("IMUL\0",D_CMD|D_ALLFLAGS,0,1,0x000038FF,0x000028F6,0x00,[B_AX|B_UPD|B_PSEUDO,B_INT8|B_SIGNED|B_SHOWSIZE,B_AL|B_SIGNED|B_PSEUDO,B_NONE]),
715 AsmInstrDsc("IMUL\0",D_CMD|D_ALLFLAGS,0,1,0x000038FF,0x000028F7,0x00,[B_DXEDX|B_CHG|B_PSEUDO,B_ACC|B_UPD|B_PSEUDO,B_INT1632|B_SIGNED|B_NOESP|B_SHOWSIZE,B_NONE]),
716 AsmInstrDsc("IMUL\0",D_CMD|D_ALLFLAGS,0,2,0x0000FFFF,0x0000AF0F,0x00,[B_REG|B_UPD,B_INT|B_NOESP,B_NONE,B_NONE]),
717 AsmInstrDsc("IMUL\0",D_CMD|D_ALLFLAGS,0,1,0x000000FF,0x0000006B,0x00,[B_REG|B_CHG,B_INT|B_NOESP,B_SXTCONST,B_NONE]),
718 AsmInstrDsc("IMUL\0",D_CMD|D_ALLFLAGS,0,1,0x000000FF,0x00000069,0x00,[B_REG|B_CHG,B_INT|B_NOESP,B_CONST|B_SIGNED,B_NONE]),
719 AsmInstrDsc("IN\0",D_IO|D_SIZE01|D_RARE,0,1,0x000000FE,0x000000E4,0x00,[B_ACC|B_CHG,B_CONST8|B_PORT,B_NONE,B_NONE]),
720 AsmInstrDsc("IN\0",D_IO|D_SIZE01|D_RARE,0,1,0x000000FE,0x000000EC,0x00,[B_ACC|B_CHG,B_DXPORT|B_PORT,B_NONE,B_NONE]),
721 AsmInstrDsc("INC\0",D_CMD|D_SIZE01|D_LOCKABLE|D_NOCFLAG,DX_JZ,1,0x000038FE,0x000000FE,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_NONE,B_NONE,B_NONE]),
722 AsmInstrDsc("INC\0",D_CMD|D_NOCFLAG,DX_JZ,1,0x000000F8,0x00000040,0x00,[B_REGCMD|B_UPD,B_NONE,B_NONE,B_NONE]),
723 AsmInstrDsc("INT\0",D_INT,0,1,0x000000FF,0x000000CD,0x00,[B_CONST8,B_NONE,B_NONE,B_NONE]),
724 AsmInstrDsc("INT3\0",D_INT|D_RARE,0,1,0x000000FF,0x000000CC,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
725 AsmInstrDsc("INTO\0",D_INT|D_RARE,0,1,0x000000FF,0x000000CE,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
726 AsmInstrDsc("INT1\0",D_INT|D_UNDOC,0,1,0x000000FF,0x000000F1,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
727 AsmInstrDsc("ICEBP\0",D_INT|D_UNDOC,0,1,0x000000FF,0x000000F1,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
728 AsmInstrDsc("INVD\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000080F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
729 AsmInstrDsc("INVLPG\0",D_PRIVILEGED|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0038010F,0x00,[B_ANYMEM|B_MEMONLY,B_NONE,B_NONE,B_NONE]),
730 AsmInstrDsc("IRET*\0",D_RETFAR|D_ALLFLAGS|D_CHGESP|D_WILDCARD|D_RARE,0,1,0x000000FF,0x000000CF,0x00,[B_STKTOPFAR|B_JMPCALLFAR|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
731 AsmInstrDsc("JO\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x00000070,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
732 AsmInstrDsc("JO\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x0000800F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
733 AsmInstrDsc("JNO\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x00000071,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
734 AsmInstrDsc("JNO\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x0000810F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
735 AsmInstrDsc("JB\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JB,1,0x000000FF,0x00000072,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
736 AsmInstrDsc("JC\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JC,1,0x000000FF,0x00000072,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
737 AsmInstrDsc("JNAE\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JB,1,0x000000FF,0x00000072,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
738 AsmInstrDsc("JB\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000820F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
739 AsmInstrDsc("JC\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JC,2,0x0000FFFF,0x0000820F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
740 AsmInstrDsc("JNAE\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000820F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
741 AsmInstrDsc("JAE\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JB,1,0x000000FF,0x00000073,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
742 AsmInstrDsc("JNB\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JB,1,0x000000FF,0x00000073,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
743 AsmInstrDsc("JNC\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JC,1,0x000000FF,0x00000073,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
744 AsmInstrDsc("JAE\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000830F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
745 AsmInstrDsc("JNB\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000830F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
746 AsmInstrDsc("JNC\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,DX_JC,2,0x0000FFFF,0x0000830F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
747 AsmInstrDsc("JE\0",D_JMC|D_BHINT|D_COND,DX_JE,1,0x000000FF,0x00000074,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
748 AsmInstrDsc("JZ\0",D_JMC|D_BHINT|D_COND,DX_JZ,1,0x000000FF,0x00000074,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
749 AsmInstrDsc("JE\0",D_JMC|D_BHINT|D_COND,DX_JE,2,0x0000FFFF,0x0000840F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
750 AsmInstrDsc("JZ\0",D_JMC|D_BHINT|D_COND,DX_JZ,2,0x0000FFFF,0x0000840F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
751 AsmInstrDsc("JNE\0",D_JMC|D_BHINT|D_COND,DX_JE,1,0x000000FF,0x00000075,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
752 AsmInstrDsc("JNZ\0",D_JMC|D_BHINT|D_COND,DX_JZ,1,0x000000FF,0x00000075,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
753 AsmInstrDsc("JNE\0",D_JMC|D_BHINT|D_COND,DX_JE,2,0x0000FFFF,0x0000850F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
754 AsmInstrDsc("JNZ\0",D_JMC|D_BHINT|D_COND,DX_JZ,2,0x0000FFFF,0x0000850F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
755 AsmInstrDsc("JBE\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,0,1,0x000000FF,0x00000076,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
756 AsmInstrDsc("JNA\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,0,1,0x000000FF,0x00000076,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
757 AsmInstrDsc("JBE\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000860F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
758 AsmInstrDsc("JNA\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000860F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
759 AsmInstrDsc("JA\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,0,1,0x000000FF,0x00000077,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
760 AsmInstrDsc("JNBE\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,0,1,0x000000FF,0x00000077,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
761 AsmInstrDsc("JA\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000870F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
762 AsmInstrDsc("JNBE\0",D_JMC|D_BHINT|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000870F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
763 AsmInstrDsc("JS\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x00000078,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
764 AsmInstrDsc("JS\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x0000880F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
765 AsmInstrDsc("JNS\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x00000079,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
766 AsmInstrDsc("JNS\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x0000890F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
767 AsmInstrDsc("JPE\0",D_JMC|D_BHINT|D_COND|D_RARE,0,1,0x000000FF,0x0000007A,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
768 AsmInstrDsc("JP\0",D_JMC|D_BHINT|D_COND|D_RARE,0,1,0x000000FF,0x0000007A,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
769 AsmInstrDsc("JPE\0",D_JMC|D_BHINT|D_COND|D_RARE,0,2,0x0000FFFF,0x00008A0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
770 AsmInstrDsc("JP\0",D_JMC|D_BHINT|D_COND|D_RARE,0,2,0x0000FFFF,0x00008A0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
771 AsmInstrDsc("JPO\0",D_JMC|D_BHINT|D_COND|D_RARE,0,1,0x000000FF,0x0000007B,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
772 AsmInstrDsc("JNP\0",D_JMC|D_BHINT|D_COND|D_RARE,0,1,0x000000FF,0x0000007B,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
773 AsmInstrDsc("JPO\0",D_JMC|D_BHINT|D_COND|D_RARE,0,2,0x0000FFFF,0x00008B0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
774 AsmInstrDsc("JNP\0",D_JMC|D_BHINT|D_COND|D_RARE,0,2,0x0000FFFF,0x00008B0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
775 AsmInstrDsc("JL\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x0000007C,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
776 AsmInstrDsc("JNGE\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x0000007C,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
777 AsmInstrDsc("JL\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x00008C0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
778 AsmInstrDsc("JNGE\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x00008C0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
779 AsmInstrDsc("JGE\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x0000007D,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
780 AsmInstrDsc("JNL\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x0000007D,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
781 AsmInstrDsc("JGE\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x00008D0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
782 AsmInstrDsc("JNL\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x00008D0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
783 AsmInstrDsc("JLE\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x0000007E,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
784 AsmInstrDsc("JNG\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x0000007E,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
785 AsmInstrDsc("JLE\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x00008E0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
786 AsmInstrDsc("JNG\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x00008E0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
787 AsmInstrDsc("JG\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x0000007F,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
788 AsmInstrDsc("JNLE\0",D_JMC|D_BHINT|D_COND,0,1,0x000000FF,0x0000007F,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
789 AsmInstrDsc("JG\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x00008F0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
790 AsmInstrDsc("JNLE\0",D_JMC|D_BHINT|D_COND,0,2,0x0000FFFF,0x00008F0F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
791 AsmInstrDsc("JCXZ\0",D_JMCX|D_ADDR16|D_BHINT,0,1,0x000000FF,0x000000E3,0x00,[B_CX|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
792 AsmInstrDsc("JECXZ\0",D_JMCX|D_ADDR32|D_BHINT,0,1,0x000000FF,0x000000E3,0x00,[B_ECX|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
793 AsmInstrDsc("JMP\0",D_JMP,0,1,0x000000FF,0x000000EB,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
794 AsmInstrDsc("JMP\0",D_JMP,0,1,0x000000FF,0x000000E9,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
795 AsmInstrDsc("JMP\0",D_JMP,0,1,0x000038FF,0x000020FF,0x00,[B_INT|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
796 AsmInstrDsc("JMP\0",D_JMPFAR|D_SUSPICIOUS,0,1,0x000000FF,0x000000EA,0x00,[B_FARCONST|B_JMPCALLFAR,B_NONE,B_NONE,B_NONE]),
797 AsmInstrDsc("JMP\0",D_JMPFAR|D_RARE,0,1,0x000038FF,0x000028FF,0x00,[B_SEGOFFS|B_JMPCALLFAR|B_MEMONLY|B_SHOWSIZE,B_NONE,B_NONE,B_NONE]),
798 AsmInstrDsc("LAHF\0",D_CMD,0,1,0x000000FF,0x0000009F,0x00,[B_AH|B_CHG|B_PSEUDO,B_FLAGS8|B_PSEUDO,B_NONE,B_NONE]),
799 AsmInstrDsc("LAR\0",D_CMD|D_FLAGZ|D_RARE,DX_JZ,2,0x0000FFFF,0x0000020F,0x00,[B_REG|B_BINARY|B_NOESP|B_CHG,B_INT|B_BINARY|B_NOESP,B_NONE,B_NONE]),
800 AsmInstrDsc("LDS\0",D_CMD|D_RARE,0,1,0x000000FF,0x000000C5,0x00,[B_SEGDS|B_CHG|B_PSEUDO,B_REG|B_BINARY|B_CHG,B_SEGOFFS|B_MEMONLY,B_NONE]),
801 AsmInstrDsc("LES\0",D_CMD|D_RARE,0,1,0x000000FF,0x000000C4,0x00,[B_SEGES|B_CHG|B_PSEUDO,B_REG|B_BINARY|B_CHG,B_SEGOFFS|B_MEMONLY,B_NONE]),
802 AsmInstrDsc("LFS\0",D_CMD|D_RARE,0,2,0x0000FFFF,0x0000B40F,0x00,[B_SEGFS|B_CHG|B_PSEUDO,B_REG|B_BINARY|B_CHG,B_SEGOFFS|B_MEMONLY,B_NONE]),
803 AsmInstrDsc("LGS\0",D_CMD|D_RARE,0,2,0x0000FFFF,0x0000B50F,0x00,[B_SEGGS|B_CHG|B_PSEUDO,B_REG|B_BINARY|B_CHG,B_SEGOFFS|B_MEMONLY,B_NONE]),
804 AsmInstrDsc("LSS\0",D_CMD|D_RARE,0,2,0x0000FFFF,0x0000B20F,0x00,[B_SEGSS|B_CHG|B_PSEUDO,B_REG|B_BINARY|B_CHG,B_SEGOFFS|B_MEMONLY,B_NONE]),
805 AsmInstrDsc("LEA\0",D_CMD|D_HLADIR,DX_LEA,1,0x000000FF,0x0000008D,0x00,[B_REG|B_BINARY|B_CHG,B_ANYMEM|B_MEMONLY|B_NOSEG,B_NONE,B_NONE]),
806 AsmInstrDsc("LEAVE\0",D_CMD|D_CHGESP,0,1,0x000000FF,0x000000C9,0x00,[B_BPEBP|B_CHG|B_PSEUDO,B_EBPMEM|B_PSEUDO,B_NONE,B_NONE]),
807 AsmInstrDsc("LGDT\0",D_PRIVILEGED|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0010010F,0x00,[B_DESCR|B_MEMONLY,B_NONE,B_NONE,B_NONE]),
808 AsmInstrDsc("LIDT\0",D_PRIVILEGED|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0018010F,0x00,[B_DESCR|B_MEMONLY,B_NONE,B_NONE,B_NONE]),
809 AsmInstrDsc("LLDT\0",D_PRIVILEGED|D_RARE,0,2,0x0038FFFF,0x0010000F,0x00,[B_INT16|B_NOESP,B_NONE,B_NONE,B_NONE]),
810 AsmInstrDsc("LMSW\0",D_PRIVILEGED|D_RARE,0,2,0x0038FFFF,0x0030010F,0x00,[B_CR0|B_UPD|B_PSEUDO,B_INT16|B_NOESP,B_NONE,B_NONE]),
811 AsmInstrDsc("LOOP\0",D_JMCX|D_ADDR32,0,1,0x000000FF,0x000000E2,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
812 AsmInstrDsc("LOOPD\0",D_JMCX|D_ADDR32,0,1,0x000000FF,0x000000E2,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
813 AsmInstrDsc("LOOPW\0",D_JMCX|D_ADDR16,0,1,0x000000FF,0x000000E2,0x00,[B_CX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
814 AsmInstrDsc("LOOPZ\0",D_JMCX|D_ADDR32|D_COND,0,1,0x000000FF,0x000000E1,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
815 AsmInstrDsc("LOOPDZ\0",D_JMCX|D_ADDR32|D_COND,0,1,0x000000FF,0x000000E1,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
816 AsmInstrDsc("LOOPWZ\0",D_JMCX|D_ADDR16|D_COND,0,1,0x000000FF,0x000000E1,0x00,[B_CX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
817 AsmInstrDsc("LOOPE\0",D_JMCX|D_ADDR32|D_COND,0,1,0x000000FF,0x000000E1,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
818 AsmInstrDsc("LOOPDE\0",D_JMCX|D_ADDR32|D_COND,0,1,0x000000FF,0x000000E1,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
819 AsmInstrDsc("LOOPWE\0",D_JMCX|D_ADDR16|D_COND,0,1,0x000000FF,0x000000E1,0x00,[B_CX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
820 AsmInstrDsc("LOOPNZ\0",D_JMCX|D_ADDR32|D_COND,0,1,0x000000FF,0x000000E0,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
821 AsmInstrDsc("LOOPDNZ\0",D_JMCX|D_ADDR32|D_COND,0,1,0x000000FF,0x000000E0,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
822 AsmInstrDsc("LOOPWNZ\0",D_JMCX|D_ADDR16|D_COND,0,1,0x000000FF,0x000000E0,0x00,[B_CX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
823 AsmInstrDsc("LOOPNE\0",D_JMCX|D_ADDR32|D_COND,0,1,0x000000FF,0x000000E0,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
824 AsmInstrDsc("LOOPDNE\0",D_JMCX|D_ADDR32|D_COND,0,1,0x000000FF,0x000000E0,0x00,[B_ECX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
825 AsmInstrDsc("LOOPWNE\0",D_JMCX|D_ADDR16|D_COND,0,1,0x000000FF,0x000000E0,0x00,[B_CX|B_UPD|B_PSEUDO,B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE]),
826 AsmInstrDsc("LSL\0",D_SYS|D_FLAGZ|D_RARE,0,2,0x0000FFFF,0x0000030F,0x00,[B_REG|B_NOESP|B_CHG,B_INT|B_BINARY|B_NOESP,B_NONE,B_NONE]),
827 AsmInstrDsc("LTR\0",D_PRIVILEGED|D_RARE,0,2,0x0038FFFF,0x0018000F,0x00,[B_INT16|B_NOESP,B_NONE,B_NONE,B_NONE]),
828 AsmInstrDsc("MOV\0",D_MOV|D_SIZE01,0,1,0x000000FE,0x00000088,0x00,[B_INT|B_CHG,B_REG,B_NONE,B_NONE]),
829 AsmInstrDsc("MOV\0",D_MOV|D_SIZE01,0,1,0x000000FE,0x0000008A,0x00,[B_REG|B_CHG,B_INT,B_NONE,B_NONE]),
830 AsmInstrDsc("MOV\0",D_CMD|D_REGISTER|D_RARE,0,1,0x0000C0FF,0x0000C08C,0x00,[B_INT|B_REGISTER|B_NOESP|B_CHG,B_SEG,B_NONE,B_NONE]),
831 AsmInstrDsc("MOV\0",D_CMD|D_MEMORY|D_RARE,0,1,0x000000FF,0x0000008C,0x00,[B_INT16|B_MEMORY|B_CHG,B_SEG,B_NONE,B_NONE]),
832 AsmInstrDsc("MOV\0",D_CMD|D_RARE,0,1,0x000000FF,0x0000008E,0x00,[B_SEGNOCS|B_CHG,B_INT|B_REGISTER|B_NOESP,B_NONE,B_NONE]),
833 AsmInstrDsc("MOV\0",D_CMD|D_RARE,0,1,0x000000FF,0x0000008E,0x00,[B_SEGNOCS|B_CHG,B_INT16|B_MEMORY|B_NOESP,B_NONE,B_NONE]),
834 AsmInstrDsc("MOV\0",D_MOV|D_SIZE01,0,1,0x000000FE,0x000000A0,0x00,[B_ACC|B_CHG,B_IMMINT,B_NONE,B_NONE]),
835 AsmInstrDsc("MOV\0",D_MOV|D_SIZE01,0,1,0x000000FE,0x000000A2,0x00,[B_IMMINT|B_CHG,B_ACC,B_NONE,B_NONE]),
836 AsmInstrDsc("MOV\0",D_MOV,0,1,0x000000F8,0x000000B0,0x00,[B_REGCMD8|B_CHG,B_CONST8,B_NONE,B_NONE]),
837 AsmInstrDsc("MOV\0",D_MOV,0,1,0x000000F8,0x000000B8,0x00,[B_REGCMD|B_NOESP|B_CHG,B_CONST,B_NONE,B_NONE]),
838 AsmInstrDsc("MOV\0",D_MOV|D_SIZE01,0,1,0x000038FE,0x000000C6,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_CHG,B_CONST,B_NONE,B_NONE]),
839 AsmInstrDsc("MOV\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000220F,0x00,[B_CR|B_CHG,B_INT32|B_BINARY|B_REGONLY|B_NOESP,B_NONE,B_NONE]),
840 AsmInstrDsc("MOV\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000200F,0x00,[B_INT32|B_BINARY|B_REGONLY|B_NOESP|B_CHG,B_CR,B_NONE,B_NONE]),
841 AsmInstrDsc("MOV\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000230F,0x00,[B_DR|B_CHG,B_INT32|B_BINARY|B_REGONLY|B_NOESP,B_NONE,B_NONE]),
842 AsmInstrDsc("MOV\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000210F,0x00,[B_INT32|B_BINARY|B_REGONLY|B_NOESP|B_CHG,B_DR,B_NONE,B_NONE]),
843 AsmInstrDsc("MOVSX\0",D_MOV,0,2,0x0000FFFF,0x0000BE0F,0x00,[B_REG|B_NOESP|B_CHG,B_INT8|B_SIGNED|B_SHOWSIZE,B_NONE,B_NONE]),
844 AsmInstrDsc("MOVSX\0",D_MOV,0,2,0x0000FFFF,0x0000BF0F,0x00,[B_REG32|B_NOESP|B_CHG,B_INT16|B_SIGNED|B_SHOWSIZE,B_NONE,B_NONE]),
845 AsmInstrDsc("MOVZX\0",D_MOV,0,2,0x0000FFFF,0x0000B60F,0x00,[B_REG|B_NOESP|B_CHG,B_INT8|B_SHOWSIZE,B_NONE,B_NONE]),
846 AsmInstrDsc("MOVZX\0",D_MOV,0,2,0x0000FFFF,0x0000B70F,0x00,[B_REG32|B_NOESP|B_CHG,B_INT16|B_SHOWSIZE,B_NONE,B_NONE]),
847 AsmInstrDsc("MUL\0",D_CMD|D_ALLFLAGS,0,1,0x000038FF,0x000020F6,0x00,[B_AX|B_UPD|B_PSEUDO,B_AL|B_PSEUDO,B_INT8|B_UNSIGNED|B_SHOWSIZE,B_NONE]),
848 AsmInstrDsc("MUL\0",D_CMD|D_ALLFLAGS,0,1,0x000038FF,0x000020F7,0x00,[B_DXEDX|B_CHG|B_PSEUDO,B_ACC|B_UPD|B_PSEUDO,B_INT1632|B_UNSIGNED|B_NOESP|B_SHOWSIZE,B_NONE]),
849 AsmInstrDsc("NEG\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000018F6,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_NONE,B_NONE,B_NONE]),
850 AsmInstrDsc("NOT\0",D_CMD|D_SIZE01|D_LOCKABLE,0,1,0x000038FE,0x000010F6,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_NONE,B_NONE,B_NONE]),
851 AsmInstrDsc("OR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JB,1,0x000000FE,0x0000000C,0x00,[B_ACC|B_BINARY|B_UPD,B_CONST|B_BINARY,B_NONE,B_NONE]),
852 AsmInstrDsc("OR\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JB,1,0x000038FE,0x00000880,0x00,[B_INT|B_BINARY|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST|B_BINARY,B_NONE,B_NONE]),
853 AsmInstrDsc("OR\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JB,1,0x000038FE,0x00000882,0x00,[B_INT|B_BINARY|B_NOESP|B_SHOWSIZE|B_UPD,B_SXTCONST|B_BINARY,B_NONE,B_NONE]),
854 AsmInstrDsc("OR\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JB,1,0x000000FE,0x00000008,0x00,[B_INT|B_BINARY|B_NOESP|B_UPD,B_REG|B_BINARY,B_NONE,B_NONE]),
855 AsmInstrDsc("OR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JB,1,0x000000FE,0x0000000A,0x00,[B_REG|B_BINARY|B_NOESP|B_UPD,B_INT|B_BINARY,B_NONE,B_NONE]),
856 AsmInstrDsc("OUT\0",D_IO|D_SIZE01|D_RARE,0,1,0x000000FE,0x000000E6,0x00,[B_CONST8|B_PORT,B_ACC,B_NONE,B_NONE]),
857 AsmInstrDsc("OUT\0",D_IO|D_SIZE01|D_RARE,0,1,0x000000FE,0x000000EE,0x00,[B_DXPORT|B_PORT,B_ACC,B_NONE,B_NONE]),
858 AsmInstrDsc("POP\0",D_POP|D_CHGESP,0,1,0x000038FF,0x0000008F,0x00,[B_INT|B_SHOWSIZE|B_CHG,B_STKTOP|B_PSEUDO,B_NONE,B_NONE]),
859 AsmInstrDsc("POP\0",D_POP|D_CHGESP,0,1,0x000000F8,0x00000058,0x00,[B_REGCMD|B_CHG,B_STKTOP|B_PSEUDO,B_NONE,B_NONE]),
860 AsmInstrDsc("POP\0",D_POP|D_CHGESP|D_RARE,0,1,0x000000FF,0x0000001F,0x00,[B_SEGDS|B_CHG,B_STKTOP|B_PSEUDO,B_NONE,B_NONE]),
861 AsmInstrDsc("POP\0",D_POP|D_CHGESP|D_RARE,0,1,0x000000FF,0x00000007,0x00,[B_SEGES|B_CHG,B_STKTOP|B_PSEUDO,B_NONE,B_NONE]),
862 AsmInstrDsc("POP\0",D_POP|D_CHGESP|D_RARE,DX_JB,1,0x000000FF,0x00000017,0x00,[B_SEGSS|B_CHG,B_STKTOP|B_PSEUDO,B_NONE,B_NONE]),
863 AsmInstrDsc("POP\0",D_POP|D_CHGESP|D_RARE,0,2,0x0000FFFF,0x0000A10F,0x00,[B_SEGFS|B_CHG,B_STKTOP|B_PSEUDO,B_NONE,B_NONE]),
864 AsmInstrDsc("POP\0",D_POP|D_CHGESP|D_RARE,0,2,0x0000FFFF,0x0000A90F,0x00,[B_SEGGS|B_CHG,B_STKTOP|B_PSEUDO,B_NONE,B_NONE]),
865 AsmInstrDsc("POPA*\0",D_CMD|D_CHGESP|D_WILDCARD,0,1,0x000000FF,0x00000061,0x00,[B_STKTOPA|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
866 AsmInstrDsc("POPF*\0",D_POP|D_ALLFLAGS|D_CHGESP|D_WILDCARD,0,1,0x000000FF,0x0000009D,0x00,[B_EFL|B_CHG|B_PSEUDO,B_STKTOPEFL|B_PSEUDO,B_NONE,B_NONE]),
867 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP,0,1,0x000038FF,0x000030FF,0x00,[B_INT|B_SHOWSIZE,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
868 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP,0,1,0x000000F8,0x00000050,0x00,[B_REGCMD,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
869 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP,0,1,0x000000FF,0x0000006A,0x00,[B_SXTCONST|B_SHOWSIZE,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
870 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP,0,1,0x000000FF,0x00000068,0x00,[B_CONSTL|B_SHOWSIZE,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
871 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP|D_RARE,0,1,0x000000FF,0x0000000E,0x00,[B_SEGCS,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
872 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP|D_RARE,0,1,0x000000FF,0x00000016,0x00,[B_SEGSS,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
873 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP|D_RARE,0,1,0x000000FF,0x0000001E,0x00,[B_SEGDS,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
874 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP|D_RARE,0,1,0x000000FF,0x00000006,0x00,[B_SEGES,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
875 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP|D_RARE,0,2,0x0000FFFF,0x0000A00F,0x00,[B_SEGFS,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
876 AsmInstrDsc("PUSH\0",D_PUSH|D_CHGESP|D_RARE,0,2,0x0000FFFF,0x0000A80F,0x00,[B_SEGGS,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
877 AsmInstrDsc("PUSHA*\0",D_CMD|D_CHGESP|D_WILDCARD,0,1,0x000000FF,0x00000060,0x00,[B_PUSHA|B_CHG|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
878 AsmInstrDsc("PUSHF*\0",D_PUSH|D_CHGESP|D_WILDCARD,DX_JB,1,0x000000FF,0x0000009C,0x00,[B_EFL|B_PSEUDO,B_PUSH|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
879 AsmInstrDsc("RCL\0",D_CMD|D_SIZE01|D_FLAGSCO|D_USESCARRY,DX_JC,1,0x000038FE,0x000010D0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_1|B_SHIFTCNT,B_NONE,B_NONE]),
880 AsmInstrDsc("RCL\0",D_CMD|D_SIZE01|D_FLAGSCO|D_USESCARRY,DX_JC,1,0x000038FE,0x000010D2,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CL|B_SHIFTCNT,B_NONE,B_NONE]),
881 AsmInstrDsc("RCL\0",D_CMD|D_SIZE01|D_FLAGSCO|D_USESCARRY,DX_JC,1,0x000038FE,0x000010C0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_SHIFTCNT,B_NONE,B_NONE]),
882 AsmInstrDsc("RCR\0",D_CMD|D_SIZE01|D_FLAGSCO|D_USESCARRY,DX_JC,1,0x000038FE,0x000018D0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_1|B_SHIFTCNT,B_NONE,B_NONE]),
883 AsmInstrDsc("RCR\0",D_CMD|D_SIZE01|D_FLAGSCO|D_USESCARRY,DX_JC,1,0x000038FE,0x000018D2,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CL|B_SHIFTCNT,B_NONE,B_NONE]),
884 AsmInstrDsc("RCR\0",D_CMD|D_SIZE01|D_FLAGSCO|D_USESCARRY,DX_JC,1,0x000038FE,0x000018C0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_SHIFTCNT,B_NONE,B_NONE]),
885 AsmInstrDsc("ROL\0",D_CMD|D_SIZE01|D_FLAGSCO,DX_JC,1,0x000038FE,0x000000D0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_1|B_SHIFTCNT,B_NONE,B_NONE]),
886 AsmInstrDsc("ROL\0",D_CMD|D_SIZE01|D_FLAGSCO,DX_JC,1,0x000038FE,0x000000D2,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CL|B_SHIFTCNT,B_NONE,B_NONE]),
887 AsmInstrDsc("ROL\0",D_CMD|D_SIZE01|D_FLAGSCO,DX_JC,1,0x000038FE,0x000000C0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_SHIFTCNT,B_NONE,B_NONE]),
888 AsmInstrDsc("ROR\0",D_CMD|D_SIZE01|D_FLAGSCO,DX_JC,1,0x000038FE,0x000008D0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_1|B_SHIFTCNT,B_NONE,B_NONE]),
889 AsmInstrDsc("ROR\0",D_CMD|D_SIZE01|D_FLAGSCO,DX_JC,1,0x000038FE,0x000008D2,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CL|B_SHIFTCNT,B_NONE,B_NONE]),
890 AsmInstrDsc("ROR\0",D_CMD|D_SIZE01|D_FLAGSCO,DX_JC,1,0x000038FE,0x000008C0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_SHIFTCNT,B_NONE,B_NONE]),
891 AsmInstrDsc("RDMSR\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000320F,0x00,[B_EDX|B_BINARY|B_CHG|B_PSEUDO,B_EAX|B_BINARY|B_CHG|B_PSEUDO,B_ECX|B_PSEUDO,B_NONE]),
892 AsmInstrDsc("RDPMC\0",D_SYS|D_RARE,0,2,0x0000FFFF,0x0000330F,0x00,[B_EDX|B_BINARY|B_CHG|B_PSEUDO,B_EAX|B_BINARY|B_CHG|B_PSEUDO,B_ECX|B_PSEUDO,B_NONE]),
893 AsmInstrDsc("RDTSC\0",D_SYS|D_RARE,0,2,0x0000FFFF,0x0000310F,0x00,[B_EDX|B_BINARY|B_CHG|B_PSEUDO,B_EAX|B_BINARY|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
894 AsmInstrDsc("RDTSCP\0",D_SYS|D_RARE,0,3,0x00FFFFFF,0x00F9010F,0x00,[B_EDX|B_BINARY|B_CHG|B_PSEUDO,B_EAX|B_BINARY|B_CHG|B_PSEUDO,B_ECX|B_BINARY|B_CHG|B_PSEUDO,B_NONE]),
895 AsmInstrDsc("RETN\0",D_RET|D_NOREP|D_CHGESP,DX_RETN,1,0x000000FF,0x000000C3,0x00,[B_STKTOP|B_JMPCALL|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
896 AsmInstrDsc("RET\0",D_RET|D_NOREP|D_CHGESP,0,1,0x000000FF,0x000000C3,0x00,[B_STKTOP|B_JMPCALL|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
897 AsmInstrDsc("RETN\0",D_RET|D_MUSTREP|D_CHGESP,DX_RETN,1,0x000000FF,0x000000C3,0x00,[B_STKTOP|B_JMPCALL|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
898 AsmInstrDsc("RET\0",D_RET|D_MUSTREP|D_CHGESP,0,1,0x000000FF,0x000000C3,0x00,[B_STKTOP|B_JMPCALL|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
899 AsmInstrDsc("RETN\0",D_RET|D_CHGESP,DX_RETN,1,0x000000FF,0x000000C2,0x00,[B_STKTOP|B_JMPCALL|B_PSEUDO,B_CONST16|B_STACKINC,B_NONE,B_NONE]),
900 AsmInstrDsc("RET\0",D_RET|D_CHGESP,0,1,0x000000FF,0x000000C2,0x00,[B_STKTOP|B_JMPCALL|B_PSEUDO,B_CONST16|B_STACKINC,B_NONE,B_NONE]),
901 AsmInstrDsc("RETF\0",D_RETFAR|D_CHGESP|D_RARE,0,1,0x000000FF,0x000000CB,0x00,[B_STKTOPFAR|B_JMPCALLFAR|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
902 AsmInstrDsc("RETF\0",D_RETFAR|D_CHGESP|D_RARE,0,1,0x000000FF,0x000000CA,0x00,[B_STKTOPFAR|B_JMPCALLFAR|B_PSEUDO,B_CONST16|B_STACKINC,B_NONE,B_NONE]),
903 AsmInstrDsc("RSM\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000AA0F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
904 AsmInstrDsc("SAHF\0",D_CMD|D_ALLFLAGS,0,1,0x000000FF,0x0000009E,0x00,[B_AH|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
905 AsmInstrDsc("SHL\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000020D0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_1|B_SHIFTCNT,B_NONE,B_NONE]),
906 AsmInstrDsc("SHL\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000020D2,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CL|B_SHIFTCNT,B_NONE,B_NONE]),
907 AsmInstrDsc("SHL\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000020C0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_SHIFTCNT,B_NONE,B_NONE]),
908 AsmInstrDsc("SAL\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000020D0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_1|B_SHIFTCNT,B_NONE,B_NONE]),
909 AsmInstrDsc("SAL\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000020D2,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CL|B_SHIFTCNT,B_NONE,B_NONE]),
910 AsmInstrDsc("SAL\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000020C0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_SHIFTCNT,B_NONE,B_NONE]),
911 AsmInstrDsc("SAL\0",D_CMD|D_SIZE01|D_ALLFLAGS|D_UNDOC,DX_JZ|DX_JC,1,0x000038FE,0x000030D0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_1|B_SHIFTCNT,B_NONE,B_NONE]),
912 AsmInstrDsc("SAL\0",D_CMD|D_SIZE01|D_ALLFLAGS|D_UNDOC,DX_JZ|DX_JC,1,0x000038FE,0x000030D2,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CL|B_SHIFTCNT,B_NONE,B_NONE]),
913 AsmInstrDsc("SAL\0",D_CMD|D_SIZE01|D_ALLFLAGS|D_UNDOC,DX_JZ|DX_JC,1,0x000038FE,0x000030C0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_SHIFTCNT,B_NONE,B_NONE]),
914 AsmInstrDsc("SALC\0",D_CMD|D_ALLFLAGS|D_UNDOC,DX_JZ|DX_JC,1,0x000000FF,0x000000D6,0x00,[B_AL|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
915 AsmInstrDsc("SHR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000028D0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_1|B_SHIFTCNT,B_NONE,B_NONE]),
916 AsmInstrDsc("SHR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000028D2,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CL|B_SHIFTCNT,B_NONE,B_NONE]),
917 AsmInstrDsc("SHR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000028C0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_SHIFTCNT,B_NONE,B_NONE]),
918 AsmInstrDsc("SAR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000038D0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_1|B_SHIFTCNT,B_NONE,B_NONE]),
919 AsmInstrDsc("SAR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000038D2,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CL|B_SHIFTCNT,B_NONE,B_NONE]),
920 AsmInstrDsc("SAR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JC,1,0x000038FE,0x000038C0,0x00,[B_INT|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST8|B_SHIFTCNT,B_NONE,B_NONE]),
921 AsmInstrDsc("SBB\0",D_CMD|D_SIZE01|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000000FE,0x0000001C,0x00,[B_ACC|B_UPD,B_CONST,B_NONE,B_NONE]),
922 AsmInstrDsc("SBB\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000038FE,0x00001880,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_CONST,B_NONE,B_NONE]),
923 AsmInstrDsc("SBB\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000038FE,0x00001882,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_SXTCONST,B_NONE,B_NONE]),
924 AsmInstrDsc("SBB\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000000FE,0x00000018,0x00,[B_INT|B_UPD,B_REG,B_NONE,B_NONE]),
925 AsmInstrDsc("SBB\0",D_CMD|D_SIZE01|D_ALLFLAGS|D_USESCARRY,DX_JZ|DX_JB,1,0x000000FE,0x0000001A,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
926 AsmInstrDsc("SETO\0",D_SETC|D_COND,0,2,0x0000FFFF,0x0000900F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
927 AsmInstrDsc("SETNO\0",D_SETC|D_COND,0,2,0x0000FFFF,0x0000910F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
928 AsmInstrDsc("SETB\0",D_SETC|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000920F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
929 AsmInstrDsc("SETC\0",D_SETC|D_COND|D_USESCARRY,DX_JC,2,0x0000FFFF,0x0000920F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
930 AsmInstrDsc("SETNAE\0",D_SETC|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000920F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
931 AsmInstrDsc("SETAE\0",D_SETC|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000930F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
932 AsmInstrDsc("SETNB\0",D_SETC|D_COND|D_USESCARRY,DX_JB,2,0x0000FFFF,0x0000930F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
933 AsmInstrDsc("SETNC\0",D_SETC|D_COND|D_USESCARRY,DX_JC,2,0x0000FFFF,0x0000930F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
934 AsmInstrDsc("SETE\0",D_SETC|D_COND,DX_JE,2,0x0000FFFF,0x0000940F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
935 AsmInstrDsc("SETZ\0",D_SETC|D_COND,DX_JZ,2,0x0000FFFF,0x0000940F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
936 AsmInstrDsc("SETNE\0",D_SETC|D_COND,DX_JE,2,0x0000FFFF,0x0000950F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
937 AsmInstrDsc("SETNZ\0",D_SETC|D_COND,DX_JZ,2,0x0000FFFF,0x0000950F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
938 AsmInstrDsc("SETBE\0",D_SETC|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000960F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
939 AsmInstrDsc("SETNA\0",D_SETC|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000960F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
940 AsmInstrDsc("SETA\0",D_SETC|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000970F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
941 AsmInstrDsc("SETNBE\0",D_SETC|D_COND|D_USESCARRY,0,2,0x0000FFFF,0x0000970F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
942 AsmInstrDsc("SETS\0",D_SETC|D_COND,0,2,0x0000FFFF,0x0000980F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
943 AsmInstrDsc("SETNS\0",D_SETC|D_COND,0,2,0x0000FFFF,0x0000990F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
944 AsmInstrDsc("SETPE\0",D_SETC|D_COND|D_RARE,0,2,0x0000FFFF,0x00009A0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
945 AsmInstrDsc("SETP\0",D_SETC|D_COND|D_RARE,0,2,0x0000FFFF,0x00009A0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
946 AsmInstrDsc("SETPO\0",D_SETC|D_COND|D_RARE,0,2,0x0000FFFF,0x00009B0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
947 AsmInstrDsc("SETNP\0",D_SETC|D_COND|D_RARE,0,2,0x0000FFFF,0x00009B0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
948 AsmInstrDsc("SETL\0",D_SETC|D_COND,0,2,0x0000FFFF,0x00009C0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
949 AsmInstrDsc("SETNGE\0",D_SETC|D_COND,0,2,0x0000FFFF,0x00009C0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
950 AsmInstrDsc("SETGE\0",D_SETC|D_COND,0,2,0x0000FFFF,0x00009D0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
951 AsmInstrDsc("SETNL\0",D_SETC|D_COND,0,2,0x0000FFFF,0x00009D0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
952 AsmInstrDsc("SETLE\0",D_SETC|D_COND,0,2,0x0000FFFF,0x00009E0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
953 AsmInstrDsc("SETNG\0",D_SETC|D_COND,0,2,0x0000FFFF,0x00009E0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
954 AsmInstrDsc("SETG\0",D_SETC|D_COND,0,2,0x0000FFFF,0x00009F0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
955 AsmInstrDsc("SETNLE\0",D_SETC|D_COND,0,2,0x0000FFFF,0x00009F0F,0x00,[B_INT8|B_CHG,B_ANYREG|B_PSEUDO,B_NONE,B_NONE]),
956 AsmInstrDsc("SGDT\0",D_SYS|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0000010F,0x00,[B_DESCR|B_MEMONLY|B_CHG,B_NONE,B_NONE,B_NONE]),
957 AsmInstrDsc("SIDT\0",D_SYS|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0008010F,0x00,[B_DESCR|B_MEMONLY|B_CHG,B_NONE,B_NONE,B_NONE]),
958 AsmInstrDsc("SHLD\0",D_CMD|D_ALLFLAGS,DX_JZ|DX_JC,2,0x0000FFFF,0x0000A40F,0x00,[B_INT|B_NOESP|B_UPD,B_REG,B_CONST8|B_SHIFTCNT,B_NONE]),
959 AsmInstrDsc("SHLD\0",D_CMD|D_ALLFLAGS,DX_JZ|DX_JC,2,0x0000FFFF,0x0000A50F,0x00,[B_INT|B_NOESP|B_UPD,B_REG,B_CL|B_SHIFTCNT,B_NONE]),
960 AsmInstrDsc("SHRD\0",D_CMD|D_ALLFLAGS,DX_JZ|DX_JC,2,0x0000FFFF,0x0000AC0F,0x00,[B_INT|B_NOESP|B_UPD,B_REG,B_CONST8|B_SHIFTCNT,B_NONE]),
961 AsmInstrDsc("SHRD\0",D_CMD|D_ALLFLAGS,DX_JZ|DX_JC,2,0x0000FFFF,0x0000AD0F,0x00,[B_INT|B_NOESP|B_UPD,B_REG,B_CL|B_SHIFTCNT,B_NONE]),
962 AsmInstrDsc("SLDT\0",D_SYS|D_RARE,0,2,0x0038FFFF,0x0000000F,0x00,[B_INT|B_NOESP|B_CHG,B_NONE,B_NONE,B_NONE]),
963 AsmInstrDsc("SMSW\0",D_SYS|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0020010F,0x00,[B_INT16|B_MEMONLY|B_CHG,B_CR0|B_PSEUDO,B_NONE,B_NONE]),
964 AsmInstrDsc("SMSW\0",D_SYS|D_REGISTER|D_RARE,0,2,0x0038FFFF,0x0020010F,0x00,[B_INT|B_REGONLY|B_NOESP|B_CHG,B_CR0|B_PSEUDO,B_NONE,B_NONE]),
965 AsmInstrDsc("STC\0",D_CMD|D_FLAGC,0,1,0x000000FF,0x000000F9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
966 AsmInstrDsc("STD\0",D_CMD|D_FLAGD,0,1,0x000000FF,0x000000FD,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
967 AsmInstrDsc("STI\0",D_CMD|D_RARE,0,1,0x000000FF,0x000000FB,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
968 AsmInstrDsc("STMXCSR\0",D_CMD|D_MEMORY,0,2,0x0038FFFF,0x0018AE0F,0x00,[B_INT32|B_BINARY|B_MEMONLY|B_NOESP|B_SHOWSIZE|B_CHG,B_MXCSR|B_PSEUDO,B_NONE,B_NONE]),
969 AsmInstrDsc("STR\0",D_SYS|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0008000F,0x00,[B_INT16|B_MEMONLY|B_CHG,B_NONE,B_NONE,B_NONE]),
970 AsmInstrDsc("STR\0",D_SYS|D_REGISTER|D_RARE,0,2,0x0038FFFF,0x0008000F,0x00,[B_INT|B_REGONLY|B_NOESP|B_CHG,B_NONE,B_NONE,B_NONE]),
971 AsmInstrDsc("SUB\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JB|DX_SUB,1,0x000000FE,0x0000002C,0x00,[B_ACC|B_UPD,B_CONST,B_NONE,B_NONE]),
972 AsmInstrDsc("SUB\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JB|DX_SUB,1,0x000038FE,0x00002880,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_CONST,B_NONE,B_NONE]),
973 AsmInstrDsc("SUB\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JB|DX_SUB,1,0x000038FE,0x00002882,0x00,[B_INT|B_SHOWSIZE|B_UPD,B_SXTCONST,B_NONE,B_NONE]),
974 AsmInstrDsc("SUB\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ|DX_JB|DX_SUB,1,0x000000FE,0x00000028,0x00,[B_INT|B_UPD,B_REG,B_NONE,B_NONE]),
975 AsmInstrDsc("SUB\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ|DX_JB|DX_SUB,1,0x000000FE,0x0000002A,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
976 AsmInstrDsc("SYSENTER\0",D_SYS|D_RARE,0,2,0x0000FFFF,0x0000340F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
977 AsmInstrDsc("SYSEXIT\0",D_SYS|D_ALLFLAGS|D_SUSPICIOUS,0,2,0x0000FFFF,0x0000350F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
978 AsmInstrDsc("TEST\0",D_TEST|D_SIZE01|D_ALLFLAGS,DX_JZ,1,0x000000FE,0x000000A8,0x00,[B_ACC|B_BINARY,B_CONST|B_BINARY,B_NONE,B_NONE]),
979 AsmInstrDsc("TEST\0",D_TEST|D_SIZE01|D_ALLFLAGS,DX_JZ,1,0x000038FE,0x000000F6,0x00,[B_INT|B_BINARY|B_SHOWSIZE,B_CONST|B_BINARY,B_NONE,B_NONE]),
980 AsmInstrDsc("TEST\0",D_TEST|D_SIZE01|D_ALLFLAGS|D_UNDOC,DX_JZ,1,0x000038FE,0x000008F6,0x00,[B_INT|B_BINARY|B_SHOWSIZE,B_CONST|B_BINARY,B_NONE,B_NONE]),
981 AsmInstrDsc("TEST\0",D_TEST|D_SIZE01|D_ALLFLAGS,DX_JZ,1,0x000000FE,0x00000084,0x00,[B_INT|B_BINARY,B_REG|B_BINARY,B_NONE,B_NONE]),
982 AsmInstrDsc("TEST\0",D_TEST|D_SIZE01|D_ALLFLAGS,DX_JZ,1,0x000000FE,0x00000084,0x00,[B_REG|B_BINARY,B_INT|B_BINARY,B_NONE,B_NONE]),
983 AsmInstrDsc("UD1\0",D_CMD|D_UNDOC,0,2,0x0000FFFF,0x0000B90F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
984 AsmInstrDsc("UD2\0",D_CMD,0,2,0x0000FFFF,0x00000B0F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
985 AsmInstrDsc("VERR\0",D_CMD|D_FLAGZ|D_RARE,0,2,0x0038FFFF,0x0020000F,0x00,[B_INT16|B_NOESP,B_NONE,B_NONE,B_NONE]),
986 AsmInstrDsc("VERW\0",D_CMD|D_FLAGZ|D_RARE,0,2,0x0038FFFF,0x0028000F,0x00,[B_INT16|B_NOESP,B_NONE,B_NONE,B_NONE]),
987 AsmInstrDsc("WBINVD\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000090F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
988 AsmInstrDsc("WRMSR\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000300F,0x00,[B_EDX|B_BINARY|B_PSEUDO,B_EAX|B_BINARY|B_PSEUDO,B_ECX|B_PSEUDO,B_NONE]),
989 AsmInstrDsc("XADD\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JE|DX_JB,2,0x0000FEFF,0x0000C00F,0x00,[B_INT|B_UPD,B_REG|B_CHG,B_NONE,B_NONE]),
990 AsmInstrDsc("XCHG\0",D_MOV|D_LOCKABLE,0,1,0x000000F8,0x00000090,0x00,[B_ACC|B_CHG,B_REGCMD|B_CHG,B_NONE,B_NONE]),
991 AsmInstrDsc("XCHG\0",D_MOV,0,1,0x000000F8,0x00000090,0x00,[B_REGCMD|B_CHG,B_ACC|B_CHG,B_NONE,B_NONE]),
992 AsmInstrDsc("XCHG\0",D_MOV|D_SIZE01|D_LOCKABLE,0,1,0x000000FE,0x00000086,0x00,[B_INT|B_CHG,B_REG|B_CHG,B_NONE,B_NONE]),
993 AsmInstrDsc("XCHG\0",D_MOV|D_SIZE01|D_LOCKABLE,0,1,0x000000FE,0x00000086,0x00,[B_REG|B_CHG,B_INT|B_CHG,B_NONE,B_NONE]),
994 AsmInstrDsc("XLAT\0",D_CMD,0,1,0x000000FF,0x000000D7,0x00,[B_AL|B_CHG|B_PSEUDO,B_XLATMEM,B_NONE,B_NONE]),
995 AsmInstrDsc("XLATB\0",D_CMD,0,1,0x000000FF,0x000000D7,0x00,[B_AL|B_UPD|B_PSEUDO,B_XLATMEM|B_PSEUDO,B_NONE,B_NONE]),
996 AsmInstrDsc("XOR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ,1,0x000000FE,0x00000034,0x00,[B_ACC|B_BINARY|B_UPD,B_CONST|B_BINARY,B_NONE,B_NONE]),
997 AsmInstrDsc("XOR\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ,1,0x000038FE,0x00003080,0x00,[B_INT|B_BINARY|B_NOESP|B_SHOWSIZE|B_UPD,B_CONST|B_BINARY,B_NONE,B_NONE]),
998 AsmInstrDsc("XOR\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ,1,0x000038FE,0x00003082,0x00,[B_INT|B_BINARY|B_NOESP|B_SHOWSIZE|B_UPD,B_SXTCONST|B_BINARY,B_NONE,B_NONE]),
999 AsmInstrDsc("XOR\0",D_CMD|D_SIZE01|D_LOCKABLE|D_ALLFLAGS,DX_JZ,1,0x000000FE,0x00000030,0x00,[B_INT|B_BINARY|B_UPD,B_REG|B_BINARY,B_NONE,B_NONE]),
1000 AsmInstrDsc("XOR\0",D_CMD|D_SIZE01|D_ALLFLAGS,DX_JZ,1,0x000000FE,0x00000032,0x00,[B_REG|B_BINARY|B_UPD,B_INT|B_BINARY,B_NONE,B_NONE]),
1001 AsmInstrDsc("CMPS\0",D_CMD|D_SIZE01|D_LONGFORM|D_NOREP|D_ALLFLAGS|D_HLADIR,DX_JE|DX_JB,1,0x000000FE,0x000000A6,0x00,[B_STRSRC|B_SHOWSIZE,B_STRDEST|B_SHOWSIZE,B_NONE,B_NONE]),
1002 AsmInstrDsc("CMPSB\0",D_CMD|D_NOREP|D_ALLFLAGS,DX_JE|DX_JB,1,0x000000FF,0x000000A6,0x00,[B_STRSRC8|B_PSEUDO,B_STRDEST8|B_PSEUDO,B_NONE,B_NONE]),
1003 AsmInstrDsc("CMPS*\0",D_CMD|D_NOREP|D_ALLFLAGS|D_WILDCARD,DX_JE|DX_JB,1,0x000000FF,0x000000A7,0x00,[B_STRSRC|B_PSEUDO,B_STRDEST|B_PSEUDO,B_NONE,B_NONE]),
1004 AsmInstrDsc("CMPS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREPE|D_ALLFLAGS|D_HLADIR,0,1,0x000000FE,0x000000A6,0x00,[B_STRSRC|B_SHOWSIZE,B_STRDEST|B_SHOWSIZE,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1005 AsmInstrDsc("CMPSB\0",D_STRING|D_MUSTREPE|D_ALLFLAGS,0,1,0x000000FF,0x000000A6,0x00,[B_STRSRC8|B_PSEUDO,B_STRDEST8|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1006 AsmInstrDsc("CMPS*\0",D_STRING|D_MUSTREPE|D_ALLFLAGS|D_WILDCARD,0,1,0x000000FF,0x000000A7,0x00,[B_STRSRC|B_PSEUDO,B_STRDEST|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1007 AsmInstrDsc("CMPS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREPNE|D_ALLFLAGS|D_HLADIR,0,1,0x000000FE,0x000000A6,0x00,[B_STRSRC|B_SHOWSIZE,B_STRDEST|B_SHOWSIZE,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1008 AsmInstrDsc("CMPSB\0",D_STRING|D_MUSTREPNE|D_ALLFLAGS,0,1,0x000000FF,0x000000A6,0x00,[B_STRSRC8|B_PSEUDO,B_STRDEST8|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1009 AsmInstrDsc("CMPS*\0",D_STRING|D_MUSTREPNE|D_ALLFLAGS|D_WILDCARD,0,1,0x000000FF,0x000000A7,0x00,[B_STRSRC|B_PSEUDO,B_STRDEST|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1010 AsmInstrDsc("LODS\0",D_CMD|D_SIZE01|D_LONGFORM|D_NOREP,0,1,0x000000FE,0x000000AC,0x00,[B_ACC|B_CHG|B_PSEUDO,B_STRSRC|B_SHOWSIZE,B_NONE,B_NONE]),
1011 AsmInstrDsc("LODSB\0",D_CMD|D_NOREP,0,1,0x000000FF,0x000000AC,0x00,[B_AL|B_CHG|B_PSEUDO,B_STRSRC8|B_PSEUDO,B_NONE,B_NONE]),
1012 AsmInstrDsc("LODS*\0",D_CMD|D_NOREP|D_WILDCARD,0,1,0x000000FF,0x000000AD,0x00,[B_ACC|B_CHG|B_PSEUDO,B_STRSRC|B_PSEUDO,B_NONE,B_NONE]),
1013 AsmInstrDsc("LODS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREP|D_RARE,0,1,0x000000FE,0x000000AC,0x00,[B_ACC|B_CHG|B_PSEUDO,B_STRSRC|B_SHOWSIZE,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1014 AsmInstrDsc("LODSB\0",D_STRING|D_MUSTREP|D_RARE,0,1,0x000000FF,0x000000AC,0x00,[B_AL|B_CHG|B_PSEUDO,B_STRSRC8|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1015 AsmInstrDsc("LODS*\0",D_STRING|D_MUSTREP|D_WILDCARD|D_RARE,0,1,0x000000FF,0x000000AD,0x00,[B_ACC|B_CHG|B_PSEUDO,B_STRSRC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1016 AsmInstrDsc("LODS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREPNE|D_UNDOC,0,1,0x000000FE,0x000000AC,0x00,[B_ACC|B_CHG|B_PSEUDO,B_STRSRC|B_SHOWSIZE,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1017 AsmInstrDsc("LODSB\0",D_STRING|D_MUSTREPNE|D_UNDOC,0,1,0x000000FF,0x000000AC,0x00,[B_AL|B_CHG|B_PSEUDO,B_STRSRC8|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1018 AsmInstrDsc("LODS*\0",D_STRING|D_MUSTREPNE|D_WILDCARD|D_UNDOC,0,1,0x000000FF,0x000000AD,0x00,[B_ACC|B_CHG|B_PSEUDO,B_STRSRC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1019 AsmInstrDsc("MOVS\0",D_CMD|D_SIZE01|D_LONGFORM|D_NOREP,0,1,0x000000FE,0x000000A4,0x00,[B_STRDEST|B_SHOWSIZE|B_CHG,B_STRSRC|B_SHOWSIZE,B_NONE,B_NONE]),
1020 AsmInstrDsc("MOVSB\0",D_CMD|D_NOREP,0,1,0x000000FF,0x000000A4,0x00,[B_STRDEST8|B_CHG|B_PSEUDO,B_STRSRC8|B_PSEUDO,B_NONE,B_NONE]),
1021 AsmInstrDsc("MOVS*\0",D_CMD|D_NOREP|D_WILDCARD,0,1,0x000000FF,0x000000A5,0x00,[B_STRDEST|B_CHG|B_PSEUDO,B_STRSRC|B_PSEUDO,B_NONE,B_NONE]),
1022 AsmInstrDsc("MOVS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREP,0,1,0x000000FE,0x000000A4,0x00,[B_STRDEST|B_SHOWSIZE|B_CHG,B_STRSRC|B_SHOWSIZE,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1023 AsmInstrDsc("MOVSB\0",D_STRING|D_MUSTREP,0,1,0x000000FF,0x000000A4,0x00,[B_STRDEST8|B_CHG|B_PSEUDO,B_STRSRC8|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1024 AsmInstrDsc("MOVS*\0",D_STRING|D_MUSTREP|D_WILDCARD,0,1,0x000000FF,0x000000A5,0x00,[B_STRDEST|B_CHG|B_PSEUDO,B_STRSRC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1025 AsmInstrDsc("MOVS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREPNE|D_UNDOC,0,1,0x000000FE,0x000000A4,0x00,[B_STRDEST|B_SHOWSIZE|B_CHG,B_STRSRC|B_SHOWSIZE,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1026 AsmInstrDsc("MOVSB\0",D_STRING|D_MUSTREPNE|D_UNDOC,0,1,0x000000FF,0x000000A4,0x00,[B_STRDEST8|B_CHG|B_PSEUDO,B_STRSRC8|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1027 AsmInstrDsc("MOVS*\0",D_STRING|D_MUSTREPNE|D_WILDCARD|D_UNDOC,0,1,0x000000FF,0x000000A5,0x00,[B_STRDEST|B_CHG|B_PSEUDO,B_STRSRC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1028 AsmInstrDsc("SCAS\0",D_CMD|D_SIZE01|D_LONGFORM|D_NOREP|D_ALLFLAGS,DX_JE|DX_JB,1,0x000000FE,0x000000AE,0x00,[B_STRDEST|B_SHOWSIZE,B_ACC|B_PSEUDO,B_NONE,B_NONE]),
1029 AsmInstrDsc("SCASB\0",D_CMD|D_NOREP|D_ALLFLAGS,DX_JE|DX_JB,1,0x000000FF,0x000000AE,0x00,[B_STRDEST8|B_PSEUDO,B_AL|B_PSEUDO,B_NONE,B_NONE]),
1030 AsmInstrDsc("SCAS*\0",D_CMD|D_NOREP|D_ALLFLAGS|D_WILDCARD,DX_JE|DX_JB,1,0x000000FF,0x000000AF,0x00,[B_STRDEST|B_PSEUDO,B_ACC|B_PSEUDO,B_NONE,B_NONE]),
1031 AsmInstrDsc("SCAS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREPE|D_ALLFLAGS,0,1,0x000000FE,0x000000AE,0x00,[B_STRDEST|B_SHOWSIZE,B_ACC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1032 AsmInstrDsc("SCASB\0",D_STRING|D_MUSTREPE|D_ALLFLAGS,0,1,0x000000FF,0x000000AE,0x00,[B_STRDEST8|B_PSEUDO,B_AL|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1033 AsmInstrDsc("SCAS*\0",D_STRING|D_MUSTREPE|D_ALLFLAGS|D_WILDCARD,0,1,0x000000FF,0x000000AF,0x00,[B_STRDEST|B_PSEUDO,B_ACC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1034 AsmInstrDsc("SCAS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREPNE|D_ALLFLAGS,0,1,0x000000FE,0x000000AE,0x00,[B_STRDEST|B_SHOWSIZE,B_ACC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1035 AsmInstrDsc("SCASB\0",D_STRING|D_MUSTREPNE|D_ALLFLAGS,0,1,0x000000FF,0x000000AE,0x00,[B_STRDEST8|B_PSEUDO,B_AL|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1036 AsmInstrDsc("SCAS*\0",D_STRING|D_MUSTREPNE|D_ALLFLAGS|D_WILDCARD,0,1,0x000000FF,0x000000AF,0x00,[B_STRDEST|B_PSEUDO,B_ACC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1037 AsmInstrDsc("STOS\0",D_CMD|D_SIZE01|D_LONGFORM|D_NOREP,0,1,0x000000FE,0x000000AA,0x00,[B_STRDEST|B_SHOWSIZE|B_CHG,B_ACC|B_PSEUDO,B_NONE,B_NONE]),
1038 AsmInstrDsc("STOSB\0",D_CMD|D_NOREP,0,1,0x000000FF,0x000000AA,0x00,[B_STRDEST8|B_CHG|B_PSEUDO,B_AL|B_PSEUDO,B_NONE,B_NONE]),
1039 AsmInstrDsc("STOS*\0",D_CMD|D_NOREP|D_WILDCARD,0,1,0x000000FF,0x000000AB,0x00,[B_STRDEST|B_CHG|B_PSEUDO,B_ACC|B_PSEUDO,B_NONE,B_NONE]),
1040 AsmInstrDsc("STOS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREP,0,1,0x000000FE,0x000000AA,0x00,[B_STRDEST|B_SHOWSIZE|B_CHG,B_ACC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1041 AsmInstrDsc("STOSB\0",D_STRING|D_MUSTREP,0,1,0x000000FF,0x000000AA,0x00,[B_STRDEST8|B_CHG|B_PSEUDO,B_AL|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1042 AsmInstrDsc("STOS*\0",D_STRING|D_MUSTREP|D_WILDCARD,0,1,0x000000FF,0x000000AB,0x00,[B_STRDEST|B_CHG|B_PSEUDO,B_ACC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1043 AsmInstrDsc("STOS\0",D_STRING|D_SIZE01|D_LONGFORM|D_MUSTREPNE|D_UNDOC,0,1,0x000000FE,0x000000AA,0x00,[B_STRDEST|B_SHOWSIZE|B_CHG,B_ACC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1044 AsmInstrDsc("STOSB\0",D_STRING|D_MUSTREPNE|D_UNDOC,0,1,0x000000FF,0x000000AA,0x00,[B_STRDEST8|B_CHG|B_PSEUDO,B_AL|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1045 AsmInstrDsc("STOS*\0",D_STRING|D_MUSTREPNE|D_WILDCARD|D_UNDOC,0,1,0x000000FF,0x000000AB,0x00,[B_STRDEST|B_CHG|B_PSEUDO,B_ACC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1046 AsmInstrDsc("INS\0",D_IO|D_SIZE01|D_LONGFORM|D_NOREP|D_RARE,0,1,0x000000FE,0x0000006C,0x00,[B_STRDEST|B_SHOWSIZE|B_CHG,B_DXPORT|B_PORT,B_NONE,B_NONE]),
1047 AsmInstrDsc("INSB\0",D_IO|D_NOREP|D_RARE,0,1,0x000000FF,0x0000006C,0x00,[B_STRDEST8|B_CHG|B_PSEUDO,B_DXPORT|B_PORT|B_PSEUDO,B_NONE,B_NONE]),
1048 AsmInstrDsc("INS*\0",D_IO|D_NOREP|D_WILDCARD|D_RARE,0,1,0x000000FF,0x0000006D,0x00,[B_STRDEST|B_CHG|B_PSEUDO,B_DXPORT|B_PORT|B_PSEUDO,B_NONE,B_NONE]),
1049 AsmInstrDsc("INS\0",D_IO|D_SIZE01|D_LONGFORM|D_MUSTREP|D_RARE,0,1,0x000000FE,0x0000006C,0x00,[B_STRDEST|B_SHOWSIZE|B_CHG,B_DXPORT|B_PORT,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1050 AsmInstrDsc("INSB\0",D_IO|D_MUSTREP|D_RARE,0,1,0x000000FF,0x0000006C,0x00,[B_STRDEST8|B_CHG|B_PSEUDO,B_DXPORT|B_PORT|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1051 AsmInstrDsc("INS*\0",D_IO|D_MUSTREP|D_WILDCARD|D_RARE,0,1,0x000000FF,0x0000006D,0x00,[B_STRDEST|B_CHG|B_PSEUDO,B_DXPORT|B_PORT|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1052 AsmInstrDsc("INS\0",D_IO|D_SIZE01|D_LONGFORM|D_MUSTREPNE|D_UNDOC,0,1,0x000000FE,0x0000006C,0x00,[B_STRDEST|B_SHOWSIZE|B_CHG,B_DXPORT|B_PORT,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1053 AsmInstrDsc("INSB\0",D_IO|D_MUSTREPNE|D_UNDOC,0,1,0x000000FF,0x0000006C,0x00,[B_STRDEST8|B_CHG|B_PSEUDO,B_DXPORT|B_PORT|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1054 AsmInstrDsc("INS*\0",D_IO|D_MUSTREPNE|D_WILDCARD|D_UNDOC,0,1,0x000000FF,0x0000006D,0x00,[B_STRDEST|B_CHG|B_PSEUDO,B_DXPORT|B_PORT|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1055 AsmInstrDsc("OUTS\0",D_IO|D_SIZE01|D_LONGFORM|D_NOREP|D_RARE,0,1,0x000000FE,0x0000006E,0x00,[B_DXPORT|B_PORT,B_STRSRC|B_SHOWSIZE,B_NONE,B_NONE]),
1056 AsmInstrDsc("OUTSB\0",D_IO|D_NOREP|D_RARE,0,1,0x000000FF,0x0000006E,0x00,[B_DXPORT|B_PORT|B_PSEUDO,B_STRSRC8|B_PSEUDO,B_NONE,B_NONE]),
1057 AsmInstrDsc("OUTS*\0",D_IO|D_NOREP|D_WILDCARD|D_RARE,0,1,0x000000FF,0x0000006F,0x00,[B_DXPORT|B_PORT|B_PSEUDO,B_STRSRC|B_PSEUDO,B_NONE,B_NONE]),
1058 AsmInstrDsc("OUTS\0",D_IO|D_SIZE01|D_LONGFORM|D_MUSTREP|D_RARE,0,1,0x000000FE,0x0000006E,0x00,[B_DXPORT|B_PORT,B_STRSRC|B_SHOWSIZE,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1059 AsmInstrDsc("OUTSB\0",D_IO|D_MUSTREP|D_RARE,0,1,0x000000FF,0x0000006E,0x00,[B_DXPORT|B_PORT|B_PSEUDO,B_STRSRC8|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1060 AsmInstrDsc("OUTS*\0",D_IO|D_MUSTREP|D_WILDCARD|D_RARE,0,1,0x000000FF,0x0000006F,0x00,[B_DXPORT|B_PORT|B_PSEUDO,B_STRSRC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1061 AsmInstrDsc("OUTS\0",D_IO|D_SIZE01|D_LONGFORM|D_MUSTREPNE|D_UNDOC,0,1,0x000000FE,0x0000006E,0x00,[B_DXPORT|B_PORT,B_STRSRC|B_SHOWSIZE,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1062 AsmInstrDsc("OUTSB\0",D_IO|D_MUSTREPNE|D_UNDOC,0,1,0x000000FF,0x0000006E,0x00,[B_DXPORT|B_PORT|B_PSEUDO,B_STRSRC8|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1063 AsmInstrDsc("OUTS*\0",D_IO|D_MUSTREPNE|D_WILDCARD|D_UNDOC,0,1,0x000000FF,0x0000006F,0x00,[B_DXPORT|B_PORT|B_PSEUDO,B_STRSRC|B_PSEUDO,B_STRCNT|B_UPD|B_PSEUDO,B_NONE]),
1064 AsmInstrDsc("MOVBE\0",D_CMD|D_NOREP,0,3,0x00FFFFFF,0x00F0380F,0x00,[B_REG|B_CHG,B_INT|B_MEMONLY,B_NONE,B_NONE]),
1065 AsmInstrDsc("MOVBE\0",D_CMD|D_NOREP,0,3,0x00FFFFFF,0x00F1380F,0x00,[B_INT|B_MEMONLY|B_CHG,B_REG,B_NONE,B_NONE]),
1066 AsmInstrDsc("XGETBV\0",D_SYS|D_MUSTNONE|D_RARE,0,3,0x00FFFFFF,0x00D0010F,0x00,[B_EAX|B_CHG|B_PSEUDO,B_EDX|B_CHG|B_PSEUDO,B_ECX|B_PSEUDO,B_NONE]),
1067 AsmInstrDsc("XSETBV\0",D_PRIVILEGED|D_MUSTNONE|D_RARE,0,3,0x00FFFFFF,0x00D1010F,0x00,[B_EAX|B_PSEUDO,B_EDX|B_PSEUDO,B_ECX|B_PSEUDO,B_NONE]),
1068 AsmInstrDsc("XRSTOR\0",D_SYS|D_MUSTNONE|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0028AE0F,0x00,[B_ANYMEM|B_MEMONLY,B_EAX|B_PSEUDO,B_EDX|B_PSEUDO,B_NONE]),
1069 AsmInstrDsc("XSAVE\0",D_SYS|D_MUSTNONE|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0020AE0F,0x00,[B_ANYMEM|B_MEMONLY|B_CHG,B_EAX|B_PSEUDO,B_EDX|B_PSEUDO,B_NONE]),
1070 AsmInstrDsc("F2XM1\0",D_FPU,0,2,0x0000FFFF,0x0000F0D9,0x00,[B_ST0|B_CHG|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1071 AsmInstrDsc("FABS\0",D_FPU,0,2,0x0000FFFF,0x0000E1D9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1072 AsmInstrDsc("FCHS\0",D_FPU,0,2,0x0000FFFF,0x0000E0D9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1073 AsmInstrDsc("FCLEX\0",D_FPU,0,2,0x0000FFFF,0x0000E2DB,0x00,[B_FST|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1074 AsmInstrDsc("FCOMPP\0",D_FPU|D_FPUPOP2,0,2,0x0000FFFF,0x0000D9DE,0x00,[B_ST0|B_PSEUDO,B_ST1|B_PSEUDO,B_NONE,B_NONE]),
1075 AsmInstrDsc("FCOS\0",D_FPU,0,2,0x0000FFFF,0x0000FFD9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1076 AsmInstrDsc("FDECSTP\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000F6D9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1077 AsmInstrDsc("FINCSTP\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000F7D9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1078 AsmInstrDsc("FINIT\0",D_FPU,0,2,0x0000FFFF,0x0000E3DB,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1079 AsmInstrDsc("FLD1\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000E8D9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1080 AsmInstrDsc("FLDL2T\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000E9D9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1081 AsmInstrDsc("FLDL2E\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000EAD9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1082 AsmInstrDsc("FLDPI\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000EBD9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1083 AsmInstrDsc("FLDLG2\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000ECD9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1084 AsmInstrDsc("FLDLN2\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000EDD9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1085 AsmInstrDsc("FLDZ\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000EED9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1086 AsmInstrDsc("FNOP\0",D_FPU,0,2,0x0000FFFF,0x0000D0D9,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1087 AsmInstrDsc("FPATAN\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000F3D9,0x00,[B_ST1|B_UPD|B_PSEUDO,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1088 AsmInstrDsc("FPREM\0",D_FPU,0,2,0x0000FFFF,0x0000F8D9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_ST1|B_PSEUDO,B_NONE,B_NONE]),
1089 AsmInstrDsc("FPREM1\0",D_FPU,0,2,0x0000FFFF,0x0000F5D9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_ST1|B_PSEUDO,B_NONE,B_NONE]),
1090 AsmInstrDsc("FPTAN\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000F2D9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1091 AsmInstrDsc("FRNDINT\0",D_FPU,0,2,0x0000FFFF,0x0000FCD9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1092 AsmInstrDsc("FSCALE\0",D_FPU,0,2,0x0000FFFF,0x0000FDD9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_ST1|B_PSEUDO,B_NONE,B_NONE]),
1093 AsmInstrDsc("FSIN\0",D_FPU,0,2,0x0000FFFF,0x0000FED9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1094 AsmInstrDsc("FSINCOS\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000FBD9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1095 AsmInstrDsc("FSQRT\0",D_FPU,0,2,0x0000FFFF,0x0000FAD9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1096 AsmInstrDsc("FSTSW\0",D_FPU,0,2,0x0000FFFF,0x0000E0DF,0x00,[B_AX|B_CHG,B_FST|B_PSEUDO,B_NONE,B_NONE]),
1097 AsmInstrDsc("FTST\0",D_FPU,0,2,0x0000FFFF,0x0000E4D9,0x00,[B_ST0|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1098 AsmInstrDsc("FUCOMPP\0",D_FPU|D_FPUPOP2,0,2,0x0000FFFF,0x0000E9DA,0x00,[B_ST0|B_PSEUDO,B_ST1|B_PSEUDO,B_NONE,B_NONE]),
1099 AsmInstrDsc("FXAM\0",D_FPU,0,2,0x0000FFFF,0x0000E5D9,0x00,[B_ST0|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1100 AsmInstrDsc("FXTRACT\0",D_FPU|D_FPUPUSH,0,2,0x0000FFFF,0x0000F4D9,0x00,[B_ST0|B_UPD|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1101 AsmInstrDsc("FYL2X\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000F1D9,0x00,[B_ST1|B_UPD|B_PSEUDO,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1102 AsmInstrDsc("FYL2XP1\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000F9D9,0x00,[B_ST1|B_UPD|B_PSEUDO,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1103 AsmInstrDsc("FENI\0",D_FPU|D_RARE,0,2,0x0000FFFF,0x0000E0DB,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1104 AsmInstrDsc("FDISI\0",D_FPU|D_RARE,0,2,0x0000FFFF,0x0000E1DB,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1105 AsmInstrDsc("FADD\0",D_FPU,0,2,0x0000F8FF,0x0000C0D8,0x00,[B_ST0|B_UPD,B_ST,B_NONE,B_NONE]),
1106 AsmInstrDsc("FADD\0",D_FPU,0,2,0x0000F8FF,0x0000C0DC,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1107 AsmInstrDsc("FADDP\0",D_FPU|D_FPUPOP,0,2,0x0000F8FF,0x0000C0DE,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1108 AsmInstrDsc("FADDP\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000C1DE,0x00,[B_ST1|B_UPD|B_PSEUDO,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1109 AsmInstrDsc("FCMOVB\0",D_FPU|D_COND,0,2,0x0000F8FF,0x0000C0DA,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1110 AsmInstrDsc("FCMOVE\0",D_FPU|D_COND,0,2,0x0000F8FF,0x0000C8DA,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1111 AsmInstrDsc("FCMOVBE\0",D_FPU|D_COND,0,2,0x0000F8FF,0x0000D0DA,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1112 AsmInstrDsc("FCMOVU\0",D_FPU|D_COND,0,2,0x0000F8FF,0x0000D8DA,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1113 AsmInstrDsc("FCMOVNB\0",D_FPU|D_COND,0,2,0x0000F8FF,0x0000C0DB,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1114 AsmInstrDsc("FCMOVNE\0",D_FPU|D_COND,0,2,0x0000F8FF,0x0000C8DB,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1115 AsmInstrDsc("FCMOVNBE\0",D_FPU|D_COND,0,2,0x0000F8FF,0x0000D0DB,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1116 AsmInstrDsc("FCMOVNU\0",D_FPU|D_COND,0,2,0x0000F8FF,0x0000D8DB,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1117 AsmInstrDsc("FCOM\0",D_FPU,0,2,0x0000F8FF,0x0000D0D8,0x00,[B_ST0|B_PSEUDO,B_ST,B_NONE,B_NONE]),
1118 AsmInstrDsc("FCOM\0",D_FPU,0,2,0x0000FFFF,0x0000D1D8,0x00,[B_ST0|B_PSEUDO,B_ST1|B_PSEUDO,B_NONE,B_NONE]),
1119 AsmInstrDsc("FCOMP\0",D_FPU|D_FPUPOP,0,2,0x0000F8FF,0x0000D8D8,0x00,[B_ST0|B_PSEUDO,B_ST,B_NONE,B_NONE]),
1120 AsmInstrDsc("FCOMP\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000D9D8,0x00,[B_ST0|B_PSEUDO,B_ST1|B_PSEUDO,B_NONE,B_NONE]),
1121 AsmInstrDsc("FCOMI\0",D_FPU|D_FLAGSZPC,0,2,0x0000F8FF,0x0000F0DB,0x00,[B_ST0,B_ST,B_NONE,B_NONE]),
1122 AsmInstrDsc("FCOMIP\0",D_FPU|D_FLAGSZPC|D_FPUPOP,0,2,0x0000F8FF,0x0000F0DF,0x00,[B_ST0,B_ST,B_NONE,B_NONE]),
1123 AsmInstrDsc("FUCOMI\0",D_FPU|D_FLAGSZPC,0,2,0x0000F8FF,0x0000E8DB,0x00,[B_ST0,B_ST,B_NONE,B_NONE]),
1124 AsmInstrDsc("FUCOMIP\0",D_FPU|D_FLAGSZPC|D_FPUPOP,0,2,0x0000F8FF,0x0000E8DF,0x00,[B_ST0,B_ST,B_NONE,B_NONE]),
1125 AsmInstrDsc("FDIV\0",D_FPU,0,2,0x0000F8FF,0x0000F0D8,0x00,[B_ST0|B_UPD,B_ST,B_NONE,B_NONE]),
1126 AsmInstrDsc("FDIV\0",D_FPU,0,2,0x0000F8FF,0x0000F8DC,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1127 AsmInstrDsc("FDIVP\0",D_FPU|D_FPUPOP,0,2,0x0000F8FF,0x0000F8DE,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1128 AsmInstrDsc("FDIVP\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000F9DE,0x00,[B_ST1|B_UPD|B_PSEUDO,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1129 AsmInstrDsc("FDIVR\0",D_FPU,0,2,0x0000F8FF,0x0000F8D8,0x00,[B_ST0|B_UPD,B_ST,B_NONE,B_NONE]),
1130 AsmInstrDsc("FDIVR\0",D_FPU,0,2,0x0000F8FF,0x0000F0DC,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1131 AsmInstrDsc("FDIVRP\0",D_FPU|D_FPUPOP,0,2,0x0000F8FF,0x0000F0DE,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1132 AsmInstrDsc("FDIVRP\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000F1DE,0x00,[B_ST1|B_UPD|B_PSEUDO,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1133 AsmInstrDsc("FFREE\0",D_FPU,0,2,0x0000F8FF,0x0000C0DD,0x00,[B_ST,B_NONE,B_NONE,B_NONE]),
1134 AsmInstrDsc("FFREEP\0",D_FPU|D_FPUPOP|D_UNDOC,0,2,0x0000F8FF,0x0000C0DF,0x00,[B_ST,B_NONE,B_NONE,B_NONE]),
1135 AsmInstrDsc("FLD\0",D_FPU|D_FPUPUSH,0,2,0x0000F8FF,0x0000C0D9,0x00,[B_ST,B_NONE,B_NONE,B_NONE]),
1136 AsmInstrDsc("FMUL\0",D_FPU,0,2,0x0000F8FF,0x0000C8D8,0x00,[B_ST0|B_UPD,B_ST,B_NONE,B_NONE]),
1137 AsmInstrDsc("FMUL\0",D_FPU,0,2,0x0000F8FF,0x0000C8DC,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1138 AsmInstrDsc("FMULP\0",D_FPU|D_FPUPOP,0,2,0x0000F8FF,0x0000C8DE,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1139 AsmInstrDsc("FMULP\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000C9DE,0x00,[B_ST1|B_UPD|B_PSEUDO,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1140 AsmInstrDsc("FST\0",D_FPU,0,2,0x0000F8FF,0x0000D0DD,0x00,[B_ST|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1141 AsmInstrDsc("FSTP\0",D_FPU|D_FPUPOP,0,2,0x0000F8FF,0x0000D8DD,0x00,[B_ST|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1142 AsmInstrDsc("FSUB\0",D_FPU,0,2,0x0000F8FF,0x0000E0D8,0x00,[B_ST0|B_UPD,B_ST,B_NONE,B_NONE]),
1143 AsmInstrDsc("FSUB\0",D_FPU,0,2,0x0000F8FF,0x0000E8DC,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1144 AsmInstrDsc("FSUBP\0",D_FPU|D_FPUPOP,0,2,0x0000F8FF,0x0000E8DE,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1145 AsmInstrDsc("FSUBP\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000E9DE,0x00,[B_ST1|B_UPD|B_PSEUDO,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1146 AsmInstrDsc("FSUBR\0",D_FPU,0,2,0x0000F8FF,0x0000E8D8,0x00,[B_ST0|B_UPD,B_ST,B_NONE,B_NONE]),
1147 AsmInstrDsc("FSUBR\0",D_FPU,0,2,0x0000F8FF,0x0000E0DC,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1148 AsmInstrDsc("FSUBRP\0",D_FPU|D_FPUPOP,0,2,0x0000F8FF,0x0000E0DE,0x00,[B_ST|B_UPD,B_ST0,B_NONE,B_NONE]),
1149 AsmInstrDsc("FSUBRP\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000E1DE,0x00,[B_ST1|B_UPD|B_PSEUDO,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1150 AsmInstrDsc("FUCOM\0",D_FPU,0,2,0x0000F8FF,0x0000E0DD,0x00,[B_ST0|B_PSEUDO,B_ST,B_NONE,B_NONE]),
1151 AsmInstrDsc("FUCOM\0",D_FPU,0,2,0x0000FFFF,0x0000E1DD,0x00,[B_ST0|B_PSEUDO,B_ST1|B_PSEUDO,B_NONE,B_NONE]),
1152 AsmInstrDsc("FUCOMP\0",D_FPU|D_FPUPOP,0,2,0x0000F8FF,0x0000E8DD,0x00,[B_ST0|B_PSEUDO,B_ST,B_NONE,B_NONE]),
1153 AsmInstrDsc("FUCOMP\0",D_FPU|D_FPUPOP,0,2,0x0000FFFF,0x0000E9DD,0x00,[B_ST0|B_PSEUDO,B_ST1|B_PSEUDO,B_NONE,B_NONE]),
1154 AsmInstrDsc("FXCH\0",D_FPU,0,2,0x0000F8FF,0x0000C8D9,0x00,[B_ST0|B_CHG|B_PSEUDO,B_ST|B_CHG,B_NONE,B_NONE]),
1155 AsmInstrDsc("FXCH\0",D_FPU,0,2,0x0000FFFF,0x0000C9D9,0x00,[B_ST0|B_CHG|B_PSEUDO,B_ST1|B_CHG|B_PSEUDO,B_NONE,B_NONE]),
1156 AsmInstrDsc("FADD\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000000D8,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT32|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1157 AsmInstrDsc("FADD\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000000DC,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT64|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1158 AsmInstrDsc("FIADD\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000000DA,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1159 AsmInstrDsc("FIADD\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000000DE,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1160 AsmInstrDsc("FBLD\0",D_FPU|D_MEMORY|D_FPUPUSH|D_RARE,0,1,0x000038FF,0x000020DF,0x00,[B_BCD|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1161 AsmInstrDsc("FBSTP\0",D_FPU|D_MEMORY|D_FPUPOP|D_RARE,0,1,0x000038FF,0x000030DF,0x00,[B_BCD|B_MEMORY|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1162 AsmInstrDsc("FCOM\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000010D8,0x00,[B_ST0|B_PSEUDO,B_FLOAT32|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1163 AsmInstrDsc("FCOM\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000010DC,0x00,[B_ST0|B_PSEUDO,B_FLOAT64|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1164 AsmInstrDsc("FCOMP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000018D8,0x00,[B_ST0|B_PSEUDO,B_FLOAT32|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1165 AsmInstrDsc("FCOMP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000018DC,0x00,[B_ST0|B_PSEUDO,B_FLOAT64|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1166 AsmInstrDsc("FDIV\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000030D8,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT32|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1167 AsmInstrDsc("FDIV\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000030DC,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT64|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1168 AsmInstrDsc("FIDIV\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000030DA,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1169 AsmInstrDsc("FIDIV\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000030DE,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1170 AsmInstrDsc("FDIVR\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000038D8,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT32|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1171 AsmInstrDsc("FDIVR\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000038DC,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT64|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1172 AsmInstrDsc("FIDIVR\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000038DA,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1173 AsmInstrDsc("FIDIVR\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000038DE,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1174 AsmInstrDsc("FICOM\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000010DE,0x00,[B_ST0|B_PSEUDO,B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1175 AsmInstrDsc("FICOM\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000010DA,0x00,[B_ST0|B_PSEUDO,B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1176 AsmInstrDsc("FICOMP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000018DE,0x00,[B_ST0|B_PSEUDO,B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1177 AsmInstrDsc("FICOMP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000018DA,0x00,[B_ST0|B_PSEUDO,B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1178 AsmInstrDsc("FILD\0",D_FPU|D_MEMORY|D_FPUPUSH,0,1,0x000038FF,0x000000DF,0x00,[B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE,B_NONE]),
1179 AsmInstrDsc("FILD\0",D_FPU|D_MEMORY|D_FPUPUSH,0,1,0x000038FF,0x000000DB,0x00,[B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE,B_NONE]),
1180 AsmInstrDsc("FILD\0",D_FPU|D_MEMORY|D_FPUPUSH,0,1,0x000038FF,0x000028DF,0x00,[B_INT64|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE,B_NONE]),
1181 AsmInstrDsc("FIST\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000010DF,0x00,[B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1182 AsmInstrDsc("FIST\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000010DB,0x00,[B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1183 AsmInstrDsc("FISTP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000018DF,0x00,[B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1184 AsmInstrDsc("FISTP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000018DB,0x00,[B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1185 AsmInstrDsc("FISTP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000038DF,0x00,[B_INT64|B_SIGNED|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1186 AsmInstrDsc("FISTTP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000008DF,0x00,[B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1187 AsmInstrDsc("FISTTP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000008DB,0x00,[B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1188 AsmInstrDsc("FISTTP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000008DD,0x00,[B_INT64|B_SIGNED|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1189 AsmInstrDsc("FLD\0",D_FPU|D_MEMORY|D_FPUPUSH,0,1,0x000038FF,0x000000D9,0x00,[B_FLOAT32|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE,B_NONE]),
1190 AsmInstrDsc("FLD\0",D_FPU|D_MEMORY|D_FPUPUSH,0,1,0x000038FF,0x000000DD,0x00,[B_FLOAT64|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE,B_NONE]),
1191 AsmInstrDsc("FLD\0",D_FPU|D_MEMORY|D_FPUPUSH,0,1,0x000038FF,0x000028DB,0x00,[B_FLOAT80|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE,B_NONE]),
1192 AsmInstrDsc("FLDCW\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000028D9,0x00,[B_FCW|B_CHG|B_PSEUDO,B_INT16|B_BINARY|B_MEMORY,B_NONE,B_NONE]),
1193 AsmInstrDsc("FLDENV\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000020D9,0x00,[B_LONGDATA|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1194 AsmInstrDsc("FMUL\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000008D8,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT32|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1195 AsmInstrDsc("FMUL\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000008DC,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT64|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1196 AsmInstrDsc("FIMUL\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000008DA,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1197 AsmInstrDsc("FIMUL\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000008DE,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1198 AsmInstrDsc("FRSTOR\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000020DD,0x00,[B_LONGDATA|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1199 AsmInstrDsc("FSAVE\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000030DD,0x00,[B_LONGDATA|B_MEMORY|B_CHG,B_NONE,B_NONE,B_NONE]),
1200 AsmInstrDsc("FST\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000010D9,0x00,[B_FLOAT32|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1201 AsmInstrDsc("FST\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000010DD,0x00,[B_FLOAT64|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1202 AsmInstrDsc("FSTP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000018D9,0x00,[B_FLOAT32|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1203 AsmInstrDsc("FSTP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000018DD,0x00,[B_FLOAT64|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1204 AsmInstrDsc("FSTP\0",D_FPU|D_MEMORY|D_FPUPOP,0,1,0x000038FF,0x000038DB,0x00,[B_FLOAT80|B_MEMORY|B_SHOWSIZE|B_CHG,B_ST0|B_PSEUDO,B_NONE,B_NONE]),
1205 AsmInstrDsc("FSTCW\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000038D9,0x00,[B_INT16|B_BINARY|B_MEMORY|B_CHG,B_FCW|B_PSEUDO,B_NONE,B_NONE]),
1206 AsmInstrDsc("FSTENV\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000030D9,0x00,[B_LONGDATA|B_MEMORY|B_CHG,B_NONE,B_NONE,B_NONE]),
1207 AsmInstrDsc("FSTSW\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000038DD,0x00,[B_INT16|B_BINARY|B_MEMORY|B_CHG,B_FST|B_PSEUDO,B_NONE,B_NONE]),
1208 AsmInstrDsc("FSUB\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000020D8,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT32|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1209 AsmInstrDsc("FSUB\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000020DC,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT64|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1210 AsmInstrDsc("FISUB\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000020DA,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1211 AsmInstrDsc("FISUB\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000020DE,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1212 AsmInstrDsc("FSUBR\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000028D8,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT32|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1213 AsmInstrDsc("FSUBR\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000028DC,0x00,[B_ST0|B_UPD|B_PSEUDO,B_FLOAT64|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1214 AsmInstrDsc("FISUBR\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000028DA,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT32|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1215 AsmInstrDsc("FISUBR\0",D_FPU|D_MEMORY,0,1,0x000038FF,0x000028DE,0x00,[B_ST0|B_UPD|B_PSEUDO,B_INT16|B_SIGNED|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1216 AsmInstrDsc("FSETPM\0",D_FPU|D_UNDOC,0,2,0x0000FFFF,0x0000E4DB,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1217 AsmInstrDsc("ADDPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000580F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1218 AsmInstrDsc("VADDPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000058,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1219 AsmInstrDsc("ADDPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000580F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1220 AsmInstrDsc("VADDPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000058,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1221 AsmInstrDsc("ADDSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000580F,0x00,[B_SREGF64L|B_UPD,B_SSEF64L,B_NONE,B_NONE]),
1222 AsmInstrDsc("VADDSD\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000058,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_SSEF64L,B_NONE]),
1223 AsmInstrDsc("ADDSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000580F,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_NONE,B_NONE]),
1224 AsmInstrDsc("VADDSS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000058,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF32L,B_NONE]),
1225 AsmInstrDsc("ADDSUBPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000D00F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1226 AsmInstrDsc("VADDSUBPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x000000D0,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1227 AsmInstrDsc("ADDSUBPS\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000D00F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1228 AsmInstrDsc("VADDSUBPS\0",D_AVX|D_MUSTF2,DX_VEX|DX_LBOTH,1,0x000000FF,0x000000D0,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1229 AsmInstrDsc("ANDPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000540F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1230 AsmInstrDsc("VANDPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000054,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1231 AsmInstrDsc("ANDPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000540F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1232 AsmInstrDsc("VANDPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000054,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1233 AsmInstrDsc("ANDNPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000550F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1234 AsmInstrDsc("VANDNPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000055,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1235 AsmInstrDsc("ANDNPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000550F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1236 AsmInstrDsc("VANDNPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000055,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1237 AsmInstrDsc("CMP*PD\0",D_SSE|D_POSTBYTE|D_MUST66|D_WILDCARD,0,2,0x0000FFFF,0x0000C20F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1238 AsmInstrDsc("VCMP*PD\0",D_AVX|D_POSTBYTE|D_MUST66|D_WILDCARD,DX_VEX|DX_LBOTH,1,0x000000FF,0x000000C2,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1239 AsmInstrDsc("CMPPD\0",D_SSE|D_MUST66|D_SUSPICIOUS,0,2,0x0000FFFF,0x0000C20F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_CONST8,B_NONE]),
1240 AsmInstrDsc("VCMPPD\0",D_AVX|D_MUST66|D_SUSPICIOUS,DX_VEX|DX_LBOTH,1,0x000000FF,0x000000C2,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_CONST8]),
1241 AsmInstrDsc("CMP*PS\0",D_SSE|D_POSTBYTE|D_MUSTNONE|D_WILDCARD,0,2,0x0000FFFF,0x0000C20F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1242 AsmInstrDsc("VCMP*PS\0",D_AVX|D_POSTBYTE|D_MUSTNONE|D_WILDCARD,DX_VEX|DX_LBOTH,1,0x000000FF,0x000000C2,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1243 AsmInstrDsc("CMPPS\0",D_SSE|D_MUSTNONE|D_SUSPICIOUS,0,2,0x0000FFFF,0x0000C20F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_CONST8,B_NONE]),
1244 AsmInstrDsc("VCMPPS\0",D_AVX|D_MUSTNONE|D_SUSPICIOUS,DX_VEX|DX_LBOTH,1,0x000000FF,0x000000C2,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_CONST8]),
1245 AsmInstrDsc("CMP*SD\0",D_SSE|D_POSTBYTE|D_MUSTF2|D_WILDCARD,0,2,0x0000FFFF,0x0000C20F,0x00,[B_SREGF64L|B_UPD,B_SSEF64L,B_NONE,B_NONE]),
1246 AsmInstrDsc("VCMP*SD\0",D_AVX|D_POSTBYTE|D_MUSTF2|D_WILDCARD,DX_VEX|DX_IGNOREL,1,0x000000FF,0x000000C2,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_SSEF64L,B_NONE]),
1247 AsmInstrDsc("CMPSD\0",D_SSE|D_MUSTF2|D_SUSPICIOUS,0,2,0x0000FFFF,0x0000C20F,0x00,[B_SREGF64L|B_UPD,B_SVEXF64L,B_CONST8,B_NONE]),
1248 AsmInstrDsc("VCMPSD\0",D_AVX|D_MUSTF2|D_SUSPICIOUS,DX_VEX|DX_IGNOREL,1,0x000000FF,0x000000C2,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_SSEF64L,B_CONST8]),
1249 AsmInstrDsc("CMP*SS\0",D_SSE|D_POSTBYTE|D_MUSTF3|D_WILDCARD,0,2,0x0000FFFF,0x0000C20F,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_NONE,B_NONE]),
1250 AsmInstrDsc("VCMP*SS\0",D_AVX|D_POSTBYTE|D_MUSTF3|D_WILDCARD,DX_VEX|DX_IGNOREL,1,0x000000FF,0x000000C2,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF32L,B_NONE]),
1251 AsmInstrDsc("CMPSS\0",D_SSE|D_MUSTF3|D_SUSPICIOUS,0,2,0x0000FFFF,0x0000C20F,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_CONST8,B_NONE]),
1252 AsmInstrDsc("VCMPSS\0",D_AVX|D_MUSTF3|D_SUSPICIOUS,DX_VEX|DX_IGNOREL,1,0x000000FF,0x000000C2,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF32L,B_CONST8]),
1253 AsmInstrDsc("COMISD\0",D_SSE|D_MUST66|D_ALLFLAGS,0,2,0x0000FFFF,0x00002F0F,0x00,[B_SREGF64L,B_SSEF64L,B_NONE,B_NONE]),
1254 AsmInstrDsc("VCOMISD\0",D_AVX|D_MUST66|D_ALLFLAGS,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x0000002F,0x00,[B_SREGF64L,B_SSEF64L,B_NONE,B_NONE]),
1255 AsmInstrDsc("COMISS\0",D_SSE|D_MUSTNONE|D_ALLFLAGS,0,2,0x0000FFFF,0x00002F0F,0x00,[B_SREGF32L,B_SSEF32L,B_NONE,B_NONE]),
1256 AsmInstrDsc("VCOMISS\0",D_AVX|D_MUSTNONE|D_ALLFLAGS,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x0000002F,0x00,[B_SREGF32L,B_SSEF32L,B_NONE,B_NONE]),
1257 AsmInstrDsc("CVTDQ2PD\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000E60F,0x00,[B_SREGF64x2|B_CHG,B_SSEI32x2L,B_NONE,B_NONE]),
1258 AsmInstrDsc("VCVTDQ2PD\0",D_AVX|D_MUSTF3|D_REGISTER,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x000000E6,0x00,[B_SREGF64x2|B_CHG,B_SSEI32x2L|B_REGISTER|B_NOVEXSIZE|B_SHOWSIZE,B_NONE,B_NONE]),
1259 AsmInstrDsc("VCVTDQ2PD\0",D_AVX|D_MUSTF3|D_MEMORY,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x000000E6,0x00,[B_SREGF64x2|B_CHG,B_SSEI32x2L|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1260 AsmInstrDsc("CVTDQ2PS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x00005B0F,0x00,[B_SREGF32x4|B_CHG,B_SSEI32x4,B_NONE,B_NONE]),
1261 AsmInstrDsc("VCVTDQ2PS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000005B,0x00,[B_SREGF32x4|B_CHG,B_SSEI32x4,B_NONE,B_NONE]),
1262 AsmInstrDsc("CVTPD2DQ\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000E60F,0x00,[B_SREGI32x2L|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1263 AsmInstrDsc("VCVTPD2DQ\0",D_AVX|D_MUSTF2,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x000000E6,0x00,[B_SREGI32x2L|B_NOVEXSIZE|B_CHG,B_SSEF64x2|B_SHOWSIZE,B_NONE,B_NONE]),
1264 AsmInstrDsc("CVTPD2PI\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00002D0F,0x00,[B_MREG32x2|B_SIGNED|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1265 AsmInstrDsc("CVTPD2PS\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00005A0F,0x00,[B_SREGF32x2L|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1266 AsmInstrDsc("VCVTPD2PS\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000005A,0x00,[B_SREGF32x2L|B_NOVEXSIZE|B_CHG,B_SSEF64x2|B_SHOWSIZE,B_NONE,B_NONE]),
1267 AsmInstrDsc("CVTPI2PD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00002A0F,0x00,[B_SREGF64x2|B_CHG,B_MMX32x2|B_SIGNED,B_NONE,B_NONE]),
1268 AsmInstrDsc("CVTPI2PS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x00002A0F,0x00,[B_SREGF32x2L|B_CHG,B_MMX32x2|B_SIGNED,B_NONE,B_NONE]),
1269 AsmInstrDsc("CVTPS2DQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00005B0F,0x00,[B_SREGI32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1270 AsmInstrDsc("VCVTPS2DQ\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000005B,0x00,[B_SREGI32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1271 AsmInstrDsc("CVTPS2PD\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x00005A0F,0x00,[B_SREGF64x2|B_CHG,B_SSEF32x2L,B_NONE,B_NONE]),
1272 AsmInstrDsc("VCVTPS2PD\0",D_AVX|D_MUSTNONE|D_REGISTER,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000005A,0x00,[B_SREGF64x2|B_CHG,B_SSEF32x2L|B_REGISTER|B_NOVEXSIZE|B_SHOWSIZE,B_NONE,B_NONE]),
1273 AsmInstrDsc("VCVTPS2PD\0",D_AVX|D_MUSTNONE|D_MEMORY,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000005A,0x00,[B_SREGF64x2|B_CHG,B_SSEF32x2L|B_MEMORY|B_SHOWSIZE,B_NONE,B_NONE]),
1274 AsmInstrDsc("CVTPS2PI\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x00002D0F,0x00,[B_MREG32x2|B_CHG,B_SSEF32x2L,B_NONE,B_NONE]),
1275 AsmInstrDsc("CVTSD2SI\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00002D0F,0x00,[B_REG32|B_CHG,B_SSEF64L,B_NONE,B_NONE]),
1276 AsmInstrDsc("VCVTSD2SI\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x0000002D,0x00,[B_REG32|B_CHG,B_SSEF64L,B_NONE,B_NONE]),
1277 AsmInstrDsc("CVTSD2SS\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00005A0F,0x00,[B_SREGF32L|B_CHG,B_SSEF64L,B_NONE,B_NONE]),
1278 AsmInstrDsc("VCVTSD2SS\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005A,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF64L,B_NONE]),
1279 AsmInstrDsc("CVTSI2SD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00002A0F,0x00,[B_SREGF64L|B_CHG,B_INT32|B_SIGNED,B_NONE,B_NONE]),
1280 AsmInstrDsc("VCVTSI2SD\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000002A,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_INT32|B_SIGNED,B_NONE]),
1281 AsmInstrDsc("CVTSI2SS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00002A0F,0x00,[B_SREGF32L|B_CHG,B_INT32|B_SIGNED,B_NONE,B_NONE]),
1282 AsmInstrDsc("VCVTSI2SS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000002A,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_INT32|B_SIGNED,B_NONE]),
1283 AsmInstrDsc("CVTSS2SD\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00005A0F,0x00,[B_SREGF64L|B_CHG,B_SSEF32L,B_NONE,B_NONE]),
1284 AsmInstrDsc("VCVTSS2SD\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005A,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_SSEF32L,B_NONE]),
1285 AsmInstrDsc("CVTSS2SI\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00002D0F,0x00,[B_REG32|B_CHG,B_SSEF32L,B_NONE,B_NONE]),
1286 AsmInstrDsc("VCVTSS2SI\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x0000002D,0x00,[B_REG32|B_CHG,B_SSEF32L,B_NONE,B_NONE]),
1287 AsmInstrDsc("CVTTPD2PI\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00002C0F,0x00,[B_MREG32x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1288 AsmInstrDsc("CVTTPD2DQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000E60F,0x00,[B_SREGI32x2L|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1289 AsmInstrDsc("VCVTTPD2DQ\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x000000E6,0x00,[B_SREGI32x2L|B_NOVEXSIZE|B_CHG,B_SSEF64x2|B_SHOWSIZE,B_NONE,B_NONE]),
1290 AsmInstrDsc("CVTTPS2DQ\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00005B0F,0x00,[B_SREGI32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1291 AsmInstrDsc("VCVTTPS2DQ\0",D_AVX|D_MUSTF3,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000005B,0x00,[B_SREGI32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1292 AsmInstrDsc("CVTTPS2PI\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x00002C0F,0x00,[B_MREG32x2|B_CHG,B_SSEF32x2L,B_NONE,B_NONE]),
1293 AsmInstrDsc("CVTTSD2SI\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00002C0F,0x00,[B_REG32|B_CHG,B_SSEF64L,B_NONE,B_NONE]),
1294 AsmInstrDsc("VCVTTSD2SI\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x0000002C,0x00,[B_REG32|B_CHG,B_SSEF64L,B_NONE,B_NONE]),
1295 AsmInstrDsc("CVTTSS2SI\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00002C0F,0x00,[B_REG32|B_CHG,B_SSEF32L,B_NONE,B_NONE]),
1296 AsmInstrDsc("VCVTTSS2SI\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x0000002C,0x00,[B_REG32|B_CHG,B_SSEF32L,B_NONE,B_NONE]),
1297 AsmInstrDsc("DIVPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00005E0F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1298 AsmInstrDsc("VDIVPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000005E,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1299 AsmInstrDsc("DIVPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x00005E0F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1300 AsmInstrDsc("VDIVPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000005E,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1301 AsmInstrDsc("DIVSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00005E0F,0x00,[B_SREGF64L|B_UPD,B_SSEF64L,B_NONE,B_NONE]),
1302 AsmInstrDsc("VDIVSD\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005E,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_SSEF64L,B_NONE]),
1303 AsmInstrDsc("DIVSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00005E0F,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_NONE,B_NONE]),
1304 AsmInstrDsc("VDIVSS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005E,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF32L,B_NONE]),
1305 AsmInstrDsc("HADDPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00007C0F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1306 AsmInstrDsc("VHADDPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000007C,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1307 AsmInstrDsc("HADDPS\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00007C0F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1308 AsmInstrDsc("VHADDPS\0",D_AVX|D_MUSTF2,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000007C,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1309 AsmInstrDsc("HSUBPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00007D0F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1310 AsmInstrDsc("VHSUBPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000007D,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1311 AsmInstrDsc("HSUBPS\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00007D0F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1312 AsmInstrDsc("VHSUBPS\0",D_AVX|D_MUSTF2,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000007D,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1313 AsmInstrDsc("LDDQU\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000F00F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1314 AsmInstrDsc("VLDDQU\0",D_AVX|D_MUSTF2,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x000000F0,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1315 AsmInstrDsc("LDMXCSR\0",D_CMD|D_MEMORY,0,2,0x0038FFFF,0x0010AE0F,0x00,[B_MXCSR|B_CHG|B_PSEUDO,B_INT32|B_BINARY|B_MEMORY,B_NONE,B_NONE]),
1316 AsmInstrDsc("VLDMXCSR\0",D_CMD|D_MEMORY,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000038FF,0x000010AE,0x00,[B_MXCSR|B_CHG|B_PSEUDO,B_INT32|B_BINARY|B_MEMORY,B_NONE,B_NONE]),
1317 AsmInstrDsc("VSTMXCSR\0",D_CMD|D_MEMORY,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000038FF,0x000018AE,0x00,[B_INT32|B_BINARY|B_MEMONLY|B_NOESP|B_SHOWSIZE|B_CHG,B_MXCSR|B_PSEUDO,B_NONE,B_NONE]),
1318 AsmInstrDsc("MASKMOVDQU\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00C0FFFF,0x00C0F70F,0x00,[B_SSEI8x16DI|B_UPD|B_PSEUDO,B_SREGI8x16|B_BINARY,B_SSEI8x16|B_REGISTER,B_NONE]),
1319 AsmInstrDsc("VMASKMOVDQU\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x0000C0FF,0x0000C0F7,0x00,[B_SSEI8x16DI|B_UPD|B_PSEUDO,B_SREGI8x16|B_BINARY,B_SSEI8x16|B_REGISTER,B_NONE]),
1320 AsmInstrDsc("MASKMOVQ\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00C0FFFF,0x00C0F70F,0x00,[B_MMX8x8DI|B_UPD|B_PSEUDO,B_MREG8x8,B_MMX8x8|B_REGISTER,B_NONE]),
1321 AsmInstrDsc("MAXPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00005F0F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1322 AsmInstrDsc("VMAXPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000005F,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1323 AsmInstrDsc("MAXPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x00005F0F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1324 AsmInstrDsc("VMAXPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000005F,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1325 AsmInstrDsc("MAXSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00005F0F,0x00,[B_SREGF64L|B_UPD,B_SSEF64L,B_NONE,B_NONE]),
1326 AsmInstrDsc("VMAXSD\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005F,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_SSEF64L,B_NONE]),
1327 AsmInstrDsc("MAXSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00005F0F,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_NONE,B_NONE]),
1328 AsmInstrDsc("VMAXSS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005F,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF32L,B_NONE]),
1329 AsmInstrDsc("MFENCE\0",D_SSE,0,3,0x00FFFFFF,0x00F0AE0F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1330 AsmInstrDsc("MINPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00005D0F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1331 AsmInstrDsc("VMINPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000005D,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1332 AsmInstrDsc("MINPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x00005D0F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1333 AsmInstrDsc("VMINPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000005D,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1334 AsmInstrDsc("MINSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00005D0F,0x00,[B_SREGF64L|B_UPD,B_SSEF64L,B_NONE,B_NONE]),
1335 AsmInstrDsc("VMINSD\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005D,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_SSEF64L,B_NONE]),
1336 AsmInstrDsc("MINSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00005D0F,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_NONE,B_NONE]),
1337 AsmInstrDsc("VMINSS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005D,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF32L,B_NONE]),
1338 AsmInstrDsc("MOVAPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000280F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1339 AsmInstrDsc("VMOVAPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000028,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1340 AsmInstrDsc("MOVAPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000290F,0x00,[B_SSEF64x2|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1341 AsmInstrDsc("VMOVAPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000029,0x00,[B_SSEF64x2|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1342 AsmInstrDsc("MOVAPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000280F,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1343 AsmInstrDsc("VMOVAPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000028,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1344 AsmInstrDsc("MOVAPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000290F,0x00,[B_SSEF32x4|B_CHG,B_SREGF32x4,B_NONE,B_NONE]),
1345 AsmInstrDsc("VMOVAPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000029,0x00,[B_SSEF32x4|B_CHG,B_SREGF32x4,B_NONE,B_NONE]),
1346 AsmInstrDsc("MOVD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x00006E0F,0x00,[B_MREG32x2|B_CHG,B_INT32,B_NONE,B_NONE]),
1347 AsmInstrDsc("MOVD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x00007E0F,0x00,[B_INT32|B_CHG,B_MREG32x2,B_NONE,B_NONE]),
1348 AsmInstrDsc("MOVD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00006E0F,0x00,[B_SREGI32x2L|B_CHG,B_INT32,B_NONE,B_NONE]),
1349 AsmInstrDsc("VMOVD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x0000006E,0x00,[B_SREGI32x2L|B_CHG,B_INT32,B_NONE,B_NONE]),
1350 AsmInstrDsc("MOVD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00007E0F,0x00,[B_INT32|B_CHG,B_SREGI32L,B_NONE,B_NONE]),
1351 AsmInstrDsc("VMOVD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x0000007E,0x00,[B_INT32|B_CHG,B_SREGI32L,B_NONE,B_NONE]),
1352 AsmInstrDsc("MOVDDUP\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000120F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64L,B_NONE,B_NONE]),
1353 AsmInstrDsc("VMOVDDUP\0",D_AVX|D_MUSTF2,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000012,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1354 AsmInstrDsc("MOVDQA\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00006F0F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1355 AsmInstrDsc("VMOVDQA\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000006F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1356 AsmInstrDsc("MOVDQA\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00007F0F,0x00,[B_SSEF64x2|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1357 AsmInstrDsc("VMOVDQA\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000007F,0x00,[B_SSEF64x2|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1358 AsmInstrDsc("MOVDQU\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00006F0F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1359 AsmInstrDsc("VMOVDQU\0",D_AVX|D_MUSTF3,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000006F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1360 AsmInstrDsc("MOVDQU\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00007F0F,0x00,[B_SSEF64x2|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1361 AsmInstrDsc("VMOVDQU\0",D_AVX|D_MUSTF3,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000007F,0x00,[B_SSEF64x2|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1362 AsmInstrDsc("MOVDQ2Q\0",D_MMX|D_MUSTF2|D_REGISTER,0,2,0x00C0FFFF,0x00C0D60F,0x00,[B_MREG32x2|B_CHG,B_SSEI32x2L|B_REGISTER,B_NONE,B_NONE]),
1363 AsmInstrDsc("MOVHLPS\0",D_SSE|D_MUSTNONE|D_REGISTER,0,2,0x00C0FFFF,0x00C0120F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4|B_REGISTER,B_NONE,B_NONE]),
1364 AsmInstrDsc("VMOVHLPS\0",D_AVX|D_MUSTNONE|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000C0FF,0x0000C012,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4|B_REGISTER,B_NONE]),
1365 AsmInstrDsc("MOVHPD\0",D_SSE|D_MUST66|D_MEMORY,0,2,0x0000FFFF,0x0000160F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64L|B_MEMORY,B_NONE,B_NONE]),
1366 AsmInstrDsc("VMOVHPD\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000016,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64L|B_MEMORY,B_NONE]),
1367 AsmInstrDsc("MOVHPD\0",D_SSE|D_MUST66|D_MEMORY,0,2,0x0000FFFF,0x0000170F,0x00,[B_SSEF64L|B_MEMORY|B_UPD,B_SREGF64x2,B_NONE,B_NONE]),
1368 AsmInstrDsc("VMOVHPD\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x00000017,0x00,[B_SSEF64L|B_MEMORY|B_UPD,B_SREGF64x2,B_NONE,B_NONE]),
1369 AsmInstrDsc("MOVHPS\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0000FFFF,0x0000160F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x2L|B_MEMORY,B_NONE,B_NONE]),
1370 AsmInstrDsc("VMOVHPS\0",D_AVX|D_MUSTNONE|D_MEMORY,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000016,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x2L|B_MEMORY,B_NONE]),
1371 AsmInstrDsc("MOVHPS\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0000FFFF,0x0000170F,0x00,[B_SSEF32x2L|B_MEMORY|B_UPD,B_SREGF32x4,B_NONE,B_NONE]),
1372 AsmInstrDsc("VMOVHPS\0",D_AVX|D_MUSTNONE|D_MEMORY,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x00000017,0x00,[B_SSEF32x2L|B_MEMORY|B_UPD,B_SREGF32x4,B_NONE,B_NONE]),
1373 AsmInstrDsc("MOVLHPS\0",D_SSE|D_MUSTNONE|D_REGISTER,0,2,0x00C0FFFF,0x00C0160F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x2L|B_REGISTER,B_NONE,B_NONE]),
1374 AsmInstrDsc("VMOVLHPS\0",D_AVX|D_MUSTNONE|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000C0FF,0x0000C016,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x2L|B_REGISTER,B_NONE]),
1375 AsmInstrDsc("MOVLPD\0",D_SSE|D_MUST66|D_MEMORY,0,2,0x0000FFFF,0x0000120F,0x00,[B_SREGF64L|B_UPD,B_SSEF64L|B_MEMORY,B_NONE,B_NONE]),
1376 AsmInstrDsc("VMOVLPD\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000012,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64L|B_MEMORY,B_NONE]),
1377 AsmInstrDsc("MOVLPD\0",D_SSE|D_MUST66|D_MEMORY,0,2,0x0000FFFF,0x0000130F,0x00,[B_SSEF64L|B_MEMORY|B_UPD,B_SREGF64L,B_NONE,B_NONE]),
1378 AsmInstrDsc("VMOVLPD\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x00000013,0x00,[B_SSEF64L|B_MEMORY|B_UPD,B_SREGF64L,B_NONE,B_NONE]),
1379 AsmInstrDsc("MOVLPS\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0000FFFF,0x0000120F,0x00,[B_SREGF32x2L|B_UPD,B_SSEF32x2L|B_MEMORY,B_NONE,B_NONE]),
1380 AsmInstrDsc("VMOVLPS\0",D_AVX|D_MUSTNONE|D_MEMORY,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000012,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x2L|B_MEMORY,B_NONE]),
1381 AsmInstrDsc("MOVLPS\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0000FFFF,0x0000130F,0x00,[B_SSEF32x2L|B_MEMORY|B_UPD,B_SREGF32x2L,B_NONE,B_NONE]),
1382 AsmInstrDsc("VMOVLPS\0",D_AVX|D_MUSTNONE|D_MEMORY,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x00000013,0x00,[B_SSEF32x2L|B_MEMORY|B_UPD,B_SREGF32x2L,B_NONE,B_NONE]),
1383 AsmInstrDsc("MOVMSKPD\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00C0FFFF,0x00C0500F,0x00,[B_REG32|B_CHG,B_SSEF64x2|B_REGONLY,B_NONE,B_NONE]),
1384 AsmInstrDsc("VMOVMSKPD\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x0000C0FF,0x0000C050,0x00,[B_REG32|B_CHG,B_SSEF64x2|B_REGONLY,B_NONE,B_NONE]),
1385 AsmInstrDsc("MOVMSKPS\0",D_SSE|D_MUSTNONE|D_REGISTER,0,2,0x00C0FFFF,0x00C0500F,0x00,[B_REG32|B_CHG,B_SSEF32x4|B_REGONLY,B_NONE,B_NONE]),
1386 AsmInstrDsc("VMOVMSKPS\0",D_AVX|D_MUSTNONE|D_REGISTER,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x0000C0FF,0x0000C050,0x00,[B_REG32|B_CHG,B_SSEF32x4|B_REGONLY,B_NONE,B_NONE]),
1387 AsmInstrDsc("MOVNTDQ\0",D_SSE|D_MUST66|D_MEMORY,0,2,0x0000FFFF,0x0000E70F,0x00,[B_SSEI8x16|B_MEMORY|B_CHG,B_SREGI8x16|B_BINARY,B_NONE,B_NONE]),
1388 AsmInstrDsc("VMOVNTDQ\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x000000E7,0x00,[B_SSEI8x16|B_MEMORY|B_CHG,B_SREGI8x16|B_BINARY,B_NONE,B_NONE]),
1389 AsmInstrDsc("MOVNTI\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0000FFFF,0x0000C30F,0x00,[B_INT32|B_MEMORY|B_CHG,B_REG32,B_NONE,B_NONE]),
1390 AsmInstrDsc("MOVNTPD\0",D_SSE|D_MUST66|D_MEMORY,0,2,0x0000FFFF,0x00002B0F,0x00,[B_SSEF64x2|B_MEMORY|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1391 AsmInstrDsc("VMOVNTPD\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000002B,0x00,[B_SSEF64x2|B_MEMORY|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1392 AsmInstrDsc("MOVNTPS\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0000FFFF,0x00002B0F,0x00,[B_SSEF32x4|B_MEMORY|B_CHG,B_SREGF32x4,B_NONE,B_NONE]),
1393 AsmInstrDsc("VMOVNTPS\0",D_AVX|D_MUSTNONE|D_MEMORY,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x0000002B,0x00,[B_SSEF32x4|B_MEMORY|B_CHG,B_SREGF32x4,B_NONE,B_NONE]),
1394 AsmInstrDsc("MOVNTQ\0",D_MMX|D_MUSTNONE|D_MEMORY,0,2,0x0000FFFF,0x0000E70F,0x00,[B_MMX64|B_MEMORY|B_CHG,B_MREG64,B_NONE,B_NONE]),
1395 AsmInstrDsc("MOVQ\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x00006F0F,0x00,[B_MREG64|B_CHG,B_MMX64,B_NONE,B_NONE]),
1396 AsmInstrDsc("MOVQ\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x00007F0F,0x00,[B_MMX64|B_CHG,B_MREG64,B_NONE,B_NONE]),
1397 AsmInstrDsc("MOVQ\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00007E0F,0x00,[B_SREGF64L|B_CHG,B_SSEF64L,B_NONE,B_NONE]),
1398 AsmInstrDsc("VMOVQ\0",D_AVX|D_MUSTF3,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x0000007E,0x00,[B_SREGF64L|B_CHG,B_SSEF64L,B_NONE,B_NONE]),
1399 AsmInstrDsc("MOVQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000D60F,0x00,[B_SSEF64L|B_CHG,B_SREGF64L,B_NONE,B_NONE]),
1400 AsmInstrDsc("VMOVQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x000000D6,0x00,[B_SSEF64L|B_CHG,B_SREGF64L,B_NONE,B_NONE]),
1401 AsmInstrDsc("MOVQ2DQ\0",D_MMX|D_MUSTF3|D_REGISTER,0,2,0x00C0FFFF,0x00C0D60F,0x00,[B_SREGF64L|B_UPD,B_MMX8x8|B_REGISTER,B_NONE,B_NONE]),
1402 AsmInstrDsc("MOVSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000100F,0x00,[B_SREGF64L|B_UPD,B_SSEF64L,B_NONE,B_NONE]),
1403 AsmInstrDsc("VMOVSD\0",D_AVX|D_MUSTF2|D_MEMORY,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x00000010,0x00,[B_SREGF64L|B_UPD,B_SSEF64L,B_NONE,B_NONE]),
1404 AsmInstrDsc("VMOVSD\0",D_AVX|D_MUSTF2|D_REGISTER,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000010,0x00,[B_SREGF64L|B_UPD,B_SVEXF64x2,B_SSEF64L,B_NONE]),
1405 AsmInstrDsc("MOVSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000110F,0x00,[B_SSEF64L|B_UPD,B_SREGF64L,B_NONE,B_NONE]),
1406 AsmInstrDsc("VMOVSD\0",D_AVX|D_MUSTF2|D_MEMORY,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x00000011,0x00,[B_SSEF64L|B_UPD,B_SREGF64L,B_NONE,B_NONE]),
1407 AsmInstrDsc("VMOVSD\0",D_AVX|D_MUSTF2|D_REGISTER,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000011,0x00,[B_SSEF64L|B_UPD,B_SVEXF64x2,B_SREGF64L,B_NONE]),
1408 AsmInstrDsc("MOVSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000100F,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_NONE,B_NONE]),
1409 AsmInstrDsc("VMOVSS\0",D_AVX|D_MUSTF3|D_MEMORY,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x00000010,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_NONE,B_NONE]),
1410 AsmInstrDsc("VMOVSS\0",D_AVX|D_MUSTF3|D_REGISTER,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000010,0x00,[B_SREGF32L|B_UPD,B_SVEXF32x4,B_SSEF32L,B_NONE]),
1411 AsmInstrDsc("MOVSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000110F,0x00,[B_SSEF32L|B_UPD,B_SREGF32L,B_NONE,B_NONE]),
1412 AsmInstrDsc("VMOVSS\0",D_AVX|D_MUSTF3|D_MEMORY,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x00000011,0x00,[B_SSEF32L|B_UPD,B_SREGF32L,B_NONE,B_NONE]),
1413 AsmInstrDsc("VMOVSS\0",D_AVX|D_MUSTF3|D_REGISTER,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000011,0x00,[B_SSEF32L|B_UPD,B_SVEXF32x4,B_SREGF32L,B_NONE]),
1414 AsmInstrDsc("MOVSHDUP\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000160F,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1415 AsmInstrDsc("VMOVSHDUP\0",D_AVX|D_MUSTF3,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000016,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1416 AsmInstrDsc("MOVSLDUP\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000120F,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1417 AsmInstrDsc("VMOVSLDUP\0",D_AVX|D_MUSTF3,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000012,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1418 AsmInstrDsc("MOVUPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000100F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1419 AsmInstrDsc("VMOVUPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000010,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1420 AsmInstrDsc("MOVUPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000110F,0x00,[B_SSEF64x2|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1421 AsmInstrDsc("VMOVUPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000011,0x00,[B_SSEF64x2|B_CHG,B_SREGF64x2,B_NONE,B_NONE]),
1422 AsmInstrDsc("MOVUPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000100F,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1423 AsmInstrDsc("VMOVUPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000010,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1424 AsmInstrDsc("MOVUPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000110F,0x00,[B_SSEF32x4|B_CHG,B_SREGF32x4,B_NONE,B_NONE]),
1425 AsmInstrDsc("VMOVUPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000011,0x00,[B_SSEF32x4|B_CHG,B_SREGF32x4,B_NONE,B_NONE]),
1426 AsmInstrDsc("MULPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000590F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1427 AsmInstrDsc("VMULPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000059,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1428 AsmInstrDsc("MULPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000590F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1429 AsmInstrDsc("VMULPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000059,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1430 AsmInstrDsc("MULSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000590F,0x00,[B_SREGF64L|B_UPD,B_SSEF64L,B_NONE,B_NONE]),
1431 AsmInstrDsc("VMULSD\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000059,0x00,[B_SREGF64L|B_UPD,B_SVEXF64L,B_SSEF64L,B_NONE]),
1432 AsmInstrDsc("MULSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000590F,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_NONE,B_NONE]),
1433 AsmInstrDsc("VMULSS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000059,0x00,[B_SREGF32L|B_UPD,B_SVEXF32L,B_SSEF32L,B_NONE]),
1434 AsmInstrDsc("ORPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000560F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1435 AsmInstrDsc("VORPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000056,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1436 AsmInstrDsc("ORPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000560F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1437 AsmInstrDsc("VORPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000056,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1438 AsmInstrDsc("PACKSSWB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000630F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1439 AsmInstrDsc("PACKSSWB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000630F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1440 AsmInstrDsc("VPACKSSWB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000063,0x00,[B_SREGI8x16|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1441 AsmInstrDsc("PACKSSDW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x00006B0F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1442 AsmInstrDsc("PACKSSDW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00006B0F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1443 AsmInstrDsc("VPACKSSDW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x0000006B,0x00,[B_SREGI16x8|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1444 AsmInstrDsc("PACKUSWB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000670F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1445 AsmInstrDsc("PACKUSWB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000670F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1446 AsmInstrDsc("VPACKUSWB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000067,0x00,[B_SREGI8x16|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1447 AsmInstrDsc("PADDB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000FC0F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1448 AsmInstrDsc("PADDW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000FD0F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1449 AsmInstrDsc("PADDD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000FE0F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1450 AsmInstrDsc("PADDB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000FC0F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1451 AsmInstrDsc("VPADDB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000FC,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1452 AsmInstrDsc("PADDW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000FD0F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1453 AsmInstrDsc("VPADDW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000FD,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1454 AsmInstrDsc("PADDD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000FE0F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1455 AsmInstrDsc("VPADDD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000FE,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1456 AsmInstrDsc("PADDQ\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000D40F,0x00,[B_MREG64|B_UPD,B_MMX64,B_NONE,B_NONE]),
1457 AsmInstrDsc("PADDQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000D40F,0x00,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1458 AsmInstrDsc("VPADDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000D4,0x00,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1459 AsmInstrDsc("PADDSB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000EC0F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1460 AsmInstrDsc("PADDSW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000ED0F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1461 AsmInstrDsc("PADDSB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000EC0F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1462 AsmInstrDsc("VPADDSB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000EC,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1463 AsmInstrDsc("PADDSW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000ED0F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1464 AsmInstrDsc("VPADDSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000ED,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1465 AsmInstrDsc("PADDUSB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000DC0F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1466 AsmInstrDsc("PADDUSW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000DD0F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1467 AsmInstrDsc("PADDUSB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000DC0F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1468 AsmInstrDsc("VPADDUSB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000DC,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1469 AsmInstrDsc("PADDUSW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000DD0F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1470 AsmInstrDsc("VPADDUSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000DD,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1471 AsmInstrDsc("PAND\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000DB0F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1472 AsmInstrDsc("PAND\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000DB0F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1473 AsmInstrDsc("VPAND\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000DB,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1474 AsmInstrDsc("PANDN\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000DF0F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1475 AsmInstrDsc("PANDN\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000DF0F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1476 AsmInstrDsc("VPANDN\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000DF,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1477 AsmInstrDsc("PAVGB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000E00F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1478 AsmInstrDsc("PAVGW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000E30F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1479 AsmInstrDsc("PAVGB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000E00F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1480 AsmInstrDsc("VPAVGB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000E0,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1481 AsmInstrDsc("PAVGW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000E30F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1482 AsmInstrDsc("VPAVGW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000E3,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1483 AsmInstrDsc("PCMPEQB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000740F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1484 AsmInstrDsc("PCMPEQW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000750F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1485 AsmInstrDsc("PCMPEQD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000760F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1486 AsmInstrDsc("PCMPEQB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000740F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1487 AsmInstrDsc("VPCMPEQB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000074,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1488 AsmInstrDsc("PCMPEQW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000750F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1489 AsmInstrDsc("VPCMPEQW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000075,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1490 AsmInstrDsc("PCMPEQD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000760F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1491 AsmInstrDsc("VPCMPEQD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000076,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1492 AsmInstrDsc("PCMPGTB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000640F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1493 AsmInstrDsc("PCMPGTW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000650F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1494 AsmInstrDsc("PCMPGTD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000660F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1495 AsmInstrDsc("PCMPGTB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000640F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1496 AsmInstrDsc("VPCMPGTB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000064,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1497 AsmInstrDsc("PCMPGTW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000650F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1498 AsmInstrDsc("VPCMPGTW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000065,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1499 AsmInstrDsc("PCMPGTD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000660F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1500 AsmInstrDsc("VPCMPGTD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000066,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1501 AsmInstrDsc("PEXTRW\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00C0FFFF,0x00C0C50F,0x00,[B_REG32|B_CHG,B_MMX16x4|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1502 AsmInstrDsc("PEXTRW\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00C0FFFF,0x00C0C50F,0x00,[B_REG32|B_CHG,B_SSEI16x8|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1503 AsmInstrDsc("VPEXTRW\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x0000C0FF,0x0000C0C5,0x00,[B_REG32|B_CHG,B_SSEI16x8|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1504 AsmInstrDsc("PINSRW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000C40F,0x00,[B_MREG16x4|B_UPD,B_INT16,B_CONST8|B_COUNT,B_NONE]),
1505 AsmInstrDsc("PINSRW\0",D_MMX|D_MUSTNONE,0,2,0x00C0FFFF,0x00C0C40F,0x00,[B_MREG16x4|B_UPD,B_INT32|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1506 AsmInstrDsc("PINSRW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000C40F,0x00,[B_SREGI16x8|B_UPD,B_INT16,B_CONST8|B_COUNT,B_NONE]),
1507 AsmInstrDsc("VPINSRW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000C4,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_INT16,B_CONST8|B_COUNT]),
1508 AsmInstrDsc("PINSRW\0",D_SSE|D_MUST66,0,2,0x00C0FFFF,0x00C0C40F,0x00,[B_SREGI16x8|B_UPD,B_INT32|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1509 AsmInstrDsc("VPINSRW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x0000C0FF,0x0000C0C4,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_INT32|B_REGISTER,B_CONST8|B_COUNT]),
1510 AsmInstrDsc("PMADDWD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000F50F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1511 AsmInstrDsc("PMADDWD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000F50F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1512 AsmInstrDsc("VPMADDWD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000F5,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1513 AsmInstrDsc("PMAXSW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000EE0F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1514 AsmInstrDsc("PMAXSW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000EE0F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1515 AsmInstrDsc("VPMAXSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000EE,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1516 AsmInstrDsc("PMAXUB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000DE0F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1517 AsmInstrDsc("PMAXUB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000DE0F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1518 AsmInstrDsc("VPMAXUB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000DE,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1519 AsmInstrDsc("PMINSW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000EA0F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1520 AsmInstrDsc("PMINSW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000EA0F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1521 AsmInstrDsc("VPMINSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000EA,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1522 AsmInstrDsc("PMINUB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000DA0F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1523 AsmInstrDsc("PMINUB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000DA0F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1524 AsmInstrDsc("VPMINUB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000DA,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1525 AsmInstrDsc("PMOVMSKB\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00C0FFFF,0x00C0D70F,0x00,[B_REG32|B_CHG,B_MMX8x8|B_REGISTER,B_NONE,B_NONE]),
1526 AsmInstrDsc("PMOVMSKB\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00C0FFFF,0x00C0D70F,0x00,[B_REG32|B_CHG,B_SSEI8x16|B_REGISTER,B_NONE,B_NONE]),
1527 AsmInstrDsc("VPMOVMSKB\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x0000C0FF,0x0000C0D7,0x00,[B_REG32|B_CHG,B_SSEI8x16|B_REGISTER,B_NONE,B_NONE]),
1528 AsmInstrDsc("PMULHUW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000E40F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1529 AsmInstrDsc("PMULHUW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000E40F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1530 AsmInstrDsc("VPMULHUW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000E4,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1531 AsmInstrDsc("PMULHW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000E50F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1532 AsmInstrDsc("PMULHW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000E50F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1533 AsmInstrDsc("VPMULHW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000E5,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1534 AsmInstrDsc("PMULLW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000D50F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1535 AsmInstrDsc("PMULLW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000D50F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1536 AsmInstrDsc("VPMULLW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000D5,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1537 AsmInstrDsc("PMULUDQ\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000F40F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1538 AsmInstrDsc("PMULUDQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000F40F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1539 AsmInstrDsc("VPMULUDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000F4,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1540 AsmInstrDsc("POR\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000EB0F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1541 AsmInstrDsc("POR\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000EB0F,0x00,[B_SREGI8x16|B_BINARY|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1542 AsmInstrDsc("VPOR\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000EB,0x00,[B_SREGI8x16|B_BINARY|B_UPD,B_SVEXI8x16|B_BINARY,B_SSEI8x16,B_NONE]),
1543 AsmInstrDsc("PSADBW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000F60F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1544 AsmInstrDsc("PSADBW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000F60F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1545 AsmInstrDsc("VPSADBW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000F6,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1546 AsmInstrDsc("PSHUFD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000700F,0x00,[B_SREGI32x4|B_CHG,B_SSEI32x4,B_CONST8|B_BINARY,B_NONE]),
1547 AsmInstrDsc("VPSHUFD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x00000070,0x00,[B_SREGI32x4|B_CHG,B_SSEI32x4,B_CONST8|B_BINARY,B_NONE]),
1548 AsmInstrDsc("PSHUFHW\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000700F,0x00,[B_SREGI16x8|B_CHG,B_SSEI16x8,B_CONST8|B_BINARY,B_NONE]),
1549 AsmInstrDsc("VPSHUFHW\0",D_AVX|D_MUSTF3,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x00000070,0x00,[B_SREGI16x8|B_CHG,B_SSEI16x8,B_CONST8|B_BINARY,B_NONE]),
1550 AsmInstrDsc("PSHUFLW\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000700F,0x00,[B_SREGI16x8|B_CHG,B_SSEI16x8,B_CONST8|B_BINARY,B_NONE]),
1551 AsmInstrDsc("VPSHUFLW\0",D_AVX|D_MUSTF2,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x00000070,0x00,[B_SREGI16x8|B_CHG,B_SSEI16x8,B_CONST8|B_BINARY,B_NONE]),
1552 AsmInstrDsc("PSHUFW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000700F,0x00,[B_MREG16x4|B_CHG,B_MMX16x4,B_CONST8|B_BINARY,B_NONE]),
1553 AsmInstrDsc("PSLLDQ\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00F8730F,0x00,[B_SSEI8x16|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1554 AsmInstrDsc("VPSLLDQ\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000F873,0x00,[B_SVEXI8x16|B_UPD,B_SSEI8x16|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1555 AsmInstrDsc("PSLLW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000F10F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1556 AsmInstrDsc("PSLLW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000F10F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1557 AsmInstrDsc("VPSLLW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000F1,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1558 AsmInstrDsc("PSLLW\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00F8FFFF,0x00F0710F,0x00,[B_MMX16x4|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1559 AsmInstrDsc("PSLLW\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00F0710F,0x00,[B_SSEI16x8|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1560 AsmInstrDsc("VPSLLW\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000F071,0x00,[B_SVEXI16x8|B_UPD,B_SSEI16x8|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1561 AsmInstrDsc("PSLLD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000F20F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1562 AsmInstrDsc("PSLLD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000F20F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1563 AsmInstrDsc("VPSLLD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000F2,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1564 AsmInstrDsc("PSLLD\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00F8FFFF,0x00F0720F,0x00,[B_MMX32x2|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1565 AsmInstrDsc("PSLLD\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00F0720F,0x00,[B_SSEI32x4|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1566 AsmInstrDsc("VPSLLD\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000F072,0x00,[B_SVEXI32x4|B_UPD,B_SSEI32x4|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1567 AsmInstrDsc("PSLLQ\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000F30F,0x00,[B_MREG64|B_UPD,B_MMX64,B_NONE,B_NONE]),
1568 AsmInstrDsc("PSLLQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000F30F,0x00,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1569 AsmInstrDsc("VPSLLQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000F3,0x00,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1570 AsmInstrDsc("PSLLQ\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00F8FFFF,0x00F0730F,0x00,[B_MMX64|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1571 AsmInstrDsc("PSLLQ\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00F0730F,0x00,[B_SSEI64x2|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1572 AsmInstrDsc("VPSLLQ\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000F073,0x00,[B_SVEXI64x2|B_UPD,B_SSEI64x2|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1573 AsmInstrDsc("PSRAW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000E10F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1574 AsmInstrDsc("PSRAW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000E10F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1575 AsmInstrDsc("VPSRAW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000E1,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1576 AsmInstrDsc("PSRAW\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00F8FFFF,0x00E0710F,0x00,[B_MMX16x4|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1577 AsmInstrDsc("PSRAW\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00E0710F,0x00,[B_SSEI16x8|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1578 AsmInstrDsc("VPSRAW\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000E071,0x00,[B_SVEXI16x8|B_UPD,B_SSEI16x8|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1579 AsmInstrDsc("PSRAD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000E20F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1580 AsmInstrDsc("PSRAD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000E20F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1581 AsmInstrDsc("VPSRAD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000E2,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1582 AsmInstrDsc("PSRAD\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00F8FFFF,0x00E0720F,0x00,[B_MMX32x2|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1583 AsmInstrDsc("PSRAD\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00E0720F,0x00,[B_SSEI32x4|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1584 AsmInstrDsc("VPSRAD\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000E072,0x00,[B_SVEXI32x4|B_UPD,B_SSEI32x4|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1585 AsmInstrDsc("PSRLDQ\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00D8730F,0x00,[B_SSEI8x16|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1586 AsmInstrDsc("VPSRLDQ\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000D873,0x00,[B_SVEXI8x16|B_UPD,B_SSEI8x16|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1587 AsmInstrDsc("PSRLW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000D10F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1588 AsmInstrDsc("PSRLW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000D10F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1589 AsmInstrDsc("VPSRLW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000D1,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1590 AsmInstrDsc("PSRLW\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00F8FFFF,0x00D0710F,0x00,[B_MMX16x4|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1591 AsmInstrDsc("PSRLW\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00D0710F,0x00,[B_SSEI16x8|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1592 AsmInstrDsc("VPSRLW\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000D071,0x00,[B_SVEXI16x8|B_UPD,B_SSEI16x8|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1593 AsmInstrDsc("PSRLD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000D20F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1594 AsmInstrDsc("PSRLD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000D20F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1595 AsmInstrDsc("VPSRLD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000D2,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1596 AsmInstrDsc("PSRLD\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00F8FFFF,0x00D0720F,0x00,[B_MMX32x2|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1597 AsmInstrDsc("PSRLD\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00D0720F,0x00,[B_SSEI32x4|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1598 AsmInstrDsc("VPSRLD\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000D072,0x00,[B_SVEXI32x4|B_UPD,B_SSEI32x4|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1599 AsmInstrDsc("PSRLQ\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000D30F,0x00,[B_MREG64|B_UPD,B_MMX64,B_NONE,B_NONE]),
1600 AsmInstrDsc("PSRLQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000D30F,0x00,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1601 AsmInstrDsc("VPSRLQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000D3,0x00,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1602 AsmInstrDsc("PSRLQ\0",D_MMX|D_MUSTNONE|D_REGISTER,0,2,0x00F8FFFF,0x00D0730F,0x00,[B_MMX64|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1603 AsmInstrDsc("PSRLQ\0",D_SSE|D_MUST66|D_REGISTER,0,2,0x00F8FFFF,0x00D0730F,0x00,[B_SSEI64x2|B_REGISTER|B_UPD,B_CONST8|B_COUNT,B_NONE,B_NONE]),
1604 AsmInstrDsc("VPSRLQ\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT,1,0x0000F8FF,0x0000D073,0x00,[B_SVEXI64x2|B_UPD,B_SSEI64x2|B_REGISTER,B_CONST8|B_COUNT,B_NONE]),
1605 AsmInstrDsc("PSUBB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000F80F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1606 AsmInstrDsc("PSUBW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000F90F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1607 AsmInstrDsc("PSUBD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000FA0F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1608 AsmInstrDsc("PSUBB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000F80F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1609 AsmInstrDsc("VPSUBB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000F8,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1610 AsmInstrDsc("PSUBW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000F90F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1611 AsmInstrDsc("VPSUBW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000F9,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1612 AsmInstrDsc("PSUBD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000FA0F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1613 AsmInstrDsc("VPSUBD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000FA,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1614 AsmInstrDsc("PSUBQ\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000FB0F,0x00,[B_MREG64|B_UPD,B_MMX64,B_NONE,B_NONE]),
1615 AsmInstrDsc("PSUBQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000FB0F,0x00,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1616 AsmInstrDsc("VPSUBQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000FB,0x00,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1617 AsmInstrDsc("PSUBSB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000E80F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1618 AsmInstrDsc("PSUBSW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000E90F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1619 AsmInstrDsc("PSUBSB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000E80F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1620 AsmInstrDsc("VPSUBSB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000E8,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1621 AsmInstrDsc("PSUBSW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000E90F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1622 AsmInstrDsc("VPSUBSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000E9,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1623 AsmInstrDsc("PSUBUSB\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000D80F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1624 AsmInstrDsc("PSUBUSW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000D90F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1625 AsmInstrDsc("PSUBUSB\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000D80F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1626 AsmInstrDsc("VPSUBUSB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000D8,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1627 AsmInstrDsc("PSUBUSW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000D90F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1628 AsmInstrDsc("VPSUBUSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000D9,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1629 AsmInstrDsc("PUNPCKHBW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000680F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1630 AsmInstrDsc("PUNPCKHBW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000680F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1631 AsmInstrDsc("VPUNPCKHBW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000068,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1632 AsmInstrDsc("PUNPCKHWD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000690F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1633 AsmInstrDsc("PUNPCKHWD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000690F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1634 AsmInstrDsc("VPUNPCKHWD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000069,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1635 AsmInstrDsc("PUNPCKHDQ\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x00006A0F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1636 AsmInstrDsc("PUNPCKHDQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00006A0F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1637 AsmInstrDsc("VPUNPCKHDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x0000006A,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1638 AsmInstrDsc("PUNPCKHQDQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00006D0F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1639 AsmInstrDsc("VPUNPCKHQDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x0000006D,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1640 AsmInstrDsc("PUNPCKLBW\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000600F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1641 AsmInstrDsc("PUNPCKLBW\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000600F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1642 AsmInstrDsc("VPUNPCKLBW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000060,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1643 AsmInstrDsc("PUNPCKLWD\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000610F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1644 AsmInstrDsc("PUNPCKLWD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000610F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1645 AsmInstrDsc("VPUNPCKLWD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000061,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1646 AsmInstrDsc("PUNPCKLDQ\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000620F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1647 AsmInstrDsc("PUNPCKLDQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000620F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1648 AsmInstrDsc("VPUNPCKLDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x00000062,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1649 AsmInstrDsc("PUNPCKLQDQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00006C0F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1650 AsmInstrDsc("VPUNPCKLQDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x0000006C,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1651 AsmInstrDsc("PXOR\0",D_MMX|D_MUSTNONE,0,2,0x0000FFFF,0x0000EF0F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1652 AsmInstrDsc("PXOR\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000EF0F,0x00,[B_SREGI8x16|B_BINARY|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1653 AsmInstrDsc("VPXOR\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT,1,0x000000FF,0x000000EF,0x00,[B_SREGI8x16|B_BINARY|B_UPD,B_SVEXI8x16|B_BINARY,B_SSEI8x16,B_NONE]),
1654 AsmInstrDsc("RCPPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000530F,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1655 AsmInstrDsc("VRCPPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000053,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1656 AsmInstrDsc("RCPSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000530F,0x00,[B_SREGF32L|B_CHG,B_SSEF32L,B_NONE,B_NONE]),
1657 AsmInstrDsc("VRCPSS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000053,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L|B_CHG,B_SSEF32L,B_NONE]),
1658 AsmInstrDsc("RSQRTPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000520F,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1659 AsmInstrDsc("VRSQRTPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000052,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1660 AsmInstrDsc("RSQRTSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000520F,0x00,[B_SREGF32L|B_CHG,B_SSEF32L,B_NONE,B_NONE]),
1661 AsmInstrDsc("VRSQRTSS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000052,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF32L,B_NONE]),
1662 AsmInstrDsc("SHUFPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000C60F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_CONST8|B_BINARY,B_NONE]),
1663 AsmInstrDsc("VSHUFPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x000000C6,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_CONST8|B_BINARY]),
1664 AsmInstrDsc("SHUFPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000C60F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_CONST8|B_BINARY,B_NONE]),
1665 AsmInstrDsc("VSHUFPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x000000C6,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_CONST8|B_BINARY]),
1666 AsmInstrDsc("SQRTPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000510F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1667 AsmInstrDsc("VSQRTPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000051,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_NONE,B_NONE]),
1668 AsmInstrDsc("SQRTPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000510F,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1669 AsmInstrDsc("VSQRTPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH|DX_NOVREG,1,0x000000FF,0x00000051,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_NONE,B_NONE]),
1670 AsmInstrDsc("SQRTSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000510F,0x00,[B_SREGF64L|B_CHG,B_SSEF64L,B_NONE,B_NONE]),
1671 AsmInstrDsc("VSQRTSD\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000051,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_SSEF64L,B_NONE]),
1672 AsmInstrDsc("SQRTSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x0000510F,0x00,[B_SREGF32L|B_CHG,B_SSEF32L,B_NONE,B_NONE]),
1673 AsmInstrDsc("VSQRTSS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x00000051,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF32L,B_NONE]),
1674 AsmInstrDsc("SUBPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x00005C0F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1675 AsmInstrDsc("VSUBPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000005C,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1676 AsmInstrDsc("SUBPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x00005C0F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1677 AsmInstrDsc("VSUBPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x0000005C,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1678 AsmInstrDsc("SUBSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00005C0F,0x00,[B_SREGF64L|B_UPD,B_SSEF64L,B_NONE,B_NONE]),
1679 AsmInstrDsc("VSUBSD\0",D_AVX|D_MUSTF2,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005C,0x00,[B_SREGF64L|B_UPD,B_SVEXF64L,B_SSEF64L,B_NONE]),
1680 AsmInstrDsc("SUBSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00005C0F,0x00,[B_SREGF32L|B_UPD,B_SSEF32L,B_NONE,B_NONE]),
1681 AsmInstrDsc("VSUBSS\0",D_AVX|D_MUSTF3,DX_VEX|DX_IGNOREL,1,0x000000FF,0x0000005C,0x00,[B_SREGF32L|B_UPD,B_SVEXF32L,B_SSEF32L,B_NONE]),
1682 AsmInstrDsc("UNPCKHPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000150F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1683 AsmInstrDsc("VUNPCKHPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000015,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1684 AsmInstrDsc("UNPCKHPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000150F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1685 AsmInstrDsc("VUNPCKHPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000015,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1686 AsmInstrDsc("UNPCKLPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000140F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1687 AsmInstrDsc("VUNPCKLPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000014,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1688 AsmInstrDsc("UNPCKLPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000140F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1689 AsmInstrDsc("VUNPCKLPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000014,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1690 AsmInstrDsc("UCOMISD\0",D_SSE|D_MUST66|D_ALLFLAGS,0,2,0x0000FFFF,0x00002E0F,0x00,[B_SREGF64L,B_SSEF64L,B_NONE,B_NONE]),
1691 AsmInstrDsc("VUCOMISD\0",D_AVX|D_MUST66|D_ALLFLAGS,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x0000002E,0x00,[B_SREGF64L,B_SSEF64L,B_NONE,B_NONE]),
1692 AsmInstrDsc("UCOMISS\0",D_SSE|D_MUSTNONE|D_ALLFLAGS,0,2,0x0000FFFF,0x00002E0F,0x00,[B_SREGF32L,B_SSEF32L,B_NONE,B_NONE]),
1693 AsmInstrDsc("VUCOMISS\0",D_AVX|D_MUSTNONE|D_ALLFLAGS,DX_VEX|DX_IGNOREL|DX_NOVREG,1,0x000000FF,0x0000002E,0x00,[B_SREGF32L,B_SSEF32L,B_NONE,B_NONE]),
1694 AsmInstrDsc("XORPD\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000570F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_NONE,B_NONE]),
1695 AsmInstrDsc("VXORPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000057,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_NONE]),
1696 AsmInstrDsc("XORPS\0",D_SSE|D_MUSTNONE,0,2,0x0000FFFF,0x0000570F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_NONE,B_NONE]),
1697 AsmInstrDsc("VXORPS\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LBOTH,1,0x000000FF,0x00000057,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_NONE]),
1698 AsmInstrDsc("FXRSTOR\0",D_SSE|D_MEMORY,0,2,0x0038FFFF,0x0008AE0F,0x00,[B_LONGDATA|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1699 AsmInstrDsc("FXSAVE\0",D_SSE|D_MEMORY,0,2,0x0038FFFF,0x0000AE0F,0x00,[B_LONGDATA|B_MEMORY|B_CHG,B_NONE,B_NONE,B_NONE]),
1700 AsmInstrDsc("LFENCE\0",D_SSE,0,3,0x00FFFFFF,0x00E8AE0F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1701 AsmInstrDsc("PREFETCHT0\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0038FFFF,0x0008180F,0x00,[B_ANYMEM|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1702 AsmInstrDsc("PREFETCHT1\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0038FFFF,0x0010180F,0x00,[B_ANYMEM|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1703 AsmInstrDsc("PREFETCHT2\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0038FFFF,0x0018180F,0x00,[B_ANYMEM|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1704 AsmInstrDsc("PREFETCHNTA\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0038FFFF,0x0000180F,0x00,[B_ANYMEM|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1705 AsmInstrDsc("NOP\0",D_SSE|D_MUSTNONE|D_MEMORY|D_UNDOC,DX_NOP,2,0x0020FFFF,0x0020180F,0x00,[B_ANYMEM|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1706 AsmInstrDsc("PREFETCH\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0038FFFF,0x00000D0F,0x00,[B_ANYMEM|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1707 AsmInstrDsc("PREFETCHW\0",D_SSE|D_MUSTNONE|D_MEMORY,0,2,0x0038FFFF,0x00080D0F,0x00,[B_ANYMEM|B_MEMORY,B_NONE,B_NONE,B_NONE]),
1708 AsmInstrDsc("SFENCE\0",D_SSE,0,3,0x00FFFFFF,0x00F8AE0F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1709 AsmInstrDsc("BLENDPD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x000D3A0F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_CONST8|B_BINARY,B_NONE]),
1710 AsmInstrDsc("VBLENDPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_LEAD3A,1,0x000000FF,0x0000000D,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_CONST8|B_BINARY]),
1711 AsmInstrDsc("BLENDPS\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x000C3A0F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_CONST8|B_BINARY,B_NONE]),
1712 AsmInstrDsc("VBLENDPS\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_LEAD3A,1,0x000000FF,0x0000000C,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_CONST8|B_BINARY]),
1713 AsmInstrDsc("BLENDVPD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0015380F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_XMM0I64x2,B_NONE]),
1714 AsmInstrDsc("BLENDVPD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0015380F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_XMM0I64x2|B_PSEUDO,B_NONE]),
1715 AsmInstrDsc("VBLENDVPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_W0|DX_LEAD3A,1,0x000000FF,0x0000004B,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_SIMMI8x16]),
1716 AsmInstrDsc("BLENDVPS\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0014380F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_XMM0I32x4,B_NONE]),
1717 AsmInstrDsc("BLENDVPS\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0014380F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_XMM0I32x4|B_PSEUDO,B_NONE]),
1718 AsmInstrDsc("VBLENDVPS\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_W0|DX_LEAD3A,1,0x000000FF,0x0000004A,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_SIMMI8x16]),
1719 AsmInstrDsc("CRC32\0",D_CMD|D_NEEDF2,0,3,0x00FFFFFF,0x00F0380F,0x00,[B_REG32|B_NOADDR|B_UPD,B_INT8|B_SHOWSIZE,B_NONE,B_NONE]),
1720 AsmInstrDsc("CRC32\0",D_CMD|D_NEEDF2,0,3,0x00FFFFFF,0x00F1380F,0x00,[B_REG32|B_NOADDR|B_UPD,B_INT1632|B_NOADDR|B_SHOWSIZE,B_NONE,B_NONE]),
1721 AsmInstrDsc("DPPD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00413A0F,0x00,[B_SREGF64x2|B_UPD,B_SSEF64x2,B_CONST8|B_BINARY,B_NONE]),
1722 AsmInstrDsc("VDPPD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x00000041,0x00,[B_SREGF64x2|B_UPD,B_SVEXF64x2,B_SSEF64x2,B_CONST8|B_BINARY]),
1723 AsmInstrDsc("DPPS\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00403A0F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32x4,B_CONST8|B_BINARY,B_NONE]),
1724 AsmInstrDsc("VDPPS\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_LEAD3A,1,0x000000FF,0x00000040,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32x4,B_CONST8|B_BINARY]),
1725 AsmInstrDsc("EXTRACTPS\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00173A0F,0x00,[B_INT32|B_CHG,B_SREGF32x4,B_CONST8|B_BINARY,B_NONE]),
1726 AsmInstrDsc("VEXTRACTPS\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x00000017,0x00,[B_INT32|B_CHG,B_SREGF32x4,B_CONST8|B_BINARY,B_NONE]),
1727 AsmInstrDsc("INSERTPS\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00213A0F,0x00,[B_SREGF32x4|B_UPD,B_SSEF32L,B_CONST8|B_BINARY,B_NONE]),
1728 AsmInstrDsc("VINSERTPS\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x00000021,0x00,[B_SREGF32x4|B_UPD,B_SVEXF32x4,B_SSEF32L,B_CONST8|B_BINARY]),
1729 AsmInstrDsc("MOVNTDQA\0",D_SSE|D_MUST66|D_MEMORY,0,3,0x00FFFFFF,0x002A380F,0x00,[B_SREGI8x16|B_BINARY|B_CHG,B_SSEI8x16|B_MEMORY,B_NONE,B_NONE]),
1730 AsmInstrDsc("VMOVNTDQA\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x0000002A,0x00,[B_SREGI8x16|B_BINARY|B_CHG,B_SSEI8x16|B_MEMORY,B_NONE,B_NONE]),
1731 AsmInstrDsc("MPSADBW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00423A0F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_CONST8|B_BINARY,B_NONE]),
1732 AsmInstrDsc("VMPSADBW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x00000042,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_CONST8|B_BINARY]),
1733 AsmInstrDsc("PACKUSDW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x002B380F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1734 AsmInstrDsc("VPACKUSDW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x0000002B,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4|B_UPD,B_SSEI32x4,B_NONE]),
1735 AsmInstrDsc("PBLENDVB\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0010380F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_XMM0I8x16,B_NONE]),
1736 AsmInstrDsc("PBLENDVB\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0010380F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_XMM0I8x16|B_PSEUDO,B_NONE]),
1737 AsmInstrDsc("VPBLENDVB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_W0|DX_LEAD3A,1,0x000000FF,0x0000004C,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16,B_SIMMI8x16]),
1738 AsmInstrDsc("PBLENDW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x000E3A0F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_CONST8|B_BINARY,B_NONE]),
1739 AsmInstrDsc("VPBLENDW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x0000000E,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_CONST8|B_BINARY]),
1740 AsmInstrDsc("PCLMULLQLQDQ\0",D_SSE|D_POSTBYTE|D_MUST66,0,3,0x00FFFFFF,0x00443A0F,0x00,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1741 AsmInstrDsc("VPCLMULLQLQDQ\0",D_AVX|D_POSTBYTE|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x00000044,0x00,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1742 AsmInstrDsc("PCLMULHQLQDQ\0",D_SSE|D_POSTBYTE|D_MUST66,0,3,0x00FFFFFF,0x00443A0F,0x01,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1743 AsmInstrDsc("VPCLMULHQLQDQ\0",D_AVX|D_POSTBYTE|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x00000044,0x01,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1744 AsmInstrDsc("PCLMULLQHDQ\0",D_SSE|D_POSTBYTE|D_MUST66,0,3,0x00FFFFFF,0x00443A0F,0x10,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1745 AsmInstrDsc("VPCLMULLQHDQ\0",D_AVX|D_POSTBYTE|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x00000044,0x10,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1746 AsmInstrDsc("PCLMULHQHDQ\0",D_SSE|D_POSTBYTE|D_MUST66,0,3,0x00FFFFFF,0x00443A0F,0x11,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1747 AsmInstrDsc("VPCLMULHQHDQ\0",D_AVX|D_POSTBYTE|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x00000044,0x11,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1748 AsmInstrDsc("PCLMULQDQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00443A0F,0x00,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_CONST8|B_BINARY,B_NONE]),
1749 AsmInstrDsc("VPCLMULQDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x00000044,0x00,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_CONST8|B_BINARY]),
1750 AsmInstrDsc("PCMPEQQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0029380F,0x00,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1751 AsmInstrDsc("VPCMPEQQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000029,0x00,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1752 AsmInstrDsc("PCMPESTRI\0",D_SSE|D_MUST66|D_ALLFLAGS,0,3,0x00FFFFFF,0x00613A0F,0x00,[B_SREGI8x16,B_SSEI8x16,B_CONST8|B_BINARY,B_NONE]),
1753 AsmInstrDsc("VPCMPESTRI\0",D_AVX|D_MUST66|D_ALLFLAGS,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x00000061,0x00,[B_SREGI8x16,B_SSEI8x16,B_CONST8|B_BINARY,B_NONE]),
1754 AsmInstrDsc("PCMPESTRM\0",D_SSE|D_MUST66|D_ALLFLAGS,0,3,0x00FFFFFF,0x00603A0F,0x00,[B_SREGI8x16,B_SSEI8x16,B_CONST8|B_BINARY,B_NONE]),
1755 AsmInstrDsc("VPCMPESTRM\0",D_AVX|D_MUST66|D_ALLFLAGS,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x00000060,0x00,[B_SREGI8x16,B_SSEI8x16,B_CONST8|B_BINARY,B_NONE]),
1756 AsmInstrDsc("PCMPISTRI\0",D_SSE|D_MUST66|D_ALLFLAGS,0,3,0x00FFFFFF,0x00633A0F,0x00,[B_SREGI8x16,B_SSEI8x16,B_CONST8|B_BINARY,B_NONE]),
1757 AsmInstrDsc("VPCMPISTRI\0",D_AVX|D_MUST66|D_ALLFLAGS,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x00000063,0x00,[B_SREGI8x16,B_SSEI8x16,B_CONST8|B_BINARY,B_NONE]),
1758 AsmInstrDsc("PCMPISTRM\0",D_SSE|D_MUST66|D_ALLFLAGS,0,3,0x00FFFFFF,0x00623A0F,0x00,[B_SREGI8x16,B_SSEI8x16,B_CONST8|B_BINARY,B_NONE]),
1759 AsmInstrDsc("VPCMPISTRM\0",D_AVX|D_MUST66|D_ALLFLAGS,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x00000062,0x00,[B_SREGI8x16,B_SSEI8x16,B_CONST8|B_BINARY,B_NONE]),
1760 AsmInstrDsc("PCMPGTQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0037380F,0x00,[B_SREGI64x2|B_UPD,B_SSEI64x2,B_NONE,B_NONE]),
1761 AsmInstrDsc("VPCMPGTQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000037,0x00,[B_SREGI64x2|B_UPD,B_SVEXI64x2,B_SSEI64x2,B_NONE]),
1762 AsmInstrDsc("PEXTRB\0",D_SSE|D_MUST66|D_MEMORY,0,3,0x00FFFFFF,0x00143A0F,0x00,[B_INT8|B_MEMORY|B_CHG,B_SREGI8x16,B_CONST8|B_BINARY,B_NONE]),
1763 AsmInstrDsc("PEXTRB\0",D_SSE|D_MUST66|D_REGISTER,0,3,0x00FFFFFF,0x00143A0F,0x00,[B_INT32|B_REGISTER|B_CHG,B_SREGI8x16,B_CONST8|B_BINARY,B_NONE]),
1764 AsmInstrDsc("VPEXTRB\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LSHORT|DX_NOVREG|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000014,0x00,[B_INT8|B_MEMORY|B_CHG,B_SREGI8x16,B_CONST8|B_BINARY,B_NONE]),
1765 AsmInstrDsc("VPEXTRB\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT|DX_NOVREG|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000014,0x00,[B_INT32|B_REGISTER|B_CHG,B_SREGI8x16,B_CONST8|B_BINARY,B_NONE]),
1766 AsmInstrDsc("PEXTRD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00163A0F,0x00,[B_INT32|B_CHG,B_SREGI32x4,B_CONST8|B_BINARY,B_NONE]),
1767 AsmInstrDsc("VPEXTRD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x00000016,0x00,[B_INT32|B_CHG,B_SREGI32x4,B_CONST8|B_BINARY,B_NONE]),
1768 AsmInstrDsc("PEXTRW\0",D_SSE|D_MUST66|D_MEMORY,0,3,0x00FFFFFF,0x00153A0F,0x00,[B_INT16|B_MEMORY|B_CHG,B_SREGI16x8,B_CONST8|B_BINARY,B_NONE]),
1769 AsmInstrDsc("PEXTRW\0",D_SSE|D_MUST66|D_REGISTER,0,3,0x00FFFFFF,0x00153A0F,0x00,[B_INT32|B_REGISTER|B_CHG,B_SREGI16x8,B_CONST8|B_BINARY,B_NONE]),
1770 AsmInstrDsc("VPEXTRW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x00000015,0x00,[B_INT16|B_CHG,B_SREGI16x8,B_CONST8|B_BINARY,B_NONE]),
1771 AsmInstrDsc("PHMINPOSUW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0041380F,0x00,[B_SREGI16x8|B_CHG,B_SSEI16x8,B_NONE,B_NONE]),
1772 AsmInstrDsc("VPHMINPOSUW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000041,0x00,[B_SREGI16x8|B_CHG,B_SSEI16x8,B_NONE,B_NONE]),
1773 AsmInstrDsc("PINSRB\0",D_SSE|D_MUST66|D_MEMORY,0,3,0x00FFFFFF,0x00203A0F,0x00,[B_SREGI8x16|B_UPD,B_INT8|B_MEMORY,B_CONST8|B_BINARY,B_NONE]),
1774 AsmInstrDsc("VPINSRB\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LSHORT|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000020,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_INT8|B_MEMORY,B_CONST8|B_BINARY]),
1775 AsmInstrDsc("PINSRB\0",D_SSE|D_MUST66|D_REGISTER,0,3,0x00FFFFFF,0x00203A0F,0x00,[B_SREGI8x16|B_UPD,B_INT32|B_REGISTER,B_CONST8|B_BINARY,B_NONE]),
1776 AsmInstrDsc("VPINSRB\0",D_AVX|D_MUST66|D_REGISTER,DX_VEX|DX_LSHORT|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000020,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_INT32|B_REGISTER,B_CONST8|B_BINARY]),
1777 AsmInstrDsc("PINSRD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00223A0F,0x00,[B_SREGI32x4|B_UPD,B_INT32,B_CONST8|B_BINARY,B_NONE]),
1778 AsmInstrDsc("VPINSRD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000022,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_INT32,B_CONST8|B_BINARY]),
1779 AsmInstrDsc("PMAXSB\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x003C380F,0x00,[B_SREGI8x16|B_SIGNED|B_UPD,B_SSEI8x16|B_SIGNED,B_NONE,B_NONE]),
1780 AsmInstrDsc("VPMAXSB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x0000003C,0x00,[B_SREGI8x16|B_SIGNED|B_UPD,B_SVEXI8x16|B_SIGNED,B_SSEI8x16|B_SIGNED,B_NONE]),
1781 AsmInstrDsc("PMAXSD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x003D380F,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SSEI32x4|B_SIGNED,B_NONE,B_NONE]),
1782 AsmInstrDsc("VPMAXSD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x0000003D,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SVEXI32x4|B_SIGNED,B_SSEI32x4|B_SIGNED,B_NONE]),
1783 AsmInstrDsc("PMAXUD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x003F380F,0x00,[B_SREGI32x4|B_UNSIGNED|B_UPD,B_SSEI32x4|B_UNSIGNED,B_NONE,B_NONE]),
1784 AsmInstrDsc("VPMAXUD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x0000003F,0x00,[B_SREGI32x4|B_UNSIGNED|B_UPD,B_SVEXI32x4|B_UNSIGNED,B_SSEI32x4|B_UNSIGNED,B_NONE]),
1785 AsmInstrDsc("PMAXUW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x003E380F,0x00,[B_SREGI16x8|B_UNSIGNED|B_UPD,B_SSEI16x8|B_UNSIGNED,B_NONE,B_NONE]),
1786 AsmInstrDsc("VPMAXUW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x0000003E,0x00,[B_SREGI16x8|B_UNSIGNED|B_UPD,B_SVEXI16x8|B_UNSIGNED,B_SSEI16x8|B_UNSIGNED,B_NONE]),
1787 AsmInstrDsc("PMINSB\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0038380F,0x00,[B_SREGI8x16|B_SIGNED|B_UPD,B_SSEI8x16|B_SIGNED,B_NONE,B_NONE]),
1788 AsmInstrDsc("VPMINSB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000038,0x00,[B_SREGI8x16|B_SIGNED|B_UPD,B_SVEXI8x16|B_SIGNED,B_SSEI8x16|B_SIGNED,B_NONE]),
1789 AsmInstrDsc("PMINSD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0039380F,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SSEI32x4|B_SIGNED,B_NONE,B_NONE]),
1790 AsmInstrDsc("VPMINSD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000039,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SVEXI32x4|B_SIGNED,B_SSEI32x4|B_SIGNED,B_NONE]),
1791 AsmInstrDsc("PMINUD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x003B380F,0x00,[B_SREGI32x4|B_UNSIGNED|B_UPD,B_SSEI32x4|B_UNSIGNED,B_NONE,B_NONE]),
1792 AsmInstrDsc("VPMINUD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x0000003B,0x00,[B_SREGI32x4|B_UNSIGNED|B_UPD,B_SVEXI32x4|B_UNSIGNED,B_SSEI32x4|B_UNSIGNED,B_NONE]),
1793 AsmInstrDsc("PMINUW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x003A380F,0x00,[B_SREGI16x8|B_UNSIGNED|B_UPD,B_SSEI16x8|B_UNSIGNED,B_NONE,B_NONE]),
1794 AsmInstrDsc("VPMINUW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x0000003A,0x00,[B_SREGI16x8|B_UNSIGNED|B_UPD,B_SVEXI16x8|B_UNSIGNED,B_SSEI16x8|B_UNSIGNED,B_NONE]),
1795 AsmInstrDsc("PMOVSXBW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0020380F,0x00,[B_SREGI16x8|B_SIGNED|B_CHG,B_SSEI8x8L,B_NONE,B_NONE]),
1796 AsmInstrDsc("VPMOVSXBW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000020,0x00,[B_SREGI16x8|B_SIGNED|B_CHG,B_SSEI8x8L,B_NONE,B_NONE]),
1797 AsmInstrDsc("PMOVSXBD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0021380F,0x00,[B_SREGI32x4|B_SIGNED|B_CHG,B_SSEI8x4L,B_NONE,B_NONE]),
1798 AsmInstrDsc("VPMOVSXBD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000021,0x00,[B_SREGI32x4|B_SIGNED|B_CHG,B_SSEI8x4L,B_NONE,B_NONE]),
1799 AsmInstrDsc("PMOVSXBQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0022380F,0x00,[B_SREGI64x2|B_SIGNED|B_CHG,B_SSEI8x2L,B_NONE,B_NONE]),
1800 AsmInstrDsc("VPMOVSXBQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000022,0x00,[B_SREGI64x2|B_SIGNED|B_CHG,B_SSEI8x2L,B_NONE,B_NONE]),
1801 AsmInstrDsc("PMOVSXWD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0023380F,0x00,[B_SREGI32x4|B_SIGNED|B_CHG,B_SSEI16x4L,B_NONE,B_NONE]),
1802 AsmInstrDsc("VPMOVSXWD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000023,0x00,[B_SREGI32x4|B_SIGNED|B_CHG,B_SSEI16x4L,B_NONE,B_NONE]),
1803 AsmInstrDsc("PMOVSXWQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0024380F,0x00,[B_SREGI64x2|B_SIGNED|B_CHG,B_SSEI16x2L,B_NONE,B_NONE]),
1804 AsmInstrDsc("VPMOVSXWQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000024,0x00,[B_SREGI64x2|B_SIGNED|B_CHG,B_SSEI16x2L,B_NONE,B_NONE]),
1805 AsmInstrDsc("PMOVSXDQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0025380F,0x00,[B_SREGI64x2|B_SIGNED|B_CHG,B_SSEI32x2L,B_NONE,B_NONE]),
1806 AsmInstrDsc("VPMOVSXDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000025,0x00,[B_SREGI64x2|B_SIGNED|B_CHG,B_SSEI32x2L,B_NONE,B_NONE]),
1807 AsmInstrDsc("PMOVZXBW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0030380F,0x00,[B_SREGI16x8|B_CHG,B_SSEI8x8L,B_NONE,B_NONE]),
1808 AsmInstrDsc("VPMOVZXBW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000030,0x00,[B_SREGI16x8|B_CHG,B_SSEI8x8L,B_NONE,B_NONE]),
1809 AsmInstrDsc("PMOVZXBD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0031380F,0x00,[B_SREGI32x4|B_CHG,B_SSEI8x4L,B_NONE,B_NONE]),
1810 AsmInstrDsc("VPMOVZXBD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000031,0x00,[B_SREGI32x4|B_CHG,B_SSEI8x4L,B_NONE,B_NONE]),
1811 AsmInstrDsc("PMOVZXBQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0032380F,0x00,[B_SREGI64x2|B_CHG,B_SSEI8x2L,B_NONE,B_NONE]),
1812 AsmInstrDsc("VPMOVZXBQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000032,0x00,[B_SREGI64x2|B_CHG,B_SSEI8x2L,B_NONE,B_NONE]),
1813 AsmInstrDsc("PMOVZXWD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0033380F,0x00,[B_SREGI32x4|B_CHG,B_SSEI16x4L,B_NONE,B_NONE]),
1814 AsmInstrDsc("VPMOVZXWD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000033,0x00,[B_SREGI32x4|B_CHG,B_SSEI16x4L,B_NONE,B_NONE]),
1815 AsmInstrDsc("PMOVZXWQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0034380F,0x00,[B_SREGI64x2|B_CHG,B_SSEI16x2L,B_NONE,B_NONE]),
1816 AsmInstrDsc("VPMOVZXWQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000034,0x00,[B_SREGI64x2|B_CHG,B_SSEI16x2L,B_NONE,B_NONE]),
1817 AsmInstrDsc("PMOVZXDQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0035380F,0x00,[B_SREGI64x2|B_CHG,B_SSEI32x2L,B_NONE,B_NONE]),
1818 AsmInstrDsc("VPMOVZXDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000035,0x00,[B_SREGI64x2|B_CHG,B_SSEI32x2L,B_NONE,B_NONE]),
1819 AsmInstrDsc("PMULDQ\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0028380F,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SSEI32x4|B_SIGNED,B_NONE,B_NONE]),
1820 AsmInstrDsc("VPMULDQ\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000028,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SVEXI32x4|B_SIGNED,B_SSEI32x4|B_SIGNED,B_NONE]),
1821 AsmInstrDsc("PMULLD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0040380F,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SSEI32x4|B_SIGNED,B_NONE,B_NONE]),
1822 AsmInstrDsc("VPMULLD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000040,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SVEXI32x4|B_SIGNED,B_SSEI32x4|B_SIGNED,B_NONE]),
1823 AsmInstrDsc("PTEST\0",D_SSE|D_MUST66|D_ALLFLAGS,0,3,0x00FFFFFF,0x0017380F,0x00,[B_SREGI32x4,B_SSEI32x4,B_NONE,B_NONE]),
1824 AsmInstrDsc("VPTEST\0",D_AVX|D_MUST66|D_ALLFLAGS,DX_VEX|DX_LBOTH|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x00000017,0x00,[B_SREGI32x4,B_SSEI32x4,B_NONE,B_NONE]),
1825 AsmInstrDsc("ROUNDPD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00093A0F,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_CONST8|B_BINARY,B_NONE]),
1826 AsmInstrDsc("VROUNDPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x00000009,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_CONST8|B_BINARY,B_NONE]),
1827 AsmInstrDsc("ROUNDPS\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00083A0F,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_CONST8|B_BINARY,B_NONE]),
1828 AsmInstrDsc("VROUNDPS\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x00000008,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_CONST8|B_BINARY,B_NONE]),
1829 AsmInstrDsc("ROUNDSD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x000B3A0F,0x00,[B_SREGF64L|B_CHG,B_SSEF64L,B_CONST8|B_BINARY,B_NONE]),
1830 AsmInstrDsc("VROUNDSD\0",D_AVX|D_MUST66,DX_VEX|DX_IGNOREL|DX_LEAD3A,1,0x000000FF,0x0000000B,0x00,[B_SREGF64L|B_CHG,B_SVEXF64L,B_SSEF64L,B_CONST8|B_BINARY]),
1831 AsmInstrDsc("ROUNDSS\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x000A3A0F,0x00,[B_SREGF32L|B_CHG,B_SSEF32L,B_CONST8|B_BINARY,B_NONE]),
1832 AsmInstrDsc("VROUNDSS\0",D_AVX|D_MUST66,DX_VEX|DX_IGNOREL|DX_LEAD3A,1,0x000000FF,0x0000000A,0x00,[B_SREGF32L|B_CHG,B_SVEXF32L,B_SSEF32L,B_CONST8|B_BINARY]),
1833 AsmInstrDsc("PABSB\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x001C380F,0x00,[B_MREG8x8|B_UNSIGNED|B_CHG,B_MMX8x8|B_SIGNED,B_NONE,B_NONE]),
1834 AsmInstrDsc("PABSB\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x001C380F,0x00,[B_SREGI8x16|B_UNSIGNED|B_CHG,B_SSEI8x16|B_SIGNED,B_NONE,B_NONE]),
1835 AsmInstrDsc("VPABSB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x0000001C,0x00,[B_SREGI8x16|B_UNSIGNED|B_CHG,B_SSEI8x16|B_SIGNED,B_NONE,B_NONE]),
1836 AsmInstrDsc("PABSW\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x001D380F,0x00,[B_MREG16x4|B_UNSIGNED|B_CHG,B_MMX16x4|B_SIGNED,B_NONE,B_NONE]),
1837 AsmInstrDsc("PABSW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x001D380F,0x00,[B_SREGI16x8|B_UNSIGNED|B_CHG,B_SSEI16x8|B_SIGNED,B_NONE,B_NONE]),
1838 AsmInstrDsc("VPABSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x0000001D,0x00,[B_SREGI16x8|B_UNSIGNED|B_CHG,B_SSEI16x8|B_SIGNED,B_NONE,B_NONE]),
1839 AsmInstrDsc("PABSD\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x001E380F,0x00,[B_MREG32x2|B_UNSIGNED|B_CHG,B_MMX32x2|B_SIGNED,B_NONE,B_NONE]),
1840 AsmInstrDsc("PABSD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x001E380F,0x00,[B_SREGI32x4|B_UNSIGNED|B_CHG,B_SSEI32x4|B_SIGNED,B_NONE,B_NONE]),
1841 AsmInstrDsc("VPABSD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x0000001E,0x00,[B_SREGI32x4|B_UNSIGNED|B_CHG,B_SSEI32x4|B_SIGNED,B_NONE,B_NONE]),
1842 AsmInstrDsc("PALIGNR\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x000F3A0F,0x00,[B_MREG8x8|B_BINARY|B_UPD,B_MMX8x8|B_BINARY,B_CONST8|B_UNSIGNED,B_NONE]),
1843 AsmInstrDsc("PALIGNR\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x000F3A0F,0x00,[B_SREGI8x16|B_BINARY|B_UPD,B_SSEI8x16|B_BINARY,B_CONST8|B_UNSIGNED,B_NONE]),
1844 AsmInstrDsc("VPALIGNR\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD3A,1,0x000000FF,0x0000000F,0x00,[B_SREGI8x16|B_BINARY|B_UPD,B_SVEXI8x16|B_BINARY,B_SSEI8x16|B_BINARY,B_CONST8|B_UNSIGNED]),
1845 AsmInstrDsc("PHADDW\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0001380F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1846 AsmInstrDsc("PHADDW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0001380F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1847 AsmInstrDsc("VPHADDW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000001,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1848 AsmInstrDsc("PHADDD\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0002380F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1849 AsmInstrDsc("PHADDD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0002380F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1850 AsmInstrDsc("VPHADDD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000002,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1851 AsmInstrDsc("PHSUBW\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0005380F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1852 AsmInstrDsc("PHSUBW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0005380F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1853 AsmInstrDsc("VPHSUBW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000005,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1854 AsmInstrDsc("PHSUBD\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0006380F,0x00,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1855 AsmInstrDsc("PHSUBD\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0006380F,0x00,[B_SREGI32x4|B_UPD,B_SSEI32x4,B_NONE,B_NONE]),
1856 AsmInstrDsc("VPHSUBD\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000006,0x00,[B_SREGI32x4|B_UPD,B_SVEXI32x4,B_SSEI32x4,B_NONE]),
1857 AsmInstrDsc("PHADDSW\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0003380F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1858 AsmInstrDsc("PHADDSW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0003380F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1859 AsmInstrDsc("VPHADDSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000003,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1860 AsmInstrDsc("PHSUBSW\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0007380F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1861 AsmInstrDsc("PHSUBSW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0007380F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1862 AsmInstrDsc("VPHSUBSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000007,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1863 AsmInstrDsc("PMADDUBSW\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0004380F,0x00,[B_MREG8x8|B_UNSIGNED|B_UPD,B_MMX8x8|B_SIGNED,B_NONE,B_NONE]),
1864 AsmInstrDsc("PMADDUBSW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0004380F,0x00,[B_SREGI8x16|B_UNSIGNED|B_UPD,B_SSEI8x16|B_SIGNED,B_NONE,B_NONE]),
1865 AsmInstrDsc("VPMADDUBSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000004,0x00,[B_SREGI8x16|B_UNSIGNED|B_UPD,B_SVEXI8x16|B_UNSIGNED,B_SSEI8x16|B_SIGNED,B_NONE]),
1866 AsmInstrDsc("PMULHRSW\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x000B380F,0x00,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1867 AsmInstrDsc("PMULHRSW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x000B380F,0x00,[B_SREGI16x8|B_UPD,B_SSEI16x8,B_NONE,B_NONE]),
1868 AsmInstrDsc("VPMULHRSW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x0000000B,0x00,[B_SREGI16x8|B_UPD,B_SVEXI16x8,B_SSEI16x8,B_NONE]),
1869 AsmInstrDsc("PSHUFB\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0000380F,0x00,[B_MREG8x8|B_UPD,B_MMX8x8|B_BINARY,B_NONE,B_NONE]),
1870 AsmInstrDsc("PSHUFB\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0000380F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16|B_BINARY,B_NONE,B_NONE]),
1871 AsmInstrDsc("VPSHUFB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000000,0x00,[B_SREGI8x16|B_UPD,B_SVEXI8x16,B_SSEI8x16|B_BINARY,B_NONE]),
1872 AsmInstrDsc("PSIGNB\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0008380F,0x00,[B_MREG8x8|B_SIGNED|B_UPD,B_MMX8x8|B_SIGNED,B_NONE,B_NONE]),
1873 AsmInstrDsc("PSIGNB\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0008380F,0x00,[B_SREGI8x16|B_SIGNED|B_UPD,B_SSEI8x16|B_SIGNED,B_NONE,B_NONE]),
1874 AsmInstrDsc("VPSIGNB\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000008,0x00,[B_SREGI8x16|B_SIGNED|B_UPD,B_SVEXI8x16|B_SIGNED,B_SSEI8x16|B_SIGNED,B_NONE]),
1875 AsmInstrDsc("PSIGNW\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x0009380F,0x00,[B_MREG16x4|B_SIGNED|B_UPD,B_MMX16x4|B_SIGNED,B_NONE,B_NONE]),
1876 AsmInstrDsc("PSIGNW\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x0009380F,0x00,[B_SREGI16x8|B_SIGNED|B_UPD,B_SSEI16x8|B_SIGNED,B_NONE,B_NONE]),
1877 AsmInstrDsc("VPSIGNW\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x00000009,0x00,[B_SREGI16x8|B_SIGNED|B_UPD,B_SVEXI16x8|B_SIGNED,B_SSEI16x8|B_SIGNED,B_NONE]),
1878 AsmInstrDsc("PSIGND\0",D_MMX|D_MUSTNONE,0,3,0x00FFFFFF,0x000A380F,0x00,[B_MREG32x2|B_SIGNED|B_UPD,B_MMX32x2|B_SIGNED,B_NONE,B_NONE]),
1879 AsmInstrDsc("PSIGND\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x000A380F,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SSEI32x4|B_SIGNED,B_NONE,B_NONE]),
1880 AsmInstrDsc("VPSIGND\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x0000000A,0x00,[B_SREGI32x4|B_SIGNED|B_UPD,B_SVEXI32x4|B_SIGNED,B_SSEI32x4|B_SIGNED,B_NONE]),
1881 AsmInstrDsc("VBROADCASTSS\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LBOTH|DX_NOVREG|DX_W0|DX_LEAD38,1,0x000000FF,0x00000018,0x00,[B_SREGF32x4|B_CHG,B_SSEF32L|B_MEMORY,B_NONE,B_NONE]),
1882 AsmInstrDsc("VBROADCASTSD\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LLONG|DX_NOVREG|DX_W0|DX_LEAD38,1,0x000000FF,0x00000019,0x00,[B_SREGF64x2|B_CHG,B_SSEF64L|B_MEMORY,B_NONE,B_NONE]),
1883 AsmInstrDsc("VBROADCASTF128\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LLONG|DX_NOVREG|DX_W0|DX_LEAD38,1,0x000000FF,0x0000001A,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2|B_MEMORY|B_NOVEXSIZE|B_SHOWSIZE,B_NONE,B_NONE]),
1884 AsmInstrDsc("VEXTRACTF128\0",D_AVX|D_MUST66,DX_VEX|DX_LLONG|DX_NOVREG|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000019,0x00,[B_SSEF64x2|B_NOVEXSIZE|B_SHOWSIZE|B_CHG,B_SREGF64x2,B_CONST8,B_NONE]),
1885 AsmInstrDsc("VINSERTF128\0",D_AVX|D_MUST66,DX_VEX|DX_LLONG|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000018,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2|B_NOVEXSIZE|B_SHOWSIZE,B_CONST8]),
1886 AsmInstrDsc("VMASKMOVPS\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LBOTH|DX_W0|DX_LEAD38,1,0x000000FF,0x0000002C,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEF32x4|B_MEMORY,B_NONE]),
1887 AsmInstrDsc("VMASKMOVPS\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LBOTH|DX_W0|DX_LEAD38,1,0x000000FF,0x0000002E,0x00,[B_SSEF32x4|B_MEMORY|B_CHG,B_SVEXF32x4,B_SREGF32x4,B_NONE]),
1888 AsmInstrDsc("VMASKMOVPD\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LBOTH|DX_W0|DX_LEAD38,1,0x000000FF,0x0000002D,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2|B_MEMORY,B_NONE]),
1889 AsmInstrDsc("VMASKMOVPD\0",D_AVX|D_MUST66|D_MEMORY,DX_VEX|DX_LBOTH|DX_W0|DX_LEAD38,1,0x000000FF,0x0000002F,0x00,[B_SSEF64x2|B_MEMORY|B_CHG,B_SVEXF64x2,B_SREGF64x2,B_NONE]),
1890 AsmInstrDsc("VPERMILPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_W0|DX_LEAD38,1,0x000000FF,0x0000000D,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEI64x2,B_NONE]),
1891 AsmInstrDsc("VPERMILPD\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000005,0x00,[B_SREGF64x2|B_CHG,B_SSEF64x2,B_CONST8,B_NONE]),
1892 AsmInstrDsc("VPERMILPS\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_W0|DX_LEAD38,1,0x000000FF,0x0000000C,0x00,[B_SREGF32x4|B_CHG,B_SVEXF32x4,B_SSEI32x4,B_NONE]),
1893 AsmInstrDsc("VPERMILPS\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000004,0x00,[B_SREGF32x4|B_CHG,B_SSEF32x4,B_CONST8,B_NONE]),
1894 AsmInstrDsc("VPERM2F128\0",D_AVX|D_MUST66,DX_VEX|DX_LLONG|DX_W0|DX_LEAD3A,1,0x000000FF,0x00000006,0x00,[B_SREGF64x2|B_CHG,B_SVEXF64x2,B_SSEF64x2,B_CONST8]),
1895 AsmInstrDsc("VTESTPS\0",D_AVX|D_MUST66|D_ALLFLAGS,DX_VEX|DX_LBOTH|DX_NOVREG|DX_W0|DX_LEAD38,1,0x000000FF,0x0000000E,0x00,[B_SREGF32x4,B_SSEF32x4,B_NONE,B_NONE]),
1896 AsmInstrDsc("VTESTPD\0",D_AVX|D_MUST66|D_ALLFLAGS,DX_VEX|DX_LBOTH|DX_NOVREG|DX_W0|DX_LEAD38,1,0x000000FF,0x0000000F,0x00,[B_SREGF64x2,B_SSEF64x2,B_NONE,B_NONE]),
1897 AsmInstrDsc("VZEROALL\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LLONG|DX_NOVREG,1,0x000000FF,0x00000077,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1898 AsmInstrDsc("VZEROUPPER\0",D_AVX|D_MUSTNONE,DX_VEX|DX_LSHORT|DX_NOVREG,1,0x000000FF,0x00000077,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1899 AsmInstrDsc("AESDEC\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00DE380F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1900 AsmInstrDsc("VAESDEC\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x000000DE,0x00,[B_SREGI8x16|B_CHG,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1901 AsmInstrDsc("AESDECLAST\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00DF380F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1902 AsmInstrDsc("VAESDECLAST\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x000000DF,0x00,[B_SREGI8x16|B_CHG,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1903 AsmInstrDsc("AESENC\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00DC380F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1904 AsmInstrDsc("VAESENC\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x000000DC,0x00,[B_SREGI8x16|B_CHG,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1905 AsmInstrDsc("AESENCLAST\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00DD380F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1906 AsmInstrDsc("VAESENCLAST\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_LEAD38,1,0x000000FF,0x000000DD,0x00,[B_SREGI8x16|B_CHG,B_SVEXI8x16,B_SSEI8x16,B_NONE]),
1907 AsmInstrDsc("AESIMC\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00DB380F,0x00,[B_SREGI8x16|B_CHG,B_SSEI8x16,B_NONE,B_NONE]),
1908 AsmInstrDsc("VAESIMC\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD38,1,0x000000FF,0x000000DB,0x00,[B_SREGI8x16|B_CHG,B_SSEI8x16,B_NONE,B_NONE]),
1909 AsmInstrDsc("AESKEYGENASSIST\0",D_SSE|D_MUST66,0,3,0x00FFFFFF,0x00DF3A0F,0x00,[B_SREGI8x16|B_CHG,B_SSEI8x16,B_CONST8|B_COUNT,B_NONE]),
1910 AsmInstrDsc("VAESKEYGENASSIST\0",D_AVX|D_MUST66,DX_VEX|DX_LSHORT|DX_NOVREG|DX_LEAD3A,1,0x000000FF,0x000000DF,0x00,[B_SREGI8x16|B_CHG,B_SSEI8x16,B_CONST8|B_COUNT,B_NONE]),
1911 AsmInstrDsc("VCVTPH2PS\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG|DX_W0|DX_LEAD38,1,0x000000FF,0x00000013,0x00,[B_SREGF32x4|B_CHG,B_SSEI16x4L,B_NONE,B_NONE]),
1912 AsmInstrDsc("VCVTPS2PH\0",D_AVX|D_MUST66,DX_VEX|DX_LBOTH|DX_NOVREG|DX_W0|DX_LEAD3A,1,0x000000FF,0x0000001D,0x00,[B_SSEI16x4L|B_CHG,B_SREGF32x4,B_NONE,B_NONE]),
1913 AsmInstrDsc("LZCNT\0",D_CMD|D_NEEDF3|D_ALLFLAGS,0,2,0x0000FFFF,0x0000BD0F,0x00,[B_REG|B_CHG,B_INT|B_BINARY,B_NONE,B_NONE]),
1914 AsmInstrDsc("POPCNT\0",D_CMD|D_NEEDF3|D_ALLFLAGS,0,2,0x0000FFFF,0x0000B80F,0x00,[B_REG|B_CHG,B_INT|B_NOADDR,B_NONE,B_NONE]),
1915 AsmInstrDsc("EXTRQ\0",D_SSE|D_MUST66,0,2,0x0038FFFF,0x0000780F,0x00,[B_SSEI8x16|B_REGONLY|B_UPD,B_CONST8|B_COUNT,B_CONST8_2|B_COUNT,B_NONE]),
1916 AsmInstrDsc("EXTRQ\0",D_SSE|D_MUST66,0,2,0x0000FFFF,0x0000790F,0x00,[B_SREGI8x16|B_UPD,B_SSEI8x2L|B_REGONLY,B_NONE,B_NONE]),
1917 AsmInstrDsc("INSERTQ\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000780F,0x00,[B_SREGI8x16|B_REGONLY|B_UPD,B_SSEI8x8L,B_CONST8|B_COUNT,B_CONST8_2|B_COUNT]),
1918 AsmInstrDsc("INSERTQ\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x0000790F,0x00,[B_SREGI8x16|B_REGONLY|B_UPD,B_SSEI8x16,B_NONE,B_NONE]),
1919 AsmInstrDsc("MOVNTSD\0",D_SSE|D_MUSTF2,0,2,0x0000FFFF,0x00002B0F,0x00,[B_SSEF64L|B_MEMONLY|B_CHG,B_SREGF64L,B_NONE,B_NONE]),
1920 AsmInstrDsc("MOVNTSS\0",D_SSE|D_MUSTF3,0,2,0x0000FFFF,0x00002B0F,0x00,[B_SSEF32L|B_MEMONLY|B_CHG,B_SREGF32L,B_NONE,B_NONE]),
1921 AsmInstrDsc("INVEPT\0",D_PRIVILEGED|D_MUST66|D_MEMORY|D_RARE,0,3,0x00FFFFFF,0x0080380F,0x00,[B_REG32,B_INT128,B_NONE,B_NONE]),
1922 AsmInstrDsc("INVVPID\0",D_PRIVILEGED|D_MUST66|D_MEMORY|D_RARE,0,3,0x00FFFFFF,0x0081380F,0x00,[B_REG32,B_INT128,B_NONE,B_NONE]),
1923 AsmInstrDsc("VMCALL\0",D_PRIVILEGED|D_RARE,0,3,0x00FFFFFF,0x00C1010F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1924 AsmInstrDsc("VMCLEAR\0",D_PRIVILEGED|D_MUST66|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0030C70F,0x00,[B_INT64|B_MEMONLY,B_NONE,B_NONE,B_NONE]),
1925 AsmInstrDsc("VMLAUNCH\0",D_PRIVILEGED|D_RARE,0,3,0x00FFFFFF,0x00C2010F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1926 AsmInstrDsc("VMFUNC\0",D_PRIVILEGED|D_RARE,0,3,0x00FFFFFF,0x00D4010F,0x00,[B_EAX|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1927 AsmInstrDsc("XEND\0",D_PRIVILEGED|D_RARE,0,3,0x00FFFFFF,0x00D5010F,0x00,[B_EAX|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1928 AsmInstrDsc("XTEST\0",D_PRIVILEGED|D_RARE,0,3,0x00FFFFFF,0x00D6010F,0x00,[B_EAX|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1929 AsmInstrDsc("VMRESUME\0",D_PRIVILEGED|D_RARE,0,3,0x00FFFFFF,0x00C3010F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1930 AsmInstrDsc("VMPTRLD\0",D_PRIVILEGED|D_MUSTNONE|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0030C70F,0x00,[B_INT64|B_MEMONLY,B_NONE,B_NONE,B_NONE]),
1931 AsmInstrDsc("VMPTRST\0",D_PRIVILEGED|D_MUSTNONE|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0038C70F,0x00,[B_INT64|B_MEMONLY|B_CHG,B_NONE,B_NONE,B_NONE]),
1932 AsmInstrDsc("VMREAD\0",D_PRIVILEGED|D_MUSTNONE|D_RARE,0,2,0x0000FFFF,0x0000780F,0x00,[B_INT32|B_CHG,B_REG32,B_NONE,B_NONE]),
1933 AsmInstrDsc("VMWRITE\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000790F,0x00,[B_REG32,B_INT32,B_NONE,B_NONE]),
1934 AsmInstrDsc("VMXOFF\0",D_PRIVILEGED|D_RARE,0,3,0x00FFFFFF,0x00C4010F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1935 AsmInstrDsc("VMXON\0",D_PRIVILEGED|D_MUSTF3|D_MEMORY|D_RARE,0,2,0x0038FFFF,0x0030C70F,0x00,[B_INT64,B_NONE,B_NONE,B_NONE]),
1936 AsmInstrDsc("GETSEC\0",D_PRIVILEGED|D_RARE,0,2,0x0000FFFF,0x0000370F,0x00,[B_EAX|B_UPD|B_PSEUDO,B_EBX|B_PSEUDO,B_ECX|B_PSEUDO,B_NONE]),
1937 AsmInstrDsc("FEMMS\0",D_CMD,0,2,0x0000FFFF,0x00000E0F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1938 AsmInstrDsc("PAVGUSB\0",D_MMX|D_POSTBYTE|D_MUSTNONE,0,2,0x0000FFFF,0x00000F0F,0xBF,[B_MREG8x8|B_UPD,B_MMX8x8,B_NONE,B_NONE]),
1939 AsmInstrDsc("PF2ID\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x1D,[B_MREG32x2|B_CHG,B_3DNOW,B_NONE,B_NONE]),
1940 AsmInstrDsc("PFACC\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0xAE,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1941 AsmInstrDsc("PFADD\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x9E,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1942 AsmInstrDsc("PFCMPEQ\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0xB0,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1943 AsmInstrDsc("PFCMPGE\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x90,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1944 AsmInstrDsc("PFCMPGT\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0xA0,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1945 AsmInstrDsc("PFMAX\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0xA4,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1946 AsmInstrDsc("PFMIN\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x94,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1947 AsmInstrDsc("PFMUL\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0xB4,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1948 AsmInstrDsc("PFRCP\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x96,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1949 AsmInstrDsc("PFRCPIT1\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0xA6,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1950 AsmInstrDsc("PFRCPIT2\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0xB6,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1951 AsmInstrDsc("PFRSQIT1\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0xA7,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1952 AsmInstrDsc("PFRSQRT\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x97,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1953 AsmInstrDsc("PFSUB\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x9A,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1954 AsmInstrDsc("PFSUBR\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0xAA,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1955 AsmInstrDsc("PI2FD\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x0D,[B_3DREG|B_UPD,B_MMX32x2|B_SIGNED,B_NONE,B_NONE]),
1956 AsmInstrDsc("PMULHRW\0",D_MMX|D_POSTBYTE|D_MUSTNONE,0,2,0x0000FFFF,0x00000F0F,0xB7,[B_MREG16x4|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1957 AsmInstrDsc("PF2IW\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x1C,[B_MREG32x2|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1958 AsmInstrDsc("PFNACC\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x8A,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1959 AsmInstrDsc("PFPNACC\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x8E,[B_3DREG|B_UPD,B_3DNOW,B_NONE,B_NONE]),
1960 AsmInstrDsc("PI2FW\0",D_3DNOW|D_POSTBYTE,0,2,0x0000FFFF,0x00000F0F,0x0C,[B_3DREG|B_UPD,B_MMX16x4,B_NONE,B_NONE]),
1961 AsmInstrDsc("PSWAPD\0",D_MMX|D_POSTBYTE|D_MUSTNONE,0,2,0x0000FFFF,0x00000F0F,0xBB,[B_MREG32x2|B_UPD,B_MMX32x2,B_NONE,B_NONE]),
1962 AsmInstrDsc("SYSCALL\0",D_SYS|D_RARE,0,2,0x0000FFFF,0x0000050F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1963 AsmInstrDsc("SYSRET\0",D_SYS|D_ALLFLAGS|D_SUSPICIOUS,0,2,0x0000FFFF,0x0000070F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1964 AsmInstrDsc("CLGI\0",D_PRIVILEGED,0,3,0x00FFFFFF,0x00DD010F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1965 AsmInstrDsc("STGI\0",D_PRIVILEGED,0,3,0x00FFFFFF,0x00DC010F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1966 AsmInstrDsc("INVLPGA\0",D_PRIVILEGED|D_RARE,0,3,0x00FFFFFF,0x00DF010F,0x00,[B_EAX|B_PSEUDO,B_ECX|B_PSEUDO,B_NONE,B_NONE]),
1967 AsmInstrDsc("SKINIT\0",D_PRIVILEGED,0,3,0x00FFFFFF,0x00DE010F,0x00,[B_EAX|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1968 AsmInstrDsc("VMLOAD\0",D_PRIVILEGED,0,3,0x00FFFFFF,0x00DA010F,0x00,[B_EAX|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1969 AsmInstrDsc("VMMCALL\0",D_SYS|D_SUSPICIOUS,0,3,0x00FFFFFF,0x00D9010F,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1970 AsmInstrDsc("VMRUN\0",D_PRIVILEGED,0,3,0x00FFFFFF,0x00D8010F,0x00,[B_EAX|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1971 AsmInstrDsc("VMSAVE\0",D_PRIVILEGED,0,3,0x00FFFFFF,0x00DB010F,0x00,[B_EAX|B_PSEUDO,B_NONE,B_NONE,B_NONE]),
1972 AsmInstrDsc("ES:\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x00000026,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1973 AsmInstrDsc("CS:\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x0000002E,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1974 AsmInstrDsc("SS:\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x00000036,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1975 AsmInstrDsc("DS:\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x0000003E,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1976 AsmInstrDsc("FS:\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x00000064,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1977 AsmInstrDsc("GS:\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x00000065,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1978 AsmInstrDsc("DATASIZE:\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x00000066,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1979 AsmInstrDsc("ADDRSIZE:\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x00000067,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1980 AsmInstrDsc("LOCK\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x000000F0,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1981 AsmInstrDsc("REPNE\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x000000F2,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1982 AsmInstrDsc("REPNZ\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x000000F2,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1983 AsmInstrDsc("REP\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x000000F3,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1984 AsmInstrDsc("REPE\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x000000F3,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1985 AsmInstrDsc("REPZ\0",D_PREFIX|D_SUSPICIOUS,0,1,0x000000FF,0x000000F3,0x00,[B_NONE,B_NONE,B_NONE,B_NONE]),
1986 // pseudocommands used by Assembler for masked search only.
1987 /+
1988 AsmInstrDsc("JCC\0",D_PSEUDO|D_BHINT|D_COND,0,1,0x000000F0,0x00000070,0x00,[B_BYTEOFFS|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
1989 AsmInstrDsc("JCC\0",D_PSEUDO|D_BHINT|D_COND,0,2,0x0000F0FF,0x0000800F,0x00,[B_OFFSET|B_JMPCALL,B_NONE,B_NONE,B_NONE]),
1990 AsmInstrDsc("SETCC\0",D_PSEUDO|D_COND,0,2,0x0038F0FF,0x0000900F,0x00,[B_INT8|B_SHOWSIZE|B_CHG,B_NONE,B_NONE,B_NONE]),
1991 AsmInstrDsc("CMOVCC\0",D_PSEUDO|D_COND,0,2,0x0000F0FF,0x0000400F,0x00,[B_REG|B_UPD,B_INT,B_NONE,B_NONE]),
1992 AsmInstrDsc("FCMOVCC\0",D_PSEUDO|D_COND,0,2,0x0000E0FF,0x0000C0DA,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1993 AsmInstrDsc("FCMOVCC\0",D_PSEUDO|D_COND,0,2,0x0000E0FF,0x0000C0DB,0x00,[B_ST0|B_CHG,B_ST,B_NONE,B_NONE]),
1994 +/
1995 ];
1996
1997
1998 // ////////////////////////////////////////////////////////////////////////// //
1999 // ///////////////////////////// SYMBOLIC NAMES ///////////////////////////// //
2000 package(iv.olly) {
2001 // 8-bit register names, sorted by 'natural' index (as understood by CPU, not
2002 // in the alphabetical order as some 'programmers' prefer).
2003 static immutable string[NREG] regname8 = ["AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"];
2004
2005 // 16-bit register names.
2006 static immutable string[NREG] regname16 = ["AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"];
2007
2008 // 32-bit register names.
2009 static immutable string[NREG] regname32 = ["EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"];
2010
2011 // Names of segment registers.
2012 static immutable string[NREG] segname = ["ES", "CS", "SS", "DS", "FS", "GS", "SEG6:", "SEG7:"];
2013
2014 // Names of FPU registers, classical form.
2015 static immutable string[NREG] fpulong = ["ST(0)", "ST(1)", "ST(2)", "ST(3)", "ST(4)", "ST(5)", "ST(6)", "ST(7)"];
2016
2017 // Names of FPU registers, short form.
2018 static immutable string[NREG] fpushort = ["ST0", "ST1", "ST2", "ST3", "ST4", "ST5", "ST6", "ST7"];
2019
2020 // Names of MMX/3DNow! registers.
2021 static immutable string[NREG] mmxname = ["MM0", "MM1", "MM2", "MM3", "MM4", "MM5", "MM6", "MM7"];
2022
2023 // Names of 128-bit SSE registers.
2024 static immutable string[NREG] sse128 = ["XMM0", "XMM1", "XMM2", "XMM3", "XMM4", "XMM5", "XMM6", "XMM7"];
2025
2026 // Names of 256-bit SSE registers.
2027 static immutable string[NREG] sse256 = ["YMM0", "YMM1", "YMM2", "YMM3", "YMM4", "YMM5", "YMM6", "YMM7"];
2028
2029 // Names of control registers.
2030 static immutable string[NREG] crname = ["CR0", "CR1", "CR2", "CR3", "CR4", "CR5", "CR6", "CR7"];
2031
2032 // Names of debug registers.
2033 static immutable string[NREG] drname = ["DR0", "DR1", "DR2", "DR3", "DR4", "DR5", "DR6", "DR7"];
2034 }
2035
2036
2037 // ////////////////////////////////////////////////////////////////////////// //
2038 private:
2039 // Declarations for data types. Depending on ssesizemode, name of 16-byte data type (DQWORD)
2040 // may be changed to XMMWORD and that of 32-bit type (QQWORD) to YMMWORD.
2041 static immutable string[33] sizename = [
2042 null, "BYTE", "WORD", null,
2043 "DWORD", null, "FWORD", null,
2044 "QWORD", null, "TBYTE", null,
2045 null, null, null, null,
2046 "DQWORD", null, null, null,
2047 null, null, null, null,
2048 null, null, null, null,
2049 null, null, null, null,
2050 "QQWORD",
2051 ];
2052
2053 // Keywords for immediate data. HLA uses sizename[] instead of sizekey[].
2054 static immutable string[33] sizekey = [
2055 null, "DB", "DW", null,
2056 "DD", null, "DF", null,
2057 "DQ", null, "DT", null,
2058 null, null, null, null,
2059 "DDQ", null, null, null,
2060 null, null, null, null,
2061 null, null, null, null,
2062 null, null, null, null,
2063 "DQQ",
2064 ];
2065
2066 // Keywords for immediate data in AT&T format.
2067 static immutable string[33] sizeatt = [
2068 null, ".BYTE", ".WORD", null,
2069 ".LONG", null, ".FWORD", null,
2070 ".QUAD", null, ".TBYTE", null,
2071 null, null, null, null,
2072 ".DQUAD", null, null, null,
2073 null, null, null, null,
2074 null, null, null, null,
2075 null, null, null, null,
2076 ".QQUAD",
2077 ];
2078
2079 // Comparison predicates in SSE [0..7] and VEX commands [0..31].
2080 static immutable string[32] ssepredicate = [
2081 "EQ", "LT", "LE", "UNORD",
2082 "NEQ", "NLT", "NLE", "ORD",
2083 "EQ_UQ", "NGE", "NGT", "FALSE",
2084 "NEQ_OQ", "GE", "GT", "TRUE",
2085 "EQ_OS", "LT_OQ", "LE_OQ", "UNORD_S",
2086 "NEQ_US", "NLT_UQ", "NLE_UQ", "ORD_S",
2087 "EQ_US", "NGE_UQ", "NGT_UQ", "FALSE_OS",
2088 "NEQ_OS", "GE_OQ", "GT_OQ", "TRUE_US",
2089 ];
2090
2091
2092 // ////////////////////////////////////////////////////////////////////////// //
2093 // ////////////////////////////// DISASSEMBLER ////////////////////////////// //
2094
2095 // Intermediate disassembler data
2096 struct t_imdata {
2097 DisasmData* da; // Result of disassembly
2098 uint damode; // Disassembling mode, set of DA_xxx
2099 const(DAConfig)* config; // Disassembler configuration
2100 const(char)[] delegate (uint addr) decodeaddress;
2101 uint prefixlist; // List of command's prefixes, PF_xxx
2102 int ssesize; // Size of SSE operands (16/32 bytes)
2103 uint immsize1; // Size of first immediate constant
2104 uint immsize2; // Size of second immediate constant
2105 uint mainsize; // Size of command with prefixes
2106 uint modsize; // Size of ModRegRM/SIB bytes
2107 uint dispsize; // Size of address offset
2108 int usesdatasize; // May have data size prefix
2109 int usesaddrsize; // May have address size prefix
2110 int usessegment; // May have segment override prefix
2111 }
2112
2113 // ////////////////////////////////////////////////////////////////////////// //
2114 // /////////////////////////// SERVICE FUNCTIONS //////////////////////////// //
2115
2116 // Nibble-to-hexdigit table, uppercase
2117 immutable string hexcharu = "0123456789ABCDEF";
2118
2119 // Nibble-to-hexdigit table, lowercase
2120 immutable string hexcharl = "0123456789abcdef";
2121
2122 private __gshared char[256] cvtlower;
2123
2124 private void tstrlwr (char[] s) {
2125 foreach (ref char ch; s) {
2126 import std.ascii : toLower;
2127 ch = ch.toLower;
2128 }
2129 }
2130
2131 // Copies at most n-1 wide characters from src to dest and assures that dest is
2132 // null-terminated. Slow but reliable. Returns number of copied characters, not
2133 // including the terminal null. Attention, does not check that input parameters
2134 // are correct!
2135 private int Tstrcopy (char* dest, int n, const(char)* src) {
2136 int i;
2137 if (n <= 0) return 0;
2138 for (i = 0; i < n-1; ++i) {
2139 if (*src == '\0') break;
2140 *dest++ = *src++;
2141 }
2142 *dest = '\0';
2143 return i;
2144 }
2145
2146 // Copies at most n-1 wide characters from src to dest and assures that dest is
2147 // null-terminated. If lowercase is 1, simultaneously converts it to lower
2148 // case. Slow but reliable. Returns number of copied characters, not including
2149 // the terminal null. Attention, does not check that input parameters are
2150 // correct!
2151 private int Tcopycase (char* dest, int n, const(char)* src, int lowercase) {
2152 int i;
2153 if (n <= 0)
2154 return 0;
2155 for (i = 0; i < n-1; i++) {
2156 if (*src == '\0') break;
2157 if (lowercase)
2158 *dest++ = cvtlower[*src++]; // Much faster than call to tolower()
2159 else
2160 *dest++ = *src++;
2161 }
2162 *dest = '\0';
2163 return i;
2164 }
2165
2166
2167 // Dumps ncode bytes of code to the string s. Returns length of resulting text,
2168 // characters, not including terminal zero. Attention, does not check that
2169 // input parameters are correct or that s has sufficient length!
2170 private int Thexdump (char* s, const(ubyte)* code, int ncode, int lowercase) {
2171 int d, n;
2172 immutable(char)* hexchar = (lowercase ? hexcharl.ptr : hexcharu.ptr);
2173 n = 0;
2174 while (ncode > 0) {
2175 d = *code++;
2176 s[n++] = hexchar[(d>>4)&0x0F];
2177 s[n++] = hexchar[d&0x0F];
2178 --ncode;
2179 }
2180 s[n] = '\0';
2181 return n;
2182 }
2183
2184 // Converts unsigned 1-, 2- or 4-byte number to hexadecimal text, according to
2185 // the specified mode and type of argument. String s must be at least SHORTNAME
2186 // characters long. Returns length of resulting text in characters, not
2187 // including the terminal zero.
2188 private int Hexprint (int size, char* s, uint u, const(t_imdata)* im, uint arg) {
2189 int i, k, ndigit, lastdigit;
2190 uint nummode, mod;
2191 char[SHORTNAME] buf;
2192 immutable(char)* hexchar;
2193 if (size == 1)
2194 u &= 0x000000FF; // 8-bit number
2195 else if (size == 2)
2196 u &= 0x0000FFFF; // 16-bit number
2197 else
2198 size = 4; // Correct possible errors
2199 mod = arg&B_MODMASK;
2200 if (mod == B_ADDR)
2201 nummode = im.config.memmode;
2202 else if (mod == B_JMPCALL || mod == B_JMPCALLFAR)
2203 nummode = im.config.jmpmode;
2204 else if (mod == B_BINARY)
2205 nummode = im.config.binconstmode;
2206 else
2207 nummode = im.config.constmode;
2208 hexchar = (im.config.lowercase?hexcharl.ptr:hexcharu.ptr);
2209 buf[SHORTNAME-1] = '\0';
2210 k = SHORTNAME-1;
2211 if ((nummode&NUM_DECIMAL) != 0 && (mod == B_SIGNED || mod == B_UNSIGNED ||
2212 (u < DECLIMIT && mod != B_BINARY && mod != B_JMPCALL && mod != B_JMPCALLFAR))
2213 ) {
2214 // Decode as decimal unsigned number.
2215 if ((nummode&NUM_STYLE) == NUM_OLLY && u >= 10)
2216 buf[--k] = '.'; // Period marks decimals in OllyDbg
2217 do {
2218 buf[--k] = hexchar[u%10];
2219 u /= 10;
2220 } while (u != 0); }
2221 else {
2222 // Decode as hexadecimal number.
2223 if (nummode&NUM_LONG) // 2, 4 or 8 significant digits
2224 ndigit = size*2;
2225 else
2226 ndigit = 1;
2227 if ((nummode&NUM_STYLE) == NUM_STD)
2228 buf[--k] = 'h';
2229 for (i = 0; i < ndigit || u != 0; i++) {
2230 lastdigit = u&0x0F;
2231 buf[--k] = hexchar[lastdigit];
2232 u = (u>>4)&0x0FFFFFFF; }
2233 if ((nummode&NUM_STYLE) == NUM_X) {
2234 buf[--k] = 'x';
2235 buf[--k] = '0'; }
2236 else if (lastdigit >= 10 &&
2237 ((nummode&NUM_STYLE) != NUM_OLLY || i < (mod == B_BINARY ? size*2 : 8)))
2238 {
2239 buf[--k] = '0';
2240 }
2241 }
2242 return Tstrcopy(s, SHORTNAME, buf.ptr+k);
2243 }
2244
2245
2246 // ////////////////////////////////////////////////////////////////////////// //
2247 // ////////////////////// INTERNAL DISASSEMBLER TABLES ////////////////////// //
2248 private:
2249 // Element of command chain
2250 struct t_chain {
2251 immutable(AsmInstrDsc)* pcmd; // Pointer to command descriptor or null
2252 t_chain* pnext; // Pointer to next element in chain
2253 }
2254
2255 // ModRM byte decoding
2256 struct t_modrm {
2257 uint size; // Total size with SIB and disp, bytes
2258 t_modrm* psib; // Pointer to SIB table or null
2259 uint dispsize; // Size of displacement or 0 if none
2260 uint features; // Operand features, set of OP_xxx
2261 int reg; // Register index or REG_UNDEF
2262 int defseg; // Default selector (SEG_xxx)
2263 ubyte[NREG] scale; // Scales of registers in memory address
2264 uint aregs; // List of registers used in address
2265 int basereg; // Register used as base or REG_UNDEF
2266 char[SHORTNAME] ardec; // Register part of address, INTEL fmt
2267 char[SHORTNAME] aratt; // Register part of address, AT&T fmt
2268 }
2269
2270 __gshared t_chain* cmdchain; // Commands sorted by first CMDMASK bits
2271 __gshared t_modrm[256] modrm16; // 16-bit ModRM decodings
2272 __gshared t_modrm[256] modrm32; // 32-bit ModRM decodings without SIB
2273 __gshared t_modrm[256] sib0; // ModRM-SIB decodings with Mod=00
2274 __gshared t_modrm[256] sib1; // ModRM-SIB decodings with Mod=01
2275 __gshared t_modrm[256] sib2; // ModRM-SIB decodings with Mod=10
2276
2277 // Initializes disassembler tables. Call this function once during startup.
2278 // Returns 0 on success and -1 if initialization was unsuccessful. In the last
2279 // case, continuation is not possible and program must terminate.
2280 private void Preparedisasm () {
2281 import core.stdc.stdlib : malloc;
2282 import core.stdc.string : memset;
2283 int n, c, reg, sreg, scale, nchain;
2284 uint u, code, mask;
2285 //immutable(AsmInstrDsc)* pcmd;
2286 t_chain* pchain;
2287 t_modrm* pmrm, psib;
2288
2289 void tsp (char[] arr, string s) {
2290 if (s.length > arr.length) assert(0, "wtf?!");
2291 arr[] = 0;
2292 arr[0..s.length] = s[];
2293 }
2294
2295 // sort command descriptors into command chains by first CMDMASK bits.
2296 cmdchain = cast(t_chain*)malloc(NCHAIN*t_chain.sizeof);
2297 if (cmdchain is null) assert(0, "out of memory"); // Low memory
2298 memset(cmdchain, 0, NCHAIN*t_chain.sizeof);
2299 nchain = CMDMASK+1; // number of command chains
2300 foreach (immutable ref pcc; asmInstrTable) {
2301 auto pcmd = &pcc;
2302 if ((pcmd.cmdtype&D_CMDTYPE) == D_PSEUDO) continue; // Pseudocommand, for search models only
2303 code = pcmd.code;
2304 mask = pcmd.mask&CMDMASK;
2305 for (u = 0; u < CMDMASK+1; ++u) {
2306 if (((u^code)&mask) != 0) continue; // Command has different first bytes
2307 pchain = cmdchain+u;
2308 while (pchain.pcmd !is null && pchain.pnext !is null) pchain = pchain.pnext; // Walk chain to the end
2309 if (pchain.pcmd is null) {
2310 pchain.pcmd = pcmd;
2311 } else if (nchain >= NCHAIN) {
2312 assert(0, "too many commands in disasm"); // Too many commands
2313 } else {
2314 pchain.pnext = cmdchain+nchain; // Prolongate chain
2315 pchain = pchain.pnext;
2316 pchain.pcmd = pcmd;
2317 ++nchain;
2318 }
2319 }
2320 }
2321 // Prepare 16-bit ModRM decodings.
2322 memset(modrm16.ptr, 0, modrm16.sizeof);
2323 for (c = 0x00, pmrm = modrm16.ptr; c <= 0xFF; ++c, ++pmrm) {
2324 reg = c&0x07;
2325 if ((c&0xC0) == 0xC0) {
2326 // Register in ModRM.
2327 pmrm.size = 1;
2328 pmrm.features = 0; // Register, its type as yet unknown
2329 pmrm.reg = reg;
2330 pmrm.defseg = SEG_UNDEF;
2331 pmrm.basereg = REG_UNDEF;
2332 } else if ((c&0xC7) == 0x06) {
2333 // Special case of immediate address.
2334 pmrm.size = 3;
2335 pmrm.dispsize = 2;
2336 pmrm.features = OP_MEMORY|OP_OPCONST|OP_ADDR16;
2337 pmrm.reg = REG_UNDEF;
2338 pmrm.defseg = SEG_DS;
2339 pmrm.basereg = REG_UNDEF;
2340 } else {
2341 pmrm.features = OP_MEMORY|OP_INDEXED|OP_ADDR16;
2342 if ((c&0xC0) == 0x40) {
2343 pmrm.dispsize = 1;
2344 pmrm.features |= OP_OPCONST;
2345 } else if ((c&0xC0) == 0x80) {
2346 pmrm.dispsize = 2;
2347 pmrm.features |= OP_OPCONST;
2348 }
2349 pmrm.size = pmrm.dispsize+1;
2350 pmrm.reg = REG_UNDEF;
2351 final switch (reg) {
2352 case 0:
2353 pmrm.scale[REG_EBX] = 1;
2354 pmrm.scale[REG_ESI] = 1;
2355 pmrm.defseg = SEG_DS;
2356 tsp(pmrm.ardec[], "BX+SI");
2357 tsp(pmrm.aratt[], "%BX, %SI");
2358 pmrm.aregs = (1<<REG_EBX)|(1<<REG_ESI);
2359 pmrm.basereg = REG_ESI;
2360 break;
2361 case 1:
2362 pmrm.scale[REG_EBX] = 1;
2363 pmrm.scale[REG_EDI] = 1;
2364 pmrm.defseg = SEG_DS;
2365 tsp(pmrm.ardec[], "BX+DI");
2366 tsp(pmrm.aratt[], "%BX, %DI");
2367 pmrm.aregs = (1<<REG_EBX)|(1<<REG_EDI);
2368 pmrm.basereg = REG_EDI;
2369 break;
2370 case 2:
2371 pmrm.scale[REG_EBP] = 1;
2372 pmrm.scale[REG_ESI] = 1;
2373 pmrm.defseg = SEG_SS;
2374 tsp(pmrm.ardec[], "BP+SI");
2375 tsp(pmrm.aratt[], "%BP, %SI");
2376 pmrm.aregs = (1<<REG_EBP)|(1<<REG_ESI);
2377 pmrm.basereg = REG_ESI;
2378 break;
2379 case 3:
2380 pmrm.scale[REG_EBP] = 1;
2381 pmrm.scale[REG_EDI] = 1;
2382 pmrm.defseg = SEG_SS;
2383 tsp(pmrm.ardec[], "BP+DI");
2384 tsp(pmrm.aratt[], "%BP, %DI");
2385 pmrm.aregs = (1<<REG_EBP)|(1<<REG_EDI);
2386 pmrm.basereg = REG_EDI;
2387 break;
2388 case 4:
2389 pmrm.scale[REG_ESI] = 1;
2390 pmrm.defseg = SEG_DS;
2391 tsp(pmrm.ardec[], "SI");
2392 tsp(pmrm.aratt[], "%SI");
2393 pmrm.aregs = (1<<REG_ESI);
2394 pmrm.basereg = REG_ESI;
2395 break;
2396 case 5:
2397 pmrm.scale[REG_EDI] = 1;
2398 pmrm.defseg = SEG_DS;
2399 tsp(pmrm.ardec[], "DI");
2400 tsp(pmrm.aratt[], "%DI");
2401 pmrm.aregs = (1<<REG_EDI);
2402 pmrm.basereg = REG_EDI;
2403 break;
2404 case 6:
2405 pmrm.scale[REG_EBP] = 1;
2406 pmrm.defseg = SEG_SS;
2407 tsp(pmrm.ardec[], "BP");
2408 tsp(pmrm.aratt[], "%BP");
2409 pmrm.aregs = (1<<REG_EBP);
2410 pmrm.basereg = REG_EBP;
2411 break;
2412 case 7:
2413 pmrm.scale[REG_EBX] = 1;
2414 pmrm.defseg = SEG_DS;
2415 tsp(pmrm.ardec[], "BX");
2416 tsp(pmrm.aratt[], "%BX");
2417 pmrm.aregs = (1<<REG_EBX);
2418 pmrm.basereg = REG_EBX;
2419 break;
2420 }
2421 }
2422 }
2423 // Prepare 32-bit ModRM decodings without SIB.
2424 memset(modrm32.ptr, 0, modrm32.sizeof);
2425 for (c = 0x00, pmrm = modrm32.ptr; c <= 0xFF; ++c, ++pmrm) {
2426 reg = c&0x07;
2427 if ((c&0xC0) == 0xC0) {
2428 // Register in ModRM.
2429 pmrm.size = 1;
2430 pmrm.features = 0; // Register, its type as yet unknown
2431 pmrm.reg = reg;
2432 pmrm.defseg = SEG_UNDEF;
2433 pmrm.basereg = REG_UNDEF;
2434 } else if ((c&0xC7) == 0x05) {
2435 // Special case of 32-bit immediate address.
2436 pmrm.size = 5;
2437 pmrm.dispsize = 4;
2438 pmrm.features = OP_MEMORY|OP_OPCONST;
2439 pmrm.reg = REG_UNDEF;
2440 pmrm.defseg = SEG_DS;
2441 pmrm.basereg = REG_UNDEF;
2442 } else {
2443 // Regular memory address.
2444 pmrm.features = OP_MEMORY;
2445 pmrm.reg = REG_UNDEF;
2446 if ((c&0xC0) == 0x40) {
2447 pmrm.dispsize = 1; // 8-bit sign-extended displacement
2448 pmrm.features |= OP_OPCONST;
2449 } else if ((c&0xC0) == 0x80) {
2450 pmrm.dispsize = 4; // 32-bit displacement
2451 pmrm.features |= OP_OPCONST;
2452 }
2453 if (reg == REG_ESP) {
2454 // SIB byte follows, decode with sib32.
2455 if ((c&0xC0) == 0x00) pmrm.psib = sib0.ptr;
2456 else if ((c&0xC0) == 0x40) pmrm.psib = sib1.ptr;
2457 else pmrm.psib = sib2.ptr;
2458 pmrm.basereg = REG_UNDEF;
2459 } else {
2460 pmrm.size = 1+pmrm.dispsize;
2461 pmrm.features |= OP_INDEXED;
2462 pmrm.defseg = (reg == REG_EBP ? SEG_SS : SEG_DS);
2463 pmrm.scale[reg] = 1;
2464 tsp(pmrm.ardec, regname32[reg]);
2465 pmrm.aratt[0] = '%';
2466 tsp(pmrm.aratt[1..$]/*, SHORTNAME-1*/, regname32[reg]);
2467 pmrm.aregs = (1<<reg);
2468 pmrm.basereg = reg;
2469 }
2470 }
2471 }
2472 // Prepare 32-bit ModRM decodings with SIB, case Mod=00: usually no disp.
2473 memset(sib0.ptr, 0, sib0.sizeof);
2474 for (c = 0x00, psib = sib0.ptr; c <= 0xFF; ++c, ++psib) {
2475 psib.features = OP_MEMORY;
2476 psib.reg = REG_UNDEF;
2477 reg = c&0x07;
2478 sreg = (c>>3)&0x07;
2479 if ((c&0xC0) == 0x00) scale = 1;
2480 else if ((c&0xC0) == 0x40) scale = 2;
2481 else if ((c&0xC0) == 0x80) scale = 4;
2482 else scale = 8;
2483 if (sreg != REG_ESP) {
2484 psib.scale[sreg] = cast(ubyte)scale;
2485 n = Tstrcopy(psib.ardec.ptr, SHORTNAME, regname32[sreg].ptr);
2486 psib.aregs = (1<<sreg);
2487 psib.features |= OP_INDEXED;
2488 if (scale > 1) {
2489 psib.ardec[n++] = '*';
2490 psib.ardec[n++] = cast(char)('0'+scale);
2491 psib.ardec[n] = '\0';
2492 }
2493 } else {
2494 n = 0;
2495 }
2496 if (reg == REG_EBP) {
2497 psib.size = 6;
2498 psib.dispsize = 4;
2499 psib.features |= OP_OPCONST;
2500 psib.defseg = SEG_DS;
2501 psib.basereg = REG_UNDEF;
2502 } else {
2503 psib.size = 2;
2504 psib.defseg = (reg == REG_ESP || reg == REG_EBP ? SEG_SS : SEG_DS);
2505 psib.scale[reg]++;
2506 psib.features |= OP_INDEXED;
2507 if (n != 0) psib.ardec[n++] = '+';
2508 Tstrcopy(psib.ardec.ptr+n, SHORTNAME-n, regname32[reg].ptr);
2509 psib.aregs |= (1<<reg);
2510 psib.basereg = reg;
2511 }
2512 if (reg != REG_EBP) {
2513 psib.aratt[0] = '%';
2514 n = 1;
2515 n += Tstrcopy(psib.aratt.ptr+n, SHORTNAME-n, regname32[reg].ptr);
2516 } else {
2517 n = 0;
2518 }
2519 if (sreg != REG_ESP) {
2520 n += Tstrcopy(psib.aratt.ptr+n, SHORTNAME-n, ", %");
2521 n += Tstrcopy(psib.aratt.ptr+n, SHORTNAME-n, regname32[sreg].ptr);
2522 if (scale > 1) {
2523 psib.aratt[n++] = ',';
2524 psib.aratt[n++] = cast(char)('0'+scale);
2525 psib.aratt[n] = '\0';
2526 }
2527 }
2528 }
2529 // Prepare 32-bit ModRM decodings with SIB, case Mod=01: 8-bit displacement.
2530 memset(sib1.ptr, 0, sib1.sizeof);
2531 for (c = 0x00, psib = sib1.ptr; c <= 0xFF; c++, psib++) {
2532 psib.features = OP_MEMORY|OP_INDEXED|OP_OPCONST;
2533 psib.reg = REG_UNDEF;
2534 reg = c&0x07;
2535 sreg = (c>>3)&0x07;
2536 if ((c&0xC0) == 0) scale = 1;
2537 else if ((c&0xC0) == 0x40) scale = 2;
2538 else if ((c&0xC0) == 0x80) scale = 4;
2539 else scale = 8;
2540 psib.size = 3;
2541 psib.dispsize = 1;
2542 psib.defseg = (reg == REG_ESP || reg == REG_EBP ? SEG_SS : SEG_DS);
2543 psib.scale[reg] = 1;
2544 psib.basereg = reg;
2545 psib.aregs = (1<<reg);
2546 if (sreg != REG_ESP) {
2547 psib.scale[sreg] += cast(ubyte)scale;
2548 n = Tstrcopy(psib.ardec.ptr, SHORTNAME, regname32[sreg].ptr);
2549 psib.aregs |= (1<<sreg);
2550 if (scale > 1) {
2551 psib.ardec[n++] = '*';
2552 psib.ardec[n++] = cast(char)('0'+scale);
2553 }
2554 } else {
2555 n = 0;
2556 }
2557 if (n != 0) psib.ardec[n++] = '+';
2558 Tstrcopy(psib.ardec.ptr+n, SHORTNAME-n, regname32[reg].ptr);
2559 psib.aratt[0] = '%'; n = 1;
2560 n += Tstrcopy(psib.aratt.ptr+n, SHORTNAME-n, regname32[reg].ptr);
2561 if (sreg != REG_ESP) {
2562 n += Tstrcopy(psib.aratt.ptr+n, SHORTNAME-n, ", %");
2563 n += Tstrcopy(psib.aratt.ptr+n, SHORTNAME-n, regname32[sreg].ptr);
2564 if (scale > 1) {
2565 psib.aratt[n++] = ',';
2566 psib.aratt[n++] = cast(char)('0'+scale);
2567 psib.aratt[n] = '\0';
2568 }
2569 }
2570 }
2571 // Prepare 32-bit ModRM decodings with SIB, case Mod=10: 32-bit displacement.
2572 memset(sib2.ptr, 0, sib2.sizeof);
2573 for (c = 0x00, psib = sib2.ptr; c <= 0xFF; c++, psib++) {
2574 psib.features = OP_MEMORY|OP_INDEXED|OP_OPCONST;
2575 psib.reg = REG_UNDEF;
2576 reg = c&0x07;
2577 sreg = (c>>3)&0x07;
2578 if ((c&0xC0) == 0) scale = 1;
2579 else if ((c&0xC0) == 0x40) scale = 2;
2580 else if ((c&0xC0) == 0x80) scale = 4;
2581 else scale = 8;
2582 psib.size = 6;
2583 psib.dispsize = 4;
2584 psib.defseg = (reg == REG_ESP || reg == REG_EBP ? SEG_SS : SEG_DS);
2585 psib.scale[reg] = 1;
2586 psib.basereg = reg;
2587 psib.aregs = (1<<reg);
2588 if (sreg != REG_ESP) {
2589 psib.scale[sreg] += cast(ubyte)scale;
2590 n = Tstrcopy(psib.ardec.ptr, SHORTNAME, regname32[sreg].ptr);
2591 psib.aregs |= (1<<sreg);
2592 if (scale > 1) {
2593 psib.ardec[n++] = '*';
2594 psib.ardec[n++] = cast(char)('0'+scale);
2595 }
2596 } else {
2597 n = 0;
2598 }
2599 if (n != 0) psib.ardec[n++] = '+';
2600 Tstrcopy(psib.ardec.ptr+n, SHORTNAME-n, regname32[reg].ptr);
2601 psib.aratt[0] = '%'; n = 1;
2602 n += Tstrcopy(psib.aratt.ptr+n, SHORTNAME-n, regname32[reg].ptr);
2603 if (sreg != REG_ESP) {
2604 n += Tstrcopy(psib.aratt.ptr+n, SHORTNAME-n, ", %");
2605 n += Tstrcopy(psib.aratt.ptr+n, SHORTNAME-n, regname32[sreg].ptr);
2606 if (scale > 1) {
2607 psib.aratt[n++] = ',';
2608 psib.aratt[n++] = cast(char)('0'+scale);
2609 psib.aratt[n] = '\0';
2610 }
2611 }
2612 }
2613 // Fill lowercase conversion table. This table replaces tolower(). When
2614 // compiled with Borland C++ Builder, spares significant time.
2615 for (c = 0; c < 256; ++c) {
2616 import std.ascii : toLower;
2617 cvtlower[c] = toLower(cast(char)c);
2618 }
2619 }
2620
2621 // Frees resources allocated by Preparedisasm(). Call this function once
2622 // during shutdown after disassembling service is no longer necessary.
2623 void Finishdisasm () {
2624 import core.stdc.stdlib : free;
2625 if (cmdchain !is null) {
2626 free(cmdchain);
2627 cmdchain = null;
2628 }
2629 }
2630
2631 shared static this () { Preparedisasm(); }
2632 shared static ~this () { Finishdisasm(); }
2633
2634
2635 ////////////////////////////////////////////////////////////////////////////////
2636 ////////////////////////////// AUXILIARY ROUTINES //////////////////////////////
2637
2638 // Given index of byte register, returns index of 32-bit container.
2639 private int Byteregtodwordreg (int bytereg) {
2640 if (bytereg < 0 || bytereg >= NREG) return REG_UNDEF;
2641 if (bytereg >= 4) return bytereg-4;
2642 return bytereg;
2643 }
2644
2645 // Checks prefix override flags and generates warnings if prefix is superfluous.
2646 // Returns index of segment register. Note that Disasm() assures that two
2647 // segment override bits in im.prefixlist can't be set simultaneously.
2648 private int Getsegment (t_imdata *im, int arg, int defseg) {
2649 if ((im.prefixlist&PF_SEGMASK) == 0) return defseg; // Optimization for most frequent case
2650 switch (im.prefixlist&PF_SEGMASK) {
2651 case PF_ES:
2652 if (defseg == SEG_ES) im.da.warnings |= DAW_DEFSEG;
2653 if (arg&B_NOSEG) im.da.warnings |= DAW_SEGPREFIX;
2654 return SEG_ES;
2655 case PF_CS:
2656 if (defseg == SEG_CS) im.da.warnings |= DAW_DEFSEG;
2657 if (arg&B_NOSEG) im.da.warnings |= DAW_SEGPREFIX;
2658 return SEG_CS;
2659 case PF_SS:
2660 if (defseg == SEG_SS) im.da.warnings |= DAW_DEFSEG;
2661 if (arg&B_NOSEG) im.da.warnings |= DAW_SEGPREFIX;
2662 return SEG_SS;
2663 case PF_DS:
2664 if (defseg == SEG_DS) im.da.warnings |= DAW_DEFSEG;
2665 if (arg&B_NOSEG) im.da.warnings |= DAW_SEGPREFIX;
2666 return SEG_DS;
2667 case PF_FS:
2668 if (defseg == SEG_FS) im.da.warnings |= DAW_DEFSEG;
2669 if (arg&B_NOSEG) im.da.warnings |= DAW_SEGPREFIX;
2670 return SEG_FS;
2671 case PF_GS:
2672 if (defseg == SEG_GS) im.da.warnings |= DAW_DEFSEG;
2673 if (arg&B_NOSEG) im.da.warnings |= DAW_SEGPREFIX;
2674 return SEG_GS;
2675 default: return defseg; // Most frequent case of default segment
2676 }
2677 }
2678
2679 private bool decodeAddr (t_imdata* im, char[] buf, uint addr) {
2680 if (im.decodeaddress is null) return false;
2681 auto name = im.decodeaddress(addr);
2682 if (name.length == 0) return false;
2683 if (name.length > buf.length-1) name = name[0..buf.length-1];
2684 buf[0..name.length] = name[];
2685 buf[name.length] = 0;
2686 return true;
2687 }
2688
2689
2690 // Decodes generalized memory address to text.
2691 private void Memaddrtotext (t_imdata* im, int arg, int datasize, int seg, const(char)* regpart, int constpart, char* s) {
2692 int n;
2693 char[TEXTLEN] label = void;
2694 if (im.config.disasmmode == DAMODE_ATT) {
2695 // AT&T memory address syntax is so different from Intel that I process it
2696 // separately from the rest.
2697 n = 0;
2698 if ((arg&B_MODMASK) == B_JMPCALL) s[n++] = '*';
2699 // On request, I show only explicit segments.
2700 if ((im.config.putdefseg && (arg&B_NOSEG) == 0) || (im.prefixlist&PF_SEGMASK) != 0) {
2701 s[n++] = '%';
2702 n += Tcopycase(s+n, TEXTLEN-n, segname[seg].ptr, im.config.lowercase);
2703 s[n++] = ':';
2704 }
2705 // Add constant part (offset).
2706 if (constpart < 0 && constpart > NEGLIMIT) {
2707 s[n++] = '-';
2708 n += Hexprint((im.prefixlist&PF_ASIZE?2:4), s+n, -constpart, im, B_ADDR);
2709 } else if (constpart != 0) {
2710 if (seg != SEG_FS && seg != SEG_GS && decodeAddr(im, label[], constpart)) {
2711 n += Tstrcopy(s+n, TEXTLEN-n, label.ptr);
2712 } else {
2713 n += Hexprint((im.prefixlist&PF_ASIZE ? 2 : 4), s+n, constpart, im, B_ADDR);
2714 }
2715 }
2716 // Add register part of address, may be absent.
2717 if (regpart[0] != '\0') {
2718 n += Tstrcopy(s+n, TEXTLEN-n, "(");
2719 n += Tcopycase(s+n, TEXTLEN-n, regpart, im.config.lowercase);
2720 n += Tstrcopy(s+n, TEXTLEN-n, ")");
2721 }
2722 } else {
2723 // Mark far and near jump/call addresses.
2724 if ((arg&B_MODMASK) == B_JMPCALLFAR) {
2725 n = Tcopycase(s, TEXTLEN, "FAR ", im.config.lowercase);
2726 } else if (im.config.shownear && (arg&B_MODMASK) == B_JMPCALL) {
2727 n = Tcopycase(s, TEXTLEN, "NEAR ", im.config.lowercase);
2728 } else {
2729 n = 0;
2730 }
2731 if (im.config.disasmmode != DAMODE_MASM) {
2732 s[n++] = '[';
2733 if ((im.prefixlist&PF_ASIZE) != 0 && regpart[0] == '\0') {
2734 n += Tcopycase(s+n, TEXTLEN-n, "SMALL ", im.config.lowercase);
2735 }
2736 }
2737 // If operand is longer than 32 bytes or of type B_ANYMEM (memory contents
2738 // unimportant), its size is not displayed. Otherwise, bit B_SHOWSIZE
2739 // indicates that explicit operand's size can't be omitted.
2740 if (datasize <= 32 && (arg&B_ARGMASK) != B_ANYMEM && (im.config.showmemsize != 0 || (arg&B_SHOWSIZE) != 0)) {
2741 if (im.config.disasmmode == DAMODE_HLA) n += Tcopycase(s+n, TEXTLEN-n, "TYPE ", im.config.lowercase);
2742 if ((arg&B_ARGMASK) == B_INTPAIR && im.config.disasmmode == DAMODE_IDEAL) {
2743 // If operand is a pair of integers (BOUND), Borland in IDEAL mode
2744 // expects size of single integer, whereas MASM requires size of the
2745 // whole pair.
2746 n += Tcopycase(s+n, TEXTLEN-n, sizename[datasize/2].ptr, im.config.lowercase);
2747 s[n++] = ' ';
2748 } else if (datasize == 16 && im.config.ssesizemode == 1) {
2749 n += Tcopycase(s+n, TEXTLEN-n, "XMMWORD ", im.config.lowercase);
2750 } else if (datasize == 32 && im.config.ssesizemode == 1) {
2751 n += Tcopycase(s+n, TEXTLEN-n, "YMMWORD ", im.config.lowercase);
2752 } else {
2753 n += Tcopycase(s+n, TEXTLEN-n, sizename[datasize].ptr, im.config.lowercase);
2754 s[n++] = ' ';
2755 }
2756 if (im.config.disasmmode == DAMODE_MASM) n += Tcopycase(s+n, TEXTLEN-n, "PTR ", im.config.lowercase);
2757 }
2758 // On request, I show only explicit segments.
2759 if ((im.config.putdefseg && (arg&B_NOSEG) == 0) || (im.prefixlist&PF_SEGMASK) != 0) {
2760 n += Tcopycase(s+n, TEXTLEN-n, segname[seg].ptr, im.config.lowercase);
2761 s[n++] = ':';
2762 }
2763 if (im.config.disasmmode == DAMODE_MASM) {
2764 s[n++] = '[';
2765 if ((im.prefixlist&PF_ASIZE) != 0 && regpart[0] == '\0') n += Tcopycase(s+n, TEXTLEN-n, "SMALL ", im.config.lowercase);
2766 }
2767 // Add register part of address, may be absent.
2768 if (regpart[0] != '\0') n += Tcopycase(s+n, TEXTLEN-n, regpart, im.config.lowercase);
2769 if (regpart[0] != '\0' && constpart < 0 && constpart > NEGLIMIT) {
2770 s[n++] = '-';
2771 n += Hexprint((im.prefixlist&PF_ASIZE ? 2 : 4), s+n, -constpart, im, B_ADDR);
2772 } else if (constpart != 0 || regpart[0] == '\0') {
2773 if (regpart[0] != '\0') s[n++] = '+';
2774 if (seg != SEG_FS && seg != SEG_GS && decodeAddr(im, label[], constpart)) {
2775 n += Tstrcopy(s+n, TEXTLEN-n, label.ptr);
2776 } else {
2777 n += Hexprint((im.prefixlist&PF_ASIZE?2:4), s+n, constpart, im, B_ADDR);
2778 }
2779 }
2780 n += Tstrcopy(s+n, TEXTLEN-n, "]");
2781 }
2782 s[n] = '\0';
2783 }
2784
2785 // Service function, returns granularity of MMX, 3DNow! and SSE operands.
2786 private int Getgranularity (uint arg) {
2787 int granularity;
2788 switch (arg&B_ARGMASK) {
2789 case B_MREG8x8: // MMX register as 8 8-bit integers
2790 case B_MMX8x8: // MMX reg/memory as 8 8-bit integers
2791 case B_MMX8x8DI: // MMX 8 8-bit integers at [DS:(E)DI]
2792 case B_XMM0I8x16: // XMM0 as 16 8-bit integers
2793 case B_SREGI8x16: // SSE register as 16 8-bit sigints
2794 case B_SVEXI8x16: // SSE reg in VEX as 16 8-bit sigints
2795 case B_SIMMI8x16: // SSE reg in immediate 8-bit constant
2796 case B_SSEI8x16: // SSE reg/memory as 16 8-bit sigints
2797 case B_SSEI8x16DI: // SSE 16 8-bit sigints at [DS:(E)DI]
2798 case B_SSEI8x8L: // Low 8 8-bit ints in SSE reg/memory
2799 case B_SSEI8x4L: // Low 4 8-bit ints in SSE reg/memory
2800 case B_SSEI8x2L: // Low 2 8-bit ints in SSE reg/memory
2801 granularity = 1;
2802 break;
2803 case B_MREG16x4: // MMX register as 4 16-bit integers
2804 case B_MMX16x4: // MMX reg/memory as 4 16-bit integers
2805 case B_SREGI16x8: // SSE register as 8 16-bit sigints
2806 case B_SVEXI16x8: // SSE reg in VEX as 8 16-bit sigints
2807 case B_SSEI16x8: // SSE reg/memory as 8 16-bit sigints
2808 case B_SSEI16x4L: // Low 4 16-bit ints in SSE reg/memory
2809 case B_SSEI16x2L: // Low 2 16-bit ints in SSE reg/memory
2810 granularity = 2;
2811 break;
2812 case B_MREG32x2: // MMX register as 2 32-bit integers
2813 case B_MMX32x2: // MMX reg/memory as 2 32-bit integers
2814 case B_3DREG: // 3DNow! register as 2 32-bit floats
2815 case B_3DNOW: // 3DNow! reg/memory as 2 32-bit floats
2816 case B_SREGF32x4: // SSE register as 4 32-bit floats
2817 case B_SVEXF32x4: // SSE reg in VEX as 4 32-bit floats
2818 case B_SREGF32L: // Low 32-bit float in SSE register
2819 case B_SVEXF32L: // Low 32-bit float in SSE in VEX
2820 case B_SREGF32x2L: // Low 2 32-bit floats in SSE register
2821 case B_SSEF32x4: // SSE reg/memory as 4 32-bit floats
2822 case B_SSEF32L: // Low 32-bit float in SSE reg/memory
2823 case B_SSEF32x2L: // Low 2 32-bit floats in SSE reg/memory
2824 granularity = 4;
2825 break;
2826 case B_XMM0I32x4: // XMM0 as 4 32-bit integers
2827 case B_SREGI32x4: // SSE register as 4 32-bit sigints
2828 case B_SVEXI32x4: // SSE reg in VEX as 4 32-bit sigints
2829 case B_SREGI32L: // Low 32-bit sigint in SSE register
2830 case B_SREGI32x2L: // Low 2 32-bit sigints in SSE register
2831 case B_SSEI32x4: // SSE reg/memory as 4 32-bit sigints
2832 case B_SSEI32x2L: // Low 2 32-bit sigints in SSE reg/memory
2833 granularity = 4;
2834 break;
2835 case B_MREG64: // MMX register as 1 64-bit integer
2836 case B_MMX64: // MMX reg/memory as 1 64-bit integer
2837 case B_XMM0I64x2: // XMM0 as 2 64-bit integers
2838 case B_SREGF64x2: // SSE register as 2 64-bit floats
2839 case B_SVEXF64x2: // SSE reg in VEX as 2 64-bit floats
2840 case B_SREGF64L: // Low 64-bit float in SSE register
2841 case B_SVEXF64L: // Low 64-bit float in SSE in VEX
2842 case B_SSEF64x2: // SSE reg/memory as 2 64-bit floats
2843 case B_SSEF64L: // Low 64-bit float in SSE reg/memory
2844 granularity = 8;
2845 break;
2846 case B_SREGI64x2: // SSE register as 2 64-bit sigints
2847 case B_SVEXI64x2: // SSE reg in VEX as 2 64-bit sigints
2848 case B_SSEI64x2: // SSE reg/memory as 2 64-bit sigints
2849 case B_SREGI64L: // Low 64-bit sigint in SSE register
2850 granularity = 8;
2851 break;
2852 default:
2853 granularity = 1; // Treat unknown ops as string of bytes
2854 break;
2855 }
2856 return granularity;
2857 }
2858
2859
2860 // ////////////////////////////////////////////////////////////////////////// //
2861 // /////////////////////// OPERAND DECODING ROUTINES //////////////////////// //
2862
2863 // Decodes 8/16/32-bit integer register operand. ATTENTION, calling routine
2864 // must set usesdatasize and usesaddrsize by itself!
2865 private void Operandintreg (t_imdata* im, uint datasize, int index, AsmOperand* op) {
2866 int n, reg32;
2867 op.features = OP_REGISTER;
2868 op.opsize = op.granularity = datasize;
2869 op.reg = index;
2870 op.seg = SEG_UNDEF;
2871 // Add container register to lists of used and modified registers.
2872 reg32 = (datasize == 1 ? Byteregtodwordreg(index) : index);
2873 if ((op.arg&B_CHG) == 0) {
2874 op.uses = (1<<reg32);
2875 im.da.uses |= (1<<reg32);
2876 }
2877 if (op.arg&(B_CHG|B_UPD)) {
2878 op.modifies = (1<<reg32);
2879 im.da.modifies |= (1<<reg32);
2880 }
2881 // Warn if ESP is misused.
2882 if ((op.arg&B_NOESP) != 0 && reg32 == REG_ESP) im.da.warnings |= DAW_NOESP;
2883 // Decode name of integer register.
2884 if (im.damode&DA_TEXT) {
2885 n = 0;
2886 if (im.config.disasmmode == DAMODE_ATT) {
2887 if ((op.arg&B_MODMASK) == B_JMPCALL) op.text[n++] = '*';
2888 op.text[n++] = '%';
2889 }
2890 // Most frequent case first
2891 if (datasize == 4) Tcopycase(op.text.ptr+n, TEXTLEN-n, regname32[index].ptr, im.config.lowercase);
2892 else if (datasize == 1) Tcopycase(op.text.ptr+n, TEXTLEN-n, regname8[index].ptr, im.config.lowercase);
2893 else Tcopycase(op.text.ptr+n, TEXTLEN-n, regname16[index].ptr, im.config.lowercase); // 16-bit registers are seldom
2894 }
2895 }
2896
2897 // Decodes 16/32-bit memory address in ModRM/SIB bytes. Returns full length of
2898 // address (ModRM+SIB+displacement) in bytes, 0 if ModRM indicates register
2899 // operand and -1 on error. ATTENTION, calling routine must set usesdatasize,
2900 // granularity (preset to datasize) and reg together with OP_MODREG by itself!
2901 private int Operandmodrm (t_imdata* im, uint datasize, const(ubyte)* cmd, uint cmdsize, AsmOperand* op) {
2902 import core.stdc.string : memcpy;
2903 char* ardec;
2904 t_modrm* pmrm;
2905 if (cmdsize == 0) { im.da.errors |= DAE_CROSS; return -1; } // Command crosses end of memory block
2906 // Decode ModRM/SIB. Most of the work is already done in Preparedisasm(), we
2907 // only need to find corresponding t_modrm.
2908 if (im.prefixlist&PF_ASIZE) {
2909 // 16-bit address
2910 pmrm = modrm16.ptr+cmd[0];
2911 im.modsize = 1;
2912 } else {
2913 pmrm = modrm32.ptr+cmd[0];
2914 if (pmrm.psib is null) {
2915 im.modsize = 1; // No SIB byte
2916 } else {
2917 if (cmdsize < 2) { im.da.errors |= DAE_CROSS; return -1; } // Command crosses end of memory block
2918 pmrm = pmrm.psib+cmd[1];
2919 im.modsize = 2; // Both ModRM and SIB
2920 }
2921 }
2922 // Check whether ModRM indicates register operand and immediately return if
2923 // true. As a side effect, modsize is already set.
2924 if ((cmd[0]&0xC0) == 0xC0) return 0;
2925 // Operand in memory.
2926 op.opsize = datasize;
2927 op.granularity = datasize; // Default, may be overriden later
2928 op.reg = REG_UNDEF;
2929 im.usesaddrsize = 1; // Address size prefix is meaningful
2930 im.usessegment = 1; // Segment override prefix is meaningful
2931 // Fetch precalculated t_modrm fields.
2932 op.features = pmrm.features;
2933 memcpy(op.scale.ptr, pmrm.scale.ptr, 8);
2934 op.aregs = pmrm.aregs;
2935 im.da.uses |= pmrm.aregs; // Mark registers used to form address
2936 // Get displacement, if any.
2937 im.dispsize = pmrm.dispsize;
2938 if (pmrm.dispsize != 0) {
2939 if (cmdsize < pmrm.size) { im.da.errors |= DAE_CROSS; return -1; } // Command crosses end of memory block
2940 if (pmrm.dispsize == 1) {
2941 // 8-bit displacement is sign-extended
2942 op.opconst = im.da.memconst = cast(byte)cmd[im.modsize];
2943 } else if (pmrm.dispsize == 4) {
2944 // 32-bit full displacement
2945 im.da.memfixup = im.mainsize+im.modsize; // Possible 32-bit fixup
2946 op.opconst = im.da.memconst = *cast(uint*)(cmd+im.modsize);
2947 } else {
2948 // 16-bit displacement, very rare
2949 op.opconst = im.da.memconst = *cast(ushort*)(cmd+im.modsize);
2950 }
2951 }
2952 // Get segment.
2953 op.seg = Getsegment(im, op.arg, pmrm.defseg);
2954 // Warn if memory contents is 16-bit jump/call destination.
2955 if (datasize == 2 && (op.arg&B_MODMASK) == B_JMPCALL) im.da.warnings |= DAW_JMP16;
2956 // Decode memory operand to text, if requested.
2957 if (im.damode&DA_TEXT) {
2958 ardec = (im.config.disasmmode == DAMODE_ATT ? pmrm.aratt.ptr : pmrm.ardec.ptr);
2959 Memaddrtotext(im, op.arg, datasize, op.seg, ardec, op.opconst, op.text.ptr);
2960 }
2961 return pmrm.size;
2962 }
2963
2964 // Decodes 16/32-bit immediate address (used only for 8/16/32-bit memory-
2965 // accumulator moves). ATTENTION, calling routine must set usesdatasize by
2966 // itself!
2967 private void Operandimmaddr (t_imdata* im, uint datasize, const(ubyte)* cmd, uint cmdsize, AsmOperand* op) {
2968 im.dispsize = (im.prefixlist&PF_ASIZE ? 2 : 4);
2969 if (cmdsize < im.dispsize) { im.da.errors |= DAE_CROSS; return; } // Command crosses end of memory block
2970 op.features = OP_MEMORY|OP_OPCONST;
2971 op.opsize = op.granularity = datasize;
2972 op.reg = REG_UNDEF;
2973 im.usesaddrsize = 1; // Address size prefix is meaningful
2974 im.usessegment = 1; // Segment override prefix is meaningful
2975 // 32-bit immediate address?
2976 if (im.dispsize == 4) {
2977 // 32-bit address means possible fixup, calculate offset.
2978 im.da.memfixup = im.mainsize;
2979 op.opconst = im.da.memconst = *cast(uint*)cmd;
2980 } else {
2981 // 16-bit immediate address, very rare
2982 op.opconst = im.da.memconst = *cast(ushort*)cmd;
2983 op.features |= OP_ADDR16;
2984 }
2985 // Get segment.
2986 op.seg = Getsegment(im, op.arg, SEG_DS);
2987 // Decode memory operand to text, if requested.
2988 if (im.damode&DA_TEXT) Memaddrtotext(im, op.arg, datasize, op.seg, "", op.opconst, op.text.ptr);
2989 }
2990
2991 // Decodes simple register address ([reg16] or [reg32]). Flag changesreg must
2992 // be 0 if register remains unchanged and 1 if it changes. If fixseg is set to
2993 // SEG_UNDEF, assumes overridable DS:, otherwise assumes fixsegment that cannot
2994 // be overriden with segment prefix. If fixaddrsize is 2 or 4, assumes 16- or
2995 // 32-bit addressing only, otherwise uses default. ATTENTION, calling routine
2996 // must set usesdatasize by itself!
2997 private void Operandindirect (t_imdata* im, int index, int changesreg, int fixseg, int fixaddrsize, uint datasize, AsmOperand* op) {
2998 int n;
2999 uint originallist;
3000 char[SHORTNAME] ardec;
3001 op.features = OP_MEMORY|OP_INDEXED;
3002 if (changesreg) {
3003 op.features |= OP_MODREG;
3004 op.reg = index;
3005 im.da.modifies |= (1<<index);
3006 } else {
3007 op.reg = REG_UNDEF;
3008 }
3009 if (fixaddrsize == 2) {
3010 op.features |= OP_ADDR16;
3011 } else if (fixaddrsize == 0) {
3012 // Address size prefix is meaningful
3013 im.usesaddrsize = 1;
3014 if (im.prefixlist&PF_ASIZE) {
3015 op.features |= OP_ADDR16;
3016 fixaddrsize = 2;
3017 }
3018 }
3019 // Get segment.
3020 if (fixseg == SEG_UNDEF) {
3021 op.seg = Getsegment(im, op.arg, SEG_DS);
3022 im.usessegment = 1; // Segment override prefix is meaningful
3023 } else {
3024 op.seg = fixseg;
3025 }
3026 op.opsize = datasize;
3027 op.granularity = datasize; // Default, may be overriden later
3028 op.scale[index] = 1;
3029 op.aregs = (1<<index);
3030 im.da.uses |= (1<<index);
3031 // Warn if memory contents is 16-bit jump/call destination.
3032 if (datasize == 2 && (op.arg&B_MODMASK) == B_JMPCALL) im.da.warnings |= DAW_JMP16;
3033 // Decode source operand to text, if requested.
3034 if (im.damode&DA_TEXT) {
3035 if (im.config.disasmmode == DAMODE_ATT) { ardec[0] = '%'; n = 1; } else n = 0;
3036 if (fixaddrsize == 2) {
3037 Tstrcopy(ardec.ptr+n, SHORTNAME-n, regname16[index].ptr);
3038 } else {
3039 Tstrcopy(ardec.ptr+n, SHORTNAME-n, regname32[index].ptr);
3040 }
3041 if (fixseg == SEG_UNDEF) {
3042 Memaddrtotext(im, op.arg, datasize, op.seg, ardec.ptr, 0, op.text.ptr);
3043 } else {
3044 originallist = im.prefixlist;
3045 im.prefixlist &= ~PF_SEGMASK;
3046 Memaddrtotext(im, op.arg, datasize, op.seg, ardec.ptr, 0, op.text.ptr);
3047 im.prefixlist = originallist;
3048 }
3049 }
3050 }
3051
3052 // Decodes XLAT source address ([(E)BX+AL]). Note that I set scale of EAX to 1,
3053 // which is not exactly true. ATTENTION, calling routine must set usesdatasize
3054 // by itself!
3055 private void Operandxlat (t_imdata* im, AsmOperand* op) {
3056 immutable(char)* ardec;
3057 op.features = OP_MEMORY|OP_INDEXED;
3058 if (im.prefixlist&PF_ASIZE) op.features |= OP_ADDR16;
3059 im.usesaddrsize = 1; // Address size prefix is meaningful
3060 im.usessegment = 1; // Segment override prefix is meaningful
3061 op.opsize = 1;
3062 op.granularity = 1;
3063 op.reg = REG_UNDEF;
3064 // Get segment.
3065 op.seg = Getsegment(im, op.arg, SEG_DS);
3066 op.scale[REG_EAX] = 1; // This is not correct!
3067 op.scale[REG_EBX] = 1;
3068 op.aregs = (1<<REG_EAX)|(1<<REG_EBX);
3069 im.da.uses |= op.aregs;
3070 // Decode address to text, if requested.
3071 if (im.damode&DA_TEXT) {
3072 if (im.config.disasmmode == DAMODE_ATT) {
3073 ardec = (im.prefixlist&PF_ASIZE ? "%BX, %AL" : "%EBX, %AL");
3074 } else {
3075 ardec = (im.prefixlist&PF_ASIZE ? "BX+AL" : "EBX+AL");
3076 }
3077 Memaddrtotext(im, op.arg, 1, op.seg, ardec, 0, op.text.ptr);
3078 }
3079 }
3080
3081 // Decodes stack pushes of any size, including implicit return address in
3082 // CALLs. ATTENTION, calling routine must set usesdatasize by itself!
3083 private void Operandpush (t_imdata* im, uint datasize, AsmOperand* op) {
3084 int n, addrsize;
3085 uint originallist;
3086 char[SHORTNAME] ardec;
3087 op.features = OP_MEMORY|OP_INDEXED|OP_MODREG;
3088 op.reg = REG_ESP;
3089 op.aregs = (1<<REG_ESP);
3090 im.da.modifies |= op.aregs;
3091 im.usesaddrsize = 1; // Address size prefix is meaningful
3092 if (im.prefixlist&PF_ASIZE) {
3093 op.features |= OP_ADDR16;
3094 addrsize = 2;
3095 } else {
3096 addrsize = 4; // Flat model!
3097 }
3098 op.seg = SEG_SS;
3099 if ((op.arg&B_ARGMASK) == B_PUSHA) {
3100 im.da.uses = 0xFF; // Uses all general registers
3101 op.opsize = datasize*8;
3102 } else if ((op.arg&B_ARGMASK) == B_PUSHRETF) {
3103 im.da.uses |= op.aregs;
3104 op.opsize = datasize*2;
3105 } else {
3106 im.da.uses |= op.aregs;
3107 // Warn if memory contents is 16-bit jump/call destination.
3108 if (datasize == 2 && (op.arg&B_MODMASK) == B_JMPCALL) im.da.warnings |= DAW_JMP16;
3109 op.opsize = datasize;
3110 }
3111 op.opconst = -cast(int)op.opsize; // ESP is predecremented
3112 op.granularity = datasize; // Default, may be overriden later
3113 op.scale[REG_ESP] = 1;
3114 // Decode source operand to text, if requested.
3115 if (im.damode&DA_TEXT) {
3116 if (im.config.disasmmode == DAMODE_ATT) { ardec[0] = '%'; n = 1; } else n = 0;
3117 if (addrsize == 2) {
3118 Tstrcopy(ardec.ptr+n, SHORTNAME-n, regname16[REG_ESP].ptr);
3119 } else {
3120 Tstrcopy(ardec.ptr+n, SHORTNAME-n, regname32[REG_ESP].ptr);
3121 }
3122 originallist = im.prefixlist;
3123 im.prefixlist &= ~PF_SEGMASK;
3124 Memaddrtotext(im, op.arg, datasize, op.seg, ardec.ptr, 0, op.text.ptr);
3125 im.prefixlist = originallist;
3126 }
3127 }
3128
3129 // Decodes segment register.
3130 private void Operandsegreg (t_imdata* im, int index, AsmOperand* op) {
3131 int n;
3132 op.features = OP_SEGREG;
3133 if (index >= NSEG) {
3134 op.features |= OP_INVALID; // Invalid segment register
3135 im.da.errors |= DAE_BADSEG;
3136 }
3137 op.opsize = op.granularity = 2;
3138 op.reg = index;
3139 op.seg = SEG_UNDEF; // Because this is not a memory address
3140 if (op.arg&(B_CHG|B_UPD)) im.da.warnings |= DAW_SEGMOD; // Modifies segment register
3141 // Decode name of segment register.
3142 if (im.damode&DA_TEXT) {
3143 n = 0;
3144 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '%';
3145 Tcopycase(op.text.ptr+n, TEXTLEN-n, segname[index].ptr, im.config.lowercase);
3146 }
3147 }
3148
3149 // Decodes FPU register operand.
3150 private void Operandfpureg (t_imdata* im, int index, AsmOperand* op) {
3151 op.features = OP_FPUREG;
3152 op.opsize = op.granularity = 10;
3153 op.reg = index;
3154 op.seg = SEG_UNDEF; // Because this is not a memory address
3155 // Decode name of FPU register.
3156 if (im.damode&DA_TEXT) {
3157 if (im.config.disasmmode == DAMODE_ATT) {
3158 if (im.config.simplifiedst && index == 0) {
3159 Tcopycase(op.text.ptr, TEXTLEN, "%ST", im.config.lowercase);
3160 } else {
3161 op.text[0] = '%';
3162 Tcopycase(op.text.ptr+1, TEXTLEN-1, fpushort[index].ptr, im.config.lowercase);
3163 }
3164 } else if (im.config.simplifiedst && index == 0) {
3165 Tcopycase(op.text.ptr, TEXTLEN, "ST", im.config.lowercase);
3166 } else if (im.config.disasmmode != DAMODE_HLA) {
3167 Tcopycase(op.text.ptr, TEXTLEN, fpulong[index].ptr, im.config.lowercase);
3168 } else {
3169 Tcopycase(op.text.ptr, TEXTLEN, fpushort[index].ptr, im.config.lowercase);
3170 }
3171 }
3172 }
3173
3174 // Decodes MMX register operands. ATTENTION, does not set correct granularity!
3175 private void Operandmmxreg (t_imdata* im, int index, AsmOperand* op) {
3176 int n;
3177 op.features = OP_MMXREG;
3178 op.opsize = 8;
3179 op.granularity = 4; // Default, correct it later!
3180 op.reg = index;
3181 op.seg = SEG_UNDEF;
3182 // Decode name of MMX/3DNow! register.
3183 if (im.damode&DA_TEXT) {
3184 n = 0;
3185 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '%';
3186 Tcopycase(op.text.ptr+n, TEXTLEN-n, mmxname[index].ptr, im.config.lowercase);
3187 }
3188 }
3189
3190 // Decodes 3DNow! register operands. ATTENTION, does not set correct
3191 // granularity!
3192 private void Operandnowreg (t_imdata* im, int index, AsmOperand* op) {
3193 int n;
3194 op.features = OP_3DNOWREG;
3195 op.opsize = 8;
3196 op.granularity = 4; // Default, correct it later!
3197 op.reg = index;
3198 op.seg = SEG_UNDEF;
3199 // Decode name of MMX/3DNow! register.
3200 if (im.damode&DA_TEXT) {
3201 n = 0;
3202 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '%';
3203 Tcopycase(op.text.ptr+n, TEXTLEN-n, mmxname[index].ptr, im.config.lowercase);
3204 }
3205 }
3206
3207 // Decodes SSE register operands. ATTENTION, does not set correct granularity!
3208 private void Operandssereg (t_imdata* im, int index, AsmOperand* op) {
3209 int n;
3210 op.features = OP_SSEREG;
3211 op.opsize = (op.arg&B_NOVEXSIZE ? 16 : im.ssesize);
3212 op.granularity = 4; // Default, correct it later!
3213 op.reg = index;
3214 op.seg = SEG_UNDEF;
3215 // Note that some rare SSE commands may use Reg without ModRM.
3216 if (im.modsize == 0) im.modsize = 1;
3217 // Decode name of SSE register.
3218 if (im.damode&DA_TEXT) {
3219 n = 0;
3220 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '%';
3221 if (op.opsize == 32) {
3222 Tcopycase(op.text.ptr+n, TEXTLEN-n, sse256[index].ptr, im.config.lowercase);
3223 } else {
3224 Tcopycase(op.text.ptr+n, TEXTLEN-n, sse128[index].ptr, im.config.lowercase);
3225 }
3226 }
3227 }
3228
3229 // Decodes flag register EFL.
3230 private void Operandefl (t_imdata* im, uint datasize, AsmOperand* op) {
3231 op.features = OP_OTHERREG;
3232 op.opsize = op.granularity = datasize;
3233 op.reg = REG_UNDEF;
3234 op.seg = SEG_UNDEF;
3235 // Decode name of register.
3236 if (im.damode&DA_TEXT) {
3237 if (im.config.disasmmode == DAMODE_ATT) {
3238 Tcopycase(op.text.ptr, TEXTLEN, "%EFL", im.config.lowercase);
3239 } else {
3240 Tcopycase(op.text.ptr, TEXTLEN, "EFL", im.config.lowercase);
3241 }
3242 }
3243 }
3244
3245 // Decodes 8/16/32-bit immediate jump/call offset relative to EIP of next
3246 // command.
3247 private void Operandoffset (t_imdata* im, uint offsetsize, uint datasize, const(ubyte)* cmd, uint cmdsize, uint offsaddr, AsmOperand* op) {
3248 int n;
3249 char[TEXTLEN] label;
3250 if (cmdsize < offsetsize) { im.da.errors |= DAE_CROSS; return; } // Command crosses end of memory block
3251 op.features = OP_CONST;
3252 op.opsize = op.granularity = datasize; // NOT offsetsize!
3253 im.immsize1 = offsetsize;
3254 op.reg = REG_UNDEF;
3255 op.seg = SEG_UNDEF;
3256 offsaddr += offsetsize;
3257 if (offsetsize == 1) {
3258 // Sign-extandable constant
3259 op.opconst = *cast(byte*)cmd+offsaddr;
3260 } else if (offsetsize == 2) {
3261 // 16-bit immediate offset, rare
3262 op.opconst = *cast(ushort*)cmd+offsaddr;
3263 } else {
3264 // 32-bit immediate offset
3265 op.opconst = *cast(uint*)cmd+offsaddr;
3266 }
3267 if (datasize == 2) { op.opconst &= 0x0000FFFF; im.da.warnings |= DAW_JMP16; } // Practically unused in Win32 code
3268 im.usesdatasize = 1;
3269 // Decode address of destination to text, if requested.
3270 if (im.damode&DA_TEXT) {
3271 if (offsetsize == 1 && im.config.disasmmode != DAMODE_HLA && im.config.disasmmode != DAMODE_ATT) {
3272 n = Tcopycase(op.text.ptr, TEXTLEN, "SHORT ", im.config.lowercase);
3273 } else {
3274 n = 0;
3275 }
3276 if (datasize == 4) {
3277 if (decodeAddr(im, label[], op.opconst)) {
3278 Tstrcopy(op.text.ptr+n, TEXTLEN-n, label.ptr);
3279 } else {
3280 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '$';
3281 Hexprint(4, op.text.ptr+n, op.opconst, im, op.arg);
3282 }
3283 } else {
3284 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '$';
3285 Hexprint(2, op.text.ptr+n, op.opconst, im, op.arg);
3286 }
3287 }
3288 }
3289
3290 // Decodes 16:16/16:32-bit immediate absolute far jump/call address.
3291 private void Operandimmfaraddr (t_imdata* im, uint datasize, const(ubyte)* cmd, uint cmdsize, AsmOperand* op) {
3292 int n;
3293 if (cmdsize < datasize+2) { im.da.errors |= DAE_CROSS; return; } // Command crosses end of memory block
3294 op.features = OP_CONST|OP_SELECTOR;
3295 op.opsize = datasize+2;
3296 op.granularity = datasize; // Attention, non-standard case!
3297 op.reg = REG_UNDEF;
3298 op.seg = SEG_UNDEF;
3299 im.immsize1 = datasize;
3300 im.immsize2 = 2;
3301 if (datasize == 2) {
3302 op.opconst = *cast(ushort*)cmd;
3303 im.da.warnings |= DAW_JMP16; // Practically unused in Win32 code
3304 } else {
3305 op.opconst = *cast(uint*)cmd;
3306 im.da.immfixup = im.mainsize;
3307 }
3308 op.selector = *cast(ushort*)(cmd+datasize);
3309 im.usesdatasize = 1;
3310 // Decode address of destination to text, if requested.
3311 if (im.damode&DA_TEXT) {
3312 if (im.config.disasmmode == DAMODE_ATT) {
3313 op.text[0] = '$';
3314 n = 1;
3315 } else {
3316 n = Tcopycase(op.text.ptr, TEXTLEN, "FAR ", im.config.lowercase);
3317 }
3318 n += Hexprint(2, op.text.ptr+n, op.selector, im, op.arg);
3319 op.text[n++] = ':';
3320 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '$';
3321 Hexprint(4, op.text.ptr+n, op.opconst, im, op.arg);
3322 }
3323 }
3324
3325 // Decodes immediate constant 1 used in shift operations.
3326 private void Operandone (t_imdata *im, AsmOperand *op) {
3327 op.features = OP_CONST;
3328 op.opsize = op.granularity = 1; // Just to make it defined
3329 op.reg = REG_UNDEF;
3330 op.seg = SEG_UNDEF;
3331 op.opconst = 1;
3332 if (im.damode&DA_TEXT) {
3333 if (im.config.disasmmode == DAMODE_ATT) {
3334 Tstrcopy(op.text.ptr, TEXTLEN, "$1");
3335 } else {
3336 Tstrcopy(op.text.ptr, TEXTLEN, "1");
3337 }
3338 }
3339 }
3340
3341 // Decodes 8/16/32-bit immediate constant (possibly placed after ModRegRM-SIB-
3342 // Disp combination). Constant is nbytes long in the command and extends to
3343 // constsize bytes. If constant is a count, it deals with data of size datasize.
3344 // ATTENTION, calling routine must set usesdatasize by itself!
3345 private void Operandimmconst (t_imdata* im, uint nbytes, uint constsize, uint datasize, const(ubyte)* cmd, uint cmdsize, int issecond, AsmOperand* op) {
3346 int n;
3347 uint u, mod;
3348 char[TEXTLEN] label;
3349 if (cmdsize < im.modsize+im.dispsize+nbytes+(issecond?im.immsize1:0)) { im.da.errors |= DAE_CROSS; return; } // Command crosses end of memory block
3350 op.features = OP_CONST;
3351 op.opsize = op.granularity = constsize;
3352 cmd += im.modsize+im.dispsize;
3353 if (issecond == 0) {
3354 im.immsize1 = nbytes; // First constant
3355 } else {
3356 im.immsize2 = nbytes; // Second constant (ENTER only)
3357 cmd += im.immsize1;
3358 }
3359 op.reg = REG_UNDEF;
3360 op.seg = SEG_UNDEF;
3361 if (nbytes == 4) {
3362 // 32-bit immediate constant
3363 op.opconst = *cast(uint*)cmd;
3364 im.da.immfixup = im.mainsize+im.modsize+im.dispsize+(issecond ? im.immsize1 : 0);
3365 } else if (nbytes == 1) {
3366 // 8-byte constant, maybe sign-extendable
3367 op.opconst = *cast(byte*)cmd;
3368 } else {
3369 // 16-bite immediate constant, rare
3370 op.opconst = *cast(ushort*)cmd;
3371 }
3372 if (constsize == 1) op.opconst &= 0x000000FF;
3373 else if (constsize == 2) op.opconst &= 0x0000FFFF;
3374 switch (op.arg&B_MODMASK) {
3375 case B_BITCNT: // Constant is a bit count
3376 if ((datasize == 4 && op.opconst > 31) || (datasize == 1 && op.opconst > 7) || (datasize == 2 && op.opconst > 15)) im.da.warnings |= DAW_SHIFT;
3377 break;
3378 case B_SHIFTCNT: // Constant is a shift count
3379 if (op.opconst == 0 || (datasize == 4 && op.opconst > 31) || (datasize == 1 && op.opconst > 7) || (datasize == 2 && op.opconst > 15)) im.da.warnings |= DAW_SHIFT;
3380 break;
3381 case B_STACKINC: // Stack increment must be DWORD-aligned
3382 if ((op.opconst&0x3) != 0) im.da.warnings |= DAW_STACK;
3383 im.da.stackinc = op.opconst;
3384 break;
3385 default: break;
3386 }
3387 if (im.damode&DA_TEXT) {
3388 mod = op.arg&B_MODMASK;
3389 n = 0;
3390 if (constsize == 1) {
3391 // 8-bit constant
3392 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '$';
3393 Hexprint(1, op.text.ptr+n, op.opconst, im, op.arg);
3394 } else if (constsize == 4) {
3395 // 32-bit constant
3396 if ((mod == B_NONSPEC || mod == B_JMPCALL || mod == B_JMPCALLFAR) && decodeAddr(im, label[], op.opconst)) {
3397 Tstrcopy(op.text.ptr+n, TEXTLEN-n, label.ptr);
3398 } else {
3399 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '$';
3400 if (mod != B_UNSIGNED && mod != B_BINARY && mod != B_PORT && cast(int)op.opconst < 0 && (mod == B_SIGNED || cast(int)op.opconst > NEGLIMIT)) {
3401 op.text[n++] = '-'; u = -cast(int)op.opconst;
3402 } else {
3403 u = op.opconst;
3404 }
3405 Hexprint(4, op.text.ptr+n, u, im, op.arg);
3406 }
3407 } else {
3408 // 16-bit constant
3409 if (im.config.disasmmode == DAMODE_ATT) {
3410 op.text[n++] = '$';
3411 } else if ((op.arg&B_SHOWSIZE) != 0) {
3412 n += Tcopycase(op.text.ptr+n, TEXTLEN-n, sizename[constsize].ptr, im.config.lowercase);
3413 n += Tstrcopy(op.text.ptr+n, TEXTLEN-n, " ");
3414 }
3415 Hexprint(2, op.text.ptr+n, op.opconst, im, op.arg);
3416 }
3417 }
3418 }
3419
3420 // Decodes contrtol register operands.
3421 private void Operandcreg (t_imdata* im, int index, AsmOperand* op) {
3422 int n;
3423 op.features = OP_CREG;
3424 op.opsize = op.granularity = 4;
3425 op.reg = index;
3426 op.seg = SEG_UNDEF;
3427 // Decode name of control register.
3428 if (im.damode&DA_TEXT) {
3429 n = 0;
3430 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '%';
3431 Tcopycase(op.text.ptr+n, TEXTLEN-n, crname[index].ptr, im.config.lowercase);
3432 }
3433 // Some control registers are physically absent.
3434 if (index != 0 && index != 2 && index != 3 && index != 4) im.da.errors |= DAE_BADCR;
3435 }
3436
3437 // Decodes debug register operands.
3438 private void Operanddreg (t_imdata* im, int index, AsmOperand* op) {
3439 int n;
3440 op.features = OP_DREG;
3441 op.opsize = op.granularity = 4;
3442 op.reg = index;
3443 op.seg = SEG_UNDEF;
3444 // Decode name of debug register.
3445 if (im.damode&DA_TEXT) {
3446 n = 0;
3447 if (im.config.disasmmode == DAMODE_ATT) op.text[n++] = '%';
3448 Tcopycase(op.text.ptr+n, TEXTLEN-n, drname[index].ptr, im.config.lowercase);
3449 }
3450 }
3451
3452 // Decodes FPU status register FST.
3453 private void Operandfst (t_imdata* im, AsmOperand* op) {
3454 op.features = OP_OTHERREG;
3455 op.opsize = op.granularity = 2;
3456 op.reg = REG_UNDEF;
3457 op.seg = SEG_UNDEF;
3458 // Decode name of register.
3459 if (im.damode&DA_TEXT) {
3460 if (im.config.disasmmode == DAMODE_ATT) {
3461 Tcopycase(op.text.ptr, TEXTLEN, "%FST", im.config.lowercase);
3462 } else {
3463 Tcopycase(op.text.ptr, TEXTLEN, "FST", im.config.lowercase);
3464 }
3465 }
3466 }
3467
3468 // Decodes FPU control register FCW.
3469 private void Operandfcw (t_imdata* im, AsmOperand* op) {
3470 op.features = OP_OTHERREG;
3471 op.opsize = op.granularity = 2;
3472 op.reg = REG_UNDEF;
3473 op.seg = SEG_UNDEF;
3474 // Decode name of register.
3475 if (im.damode&DA_TEXT) {
3476 if (im.config.disasmmode == DAMODE_ATT) {
3477 Tcopycase(op.text.ptr, TEXTLEN, "%FCW", im.config.lowercase);
3478 } else {
3479 Tcopycase(op.text.ptr, TEXTLEN, "FCW", im.config.lowercase);
3480 }
3481 }
3482 }
3483
3484 // Decodes SSE control register MXCSR.
3485 private void Operandmxcsr (t_imdata* im, AsmOperand* op) {
3486 op.features = OP_OTHERREG;
3487 op.opsize = op.granularity = 4;
3488 op.reg = REG_UNDEF;
3489 op.seg = SEG_UNDEF;
3490 // Decode name of register.
3491 if (im.damode&DA_TEXT) {
3492 if (im.config.disasmmode == DAMODE_ATT) {
3493 Tcopycase(op.text.ptr, TEXTLEN, "%MXCSR", im.config.lowercase);
3494 } else {
3495 Tcopycase(op.text.ptr, TEXTLEN, "MXCSR", im.config.lowercase);
3496 }
3497 }
3498 }
3499
3500
3501 // ////////////////////////////////////////////////////////////////////////// //
3502 // public API
3503
3504 // Disassembles first command in the binary code of given length at given
3505 // address. Assumes that address and data size attributes of all participating
3506 // segments are 32 bit (flat model). Returns length of the command or 0 in case
3507 // of severe error.
3508 public uint disasm (const(void)[] codearr, uint ip, DisasmData* da, int damode, const(DAConfig)* config, scope const(char)[] delegate (uint addr) decodeaddress=null) {
3509 import core.stdc.string : memset;
3510 int i, j, k, q, noperand, nout, enclose, vexreg, success, cfill, ofill;
3511 uint m, n, u, prefix, prefixmask, code, arg, cmdtype, datasize;
3512 uint type, vex, vexlead;
3513 t_imdata im;
3514 const(t_chain)* pchain;
3515 immutable(AsmInstrDsc)* pcmd;
3516 const(t_modrm)* pmrm;
3517 AsmOperand *op;
3518 AsmOperand pseudoop;
3519 static DAConfig defconfig; // default one
3520 const(ubyte)* cmd = cast(const(ubyte)*)codearr.ptr;
3521 static if (codearr.length.sizeof > 4) {
3522 uint cmdsize = (codearr.length > uint.max ? uint.max : cast(uint)codearr.length);
3523 } else {
3524 uint cmdsize = codearr.length;
3525 }
3526 // Verify input parameters.
3527 if (cmdsize == 0 || da is null || cmdchain is null) return 0; // Error in parameters or uninitialized
3528 // Initialize DisasmData structure that receives results of disassembly. This
3529 // structure is very large, memset() or several memset()'s would take much,
3530 // much longer.
3531 da.ip = ip;
3532 da.memfixup = da.immfixup = -1;
3533 da.errors = DAE_NOERR;
3534 da.warnings = DAW_NOWARN;
3535 da.uses = 0;
3536 da.modifies = 0;
3537 da.memconst = 0;
3538 da.stackinc = 0;
3539 for (i = 0, op = da.op.ptr; i < NOPERAND; ++i, ++op) {
3540 op.features = 0;
3541 op.arg = 0;
3542 op.opsize = op.granularity = 0;
3543 op.reg = REG_UNDEF;
3544 op.uses = 0;
3545 op.modifies = 0;
3546 op.seg = SEG_UNDEF;
3547 (cast(uint*)op.scale)[0] = 0;
3548 (cast(uint*)op.scale)[1] = 0;
3549 op.aregs = 0;
3550 op.opconst = 0;
3551 op.selector = 0;
3552 op.text[] = 0;
3553 }
3554 da.dump[] = 0;
3555 da.result[] = 0;
3556 da.masksize = 0;
3557 // Prepare intermediate data. This data allows to keep Disasm() reentrant
3558 // (thread-safe).
3559 im.da = da;
3560 im.damode = damode;
3561 if (config is null) {
3562 im.config = config = &defconfig; // Use default configuration
3563 } else {
3564 im.config = config;
3565 }
3566 im.decodeaddress = decodeaddress;
3567 im.prefixlist = 0;
3568 im.ssesize = 16; // Default
3569 im.immsize1 = im.immsize2 = 0;
3570 // Correct 80x86 command may contain up to 4 prefixes belonging to different
3571 // prefix groups. If Disasm() detects second prefix from the same group, it
3572 // flushes first prefix in the sequence as a pseudocommand. (This is not
3573 // quite true; all CPUs that I have tested accept repeating prefixes. Still,
3574 // who will place superfluous and possibly nonportable prefixes into the
3575 // code?)
3576 for (n = 0; ; ++n) {
3577 if (n >= cmdsize) {
3578 // Command crosses end of memory block
3579 n = 0;
3580 im.prefixlist = 0; // Decode as standalone prefix
3581 break;
3582 }
3583 // Note that some CPUs treat REPx and LOCK as belonging to the same group.
3584 switch (cmd[n]) {
3585 case 0x26: prefix = PF_ES; prefixmask = PF_SEGMASK; break;
3586 case 0x2E: prefix = PF_CS; prefixmask = PF_SEGMASK; break;
3587 case 0x36: prefix = PF_SS; prefixmask = PF_SEGMASK; break;
3588 case 0x3E: prefix = PF_DS; prefixmask = PF_SEGMASK; break;
3589 case 0x64: prefix = PF_FS; prefixmask = PF_SEGMASK; break;
3590 case 0x65: prefix = PF_GS; prefixmask = PF_SEGMASK; break;
3591 case 0x66: prefix = prefixmask = PF_DSIZE; break;
3592 case 0x67: prefix = prefixmask = PF_ASIZE; break;
3593 case 0xF0: prefix = prefixmask = PF_LOCK; break;
3594 case 0xF2: prefix = PF_REPNE; prefixmask = PF_REPMASK; break;
3595 case 0xF3: prefix = PF_REP; prefixmask = PF_REPMASK; break;
3596 default: prefix = 0; break;
3597 }
3598 if (prefix == 0) break;
3599 if (im.prefixlist&prefixmask) { da.errors |= DAE_SAMEPREF; break; } // Two prefixes from the same group
3600 im.prefixlist |= prefix;
3601 }
3602 // There may be VEX prefix preceding command body. Yes, VEX is supported in
3603 // the 32-bit mode! And even in the 16-bit, but who cares?
3604 vex = 0;
3605 vexlead = 0;
3606 if (cmdsize >= n+3 && (*cast(ushort*)(cmd+n)&0xC0FE) == 0xC0C4) {
3607 // VEX is not compatible with LOCK, 66, F2 and F3 prefixes. VEX is not
3608 // compatible with REX, too, but REX prefixes are missing in 32-bit mode.
3609 if (im.prefixlist&(PF_LOCK|PF_66|PF_F2|PF_F3)) {
3610 da.errors |= DAE_SAMEPREF; // Incompatible prefixes
3611 } else {
3612 if (cmd[n] == 0xC5) {
3613 // 2-byte VEX prefix.
3614 im.prefixlist |= PF_VEX2;
3615 vex = cmd[n+1];
3616 vexlead = DX_VEX|DX_LEAD0F;
3617 n += 2;
3618 } else {
3619 // 3-byte VEX prefix.
3620 im.prefixlist |= PF_VEX3;
3621 vex = cmd[n+2]+(cmd[n+1]<<8); // Note the order of the bytes!
3622 switch (vex&0x1F00) {
3623 case 0x0100: vexlead = DX_VEX|DX_LEAD0F; n += 3; break;
3624 case 0x0200: vexlead = DX_VEX|DX_LEAD38; n += 3; break;
3625 case 0x0300: vexlead = DX_VEX|DX_LEAD3A; n += 3; break;
3626 default: vex = 0; break; // Unsupported VEX, decode as LES
3627 }
3628 }
3629 if (vex != 0) {
3630 // Get size of operands.
3631 if (vex&0x0004) im.ssesize = 32; // 256-bit SSE operands
3632 // Get register encoded in VEX prefix.
3633 vexreg = (~vex>>3)&0x07;
3634 // Check for SIMD prefix.
3635 switch (vex&0x03) {
3636 case 0x0001: im.prefixlist |= PF_66; break;
3637 case 0x0002: im.prefixlist |= PF_F3; break;
3638 case 0x0003: im.prefixlist |= PF_F2; break;
3639 default:
3640 }
3641 }
3642 }
3643 if (n >= cmdsize) { n = 0; vex = 0; im.prefixlist = 0; /*Decode as LES*/ } // Command crosses end of memory block
3644 }
3645 // We have gathered all prefixes, including those that are integral part of
3646 // the SSE command.
3647 if (n > 4 || (da.errors&DAE_SAMEPREF) != 0) {
3648 if (n > 4) da.errors |= DAE_MANYPREF;
3649 n = 0; im.prefixlist = 0; // Decode as standalone prefix
3650 }
3651 da.prefixes = im.prefixlist;
3652 da.nprefix = n;
3653 // Fetch first 4 bytes of the command and find start of command chain in the
3654 // command table.
3655 if (cmdsize >= n+uint.sizeof) {
3656 code = *cast(uint*)(cmd+n); // Optimization for most frequent case
3657 } else {
3658 code = cmd[n];
3659 if (cmdsize > n+1) (cast(ubyte*)&code)[1] = cmd[n+1];
3660 if (cmdsize > n+2) (cast(ubyte*)&code)[2] = cmd[n+2];
3661 if (cmdsize > n+3) (cast(ubyte*)&code)[3] = cmd[n+3];
3662 }
3663 // Walk chain and search for matching command. Command is matched if:
3664 // (1) code bits allowed in mask coincide in command and descriptor;
3665 // (2) when command type contains D_MEMORY, ModRegRM byte must indicate
3666 // memory, and when type contains D_REGISTER, Mod must indicate register;
3667 // (3) when bits D_DATAxx or D_ADDRxx are set, size of data and/or code must
3668 // match these bits;
3669 // (4) field D_MUSTMASK must match gathered prefixes;
3670 // (5) presence or absence of VEX prefix must be matched by DX_VEX. If VEX
3671 // is present, implied leading bytes must match vexlead and bit L must
3672 // match DX_VLMASK;
3673 // (6) if short form of string commands is requested, bit D_LONGFORM must be
3674 // cleared, or segment override prefix other that DS:, or address size
3675 // prefix must be present;
3676 // (7) when bit D_POSTBYTE is set, byte after ModRegRM/SIB/offset must match
3677 // postbyte. Note that all postbyted commands include memory address in
3678 // ModRegRM form and do not include immediate constants;
3679 // (8) if alternative forms of conditional commands are requested, command
3680 // is conditional, and it is marked as DX_ZEROMASK or DX_CARRYMASK,
3681 // check whether these bits match damode. (Conditional branch on flag
3682 // Z!=0 can be disassembled either as JZ or JE. First form is preferrable
3683 // after SUB or DEC; second form is more natural after CMP);
3684 // (9) if command has mnemonics RETN but alternative form RET is expected,
3685 // skip it - RET will follow.
3686 success = 0;
3687 for (pchain = cmdchain+(code&CMDMASK); ; pchain = pchain.pnext) {
3688 if (pchain is null || pchain.pcmd is null) break; // End of chain, no match
3689 pcmd = pchain.pcmd;
3690 if (((code^pcmd.code)&pcmd.mask) != 0) continue; // (1) Different code bits
3691 cmdtype = pcmd.cmdtype;
3692 if ((damode&DA_TEXT) != 0) {
3693 if ((pcmd.exttype&DX_RETN) != 0 && config.useretform != 0) continue; // (9) RET form of near return expected
3694 if ((cmdtype&D_COND) != 0 && (pcmd.exttype&(DX_ZEROMASK|DX_CARRYMASK)) != 0) {
3695 if ((damode&DA_JZ) != 0 && (pcmd.exttype&DX_ZEROMASK) == DX_JE) continue; // (8) Wait for DX_JZ
3696 if ((damode&DA_JC) != 0 && (pcmd.exttype&DX_CARRYMASK) == DX_JB) continue; // (8) Wait for DX_JC
3697 }
3698 }
3699 if ((pcmd.exttype&(DX_VEX|DX_LEADMASK)) != vexlead) continue; // (5) Unmatched VEX prefix
3700 if (pcmd.exttype&DX_VEX) {
3701 if (((pcmd.exttype&DX_VLMASK) == DX_LSHORT && (vex&0x04) != 0) || ((pcmd.exttype&DX_VLMASK) == DX_LLONG && (vex&0x04) == 0)) continue; // (5) Unmatched VEX.L
3702 }
3703 if ((cmdtype&(D_MEMORY|D_REGISTER|D_LONGFORM|D_SIZEMASK|D_MUSTMASK|D_POSTBYTE)) == 0) { success = 1; break; } // Optimization for most frequent case
3704 switch (cmdtype&D_MUSTMASK) {
3705 case D_MUST66: // (4) (SSE) Requires 66, no F2 or F3
3706 if ((im.prefixlist&(PF_66|PF_F2|PF_F3)) != PF_66) continue;
3707 break;
3708 case D_MUSTF2: // (4) (SSE) Requires F2, no 66 or F3
3709 if ((im.prefixlist&(PF_66|PF_F2|PF_F3)) != PF_F2) continue;
3710 break;
3711 case D_MUSTF3: // (4) (SSE) Requires F3, no 66 or F2
3712 if ((im.prefixlist&(PF_66|PF_F2|PF_F3)) != PF_F3) continue;
3713 break;
3714 case D_MUSTNONE: // (4) (MMX, SSE) Requires no 66, F2, F3
3715 if ((im.prefixlist&(PF_66|PF_F2|PF_F3)) != 0) continue;
3716 break;
3717 case D_NEEDF2: // (4) (SSE) Requires F2, no F3
3718 if ((im.prefixlist&(PF_F2|PF_F3)) != PF_F2) continue;
3719 break;
3720 case D_NEEDF3: // (4) (SSE) Requires F3, no F2
3721 if ((im.prefixlist&(PF_F2|PF_F3)) != PF_F3) continue;
3722 break;
3723 case D_NOREP: // (4) Must not include F2 or F3
3724 if ((im.prefixlist&(PF_REP|PF_REPNE)) != 0) continue;
3725 break;
3726 case D_MUSTREP: // (4) Must include F3 (REP)
3727 case D_MUSTREPE: // (4) Must include F3 (REPE)
3728 if ((im.prefixlist&PF_REP) == 0) continue;
3729 break;
3730 case D_MUSTREPNE: // (4) Must include F2 (REPNE)
3731 if ((im.prefixlist&PF_REPNE) == 0) continue;
3732 break;
3733 default: break;
3734 }
3735 if ((cmdtype&D_DATA16) != 0 && (im.prefixlist&PF_DSIZE) == 0) continue; // (3) 16-bit data expected
3736 if ((cmdtype&D_DATA32) != 0 && (im.prefixlist&PF_DSIZE) != 0) continue; // (3) 32-bit data expected
3737 if ((cmdtype&D_ADDR16) != 0 && (im.prefixlist&PF_ASIZE) == 0) continue; // (3) 16-bit address expected
3738 if ((cmdtype&D_ADDR32) != 0 && (im.prefixlist&PF_ASIZE) != 0) continue; // (3) 32-bit address expected
3739 if ((cmdtype&D_LONGFORM) != 0 && config.shortstringcmds != 0 && (im.prefixlist&(PF_ES|PF_CS|PF_SS|PF_FS|PF_GS|PF_ASIZE)) == 0) continue; // (6) Short form of string cmd expected
3740 if (cmdtype&D_MEMORY) {
3741 // (2) Command expects operand in memory (Mod in ModRegRM is not 11b).
3742 if (n+pcmd.length >= cmdsize) break; // Command longer than available code
3743 if ((cmd[n+pcmd.length]&0xC0) == 0xC0) continue;
3744 } else if (cmdtype&D_REGISTER) {
3745 // (2) Command expects operand in register (Mod in ModRegRM is 11b).
3746 if (n+pcmd.length >= cmdsize) break; // Command longer than available code
3747 if ((cmd[n+pcmd.length]&0xC0) != 0xC0) continue;
3748 }
3749 if (cmdtype&D_POSTBYTE) {
3750 // Command expects postbyte after ModRegRM/SIB/offset as part of the
3751 // code. If command is longer than available code, immediately report
3752 // match - error will be reported elsewhere.
3753 m = n+pcmd.length; // Offset to ModRegRM byte
3754 if (m >= cmdsize) break; // Command longer than available code
3755 if (im.prefixlist&PF_ASIZE) {
3756 m += modrm16[cmd[m]].size; // 16-bit address
3757 } else {
3758 pmrm = modrm32.ptr+cmd[m];
3759 if (pmrm.psib is null) {
3760 m += pmrm.size; // 32-bit address without SIB
3761 } else if (m+1 >= cmdsize) {
3762 break; // Command longer than available code
3763 } else {
3764 m += pmrm.psib[cmd[m+1]].size; // 32-bit address with SIB
3765 }
3766 }
3767 if (m >= cmdsize) break; // Command longer than available code
3768 // Asterisk in SSE and AVX commands means comparison predicate. Check for predefined range.
3769 if (cmd[m] == cast(ubyte)pcmd.postbyte || ((cmdtype&D_WILDCARD) != 0 && cmd[m] < (pcmd.exttype & DX_VEX ? 32 : 8))) {
3770 im.immsize1 = 1; // (7) Interprete postbyte as imm const
3771 } else {
3772 continue; // (7)
3773 }
3774 }
3775 success = 1;
3776 break; // Perfect match, command found
3777 }
3778 // If command is bad but preceded with prefixes, decode first prefix as
3779 // standalone. In this case, list of command's prefixes is empty.
3780 if (success == 0) {
3781 pcmd = null;
3782 if (im.prefixlist != 0) {
3783 n = 0;
3784 da.nprefix = 0;
3785 da.prefixes = im.prefixlist = 0;
3786 code = cmd[n]&CMDMASK;
3787 for (pchain = cmdchain+code; ; pchain = pchain.pnext) {
3788 if (pchain is null || pchain.pcmd is null) { pcmd = null; break; } // End of chain, no match
3789 pcmd = pchain.pcmd;
3790 if ((pcmd.cmdtype&D_CMDTYPE) != D_PREFIX) continue;
3791 if (((code^pcmd.code)&pcmd.mask) == 0) {
3792 cmdtype = pcmd.cmdtype;
3793 da.errors |= DAE_BADCMD;
3794 break;
3795 }
3796 }
3797 }
3798 // If matching command is still not found, report error and return one byte
3799 // as a command length.
3800 if (pcmd is null) {
3801 if (damode&DA_DUMP) Thexdump(da.dump.ptr, cmd, 1, config.lowercase);
3802 if (damode&DA_TEXT) {
3803 if (config.disasmmode == DAMODE_HLA) j = Tcopycase(da.result.ptr, TEXTLEN, sizename[1].ptr, config.lowercase);
3804 else if (config.disasmmode == DAMODE_ATT) j = Tcopycase(da.result.ptr, TEXTLEN, sizeatt[1].ptr, config.lowercase);
3805 else j = Tcopycase(da.result.ptr, TEXTLEN, sizekey[1].ptr, config.lowercase);
3806 j += Tstrcopy(da.result.ptr+j, TEXTLEN-j, " ");
3807 Thexdump(da.result.ptr+j, cmd, 1, config.lowercase);
3808 }
3809 da.size = 1;
3810 da.nprefix = 0;
3811 da.prefixes = 0;
3812 da.cmdtype = D_BAD;
3813 da.exttype = 0;
3814 da.errors |= DAE_BADCMD; // Unrecognized command
3815 if (damode&DA_HILITE) {
3816 import core.stdc.string : strlen;
3817 da.masksize = strlen(da.result.ptr);
3818 memset(da.mask.ptr, DRAW_SUSPECT, da.masksize);
3819 }
3820 return 1;
3821 }
3822 }
3823 // Exclude prefixes that are integral part of the command from the list of
3824 // prefixes. First comparison optimizes for the most frequent case of no
3825 // obligatory prefixes.
3826 if (cmdtype&(D_SIZEMASK|D_MUSTMASK)) {
3827 switch (cmdtype&D_MUSTMASK) {
3828 case D_MUST66: // (SSE) Requires 66, no F2 or F3
3829 case D_MUSTF2: // (SSE) Requires F2, no 66 or F3
3830 case D_MUSTF3: // (SSE) Requires F3, no 66 or F2
3831 im.prefixlist &= ~(PF_66|PF_F2|PF_F3);
3832 break;
3833 case D_NEEDF2: // (SSE) Requires F2, no F3
3834 case D_NEEDF3: // (SSE) Requires F3, no F2
3835 im.prefixlist &= ~(PF_F2|PF_F3);
3836 break;
3837 default: break;
3838 }
3839 if (cmdtype&D_DATA16) im.prefixlist &= ~PF_DSIZE; // Must include data size prefix
3840 if (cmdtype&D_ADDR16) im.prefixlist &= ~PF_ASIZE; // Must include address size prefix
3841 }
3842 // Prepare for disassembling.
3843 im.modsize = 0; // Size of ModRegRM/SIB bytes
3844 im.dispsize = 0; // Size of address offset
3845 im.usesdatasize = 0;
3846 im.usesaddrsize = 0;
3847 im.usessegment = 0;
3848 da.cmdtype = cmdtype;
3849 da.exttype = pcmd.exttype;
3850 n += pcmd.length; // Offset of ModRegRM or imm constant
3851 if (n > cmdsize) { da.errors |= DAE_CROSS; goto error; } // Command crosses end of memory block
3852 im.mainsize = n; // Size of command with prefixes
3853 // Set default data size (note that many commands and operands override it).
3854 if ((cmdtype&D_SIZE01) != 0 && (cmd[n-1]&0x01) == 0) {
3855 if (im.prefixlist&PF_DSIZE) da.warnings |= DAW_DATASIZE; // Superfluous data size prefix
3856 datasize = 1;
3857 } else if (im.prefixlist&PF_DSIZE) {
3858 datasize = 2;
3859 } else {
3860 datasize = 4;
3861 }
3862 // Process operands.
3863 noperand = 0;
3864 for (i = 0; i < NOPERAND; i++) {
3865 arg = pcmd.arg[i];
3866 if ((arg&B_ARGMASK) == B_NONE) break; // Optimization for most frequent case
3867 // If pseudooperands to be skipped, I process them nevertheless. Such
3868 // operands may contain important information.
3869 if ((arg&B_PSEUDO) != 0 && (damode&DA_PSEUDO) == 0) {
3870 op = &pseudoop; // Request to skip pseudooperands
3871 } else {
3872 op = da.op.ptr+noperand++;
3873 }
3874 op.arg = arg;
3875 switch (arg&B_ARGMASK) {
3876 case B_AL: // Register AL
3877 Operandintreg(&im, 1, REG_AL, op);
3878 break;
3879 case B_AH: // Register AH
3880 Operandintreg(&im, 1, REG_AH, op);
3881 break;
3882 case B_AX: // Register AX
3883 Operandintreg(&im, 2, REG_EAX, op);
3884 break;
3885 case B_CL: // Register CL
3886 Operandintreg(&im, 1, REG_CL, op);
3887 break;
3888 case B_CX: // Register CX
3889 Operandintreg(&im, 2, REG_ECX, op);
3890 break;
3891 case B_DX: // Register DX
3892 Operandintreg(&im, 2, REG_EDX, op);
3893 break;
3894 case B_DXPORT: // Register DX as I/O port address
3895 Operandintreg(&im, 2, REG_EDX, op);
3896 op.features |= OP_PORT;
3897 break;
3898 case B_EAX: // Register EAX
3899 Operandintreg(&im, 4, REG_EAX, op);
3900 break;
3901 case B_EBX: // Register EBX
3902 Operandintreg(&im, 4, REG_EBX, op);
3903 break;
3904 case B_ECX: // Register ECX
3905 Operandintreg(&im, 4, REG_ECX, op);
3906 break;
3907 case B_EDX: // Register EDX
3908 Operandintreg(&im, 4, REG_EDX, op);
3909 break;
3910 case B_ACC: // Accumulator (AL/AX/EAX)
3911 Operandintreg(&im, datasize, REG_EAX, op);
3912 im.usesdatasize = 1;
3913 break;
3914 case B_STRCNT: // Register CX or ECX as REPxx counter
3915 Operandintreg(&im, (im.prefixlist&PF_ASIZE?2:4), REG_ECX, op);
3916 im.usesaddrsize = 1;
3917 break;
3918 case B_DXEDX: // Register DX or EDX in DIV/MUL
3919 Operandintreg(&im, datasize, REG_EDX, op);
3920 im.usesdatasize = 1;
3921 break;
3922 case B_BPEBP: // Register BP or EBP in ENTER/LEAVE
3923 Operandintreg(&im, datasize, REG_EBP, op);
3924 im.usesdatasize = 1;
3925 break;
3926 case B_REG: // 8/16/32-bit register in Reg
3927 // Note that all commands that use B_REG have also another operand
3928 // that requires ModRM, so we don't need to set modsize here.
3929 if (n >= cmdsize) {
3930 da.errors |= DAE_CROSS; // Command crosses end of memory block
3931 } else {
3932 Operandintreg(&im, datasize, (cmd[n]>>3)&0x07, op);
3933 im.usesdatasize = 1;
3934 }
3935 break;
3936 case B_REG16: // 16-bit register in Reg
3937 if (n >= cmdsize) {
3938 da.errors |= DAE_CROSS; // Command crosses end of memory block
3939 } else {
3940 Operandintreg(&im, 2, (cmd[n]>>3)&0x07, op);
3941 }
3942 break;
3943 case B_REG32: // 32-bit register in Reg
3944 if (n >= cmdsize) {
3945 da.errors |= DAE_CROSS; // Command crosses end of memory block
3946 } else {
3947 Operandintreg(&im, 4, (cmd[n]>>3)&0x07, op);
3948 }
3949 break;
3950 case B_REGCMD: // 16/32-bit register in last cmd byte
3951 Operandintreg(&im, datasize, cmd[n-1]&0x07, op);
3952 im.usesdatasize = 1;
3953 break;
3954 case B_REGCMD8: // 8-bit register in last cmd byte
3955 Operandintreg(&im, 1, cmd[n-1]&0x07, op);
3956 break;
3957 case B_ANYREG: // Reg field is unused, any allowed
3958 break;
3959 case B_INT: // 8/16/32-bit register/memory in ModRM
3960 case B_INT1632: // 16/32-bit register/memory in ModRM
3961 k = Operandmodrm(&im, datasize, cmd+n, cmdsize-n, op);
3962 if (k < 0) break; // Error in address
3963 if (k == 0) Operandintreg(&im, datasize, cmd[n]&0x07, op);
3964 im.usesdatasize = 1;
3965 break;
3966 case B_INT8: // 8-bit register/memory in ModRM
3967 k = Operandmodrm(&im, 1, cmd+n, cmdsize-n, op);
3968 if (k < 0) break; // Error in address
3969 if (k == 0) Operandintreg(&im, 1, cmd[n]&0x07, op);
3970 break;
3971 case B_INT16: // 16-bit register/memory in ModRM
3972 k = Operandmodrm(&im, 2, cmd+n, cmdsize-n, op);
3973 if (k < 0) break; // Error in address
3974 if (k == 0) Operandintreg(&im, 2, cmd[n]&0x07, op);
3975 break;
3976 case B_INT32: // 32-bit register/memory in ModRM
3977 k = Operandmodrm(&im, 4, cmd+n, cmdsize-n, op);
3978 if (k < 0) break; // Error in address
3979 if (k == 0) Operandintreg(&im, 4, cmd[n]&0x07, op);
3980 break;
3981 case B_INT64: // 64-bit integer in ModRM, memory only
3982 k = Operandmodrm(&im, 8, cmd+n, cmdsize-n, op);
3983 if (k < 0) break; // Error in address
3984 if (k == 0) {
3985 // Register is not allowed, decode as 32-bit register and set error.
3986 Operandintreg(&im, 4, cmd[n]&0x07, op);
3987 op.features |= OP_INVALID;
3988 da.errors |= DAE_MEMORY;
3989 //break;
3990 }
3991 break;
3992 case B_INT128: // 128-bit integer in ModRM, memory only
3993 k = Operandmodrm(&im, 16, cmd+n, cmdsize-n, op);
3994 if (k < 0) break; // Error in address
3995 if (k == 0) {
3996 // Register is not allowed, decode as 32-bit register and set error.
3997 Operandintreg(&im, 4, cmd[n]&0x07, op);
3998 op.features |= OP_INVALID;
3999 da.errors |= DAE_MEMORY;
4000 //break;
4001 }
4002 break;
4003 case B_IMMINT: // 8/16/32-bit int at immediate addr
4004 Operandimmaddr(&im, datasize, cmd+n, cmdsize-n, op);
4005 im.usesdatasize = 1;
4006 break;
4007 case B_INTPAIR: // Two signed 16/32 in ModRM, memory only
4008 k = Operandmodrm(&im, 2*datasize, cmd+n, cmdsize-n, op);
4009 if (k < 0) break; // Error in address
4010 op.granularity = datasize;
4011 if (k == 0) {
4012 // Register is not allowed, decode as register and set error.
4013 Operandintreg(&im, datasize, cmd[n]&0x07, op);
4014 op.features |= OP_INVALID;
4015 da.errors |= DAE_MEMORY;
4016 //break;
4017 }
4018 im.usesdatasize = 1;
4019 break;
4020 case B_SEGOFFS: // 16:16/16:32 absolute address in memory
4021 k = Operandmodrm(&im, datasize+2, cmd+n, cmdsize-n, op);
4022 if (k < 0) break; // Error in address
4023 if (k == 0) {
4024 // Register is not allowed, decode and set error.
4025 Operandintreg(&im, datasize, cmd[n]&0x07, op);
4026 op.features |= OP_INVALID;
4027 da.errors |= DAE_MEMORY;
4028 //break;
4029 }
4030 im.usesdatasize = 1;
4031 break;
4032 case B_STRDEST: // 8/16/32-bit string dest, [ES:(E)DI]
4033 Operandindirect(&im, REG_EDI, 1, SEG_ES, 0, datasize, op);
4034 im.usesdatasize = 1;
4035 break;
4036 case B_STRDEST8: // 8-bit string destination, [ES:(E)DI]
4037 Operandindirect(&im, REG_EDI, 1, SEG_ES, 0, 1, op);
4038 break;
4039 case B_STRSRC: // 8/16/32-bit string source, [(E)SI]
4040 Operandindirect(&im, REG_ESI, 1, SEG_UNDEF, 0, datasize, op);
4041 im.usesdatasize = 1;
4042 break;
4043 case B_STRSRC8: // 8-bit string source, [(E)SI]
4044 Operandindirect(&im, REG_ESI, 1, SEG_UNDEF, 0, 1, op);
4045 break;
4046 case B_XLATMEM: // 8-bit memory in XLAT, [(E)BX+AL]
4047 Operandxlat(&im, op);
4048 break;
4049 case B_EAXMEM: // Reference to memory addressed by [EAX]
4050 Operandindirect(&im, REG_EAX, 0, SEG_UNDEF, 4, 1, op);
4051 break;
4052 case B_LONGDATA: // Long data in ModRM, mem only
4053 k = Operandmodrm(&im, 256, cmd+n, cmdsize-n, op);
4054 if (k < 0) break; // Error in address
4055 op.granularity = 1; // Just a trick
4056 if (k == 0) {
4057 // Register is not allowed, decode and set error.
4058 Operandintreg(&im, 4, cmd[n]&0x07, op);
4059 op.features |= OP_INVALID;
4060 da.errors |= DAE_MEMORY;
4061 //break;
4062 }
4063 im.usesdatasize = 1; // Caveat user
4064 break;
4065 case B_ANYMEM: // Reference to memory, data unimportant
4066 k = Operandmodrm(&im, 1, cmd+n, cmdsize-n, op);
4067 if (k < 0) break; // Error in address
4068 if (k == 0) {
4069 // Register is not allowed, decode and set error.
4070 Operandintreg(&im, 4, cmd[n]&0x07, op);
4071 op.features |= OP_INVALID;
4072 da.errors |= DAE_MEMORY;
4073 }
4074 break;
4075 case B_STKTOP: // 16/32-bit int top of stack
4076 Operandindirect(&im, REG_ESP, 1, SEG_SS, 0, datasize, op);
4077 im.usesdatasize = 1;
4078 break;
4079 case B_STKTOPFAR: // Top of stack (16:16/16:32 far addr)
4080 Operandindirect(&im, REG_ESP, 1, SEG_SS, 0, datasize*2, op);
4081 op.granularity = datasize;
4082 im.usesdatasize = 1;
4083 break;
4084 case B_STKTOPEFL: // 16/32-bit flags on top of stack
4085 Operandindirect(&im, REG_ESP, 1, SEG_SS, 0, datasize, op);
4086 im.usesdatasize = 1;
4087 break;
4088 case B_STKTOPA: // 16/32-bit top of stack all registers
4089 Operandindirect(&im, REG_ESP, 1, SEG_SS, 0, datasize*8, op);
4090 op.granularity = datasize;
4091 op.modifies = da.modifies = 0xFF;
4092 im.usesdatasize = 1;
4093 break;
4094 case B_PUSH: // 16/32-bit int push to stack
4095 case B_PUSHRET: // 16/32-bit push of return address
4096 case B_PUSHRETF: // 16:16/16:32-bit push of far retaddr
4097 case B_PUSHA: // 16/32-bit push all registers
4098 Operandpush(&im, datasize, op);
4099 im.usesdatasize = 1;
4100 break;
4101 case B_EBPMEM: // 16/32-bit int at [EBP]
4102 Operandindirect(&im, REG_EBP, 1, SEG_SS, 0, datasize, op);
4103 im.usesdatasize = 1;
4104 break;
4105 case B_SEG: // Segment register in Reg
4106 if (n >= cmdsize) {
4107 da.errors |= DAE_CROSS; // Command crosses end of memory block
4108 } else {
4109 Operandsegreg(&im, (cmd[n]>>3)&0x07, op);
4110 }
4111 break;
4112 case B_SEGNOCS: // Segment register in Reg, but not CS
4113 if (n >= cmdsize) {
4114 da.errors |= DAE_CROSS; // Command crosses end of memory block
4115 } else {
4116 k = (cmd[n]>>3)&0x07;
4117 Operandsegreg(&im, k, op);
4118 if (k == SEG_SS) da.exttype |= DX_WONKYTRAP;
4119 if (k == SEG_CS) {
4120 op.features |= OP_INVALID;
4121 da.errors |= DAE_BADSEG;
4122 }
4123 }
4124 break;
4125 case B_SEGCS: // Segment register CS
4126 Operandsegreg(&im, SEG_CS, op);
4127 break;
4128 case B_SEGDS: // Segment register DS
4129 Operandsegreg(&im, SEG_DS, op);
4130 break;
4131 case B_SEGES: // Segment register ES
4132 Operandsegreg(&im, SEG_ES, op);
4133 break;
4134 case B_SEGFS: // Segment register FS
4135 Operandsegreg(&im, SEG_FS, op);
4136 break;
4137 case B_SEGGS: // Segment register GS
4138 Operandsegreg(&im, SEG_GS, op);
4139 break;
4140 case B_SEGSS: // Segment register SS
4141 Operandsegreg(&im, SEG_SS, op);
4142 break;
4143 case B_ST: // 80-bit FPU register in last cmd byte
4144 Operandfpureg(&im, cmd[n-1]&0x07, op);
4145 break;
4146 case B_ST0: // 80-bit FPU register ST0
4147 Operandfpureg(&im, 0, op);
4148 break;
4149 case B_ST1: // 80-bit FPU register ST1
4150 Operandfpureg(&im, 1, op);
4151 break;
4152 case B_FLOAT32: // 32-bit float in ModRM, memory only
4153 k = Operandmodrm(&im, 4, cmd+n, cmdsize-n, op);
4154 if (k < 0) break; // Error in address
4155 if (k == 0) {
4156 // Register is not allowed, decode as FPU register and set error.
4157 Operandfpureg(&im, cmd[n]&0x07, op);
4158 op.features |= OP_INVALID;
4159 da.errors |= DAE_MEMORY;
4160 }
4161 break;
4162 case B_FLOAT64: // 64-bit float in ModRM, memory only
4163 k = Operandmodrm(&im, 8, cmd+n, cmdsize-n, op);
4164 if (k < 0) break; // Error in address
4165 if (k == 0) {
4166 // Register is not allowed, decode as FPU register and set error.
4167 Operandfpureg(&im, cmd[n]&0x07, op);
4168 op.features |= OP_INVALID;
4169 da.errors |= DAE_MEMORY;
4170 }
4171 break;
4172 case B_FLOAT80: // 80-bit float in ModRM, memory only
4173 k = Operandmodrm(&im, 10, cmd+n, cmdsize-n, op);
4174 if (k < 0) break; // Error in address
4175 if (k == 0) {
4176 // Register is not allowed, decode as FPU register and set error.
4177 Operandfpureg(&im, cmd[n]&0x07, op);
4178 op.features |= OP_INVALID;
4179 da.errors |= DAE_MEMORY;
4180 }
4181 break;
4182 case B_BCD: // 80-bit BCD in ModRM, memory only
4183 k = Operandmodrm(&im, 10, cmd+n, cmdsize-n, op);
4184 if (k < 0) break; // Error in address
4185 if (k == 0) {
4186 // Register is not allowed, decode as FPU register and set error.
4187 Operandfpureg(&im, cmd[n]&0x07, op);
4188 op.features |= OP_INVALID;
4189 da.errors |= DAE_MEMORY;
4190 }
4191 break;
4192 case B_MREG8x8: // MMX register as 8 8-bit integers
4193 case B_MREG16x4: // MMX register as 4 16-bit integers
4194 case B_MREG32x2: // MMX register as 2 32-bit integers
4195 case B_MREG64: // MMX register as 1 64-bit integer
4196 if (n >= cmdsize) {
4197 da.errors |= DAE_CROSS; // Command crosses end of memory block
4198 } else {
4199 Operandmmxreg(&im, (cmd[n]>>3)&0x07, op);
4200 op.granularity = Getgranularity(arg);
4201 }
4202 break;
4203 case B_MMX8x8: // MMX reg/memory as 8 8-bit integers
4204 case B_MMX16x4: // MMX reg/memory as 4 16-bit integers
4205 case B_MMX32x2: // MMX reg/memory as 2 32-bit integers
4206 case B_MMX64: // MMX reg/memory as 1 64-bit integer
4207 k = Operandmodrm(&im, 8, cmd+n, cmdsize-n, op);
4208 if (k < 0) break; // Error in address
4209 if (k == 0) Operandmmxreg(&im, cmd[n]&0x07, op);
4210 op.granularity = Getgranularity(arg);
4211 break;
4212 case B_MMX8x8DI: // MMX 8 8-bit integers at [DS:(E)DI]
4213 Operandindirect(&im, REG_EDI, 0, SEG_UNDEF, 0, 8, op);
4214 op.granularity = Getgranularity(arg);
4215 break;
4216 case B_3DREG: // 3DNow! register as 2 32-bit floats
4217 if (n >= cmdsize) {
4218 da.errors |= DAE_CROSS; // Command crosses end of memory block
4219 } else {
4220 Operandnowreg(&im, (cmd[n]>>3)&0x07, op);
4221 op.granularity = 4;
4222 }
4223 break;
4224 case B_3DNOW: // 3DNow! reg/memory as 2 32-bit floats
4225 k = Operandmodrm(&im, 8, cmd+n, cmdsize-n, op);
4226 if (k < 0) break; // Error in address
4227 if (k == 0) Operandnowreg(&im, cmd[n]&0x07, op);
4228 op.granularity = 4;
4229 break;
4230 case B_SREGF32x4: // SSE register as 4 32-bit floats
4231 case B_SREGF32L: // Low 32-bit float in SSE register
4232 case B_SREGF32x2L: // Low 2 32-bit floats in SSE register
4233 case B_SREGF64x2: // SSE register as 2 64-bit floats
4234 case B_SREGF64L: // Low 64-bit float in SSE register
4235 if (n >= cmdsize) {
4236 da.errors |= DAE_CROSS; // Command crosses end of memory block
4237 } else {
4238 Operandssereg(&im, (cmd[n]>>3)&0x07, op);
4239 op.granularity = Getgranularity(arg);
4240 }
4241 break;
4242 case B_SVEXF32x4: // SSE reg in VEX as 4 32-bit floats
4243 case B_SVEXF32L: // Low 32-bit float in SSE in VEX
4244 case B_SVEXF64x2: // SSE reg in VEX as 2 64-bit floats
4245 case B_SVEXF64L: // Low 64-bit float in SSE in VEX
4246 Operandssereg(&im, vexreg, op);
4247 op.granularity = Getgranularity(arg);
4248 break;
4249 case B_SSEF32x4: // SSE reg/memory as 4 32-bit floats
4250 case B_SSEF64x2: // SSE reg/memory as 2 64-bit floats
4251 k = Operandmodrm(&im, (arg&B_NOVEXSIZE ? 16 : im.ssesize), cmd+n, cmdsize-n, op);
4252 if (k < 0) break; // Error in address
4253 if (k == 0) Operandssereg(&im, cmd[n]&0x07, op);
4254 op.granularity = Getgranularity(arg);
4255 break;
4256 case B_SSEF32L: // Low 32-bit float in SSE reg/memory
4257 k = Operandmodrm(&im, 4, cmd+n, cmdsize-n, op);
4258 if (k < 0) break; // Error in address
4259 if (k == 0) Operandssereg(&im, cmd[n]&0x07, op); // Operand in SSE register
4260 op.granularity = 4;
4261 break;
4262 case B_SSEF32x2L: // Low 2 32-bit floats in SSE reg/memory
4263 k = Operandmodrm(&im, (arg&B_NOVEXSIZE ? 16 : im.ssesize)/2, cmd+n, cmdsize-n, op);
4264 if (k < 0) break; // Error in address
4265 if (k == 0) Operandssereg(&im, cmd[n]&0x07, op); // Operand in SSE register
4266 op.granularity = 4;
4267 break;
4268 case B_SSEF64L: // Low 64-bit float in SSE reg/memory
4269 k = Operandmodrm(&im, 8, cmd+n, cmdsize-n, op);
4270 if (k < 0) break; // Error in address
4271 if (k == 0) Operandssereg(&im, cmd[n]&0x07, op); // Operand in SSE register
4272 op.granularity = 8;
4273 break;
4274 case B_XMM0I32x4: // XMM0 as 4 32-bit integers
4275 case B_XMM0I64x2: // XMM0 as 2 64-bit integers
4276 case B_XMM0I8x16: // XMM0 as 16 8-bit integers
4277 Operandssereg(&im, 0, op);
4278 op.granularity = Getgranularity(arg);
4279 break;
4280 case B_SREGI8x16: // SSE register as 16 8-bit sigints
4281 case B_SREGI16x8: // SSE register as 8 16-bit sigints
4282 case B_SREGI32x4: // SSE register as 4 32-bit sigints
4283 case B_SREGI64x2: // SSE register as 2 64-bit sigints
4284 case B_SREGI32L: // Low 32-bit sigint in SSE register
4285 case B_SREGI32x2L: // Low 2 32-bit sigints in SSE register
4286 case B_SREGI64L: // Low 64-bit sigint in SSE register
4287 if (n >= cmdsize) {
4288 da.errors |= DAE_CROSS; // Command crosses end of memory block
4289 } else {
4290 Operandssereg(&im, (cmd[n]>>3)&0x07, op);
4291 op.granularity = Getgranularity(arg);
4292 }
4293 break;
4294 case B_SVEXI8x16: // SSE reg in VEX as 16 8-bit sigints
4295 case B_SVEXI16x8: // SSE reg in VEX as 8 16-bit sigints
4296 case B_SVEXI32x4: // SSE reg in VEX as 4 32-bit sigints
4297 case B_SVEXI64x2: // SSE reg in VEX as 2 64-bit sigints
4298 Operandssereg(&im, vexreg, op);
4299 op.granularity = Getgranularity(arg);
4300 break;
4301 case B_SSEI8x16: // SSE reg/memory as 16 8-bit sigints
4302 case B_SSEI16x8: // SSE reg/memory as 8 16-bit sigints
4303 case B_SSEI32x4: // SSE reg/memory as 4 32-bit sigints
4304 case B_SSEI64x2: // SSE reg/memory as 2 64-bit sigints
4305 k = Operandmodrm(&im, (arg&B_NOVEXSIZE ? 16 : im.ssesize), cmd+n, cmdsize-n, op);
4306 if (k < 0) break; // Error in address
4307 if (k == 0) Operandssereg(&im, cmd[n]&0x07, op);
4308 op.granularity = Getgranularity(arg);
4309 break;
4310 case B_SSEI8x8L: // Low 8 8-bit ints in SSE reg/memory
4311 case B_SSEI16x4L: // Low 4 16-bit ints in SSE reg/memory
4312 case B_SSEI32x2L: // Low 2 32-bit sigints in SSE reg/memory
4313 k = Operandmodrm(&im, (arg&B_NOVEXSIZE ? 16 : im.ssesize)/2, cmd+n, cmdsize-n, op);
4314 if (k < 0) break; // Error in address
4315 if (k == 0) Operandssereg(&im, cmd[n]&0x07, op);
4316 op.granularity = Getgranularity(arg);
4317 break;
4318 case B_SSEI8x4L: // Low 4 8-bit ints in SSE reg/memory
4319 case B_SSEI16x2L: // Low 2 16-bit ints in SSE reg/memory
4320 k = Operandmodrm(&im, 4, cmd+n, cmdsize-n, op);
4321 if (k < 0) break; // Error in address
4322 if (k == 0) Operandssereg(&im, cmd[n]&0x07, op);
4323 op.granularity = Getgranularity(arg);
4324 break;
4325 case B_SSEI8x2L: // Low 2 8-bit ints in SSE reg/memory
4326 k = Operandmodrm(&im, 2, cmd+n, cmdsize-n, op);
4327 if (k < 0) break; // Error in address
4328 if (k == 0) Operandssereg(&im, cmd[n]&0x07, op);
4329 op.granularity = Getgranularity(arg);
4330 break;
4331 case B_SSEI8x16DI: // SSE 16 8-bit sigints at [DS:(E)DI]
4332 Operandindirect(&im, REG_EDI, 0, SEG_UNDEF, 0, (arg&B_NOVEXSIZE ? 16 : im.ssesize), op);
4333 op.granularity = 1;
4334 break;
4335 case B_EFL: // Flags register EFL
4336 Operandefl(&im, 4, op);
4337 break;
4338 case B_FLAGS8: // Flags (low byte)
4339 Operandefl(&im, 1, op);
4340 break;
4341 case B_OFFSET: // 16/32 const offset from next command
4342 Operandoffset(&im, datasize, datasize, cmd+n, cmdsize-n, da.ip+n, op);
4343 break;
4344 case B_BYTEOFFS: // 8-bit sxt const offset from next cmd
4345 Operandoffset(&im, 1, datasize, cmd+n, cmdsize-n, da.ip+n, op);
4346 break;
4347 case B_FARCONST: // 16:16/16:32 absolute address constant
4348 Operandimmfaraddr(&im, datasize, cmd+n, cmdsize-n, op);
4349 break;
4350 case B_DESCR: // 16:32 descriptor in ModRM
4351 k = Operandmodrm(&im, 6, cmd+n, cmdsize-n, op);
4352 if (k < 0) break; // Error in address
4353 if (k == 0) {
4354 // Register is not allowed, decode as 32-bit register and set error.
4355 Operandintreg(&im, 4, cmd[n]&0x07, op);
4356 op.features |= OP_INVALID;
4357 da.errors |= DAE_MEMORY;
4358 }
4359 break;
4360 case B_1: // Immediate constant 1
4361 Operandone(&im, op);
4362 break;
4363 case B_CONST8: // Immediate 8-bit constant
4364 Operandimmconst(&im, 1, 1, datasize, cmd+n, cmdsize-n, 0, op);
4365 if (arg&B_PORT) op.features |= OP_PORT;
4366 break;
4367 case B_SIMMI8x16: // SSE reg in immediate 8-bit constant
4368 if (cmdsize-n < im.modsize+im.dispsize+1) { da.errors |= DAE_CROSS; break; } // Command crosses end of memory block
4369 im.immsize1 = 1;
4370 Operandssereg(&im, (cmd[n+im.modsize+im.dispsize]>>4)&0x07, op);
4371 op.granularity = Getgranularity(arg);
4372 break;
4373 case B_CONST8_2: // Immediate 8-bit const, second in cmd
4374 Operandimmconst(&im, 1, 1, datasize, cmd+n, cmdsize-n, 1, op);
4375 break;
4376 case B_CONST16: // Immediate 16-bit constant
4377 Operandimmconst(&im, 2, 2, datasize, cmd+n, cmdsize-n, 0, op);
4378 break;
4379 case B_CONST: // Immediate 8/16/32-bit constant
4380 case B_CONSTL: // Immediate 16/32-bit constant
4381 Operandimmconst(&im, datasize, datasize, datasize, cmd+n, cmdsize-n, 0, op);
4382 im.usesdatasize = 1;
4383 break;
4384 case B_SXTCONST: // Immediate 8-bit sign-extended to size
4385 Operandimmconst(&im, 1, datasize, datasize, cmd+n, cmdsize-n, 0, op);
4386 im.usesdatasize = 1;
4387 break;
4388 case B_CR: // Control register in Reg
4389 Operandcreg(&im, (cmd[n]>>3)&0x07, op);
4390 break;
4391 case B_CR0: // Control register CR0
4392 Operandcreg(&im, 0, op);
4393 break;
4394 case B_DR: // Debug register in Reg
4395 Operanddreg(&im, (cmd[n]>>3)&0x07, op);
4396 break;
4397 case B_FST: // FPU status register
4398 Operandfst(&im, op);
4399 break;
4400 case B_FCW: // FPU control register
4401 Operandfcw(&im, op);
4402 break;
4403 case B_MXCSR: // SSE media control and status register
4404 Operandmxcsr(&im, op);
4405 break;
4406 default: // Internal error
4407 da.errors |= DAE_INTERN;
4408 break;
4409 }
4410 if ((arg&B_32BITONLY) != 0 && op.opsize != 4) da.warnings |= DAW_NONCLASS;
4411 if ((arg&B_MODMASK) == B_JMPCALLFAR) da.warnings |= DAW_FARADDR;
4412 if (arg&B_PSEUDO) op.features |= OP_PSEUDO;
4413 if (arg&(B_CHG|B_UPD)) op.features |= OP_MOD;
4414 }
4415 // Optimization for most frequent case
4416 if (im.prefixlist != 0) {
4417 // If LOCK prefix is present, report error if prefix is not allowed by
4418 // command and warning otherwise. Application code usually doesn't need
4419 // atomic bus access.
4420 if ((im.prefixlist&PF_LOCK) != 0) { if ((cmdtype&D_LOCKABLE) == 0) da.errors |= DAE_LOCK; else da.warnings |= DAW_LOCK; }
4421 // Warn if data size prefix is present but not used by command.
4422 if ((im.prefixlist&PF_DSIZE) != 0 && im.usesdatasize == 0 && (pcmd.exttype&DX_TYPEMASK) != DX_NOP) da.warnings |= DAW_DATASIZE;
4423 // Warn if address size prefix is present but not used by command.
4424 if ((im.prefixlist&PF_ASIZE) != 0 && im.usesaddrsize == 0) da.warnings |= DAW_ADDRSIZE;
4425 // Warn if segment override prefix is present but command doesn't access
4426 // memory. Prefixes CS: and DS: are also used as branch hints in
4427 // conditional branches.
4428 if ((im.prefixlist&PF_SEGMASK) != 0 && im.usessegment == 0) { if ((cmdtype&D_BHINT) == 0 || (im.prefixlist&PF_HINT) == 0) da.warnings |= DAW_SEGPREFIX; }
4429 // Warn if REPxx prefix is present but not used by command. Attention,
4430 // Intel frequently uses these prefixes for different means!
4431 if (im.prefixlist&PF_REPMASK) {
4432 if (((im.prefixlist&PF_REP) != 0 && (cmdtype&D_MUSTMASK) != D_MUSTREP && (cmdtype&D_MUSTMASK) != D_MUSTREPE) ||
4433 ((im.prefixlist&PF_REPNE) != 0 && (cmdtype&D_MUSTMASK) != D_MUSTREPNE))
4434 {
4435 da.warnings |= DAW_REPPREFIX;
4436 }
4437 }
4438 }
4439 // Warn on unaligned stack, I/O and privileged commands.
4440 switch (cmdtype&D_CMDTYPE) {
4441 case D_PUSH: if (datasize == 2) da.warnings |= DAW_STACK; break;
4442 case D_INT: da.warnings |= DAW_INTERRUPT; break;
4443 case D_IO: da.warnings |= DAW_IO; break;
4444 case D_PRIVILEGED: da.warnings |= DAW_PRIV; break;
4445 default:
4446 }
4447 // Warn on system, privileged and undocumented commands.
4448 if ((cmdtype&D_USEMASK) != 0) {
4449 if ((cmdtype&D_USEMASK) == D_RARE || (cmdtype&D_USEMASK) == D_SUSPICIOUS) da.warnings |= DAW_RARE;
4450 if ((cmdtype&D_USEMASK) == D_UNDOC) da.warnings |= DAW_NONCLASS;
4451 }
4452 // If command implicitly changes ESP, it uses and modifies this register.
4453 if (cmdtype&D_CHGESP) {
4454 da.uses |= (1<<REG_ESP);
4455 da.modifies |= (1<<REG_ESP);
4456 }
4457 error:
4458 // Prepare hex dump, if requested. As maximal size of command is limited to
4459 // MAXCMDSIZE = 16 bytes, string can't overflow.
4460 if (damode&DA_DUMP) {
4461 if (da.errors&DAE_CROSS) {
4462 // Incomplete command
4463 Thexdump(da.dump.ptr, cmd, cmdsize, config.lowercase);
4464 } else {
4465 j = 0;
4466 // Dump prefixes. REPxx is treated as prefix and separated from command
4467 // with semicolon; prefixes 66, F2 and F3 that are part of SSE command
4468 // are glued with command's body - well, at least if there are no other
4469 // prefixes inbetween.
4470 for (u = 0; u < da.nprefix; ++u) {
4471 j += Thexdump(da.dump.ptr+j, cmd+u, 1, config.lowercase);
4472 if (cmd[u] == 0x66 && (cmdtype&D_MUSTMASK) == D_MUST66) continue;
4473 if (cmd[u] == 0xF2 && ((cmdtype&D_MUSTMASK) == D_MUSTF2 || (cmdtype&D_MUSTMASK) == D_NEEDF2)) continue;
4474 if (cmd[u] == 0xF3 && ((cmdtype&D_MUSTMASK) == D_MUSTF3 || (cmdtype&D_MUSTMASK) == D_NEEDF3)) continue;
4475 if ((im.prefixlist&(PF_VEX2|PF_VEX3)) != 0 && u == da.nprefix-2) continue;
4476 if ((im.prefixlist&PF_VEX3) != 0 && u == da.nprefix-3) continue;
4477 da.dump[j++] = ':';
4478 }
4479 // Dump body of the command, including ModRegRM and SIB bytes.
4480 j += Thexdump(da.dump.ptr+j, cmd+u, im.mainsize+im.modsize-u, config.lowercase);
4481 // Dump displacement, if any, separated with space from command's body.
4482 if (im.dispsize > 0) {
4483 da.dump[j++] = ' ';
4484 j += Thexdump(da.dump.ptr+j, cmd+im.mainsize+im.modsize, im.dispsize, config.lowercase);
4485 }
4486 // Dump immediate constants, if any.
4487 if (im.immsize1 > 0) {
4488 da.dump[j++] = ' ';
4489 j += Thexdump(da.dump.ptr+j, cmd+im.mainsize+im.modsize+im.dispsize, im.immsize1, config.lowercase);
4490 }
4491 if (im.immsize2 > 0) {
4492 da.dump[j++] = ' ';
4493 Thexdump(da.dump.ptr+j, cmd+im.mainsize+im.modsize+im.dispsize+im.immsize1, im.immsize2, config.lowercase);
4494 }
4495 }
4496 }
4497 // Prepare disassembled command. There are many options that control look
4498 // and feel of disassembly, so the procedure is a bit, errr, boring.
4499 if (damode&DA_TEXT) {
4500 if (da.errors&DAE_CROSS) {
4501 // Incomplete command
4502 q = Tstrcopy(da.result.ptr, TEXTLEN, "???");
4503 if (damode&DA_HILITE) {
4504 memset(da.mask.ptr, DRAW_SUSPECT, q);
4505 da.masksize = q;
4506 }
4507 } else {
4508 j = 0;
4509 // If LOCK and/or REPxx prefix is present, prepend it to the command.
4510 // Such cases are rare, first comparison makes small optimization.
4511 if (im.prefixlist&(PF_LOCK|PF_REPMASK)) {
4512 if (im.prefixlist&PF_LOCK) j = Tcopycase(da.result.ptr, TEXTLEN, "LOCK ", config.lowercase);
4513 if (im.prefixlist&PF_REPNE) j += Tcopycase(da.result.ptr+j, TEXTLEN-j, "REPNE ", config.lowercase);
4514 else if (im.prefixlist&PF_REP) {
4515 if ((cmdtype&D_MUSTMASK) == D_MUSTREPE) {
4516 j += Tcopycase(da.result.ptr+j, TEXTLEN-j, "REPE ", config.lowercase);
4517 } else {
4518 j += Tcopycase(da.result.ptr+j, TEXTLEN-j, "REP ", config.lowercase);
4519 }
4520 }
4521 }
4522 // If there is a branch hint, prefix jump mnemonics with '+' (taken) or
4523 // '-' (not taken), or use pseudoprefixes BHT/BHNT. I don't know how MASM
4524 // indicates hints.
4525 if (cmdtype&D_BHINT) {
4526 if (config.jumphintmode == 0) {
4527 if (im.prefixlist&PF_TAKEN) da.result[j++] = '+';
4528 else if (im.prefixlist&PF_NOTTAKEN) da.result[j++] = '-';
4529 } else {
4530 if (im.prefixlist&PF_TAKEN) j += Tcopycase(da.result.ptr+j, TEXTLEN-j, "BHT ", config.lowercase);
4531 else if (im.prefixlist&PF_NOTTAKEN) j += Tcopycase(da.result.ptr+j, TEXTLEN-j, "BHNT ", config.lowercase);
4532 }
4533 }
4534 // Get command mnemonics. If mnemonics contains asterisk, it must be
4535 // replaced by W, D or none according to sizesens. Asterisk in SSE and
4536 // AVX commands means comparison predicate.
4537 if (cmdtype&D_WILDCARD) {
4538 for (i = 0; ; ++i) {
4539 if (pcmd.name[i] == '\0') break;
4540 else if (pcmd.name[i] != '*') da.result[j++] = pcmd.name[i];
4541 else if (cmdtype&D_POSTBYTE) j += Tstrcopy(da.result.ptr+j, TEXTLEN-j, ssepredicate[cmd[im.mainsize+im.modsize+im.dispsize]].ptr);
4542 else if (datasize == 4 && (config.sizesens == 0 || config.sizesens == 1)) da.result[j++] = 'D';
4543 else if (datasize == 2 && (config.sizesens == 1 || config.sizesens == 2)) da.result[j++] = 'W';
4544 }
4545 da.result[j] = '\0';
4546 if (config.lowercase) tstrlwr(da.result);
4547 } else {
4548 j += Tcopycase(da.result.ptr+j, TEXTLEN-j, pcmd.name.ptr, config.lowercase);
4549 if (config.disasmmode == DAMODE_ATT && im.usesdatasize != 0) {
4550 // AT&T mnemonics are suffixed with the operand's size.
4551 if ((cmdtype&D_CMDTYPE) != D_CMD &&
4552 (cmdtype&D_CMDTYPE) != D_MOV &&
4553 (cmdtype&D_CMDTYPE) != D_MOVC &&
4554 (cmdtype&D_CMDTYPE) != D_TEST &&
4555 (cmdtype&D_CMDTYPE) != D_STRING &&
4556 (cmdtype&D_CMDTYPE) != D_PUSH &&
4557 (cmdtype&D_CMDTYPE) != D_POP) {}
4558 else if (datasize == 1) j += Tcopycase(da.result.ptr+j, TEXTLEN-j, "B", config.lowercase);
4559 else if (datasize == 2) j += Tcopycase(da.result.ptr+j, TEXTLEN-j, "W", config.lowercase);
4560 else if (datasize == 4) j += Tcopycase(da.result.ptr+j, TEXTLEN-j, "L", config.lowercase);
4561 else if (datasize == 8) j += Tcopycase(da.result.ptr+j, TEXTLEN-j, "Q", config.lowercase);
4562 }
4563 }
4564 if (damode&DA_HILITE) {
4565 type = cmdtype&D_CMDTYPE;
4566 if (da.errors != 0) {
4567 cfill = DRAW_SUSPECT;
4568 } else {
4569 switch (cmdtype&D_CMDTYPE) {
4570 case D_JMP: // Unconditional near jump
4571 case D_JMPFAR: // Unconditional far jump
4572 cfill = DRAW_JUMP; break;
4573 case D_JMC: // Conditional jump on flags
4574 case D_JMCX: // Conditional jump on (E)CX (and flags)
4575 cfill = DRAW_CJMP; break;
4576 case D_PUSH: // PUSH exactly 1 (d)word of data
4577 case D_POP: // POP exactly 1 (d)word of data
4578 cfill = DRAW_PUSHPOP; break;
4579 case D_CALL: // Plain near call
4580 case D_CALLFAR: // Far call
4581 case D_INT: // Interrupt
4582 cfill = DRAW_CALL; break;
4583 case D_RET: // Plain near return from call
4584 case D_RETFAR: // Far return or IRET
4585 cfill = DRAW_RET; break;
4586 case D_FPU: // FPU command
4587 case D_MMX: // MMX instruction, incl. SSE extensions
4588 case D_3DNOW: // 3DNow! instruction
4589 case D_SSE: // SSE instruction
4590 case D_AVX: // AVX instruction
4591 cfill = DRAW_FPU; break;
4592 case D_IO: // Accesses I/O ports
4593 case D_SYS: // Legal but useful in system code only
4594 case D_PRIVILEGED: // Privileged (non-Ring3) command
4595 cfill = DRAW_SUSPECT; break;
4596 default:
4597 cfill = DRAW_PLAIN;
4598 break;
4599 }
4600 }
4601 memset(da.mask.ptr, cfill, j);
4602 da.masksize = j;
4603 }
4604 // Add decoded operands. In HLA mode, order of operands is inverted
4605 // except for comparison commands (marked with bit D_HLADIR) and
4606 // arguments are enclosed in parenthesis (except for immediate jumps).
4607 // In AT&T mode, order of operands is always inverted. Operands of type
4608 // B_PSEUDO are implicit and don't appear in text.
4609 if (config.disasmmode == DAMODE_HLA && (pcmd.arg[0]&B_ARGMASK) != B_OFFSET && (pcmd.arg[0]&B_ARGMASK) != B_BYTEOFFS && (pcmd.arg[0]&B_ARGMASK) != B_FARCONST) {
4610 enclose = 1; // Enclose operand list in parenthesis
4611 } else {
4612 enclose = 0;
4613 }
4614 if ((damode&DA_HILITE) != 0 && config.hiliteoperands != 0) cfill = DRAW_PLAIN;
4615 nout = 0;
4616 for (i = 0; i < noperand; ++i) {
4617 if ((config.disasmmode == DAMODE_HLA && (cmdtype&D_HLADIR) == 0) || config.disasmmode == DAMODE_ATT) {
4618 k = noperand-1-i; // Inverted (HLA/AT&T) order of operands
4619 } else {
4620 k = i; // Direct (Intel's) order of operands
4621 }
4622 arg = da.op[k].arg;
4623 if ((arg&B_ARGMASK) == B_NONE || (arg&B_PSEUDO) != 0) continue; // Empty or implicit operand
4624 q = j;
4625 if (nout == 0) {
4626 // Spaces between mnemonic and first operand.
4627 da.result[j++] = ' ';
4628 if (config.tabarguments) { for ( ; j < 8; ++j) da.result[j] = ' '; }
4629 if (enclose) {
4630 da.result[j++] = '(';
4631 if (config.extraspace) da.result[j++] = (' ');
4632 }
4633 } else {
4634 // Comma and optional space between operands.
4635 da.result[j++] = ',';
4636 if (config.extraspace) da.result[j++] = ' ';
4637 }
4638 if (damode&DA_HILITE) {
4639 memset(da.mask.ptr+q, cfill, j-q);
4640 da.masksize = j;
4641 }
4642 // Operand itself.
4643 q = j;
4644 op = da.op.ptr+k;
4645 j += Tstrcopy(da.result.ptr+j, TEXTLEN-j-10, op.text.ptr);
4646 if (damode&DA_HILITE) {
4647 if (config.hiliteoperands == 0) ofill = cfill;
4648 else if (op.features&OP_REGISTER) ofill = DRAW_IREG;
4649 else if (op.features&(OP_FPUREG|OP_MMXREG|OP_3DNOWREG|OP_SSEREG)) ofill = DRAW_FREG;
4650 else if (op.features&(OP_SEGREG|OP_CREG|OP_DREG)) ofill = DRAW_SYSREG;
4651 else if (op.features&OP_MEMORY) { if (op.scale[REG_ESP] != 0 || op.scale[REG_EBP] != 0) ofill = DRAW_STKMEM; else ofill = DRAW_MEM; }
4652 else if (op.features&OP_CONST) ofill = DRAW_CONST;
4653 else ofill = cfill;
4654 memset(da.mask.ptr+q, ofill, j-q);
4655 da.masksize = j;
4656 }
4657 ++nout;
4658 }
4659 // All arguments added, close list.
4660 if (enclose && nout != 0) {
4661 q = j;
4662 if (config.extraspace) da.result[j++] = ' ';
4663 da.result[j++] = ')';
4664 if (damode&DA_HILITE) {
4665 memset(da.mask.ptr+q, cfill, j-q);
4666 da.masksize = j;
4667 }
4668 }
4669 da.result[j] = '\0';
4670 }
4671 }
4672 // Calculate total size of command.
4673 if (da.errors&DAE_CROSS) {
4674 // Incomplete command
4675 n = cmdsize;
4676 } else {
4677 n += im.modsize+im.dispsize+im.immsize1+im.immsize2;
4678 }
4679 da.size = n;
4680 return n;
4681 }
4682
4683 // Given error and warning lists, returns pointer to the string describing
4684 // relatively most severe error or warning, or null if there are no errors or
4685 // warnings.
4686 public string disErrMessage (uint errors, uint warnings) {
4687 if (errors == 0 && warnings == 0) return null;
4688
4689 if (errors&DAE_BADCMD) return "Unknown command";
4690 if (errors&DAE_CROSS) return "Command crosses end of memory block";
4691 if (errors&DAE_MEMORY) return "Illegal use of register";
4692 if (errors&DAE_REGISTER) return "Memory address is not allowed";
4693 if (errors&DAE_LOCK) return "LOCK prefix is not allowed";
4694 if (errors&DAE_BADSEG) return "Invalid segment register";
4695 if (errors&DAE_SAMEPREF) return "Two prefixes from the same group";
4696 if (errors&DAE_MANYPREF) return "More than 4 prefixes";
4697 if (errors&DAE_BADCR) return "Invalid CR register";
4698 if (errors&DAE_INTERN) return "Internal error";
4699
4700 if (warnings&DAW_DATASIZE) return "Superfluous operand size prefix";
4701 if (warnings&DAW_ADDRSIZE) return "Superfluous address size prefix";
4702 if (warnings&DAW_SEGPREFIX) return "Superfluous segment override prefix";
4703 if (warnings&DAW_REPPREFIX) return "Superfluous REPxx prefix";
4704 if (warnings&DAW_DEFSEG) return "Explicit default segment register";
4705 if (warnings&DAW_JMP16) return "16-bit jump, call or return";
4706 if (warnings&DAW_FARADDR) return "Far jump or call";
4707 if (warnings&DAW_SEGMOD) return "Modification of segment register";
4708 if (warnings&DAW_PRIV) return "Privileged instruction";
4709 if (warnings&DAW_IO) return "I/O command";
4710 if (warnings&DAW_SHIFT) return "Shift out of range";
4711 if (warnings&DAW_LOCK) return "Command uses (valid) LOCK prefix";
4712 if (warnings&DAW_STACK) return "Unaligned stack operation";
4713 if (warnings&DAW_NOESP) return "Suspicious use of stack pointer";
4714 if (warnings&DAW_NONCLASS) return "Undocumented instruction or encoding";
4715
4716 return null;
4717 }
various I.V. D modules