examples/xram16x1.v

   1 /*
   2  * Copyright (c) 1999 Stephen Williams (steve@icarus.com)
   3  *
   4  *    This source code is free software; you can redistribute it
   5  *    and/or modify it in source code form under the terms of the GNU
   6  *    General Public License as published by the Free Software
   7  *    Foundation; either version 2 of the License, or (at your option)
   8  *    any later version.
   9  *
  10  *    This program is distributed in the hope that it will be useful,
  11  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *    GNU General Public License for more details.
  14  *
  15  *    You should have received a copy of the GNU General Public License
  16  *    along with this program; if not, write to the Free Software
  17  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  18  */
  19
  20 // This example describes a 16x1 RAM that can be synthesized into
  21 // a CLB ram in a Xilinx FPGA.
  22
  23 module ram16x1 (q, d, a, we, wclk);
  24    output q;
  25    input d;
  26    input [3:0] a;
  27    input we;
  28    input wclk;
  29
  30    reg mem[15:0];
  31
  32    assign q = mem[a];
  33    always @(posedge wclk) if (we) mem[a] = d;
  34
  35 endmodule /* ram16x1 */
  36
  37 module main;
  38    wire q;
  39    reg d;
  40    reg [3:0] a;
  41    reg we, wclk;
  42
  43    ram16x1 r1 (q, d, a, we, wclk);
  44
  45    initial begin
  46       $monitor("q = %b", q);
  47       d = 0;
  48       wclk = 0;
  49       a = 5;
  50       we = 1;
  51       #1 wclk = 1;
  52       #1 wclk = 0;
  53    end
  54 endmodule /* main */