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Logic gates can take part select inputs
[iverilog.git] / xnf.conf
blobffcd9ae6cf26d176dc139dc1381dc67d86d30785
1 functor:synth
2 functor:syn-rules
3 functor:xnfio
4 functor:cprop
5 functor:nodangle
6 -t:xnf
Icarus Verilog