Module.h

   1 #ifndef __Module_H
   2 #define __Module_H
   3 /*
   4  * Copyright (c) 1998-2004 Stephen Williams (steve@icarus.com)
   5  *
   6  *    This source code is free software; you can redistribute it
   7  *    and/or modify it in source code form under the terms of the GNU
   8  *    General Public License as published by the Free Software
   9  *    Foundation; either version 2 of the License, or (at your option)
  10  *    any later version.
  11  *
  12  *    This program is distributed in the hope that it will be useful,
  13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *    GNU General Public License for more details.
  16  *
  17  *    You should have received a copy of the GNU General Public License
  18  *    along with this program; if not, write to the Free Software
  19  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  20  */
  21 #ifdef HAVE_CVS_IDENT
  22 #ident "$Id: Module.h,v 1.43 2007/05/24 04:07:11 steve Exp $"
  23 #endif
  24
  25 # include  <list>
  26 # include  <map>
  27 # include  "svector.h"
  28 # include  "StringHeap.h"
  29 # include  "HName.h"
  30 # include  "named.h"
  31 # include  "LineInfo.h"
  32 # include  "netlist.h"
  33 # include  "pform_types.h"
  34 class PEvent;
  35 class PExpr;
  36 class PEIdent;
  37 class PGate;
  38 class PGenerate;
  39 class PSpecPath;
  40 class PTask;
  41 class PFunction;
  42 class PWire;
  43 class PProcess;
  44 class Design;
  45 class NetScope;
  46
  47 /*
  48  * A module is a named container and scope. A module holds a bunch of
  49  * semantic quantities such as wires and gates. The module is
  50  * therefore the handle for grasping the described circuit.
  51  */
  52
  53 class Module : public LineInfo {
  54
  55         /* The module ports are in general a vector of port_t
  56            objects. Each port has a name and an ordered list of
  57            wires. The name is the means that the outside uses to
  58            access the port, the wires are the internal connections to
  59            the port. */
  60     public:
  61       struct port_t {
  62             perm_string name;
  63             svector<PEIdent*> expr;
  64       };
  65
  66     public:
  67         /* The name passed here is the module name, not the instance
  68            name. This make must be a permallocated string. */
  69       explicit Module(perm_string name);
  70       ~Module();
  71
  72         /* Initially false. This is set to true if the module has been
  73            declared as a library module. This makes the module
  74            ineligible for being chosen as an implicit root. It has no
  75            other effect. */
  76       bool library_flag;
  77
  78       NetNet::Type default_nettype;
  79
  80         /* The module has parameters that are evaluated when the
  81            module is elaborated. During parsing, I put the parameters
  82            into this map. */
  83       struct param_expr_t {
  84             PExpr*expr;
  85             PExpr*msb;
  86             PExpr*lsb;
  87             bool signed_flag;
  88       };
  89       map<perm_string,param_expr_t>parameters;
  90       map<perm_string,param_expr_t>localparams;
  91
  92
  93         /* specparams are simpler then other params, in that they have
  94            no type information. They are merely constant
  95            expressions. */
  96       map<perm_string,PExpr*>specparams;
  97
  98         /* The module also has defparam assignments which don't create
  99            new parameters within the module, but may be used to set
 100            values within this module (when instantiated) or in other
 101            instantiated modules. */
 102       map<pform_name_t,PExpr*>defparms;
 103
 104         /* Parameters may be overridden at instantiation time;
 105            the overrides do not contain explicit parameter names,
 106            but rather refer to parameters in the order they
 107            appear in the instantiated module.  Therefore a
 108            list of names in module-order is needed to pass from
 109            a parameter-index to its name. */
 110       list<perm_string> param_names;
 111
 112         /* This is an array of port descriptors, which is in turn a
 113            named array of PEident pointers. */
 114       svector<port_t*> ports;
 115
 116         /* Keep a table of named events declared in the module. */
 117       map<perm_string,PEvent*>events;
 118
 119       map<perm_string,PExpr*> attributes;
 120
 121         /* These are the timescale for this module. The default is
 122            set by the `timescale directive. */
 123       int time_unit, time_precision;
 124
 125         /* The module has a list of genvars that may be used in
 126            various generate schemes. */
 127       list<perm_string> genvars;
 128
 129         /* the module has a list of generate schemes that appear in
 130            the module definition. These are used at elaboration time. */
 131       list<PGenerate*> generate_schemes;
 132
 133       list<PSpecPath*> specify_paths;
 134
 135       perm_string mod_name() const { return name_; }
 136
 137       void add_gate(PGate*gate);
 138
 139         // The add_wire method adds a wire by name, but only if the
 140         // wire name doesn't already exist. Either way, the result is
 141         // the existing wire or the pointer passed in.
 142       PWire* add_wire(PWire*wire);
 143
 144       void add_behavior(PProcess*behave);
 145       void add_task(perm_string name, PTask*def);
 146       void add_function(perm_string name, PFunction*def);
 147
 148       unsigned port_count() const;
 149       const svector<PEIdent*>& get_port(unsigned idx) const;
 150       unsigned find_port(const char*name) const;
 151
 152         // Find a wire by name. This is used for connecting gates to
 153         // existing wires, etc.
 154       PWire* get_wire(const pform_name_t&name) const;
 155       PGate* get_gate(perm_string name);
 156
 157       const list<PGate*>& get_gates() const;
 158       const list<PProcess*>& get_behaviors() const;
 159
 160       void dump(ostream&out) const;
 161       bool elaborate(Design*, NetScope*scope) const;
 162
 163       typedef map<perm_string,NetExpr*> replace_t;
 164       bool elaborate_scope(Design*, NetScope*scope, const replace_t&rep) const;
 165
 166       bool elaborate_sig(Design*, NetScope*scope) const;
 167
 168     private:
 169       perm_string name_;
 170
 171       map<pform_name_t,PWire*> wires_;
 172       list<PGate*> gates_;
 173       list<PProcess*> behaviors_;
 174       map<perm_string,PTask*> tasks_;
 175       map<perm_string,PFunction*> funcs_;
 176
 177     private: // Not implemented
 178       Module(const Module&);
 179       Module& operator= (const Module&);
 180 };
 181
 182
 183 /*
 184  * $Log: Module.h,v $
 185  * Revision 1.43  2007/05/24 04:07:11  steve
 186  *  Rework the heirarchical identifier parse syntax and pform
 187  *  to handle more general combinations of heirarch and bit selects.
 188  *
 189  * Revision 1.42  2007/04/19 02:52:53  steve
 190  *  Add support for -v flag in command file.
 191  *
 192  * Revision 1.41  2006/09/23 04:57:19  steve
 193  *  Basic support for specify timing.
 194  *
 195  * Revision 1.40  2006/04/10 00:37:42  steve
 196  *  Add support for generate loops w/ wires and gates.
 197  *
 198  * Revision 1.39  2006/03/30 01:49:07  steve
 199  *  Fix instance arrays indexed by overridden parameters.
 200  *
 201  * Revision 1.38  2005/07/11 16:56:50  steve
 202  *  Remove NetVariable and ivl_variable_t structures.
 203  */
 204 #endif