Merge branch 'master' of steve-icarus@icarus.com:git/verilog
[iverilog.git] / elab_lval.cc
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1 /*
2 * Copyright (c) 2000-2006 Stephen Williams (steve@icarus.com)
4 * This source code is free software; you can redistribute it
5 * and/or modify it in source code form under the terms of the GNU
6 * General Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your option)
8 * any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 #ifdef HAVE_CVS_IDENT
20 #ident "$Id: elab_lval.cc,v 1.44 2007/06/02 03:42:12 steve Exp $"
21 #endif
23 # include "config.h"
25 # include "PExpr.h"
26 # include "netlist.h"
27 # include "netmisc.h"
28 # include "compiler.h"
29 # include <iostream>
30 # include "ivl_assert.h"
33 * These methods generate a NetAssign_ object for the l-value of the
34 * assignment. This is common code for the = and <= statements.
36 * What gets generated depends on the structure of the l-value. If the
37 * l-value is a simple name (i.e., foo <= <value>) the the NetAssign_
38 * is created the width of the foo reg and connected to all the
39 * bits.
41 * If there is a part select (i.e., foo[3:1] <= <value>) the NetAssign_
42 * is made only as wide as it needs to be (3 bits in this example) and
43 * connected to the correct bits of foo. A constant bit select is a
44 * special case of the part select.
46 * If the bit-select is non-constant (i.e., foo[<expr>] = <value>) the
47 * NetAssign_ is made wide enough to connect to all the bits of foo,
48 * then the mux expression is elaborated and attached to the
49 * NetAssign_ node as a b_mux value. The target must interpret the
50 * presence of a bmux value as taking a single bit and assigning it to
51 * the bit selected by the bmux expression.
53 * If the l-value expression is non-trivial, but can be fully
54 * evaluated at compile time (meaning any bit selects are constant)
55 * then elaboration will make a single NetAssign_ that connects to a
56 * synthetic reg that in turn connects to all the proper pins of the
57 * l-value.
59 * This last case can turn up in statements like: {a, b[1]} = c;
60 * rather then create a NetAssign_ for each item in the concatenation,
61 * elaboration makes a single NetAssign_ and connects it up properly.
66 * The default interpretation of an l-value to a procedural assignment
67 * is to try to make a net elaboration, and see if the result is
68 * suitable for assignment.
70 NetAssign_* PExpr::elaborate_lval(Design*des,
71 NetScope*scope,
72 bool is_force) const
74 NetNet*ll = 0;
75 if (ll == 0) {
76 cerr << get_line() << ": Assignment l-value too complex."
77 << endl;
78 return 0;
81 NetAssign_*lv = new NetAssign_(ll);
82 return lv;
86 * Concatenation expressions can appear as l-values. Handle them here.
88 * If adjacent l-values in the concatenation are not bit selects, then
89 * merge them into a single NetAssign_ object. This can happen is code
90 * like ``{ ...a, b, ...}''. As long as "a" and "b" do not have bit
91 * selects (or the bit selects are constant) we can merge the
92 * NetAssign_ objects.
94 * Be careful to get the bit order right. In the expression ``{a, b}''
95 * a is the MSB and b the LSB. Connect the LSB to the low pins of the
96 * NetAssign_ object.
98 NetAssign_* PEConcat::elaborate_lval(Design*des,
99 NetScope*scope,
100 bool is_force) const
102 if (repeat_) {
103 cerr << get_line() << ": error: Repeat concatenations make "
104 "no sense in l-value expressions. I refuse." << endl;
105 des->errors += 1;
106 return 0;
109 NetAssign_*res = 0;
111 for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
113 if (parms_[idx] == 0) {
114 cerr << get_line() << ": error: Empty expressions "
115 << "not allowed in concatenations." << endl;
116 des->errors += 1;
117 continue;
120 NetAssign_*tmp = parms_[idx]->elaborate_lval(des, scope, is_force);
122 /* If the l-value doesn't elaborate, the error was
123 already detected and printed. We just skip it and let
124 the compiler catch more errors. */
125 if (tmp == 0)
126 continue;
128 assert(tmp);
131 /* Link the new l-value to the previous one. */
133 NetAssign_*last = tmp;
134 while (last->more)
135 last = last->more;
137 last->more = res;
138 res = tmp;
141 return res;
145 * Handle the ident as an l-value. This includes bit and part selects
146 * of that ident.
148 NetAssign_* PEIdent::elaborate_lval(Design*des,
149 NetScope*scope,
150 bool is_force) const
152 NetNet* reg = 0;
153 const NetExpr*par = 0;
154 NetEvent* eve = 0;
156 symbol_search(des, scope, path_, reg, par, eve);
157 if (reg == 0) {
158 cerr << get_line() << ": error: Could not find variable ``"
159 << path_ << "'' in ``" << scope_path(scope) <<
160 "''" << endl;
162 des->errors += 1;
163 return 0;
166 ivl_assert(*this, reg);
168 const name_component_t&name_tail = path_.back();
170 index_component_t::ctype_t use_sel = index_component_t::SEL_NONE;
171 if (!name_tail.index.empty())
172 use_sel = name_tail.index.back().sel;
174 // This is the special case that the l-value is an entire
175 // memory. This is, in fact, an error.
176 if (reg->array_dimensions() > 0 && name_tail.index.empty()) {
177 cerr << get_line() << ": error: Cannot assign to array "
178 << path_ << ". Did you forget a word index?" << endl;
179 des->errors += 1;
180 return 0;
183 if (reg->array_dimensions() > 0)
184 return elaborate_lval_net_word_(des, scope, reg);
186 if (use_sel == index_component_t::SEL_PART) {
187 NetAssign_*lv = new NetAssign_(reg);
188 elaborate_lval_net_part_(des, scope, lv);
189 return lv;
192 if (use_sel == index_component_t::SEL_IDX_UP) {
193 NetAssign_*lv = new NetAssign_(reg);
194 elaborate_lval_net_idx_up_(des, scope, lv);
195 return lv;
198 if (use_sel == index_component_t::SEL_IDX_DO) {
199 NetAssign_*lv = new NetAssign_(reg);
200 elaborate_lval_net_idx_do_(des, scope, lv);
201 return lv;
204 /* Get the signal referenced by the identifier, and make sure
205 it is a register. Wires are not allows in this context,
206 unless this is the l-value of a force. */
207 if ((reg->type() != NetNet::REG) && !is_force) {
208 cerr << get_line() << ": error: " << path_ <<
209 " is not a valid l-value in " << scope_path(scope) <<
210 "." << endl;
211 cerr << reg->get_line() << ": : " << path_ <<
212 " is declared here as " << reg->type() << "." << endl;
213 des->errors += 1;
214 return 0;
217 long msb, lsb;
218 NetExpr*mux;
220 if (use_sel == index_component_t::SEL_BIT) {
222 const index_component_t&index_tail = name_tail.index.back();
223 ivl_assert(*this, index_tail.msb != 0);
224 ivl_assert(*this, index_tail.lsb == 0);
226 /* If there is only a single select expression, it is a
227 bit select. Evaluate the constant value and treat it
228 as a part select with a bit width of 1. If the
229 expression it not constant, then return the
230 expression as a mux. */
232 NetExpr*index_expr = elab_and_eval(des, scope, index_tail.msb, -1);
234 if (NetEConst*index_con = dynamic_cast<NetEConst*> (index_expr)) {
235 msb = index_con->value().as_long();
236 lsb = index_con->value().as_long();
237 mux = 0;
239 } else {
240 msb = 0;
241 lsb = 0;
242 mux = index_expr;
245 } else {
247 /* No select expressions, so presume a part select the
248 width of the register. */
250 msb = reg->msb();
251 lsb = reg->lsb();
252 mux = 0;
256 NetAssign_*lv;
257 if (mux) {
259 /* If there is a non-constant bit select, make a
260 NetAssign_ to the target reg and attach a
261 bmux to select the target bit. */
262 lv = new NetAssign_(reg);
264 /* Correct the mux for the range of the vector. */
265 if (reg->msb() < reg->lsb())
266 mux = make_sub_expr(reg->lsb(), mux);
267 else if (reg->lsb() != 0)
268 mux = make_add_expr(mux, - reg->lsb());
270 lv->set_part(mux, 1);
272 } else if (msb == reg->msb() && lsb == reg->lsb()) {
274 /* No bit select, and part select covers the entire
275 vector. Simplest case. */
276 lv = new NetAssign_(reg);
278 } else {
280 /* If the bit/part select is constant, then make the
281 NetAssign_ only as wide as it needs to be and connect
282 only to the selected bits of the reg. */
283 unsigned loff = reg->sb_to_idx(lsb);
284 unsigned moff = reg->sb_to_idx(msb);
285 unsigned wid = moff - loff + 1;
287 if (moff < loff) {
288 cerr << get_line() << ": error: part select "
289 << reg->name() << "[" << msb<<":"<<lsb<<"]"
290 << " is reversed." << endl;
291 des->errors += 1;
292 return 0;
295 /* If the part select extends beyond the extreme of the
296 variable, then report an error. Note that loff is
297 converted to normalized form so is relative the
298 variable pins. */
300 if ((wid + loff) > reg->vector_width()) {
301 cerr << get_line() << ": error: bit/part select "
302 << reg->name() << "[" << msb<<":"<<lsb<<"]"
303 << " is out of range." << endl;
304 des->errors += 1;
305 return 0;
308 lv = new NetAssign_(reg);
309 lv->set_part(new NetEConst(verinum(loff)), wid);
313 return lv;
316 NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
317 NetScope*scope,
318 NetNet*reg) const
320 const name_component_t&name_tail = path_.back();
321 ivl_assert(*this, !name_tail.index.empty());
323 const index_component_t&index_head = name_tail.index.front();
324 ivl_assert(*this, index_head.sel == index_component_t::SEL_BIT);
325 ivl_assert(*this, index_head.msb != 0);
326 ivl_assert(*this, index_head.lsb == 0);
328 NetExpr*word = elab_and_eval(des, scope, index_head.msb, -1);
330 // If there is a non-zero base to the memory, then build an
331 // expression to calculate the canonical address.
332 if (long base = reg->array_first()) {
334 word = make_add_expr(word, 0-base);
335 if (NetExpr*tmp = word->eval_tree()) {
336 word = tmp;
340 NetAssign_*lv = new NetAssign_(reg);
341 lv->set_word(word);
343 if (debug_elaborate)
344 cerr << get_line() << ": debug: Set array word=" << *word << endl;
346 // Test for the case that the index is a constant, and is out
347 // of bounds. The "word" expression is the word index already
348 // converted to canonical address, so this just needs to check
349 // that the address is not too big.
350 if (NetEConst*word_const = dynamic_cast<NetEConst*>(word)) {
351 verinum word_val = word_const->value();
352 long index = word_val.as_long();
353 if (index < 0 || index >= reg->array_count()) {
354 cerr << get_line() << ": warning: Constant array index "
355 << (index + reg->array_first())
356 << " is out of range for array "
357 << reg->name() << "." << endl;
361 /* An array word may also have part selects applied to them. */
363 index_component_t::ctype_t use_sel = index_component_t::SEL_NONE;
364 if (name_tail.index.size() > 1)
365 use_sel = name_tail.index.back().sel;
367 if (use_sel == index_component_t::SEL_PART)
368 elaborate_lval_net_part_(des, scope, lv);
370 if (use_sel == index_component_t::SEL_IDX_UP)
371 elaborate_lval_net_idx_up_(des, scope, lv);
373 if (use_sel == index_component_t::SEL_IDX_DO)
374 elaborate_lval_net_idx_do_(des, scope, lv);
376 return lv;
379 bool PEIdent::elaborate_lval_net_part_(Design*des,
380 NetScope*scope,
381 NetAssign_*lv) const
383 long msb, lsb;
384 bool flag = calculate_parts_(des, scope, msb, lsb);
385 if (!flag)
386 return false;
388 NetNet*reg = lv->sig();
389 assert(reg);
391 if (msb == reg->msb() && lsb == reg->lsb()) {
393 /* No bit select, and part select covers the entire
394 vector. Simplest case. */
396 } else {
398 /* If the bit/part select is constant, then make the
399 NetAssign_ only as wide as it needs to be and connect
400 only to the selected bits of the reg. */
401 unsigned loff = reg->sb_to_idx(lsb);
402 unsigned moff = reg->sb_to_idx(msb);
403 unsigned wid = moff - loff + 1;
405 if (moff < loff) {
406 cerr << get_line() << ": error: part select "
407 << reg->name() << "[" << msb<<":"<<lsb<<"]"
408 << " is reversed." << endl;
409 des->errors += 1;
410 return false;
413 /* If the part select extends beyond the extreme of the
414 variable, then report an error. Note that loff is
415 converted to normalized form so is relative the
416 variable pins. */
418 if ((wid + loff) > reg->vector_width()) {
419 cerr << get_line() << ": error: bit/part select "
420 << reg->name() << "[" << msb<<":"<<lsb<<"]"
421 << " is out of range." << endl;
422 des->errors += 1;
423 return false;
426 lv->set_part(new NetEConst(verinum(loff)), wid);
429 return true;
432 bool PEIdent::elaborate_lval_net_idx_up_(Design*des,
433 NetScope*scope,
434 NetAssign_*lv) const
436 const name_component_t&name_tail = path_.back();;
437 ivl_assert(*this, !name_tail.index.empty());
439 const index_component_t&index_tail = name_tail.index.back();
440 ivl_assert(*this, index_tail.msb != 0);
441 ivl_assert(*this, index_tail.lsb != 0);
443 NetNet*reg = lv->sig();
444 assert(reg);
446 if (reg->type() != NetNet::REG) {
447 cerr << get_line() << ": error: " << path_ <<
448 " is not a reg/integer/time in " << scope_path(scope) <<
449 "." << endl;
450 cerr << reg->get_line() << ": : " << path_ <<
451 " is declared here as " << reg->type() << "." << endl;
452 des->errors += 1;
453 return false;
456 unsigned long wid;
457 calculate_up_do_width_(des, scope, wid);
459 NetExpr*base = elab_and_eval(des, scope, index_tail.msb, -1);
461 /* Correct the mux for the range of the vector. */
462 if (reg->msb() < reg->lsb())
463 base = make_sub_expr(reg->lsb(), base);
464 else if (reg->lsb() != 0)
465 base = make_add_expr(base, - reg->lsb());
467 if (debug_elaborate)
468 cerr << get_line() << ": debug: Set part select width="
469 << wid << ", base=" << *base << endl;
471 lv->set_part(base, wid);
473 return true;
476 bool PEIdent::elaborate_lval_net_idx_do_(Design*des,
477 NetScope*scope,
478 NetAssign_*lv) const
480 const name_component_t&name_tail = path_.back();;
481 ivl_assert(*this, !name_tail.index.empty());
483 const index_component_t&index_tail = name_tail.index.back();
484 ivl_assert(*this, index_tail.msb != 0);
485 ivl_assert(*this, index_tail.lsb != 0);
487 cerr << get_line() << ": internal error: don't know how to "
488 "deal with SEL_IDX_DO in lval?" << endl;
489 des->errors += 1;
490 return false;
493 NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*, bool) const
495 cerr << get_line() << ": error: Constant values not allowed "
496 << "in l-value expressions." << endl;
497 des->errors += 1;
498 return 0;
502 * $Log: elab_lval.cc,v $
503 * Revision 1.44 2007/06/02 03:42:12 steve
504 * Properly evaluate scope path expressions.
506 * Revision 1.43 2007/05/24 04:07:11 steve
507 * Rework the heirarchical identifier parse syntax and pform
508 * to handle more general combinations of heirarch and bit selects.
510 * Revision 1.42 2007/03/14 05:06:49 steve
511 * Replace some asserts with ivl_asserts.
513 * Revision 1.41 2007/03/05 05:59:10 steve
514 * Handle processes within generate loops.
516 * Revision 1.40 2007/02/27 05:14:38 steve
517 * Detect and warn about lval array index out fo bounds.
519 * Revision 1.39 2007/02/01 05:25:26 steve
520 * Error message better reflects more general reality.
522 * Revision 1.38 2007/01/16 05:44:15 steve
523 * Major rework of array handling. Memories are replaced with the
524 * more general concept of arrays. The NetMemory and NetEMemory
525 * classes are removed from the ivl core program, and the IVL_LPM_RAM
526 * lpm type is removed from the ivl_target API.
528 * Revision 1.37 2006/11/04 06:19:25 steve
529 * Remove last bits of relax_width methods, and use test_width
530 * to calculate the width of an r-value expression that may
531 * contain unsized numbers.
533 * Revision 1.36 2006/06/02 04:48:50 steve
534 * Make elaborate_expr methods aware of the width that the context
535 * requires of it. In the process, fix sizing of the width of unary
536 * minus is context determined sizes.
538 * Revision 1.35 2006/04/16 00:54:04 steve
539 * Cleanup lval part select handling.
541 * Revision 1.34 2006/04/16 00:15:43 steve
542 * Fix part selects in l-values.
544 * Revision 1.33 2006/02/02 02:43:57 steve
545 * Allow part selects of memory words in l-values.
547 * Revision 1.32 2005/07/11 16:56:50 steve
548 * Remove NetVariable and ivl_variable_t structures.
550 * Revision 1.31 2004/12/29 23:55:43 steve
551 * Unify elaboration of l-values for all proceedural assignments,
552 * including assing, cassign and force.
554 * Generate NetConcat devices for gate outputs that feed into a
555 * vector results. Use this to hande gate arrays. Also let gate
556 * arrays handle vectors of gates when the outputs allow for it.
558 * Revision 1.30 2004/12/11 02:31:25 steve
559 * Rework of internals to carry vectors through nexus instead
560 * of single bits. Make the ivl, tgt-vvp and vvp initial changes
561 * down this path.
563 * Revision 1.29 2004/10/04 01:10:52 steve
564 * Clean up spurious trailing white space.
566 * Revision 1.28 2004/08/28 14:59:44 steve
567 * More detailed error message about bad variable.
569 * Revision 1.27 2003/09/19 03:30:05 steve
570 * Fix name search in elab_lval.